Semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device. The semiconductor device uses a complementary field effect transistor. The semiconductor device includes a first complementary field effect transistor (CFET) pair. The first CFET pair includes a first n-type transistor having a first gate electrode coupled to the first input of the differential pair. The first CFET pair includes a first p-type transistor having a second gate electrode coupled to the first input of the differential pair. The semiconductor device includes a second CFET pair. The second CFET pair includes a second n-type transistor having a third gate electrode coupled to a second input of the differential pair. The second CFET pair includes a second p-type transistor having a fourth gate electrode coupled to a second input of the differential pair.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are manufactured by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor material layers on a substrate, and patterning the various material layers using lithographic techniques to form circuit components and elements on the substrate. As semiconductor devices proceed into nanometer technology nodes in the pursuit of higher device densities, higher performance and lower costs, the challenges posed by manufacturing and design issues have led to the development of three-dimensional circuit elements. SUMMARY

[0003] According to one aspect of embodiments of the present application, a semiconductor device is provided, comprising: a first complementary field effect transistor (CFET) pair including: a first n-type transistor having a first gate electrode coupled to a first input of a differential pair; and a first p-type transistor vertically stacked with the first n-type transistor and having a second gate electrode coupled to a first input of the differential pair; and a second CFET pair including: a second n-type transistor having a third gate electrode coupled to a second input of the differential pair; and a second p-type transistor vertically stacked with the second n-type transistor and having a fourth gate electrode coupled to a second input of the differential pair.

[0004] According to another aspect of embodiments of the present application, a semiconductor device is provided, comprising: a first complementary field effect transistor (CFET) pair including: a first transistor having a first gate electrode coupled to a first input of an input pair; and a second transistor vertically stacked with the first transistor and having a second gate electrode of a same type as the first transistor and coupled to a second input of the input pair, wherein the semiconductor device is configured to compare a first voltage received at the first input of the input pair to a second voltage received at the second input of the output pair.

[0005] According to yet another aspect of embodiments of the present application, a semiconductor device is provided, comprising: a differential input circuit including: a first complementary field effect transistor (CFET) pair including: a first transistor having a first gate electrode coupled to a first input of an input pair; and a second transistor vertically stacked with the first transistor and having a second gate electrode coupled to a second input of the input pair, wherein the differential input circuit is configured to compare a first voltage received at the first input of the input pair to a second voltage received at the second input of the output pair and to communicate the comparison to a gated positive feedback stage. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the present disclosure can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be emphasized that various components are not necessarily drawn to scale and that the dimensions of various components can be arbitrarily increased or decreased for the sake of clarity and discussion.

[0007] Figure 1 A perspective view of a complementary field effect transistor (CFET) is shown in accordance with some embodiments.

[0008] Figure 2 An example circuit implemented using a CFET is shown in accordance with some embodiments.

[0009] Figure 3 A layout of a circuit including a CFET is shown in accordance with some embodiments.

[0010] Figure 4 Another example circuit implemented using a CFET is shown in accordance with some embodiments.

[0011] Figure 5 Another layout of a circuit including a CFET is shown in accordance with some embodiments.

[0012] Figure 6 Yet another example circuit implemented using a CFET is shown in accordance with some embodiments.

[0013] Figure 7 Yet another layout of a circuit including a CFET is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the disclosure in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Furthermore, the present disclosure can refer to reference numerals shown in the drawings with or without accompanying text. This reference by itself is not intended to limit the aspect of the application that is discussed in the text with which the reference is associated, but no such aspect of the application is intended to be excluded, unless otherwise specifically excluded by context.

[0015] Furthermore, relative terms such as "below" or "above" or "upper" or "lower" or "bottom" or "top" can be used herein to describe a relationship of one element or component to another in a drawing. Such relative terms can be used to describe different positions or orientations of an apparatus as shown in the figures. The terms can be used herein to describe particular positions or orientations of the devices as presented in the figures and to describe particular positions or orientations of the devices during use or operation in particular modes. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the relative descriptive terms used herein can be interpreted accordingly. References to "or" can be construed as inclusive so that any terms described using "or" can indicate any of a single, more than one, and all of the described terms. References to "at least one of A and B" can be interpreted to mean A, B, or A and B. Such references used in conjunction with "comprising" or other open terminology can include other items.

[0016] Semiconductor devices can exhibit substantial variation between or across their corresponding parts. Components of these devices are sometimes physically larger than otherwise possible to reduce the impact of dimensional variations (e.g., considering photolithography or performance differences). Moreover, in some cases, the relative performance of a set (e.g., a pair) of devices can itself constitute a design goal, so reducing performance can be a preferred option to maintain matching with another device. For example, in the case of a comparator circuit, the reference value and the measurement signal should be similarly treated to reduce discrimination error. Such matching can also be useful in other circuits including differential inputs. Matching of pairs of devices can need to be more heavily weighted when the devices are arranged in a preamplification stage of a circuit. For example, the inputs of operational amplifiers (op-amps) can use physically larger devices to help with matching and other performance goals.

[0017] According to the systems and methods of the present disclosure, semiconductor devices include various circuits that use pairs of transistors, referred to as complementary field effect transistors (CFETs). In many cases, the complementary pair of a CFET can refer to complementary types of semiconductor material, such as a p-type transistor and an n-type transistor disposed in a pair. However, as used herein, a CFET sometimes refers to other complementary pairs, such as pairs that share the same footprint, a side surface of a semiconductor device, or a circuit function. For example, a CFET can refer to a first and second transistor in a pair of transistors, where the individual transistors laterally coextend and are vertically spaced apart from one another (e.g., stacked). For example, one transistor in the pair of transistors can be implemented as a front-side transistor, and the other transistor in the pair of transistors can be implemented as a back-side transistor. Such vertical pairing can further reduce circuit size, as stacked devices can exhibit higher density relative to a single device layer. The pair of transistors can include a pair of n-type and p-type transistors, p-type transistors only, or n-type transistors only. Moreover, CFETs can be used in any of a variety of circuits that can benefit from operation matching of a pair of transistors, some examples of which are provided herein.

[0018] Figure 1 A perspective view of a complementary field effect transistor (CFET) pair 100 is shown in accordance with some embodiments. The depicted CFET 100 includes a first transistor 102 and a second transistor 112, depicted as front-side and back-side transistors, respectively. The first transistor 102 and the second transistor 112 can be referred to as vertically stacked with respect to one another. With particular reference to the first transistor 102, a semiconductor channel 104 is coupled with a gate structure 106. A data structure can be coupled to the gate electrode, which is coupled with a gate oxide that contacts the semiconductor channel 104. As shown, the semiconductor channel 104 can be surrounded by the gate structure 106, as in the case of a gate-all-around (GAA) implementation. However, this description should not be construed as limiting. Various implementations of the present disclosure can include multi-channel GAA, finFET, and other implementations of the gate structure 106. The gate structure 106 is coupled with and terminates at a source / drain structure 108, which in turn is coupled with other terminals, such as an MD structure 110, which is configured to electrically couple the source / drain structure 108 and a metallization layer formed above the CFET 100.

[0019] The second transistor 112 of the CFET 100 likewise includes another semiconductor channel 114 coupled with another gate structure 116 including a gate electrode and a gate oxide. The semiconductor channel 114 of the second transistor 112 is coupled with additional source / drain structures 118. These source / drain structures 118 are electrically coupled with additional MD structures 120 that are coupled with additional metallization layers formed above the CFET 100. For example, the MD structures 110 of the first transistor 102 can be coupled to a front metallization layer formed above a front side of a semiconductor device including the CFET 100, and the MD structures 120 of the second transistor 112 can be coupled to a backside metallization layer formed above a backside of the semiconductor device including the CFET 100.

[0020] While depicted as abutting one another, the individual transistors 102, 112 can be spaced apart by intervening layers, such as spacers or substrates. For example, the individual transistors 102, 112 can be formed on opposite sides of a substrate, or from stacked nanoscale layers. The individual transistors 102, 112 can be formed symmetrically in a lateral plane that partitions the transistors. Further, while the depicted CFET 100 can be formed in a substrate, such as a semiconductor wafer or an interlayer dielectric layer, such substrates / layers are omitted for clarity of the depicted components.

[0021] Corresponding portions of the first transistor 102 and the second transistor 112 can be coincident, mirrored, or otherwise disposed face-to-face in a lateral plane between them. For example, the first gate structure 106 coupled with the first gate electrode can laterally overlap and vertically spaced apart from the second gate structure 106 of the second transistor 112. Further, the first source / drain structure 108 coupled with the first gate structure can laterally overlap and vertically spaced apart from the second gate structure 106 of the second transistor 112.

[0022] The semiconductor channels 104, 114 of the first transistor 102 and the second transistor 112 can include the same or different material types. For example, one of the first transistor 102 or the second transistor 112 can include an n-type material, while the other of the first transistor 102 and the second transistor 112 can include a p-type material. In some embodiments, both transistors of a pair are p-type or n-type transistors. Likewise, the gate oxides or gate electrodes of the first transistor 102 and the second transistor 112 can include the same or different materials. In some embodiments, the gate electrodes of like or different types of transistors can be composed of or include the same material, for example where the individual gate structures 106, 116 are electrically connected to the same gate electrode, as shown in the circuit of Figure 2

[0023] Figure 2 ​An example circuit 200 implemented using CFETs 100 is shown in accordance with some embodiments. More specifically, the present circuit 200 is depicted as an operational amplifier (op-amp). The operational amplifier includes a differential input having a non-inverting input 233 and an inverting input 235. The combination of the non-inverting input 233 and the inverting input 235 can be referred to as a differential pair. The non-inverting input 233 is coupled with the gates of the n-type transistor 204 and the p-type transistor 206 of the first CFET 202. Thus, this non-inverting input 233 can receive voltages within an operating range (e.g., greater or less than a reference voltage, sometimes referred to as ground). Similarly, the inverting input 235 is coupled with the gates of the n-type transistor 210 and the p-type transistor 212 of the second CFET 208. Thus, the non-inverting input 233 can also operate within the entire operating range.

[0024] The n-type transistors 204, 210 of the first CFET 202 and the second CFET 208 can be coupled to a first current source 214, while the p-type transistors 206, 212 of the first CFET 202 and the second CFET 208 can be coupled to a second current source 216. Thus, the transistors 204, 206, 210, 212 of each CFET 202, 208 can exhibit a controlled (e.g., identical) tail current to control the transconductance of the operational amplifier. In accordance with the present disclosure, where the transistors of each CFET pair are stacked on top of one another, the tail current provided by each transistor in the CFET pair can exhibit consistency such that process variations can be correlated to one another, which can maintain a symmetric current, increasing the signal-to-noise ratio of the operational amplifier relative to other approaches. The first current source 214 can be coupled with a first supply voltage 238 (e.g., ground). The second current source 216 can be coupled with a second supply voltage 236 (e.g., VDD). The combination of the first CFET 202, the second CFET 208, and the current sources 214, 216 can be referred to as an input stage.

[0025] The output current generated by the input stage is amplified by an output stage of the operational amplifier. The present example depicts an output stage in accordance with a cascode configuration, which includes an NMOS stack coupled with the drains of the p-type transistors 206, 212 of the input stage. More specifically, the p-type transistor 206 of the first CFET 202 is coupled with the NMOS stack via a first node 243, and the p-type transistor 212 of the second CFET 208 is coupled with the NMOS stack via a second node 245. The depicted example further depicts a PMOS stack coupled with the drains of the n-type transistors 204, 210 of the input stage. More specifically, the n-type transistor 204 of the first CFET 202 is coupled with the PMOS stack via a third node 247, and the n-type transistor 210 of the second CFET 208 is coupled with the NMOS stack via a fourth node 249.

[0026] The NMOS stack includes first transistor 218, second transistor 220, third transistor 222, and fourth transistor 224 (all n-type). The PMOS stack includes first transistor 226, second transistor 228, third transistor 230, and fourth transistor 232 (all p-type). The NMOS stack is biased according to first bias current 240, while the PMOS stack is biased according to second bias current 242, although these currents can be provided according to the same bias (e.g., can be equal or can vary according to process variations). The output 250 of the operational amplifier mapping is coupled with the output of the cascode circuit drive of the output stage or a load inductance (e.g., based on the relative electrical potential received at non-inverting input 233 and inverting input 235, one of the NMOS stack or the PMOS stack).

[0027] Figure 3 A layout diagram of a circuit including a CFET is shown, according to some embodiments. For example, Figure 2 The circuit of FIG. 1 can be implemented according to the layout depicted. Figure 3 A view of a first surface 301 (e.g., front surface) of a semiconductor device and a second surface 303 (e.g., back surface) of the semiconductor device. In some embodiments, other layers can be stacked. For example, multiple instances of the depicted layers can be stacked in a front-to-front, back-to-back, or front-to-back configuration, which can further increase lateral component density relative to other approaches. The first surface 301 includes each of a first region 305 and a second region 307. The second surface 303 includes each of a third region 309 and a fourth region 311.

[0028] The first region includes first and second p-type transistors 206, 212. The second region includes the PMOS stack. The third region includes first and second n-type transistors 204, 210. The fourth region includes the NMOS stack. Each region is laterally bounded by a polysilicon-on-diffusion (PODE) boundary. PODE is used in semiconductor designs to bound regions with multiple polysilicon gates to improve process control and yield. It helps to achieve consistent lithography and etching, for example, by preventing damage to sensitive polysilicon gates near the diffusion edge, and minimizing variations in electrical performance. An oxide diffusion (OD) is depicted as extending along each region perpendicular to the gate structures 106, 116 and the source / drain structures 108, 118. In some embodiments, such as embodiments using grown GAA channels, this region can refer to the channel itself. In some embodiments, the OD region 350 can refer to a fin region or a planar region of the substrate. In some embodiments, the OD region 350 is the same OD region 350 on the front side and the back side.

[0029] Referring to a first region 305 of the first surface 301, the non-inverting input 233 is coupled to a logic gate structure at each of the respective gate vias 302 on the first surface 301 (e.g., the front surface). The first input and second input of the differential pair may each be coupled to the same number of gate vias 302. Furthermore, the first and second transistors in each CFET 202, 208 may be coupled to the same number of gate vias 302. Each depicted gate via 302 corresponds to a separate physical gate structure 106, as shown, disposed between source / drain structures 108 (e.g., MD structure 110). Gate structures 106 may be implemented according to various techniques, including polysilicon gates, metal gates, or other gate structures. The second current source 216 and the first node 243 are connected via source / drain vias 304 to the alternating structure (e.g., using MD structure 110) in the source / drain structure 108 of the p-type transistor 206 of the first CFET 202 (which implements the non-inverting input 233). The second current source 216 and the second node 245 are connected to an alternating structure (e.g., using an MD structure 110) in the source / drain structure 108 of the p-type transistor 212 of the second CFET 208 (which implements the inverting input 235). The interconnects coupled to the gate via 302 and the source / drain via 304 of the first surface shown can be implemented in at least one metallization layer above the first surface 301 of the semiconductor device. For example, vertical interconnects can be formed in at least a first front metallization layer (FM0) and can include portions of other layers (e.g., FM1, FM2, etc.).

[0030] Referring to the second region 307 of the first surface 301, the PMOS stack is coupled to the third node 247, the fourth node 249, and the bias current 242, as follows: Figure 2 As shown. Connections to the second supply voltage 236 and output 250 are also shown. More specifically, the first transistor 226 and the second transistor 228 of the PMOS stack are interconnected and coupled to each other via a metallization layer. Gate via 302 is shown as coupling the third transistor 230 and the fourth transistor 232 of the PMOS stack to the node of bias current 242. Source / drain via 304 connects the PMOS stack to... Figure 2 The other parts of the circuit shown (including output 250) are coupled.

[0031] Referring now to the second surface 303, the third region 309 includes the n-type devices of the CFETs 202, 208. The n-type transistors 204, 210 implementing the non-inverting input 233 and the inverting input 235 are coupled with a logic gate structure at each of the respective gate vias 302 on the second surface 303 (e.g., back surface). Each gate via 302 depicted corresponds to a separate physical gate structure 116, as shown, disposed between source / drain structures 118 (e.g., using MD structures 120). For the first surface 301, these gate structures 116 can be implemented according to various techniques. The first current source 214 and the third node 247 are connected to alternating structures (e.g., using MD structures 120) in the source / drain structures 118 of the n-type transistor 204 of the first CFET 202. The first current source 214 and the fourth node 249 are connected to alternating structures (e.g., using MD structures 120) in the source / drain structures 118 of the n-type transistor 210 of the second CFET 208 (as implementing the inverting input 235).

[0032] Referring now to the fourth region of the second surface 303, the NMOS stack is depicted coupled with the first node 243 and the second node 245, as well as the node of the bias current 240, as shown. Also shown are connections to the first supply voltage 238 and the output 250. The gate via 302 is shown coupling the first transistor 218 and the second transistor 220 of the NMOS stack with the bias current 240. The third transistor 222 and the fourth transistor 224 of the NMOS stack are coupled with one another via a metallization layer. The source / drain via 304 couples the NMOS stack with other portions of the circuit, including the output 250, as shown. Figure 2 Figure 2 Thus, the output 250 can be driven by either of the PMOS stack or the NMOS stack.

[0033] ​Each transistor formed on the first surface is depicted as a p-type transistor, and each transistor formed on the second surface is an n-type transistor. This implementation can reduce the number of operations to fabricate some semiconductor devices described herein. For example, an addition or subtraction process for fabricating a semiconductor device can differ between device types. Thus, the process of forming p-type devices on the first surface 301 can be omitted from the formation of the second surface 303. Similarly, the process of forming n-type devices on the second surface 301 can be omitted when forming p-type devices on the first surface 301 (e.g., the surface opposite the second surface 303). This implementation can be used to generate a variety of circuits in addition to the circuits explicitly provided herein. Further, in some embodiments, a circuit can include regions of n-type or p-type devices (e.g., transistors), such as in lateral regions along the same surface of the devices. For example, in some embodiments, the depicted PMOS stack can be spaced laterally or vertically from the first p-type transistor 206 and the second p-type transistor 212.

[0034] Figure 4 Another example circuit 400 implemented using a CFET 402 is shown, according to some embodiments. The circuit 400 can operate as a sense amplifier or dynamic comparator, as can implement a flash analog-to-digital circuit (ADC), a successive approximation register, or other comparator. The circuit is configured to process a measurement signal received at a first input 420 and a reference signal received at a second input 422. The first input 420 is the gate of a first p-type transistor 404, and the second input 422 is the gate of a second p-type transistor 405. The first and second inputs 420, 422 can be referred to as an input pair. The first and second p-type transistors 404, 405 can be implemented as the transistors of a CFET pair 402, as they can exhibit correlated process variations to reduce discrimination error between the reference and measurement signals. The CFET 402 can be referred to as a differential input stage, which is configured to receive a measurement and a reference. The cross-coupled inverters can be referred to as a clock-gated positive feedback stage.

[0035] The reset input can be configured to receive a clock signal or other strobe signal, shown at the third transistor 406, the fourth transistor 408, and the fifth transistor 409, and the sixth transistor 410, the seventh transistor 412, and the eighth transistor 413, which implement the first half of a cross-coupled pair. The cross-coupled pair is sometimes referred to as a regenerative latch, as it latches a value until reset or resampled. The precharge transistor 414 is coupled with a supply voltage 416 to precharge the first node 431 of the comparator circuit. For example, the supply voltage 416 can be VDD referenced to a second supply voltage 418 (e.g., ground). The activation of the clock or strobe inputs 424, 426 can clear the state of the second node 433 and the third node 435 of the cross-coupled pair.

[0036] Figure 5 Implementations according to some embodiments are shown, including Figure 4 Another layout diagram of the semiconductor device, circuit 400, of CFET 402. CFET 402 includes a second p-type transistor 405 on a first surface 501 of the semiconductor device and a first p-type transistor 404 on a second surface 503 of the semiconductor device. As described above, the first p-type transistor 404 and the second p-type transistor 405 can be formed approximately symmetrically face-to-face in a lateral plane to reduce discrimination errors between reference and measurement signals and increase the lateral density of the device. For example, the first p-type transistor 404 and the second p-type transistor 405 can be mirror images of each other (e.g., any of the gate electrode, gate oxide, semiconductor channel 104, or other components can have the same dimensions and comprise or be composed of the same material).

[0037] A first region 505 of the semiconductor device is positioned along a first surface 501 and includes a second p-type transistor 405, a portion of a pre-charged transistor 414, and a fifth transistor 409. A second region 507 includes a third transistor 406 and a fourth transistor 408, which, along with the fifth transistor 409, belong to the same half of a cross-coupled pair. A third region 509 of the semiconductor device is positioned along a second surface 503 and includes a first p-type transistor 404, a portion of a pre-charged transistor 414, and an eighth transistor 413. A fourth region 511 includes a sixth transistor 410 and a seventh transistor 412, which, along with the eighth transistor 413, belong to the same half of a cross-coupled pair.

[0038] Referring to the first region 505, the second input terminal 422 (e.g., the input of a reference signal) is depicted as a logic gate structure at each of the various gate vias 302 on the first surface 501 (e.g., the front surface). Each depicted gate via 302 corresponds to a separate physical gate structure 106 of the second p-type transistor 405, as shown, which is disposed between source / drain structures 108 (e.g., MD structure 110). The source / drain structure 108 is sometimes referred to as a source / drain region, but is not limited thereto. A precharge transistor 414 is connected to the proximal separate physical gate structure 106. The gate is disposed between and coupled to the source / drain structure 108 (e.g., MD structure 110) for clock / strobe inputs 424, 426 (depicted as a bridge) and the first node 431. A fifth transistor 409 is also shown adjacent, its source / drain coupled to the source / drain of the second p-type transistor 405. The source / drain of the fifth transistor 409 is coupled to the third node 435, and the gate of the fifth transistor 409 is coupled to the fourth transistor 408 (second node 433) in the second region 507.

[0039] Referring again to region 507, the fourth transistor 408 and the third transistor 406 (third node 435) share a source / drain. A metallization layer is used to couple the other source / drain of the fourth transistor 408 to the second power supply voltage 418. The metallization layer also couples the second power supply voltage 418 to the third transistor 406.

[0040] While each of the second p-type transistor 405, the pre-charge transistor 414, and the fifth transistor 409 is configured as a p-type transistor, the third transistor 406 and the fourth transistor 408 are configured as n-type transistors. The n-type transistors are depicted as spaced apart from the p-type transistors. This spacing can correspond to lateral spacing or vertical spacing. For example, at least the second node 433 and the third node 435 may include a TSV or other conductive structure traversing from the first surface 501 of the semiconductor device to another surface. Therefore, as described above regarding... Figure 4 The n-type devices can be located on the same surface to simplify manufacturing. For example, n-type devices can be stacked on a third or fourth surface. Similarly, in some embodiments, p-type devices can be co-located on the same surface (or other areas).

[0041] Referring to the third region 509, the first input terminal 420 (e.g., an input for a measurement signal) is depicted as a logic gate structure at each of the respective gate vias 302 on the second surface 503 (e.g., the rear surface). Each depicted gate via 302 corresponds to a separate physical gate structure 106 of the first p-type transistor 404, as shown, which is disposed between the source / drain structures 118 (e.g., using MD structure 120). A precharge transistor 414 is partially connected to the proximal separate physical gate structure 116 (in... Figure 4 (Depicted as a single logic gate structure in the schematic diagram). The gate is sequentially disposed between and coupled to the source / drain structure 118 (e.g., MD structure 120) of the first node 431 and the strobe inputs 424, 426 (which may be clock-driven, performing comparisons at regular intervals). The eighth transistor 413 is also shown adjacent, its source / drain coupled to the source or drain of the first p-type transistor 404. Another of the sources / drains of the eighth transistor 413 is coupled to the second node 433, and the gate of the eighth transistor 413 is coupled to the sixth transistor 410 (third node 435) of the fourth region 511.

[0042] Referring again to region 511, the sixth transistor 410 and the seventh transistor 412 (second node 433) share a source / drain. A metallization layer couples the different sources / drains of the sixth transistor 410 to a second power supply voltage 418. The metallization layer also couples the second power supply voltage 418 to the seventh transistor 412. While each of the first p-type transistor 404, the pre-charge transistor 414, and the eighth transistor 413 is configured as a p-type transistor, the sixth transistor 410 and the seventh transistor 412 are configured as n-type transistors. As described above, p-type or n-type transistors can be located in the same region or on the same surface of the semiconductor device. The PODE region is further depicted as described above regarding... Figure 3 As described in OD region 350, the PODE region can define the boundary of the depicted OD region or area.

[0043] Figure 6 Another example circuit 600 implemented using a CFET 602 according to some embodiments is shown. For example... Figure 4 As shown, circuit 600 can implement a sense amplifier or a dynamic comparator, although the current diagram is shown with a different topology. A first input 620 receives a measurement signal, and a second input 622 receives a reference signal. The first input 620 is the gate of a first n-type transistor 604, and the second input 622 is the gate of a second n-type transistor 605. The first and second n-type transistors 604 and 605 can be implemented as CFET pairs 602 transistors, as they may exhibit relevant process variations. Therefore, although... Figure 4 The CFET 402 in this circuit includes a pair of p-type transistors, but the CFET 602 in this circuit includes a pair of n-type transistors. The CFET 402 can be referred to as a differential input stage, configured to receive a measurement and a reference value. The cross-coupled inverter can be referred to as a gating positive feedback stage (e.g., clock-gated).

[0044] The reset transistor 614 is coupled to the first input 620 and the second input 622 at the first node 631 to reset the state of the circuit 600 and the regenerative latch. The regenerative latch includes cross-coupled transistors 606, 608, 609, 610, 612, 613 to store a value through the cross-coupled second node 633 and third node 635. The reset transistor 614 couples the first node 631 to a supply voltage 616. Additional pre-charge inputs 624, 626 couple another supply voltage 618 to the second node 633 and the third node 635. Upon receiving a clock edge or other strobe pulse, the circuit will store a digital value based on the higher of the first input 620 or the second input 622. In this way, the circuit can store an indication of the larger of the inputs, can be common-source common-gate to form an ADC, or can be used for other comparator applications. The construction of the CFET helps to reduce discrimination error between a reference signal and a measurement signal. For example, as described above, the various transistors of the CFET can have similar (e.g., mirrored) geometries and similar (e.g., identical) material formations. This symmetry can include the geometry of the various structures of the transistors, as well as connections between them (such as the number of gate vias, source / drain vias, size of metallization layer connections, or other aspects of the transistors). This implementation can further increase lateral density, reducing capacitance or resistance losses due to signal routing, which can further improve the accuracy of the comparison.

[0045] Figure 7 Another layout diagram of a circuit including a CFET is shown in accordance with some embodiments. This layout uses n-type transistors in place of p-type transistors in the layout of Figure 4 Figure 4 p-type transistors in place of n-type transistors in the layout of Figure 4 The supply voltages 616, 618 can be inverted relative to the supply voltages 416, 418 of Figure 4 For example, the reset transistor 614 can pull the circuit to ground at startup, rather than another VDD referenced to ground as in the case of the pre-charge transistors 414 of Figure 5 The layout is otherwise similar to the layout of

[0046] ​In one aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a first complementary field effect transistor (CFET) pair. The first CFET pair includes a first n-type transistor having a first gate electrode coupled with a first input of a differential pair. The first CFET pair includes a first p-type transistor vertically stacked with the first n-type transistor and having a second gate electrode coupled with the first input of the differential pair. The semiconductor device includes a second CFET pair. The second CFET pair includes a second n-type transistor having a third gate electrode coupled with a second input of the differential pair. The second CFET pair includes a second p-type transistor vertically stacked with the second n-type transistor and having a fourth gate electrode coupled with the second input of the differential pair.

[0047] In some embodiments, the first n-type transistor includes: a first gate structure coupled with the first gate electrode, laterally overlapping and vertically spaced apart from a second gate structure of the first p-type transistor; and a first source / drain region coupled with the first gate structure, laterally overlapping and vertically spaced apart from the second gate structure of the first p-type transistor.

[0048] In some embodiments, the first n-type transistor and the first p-type transistor are symmetrically formed on a lateral plane that separates the first n-type transistor and the first p-type transistor.

[0049] In some embodiments, the first n-type transistor and the first p-type transistor are each coupled with a same OD region.

[0050] In some embodiments, the first input of the differential pair and the second input of the differential pair are each coupled with a same OD region.

[0051] In some embodiments, the first n-type transistor and the first p-type transistor include a same number of gate vias coupled with a metallization layer formed on the semiconductor device.

[0052] In some embodiments, the metallization layer includes: a front side metallization layer coupled with gate vias of one of the first n-type transistor or the first p-type transistor; and a back side metallization layer coupled with gate vias of the other of the first n-type transistor or the first p-type transistor.

[0053] In some embodiments, the differential pair is a differential input of an operational amplifier (op-amp), the operational amplifier including: a first plurality of transistors located on a first side of the semiconductor device, the first plurality of transistors including the first n-type transistor; and a second plurality of transistors located on a second side of the semiconductor device, the second plurality of transistors including the first p-type transistor.

[0054] In some embodiments, the operational amplifier is powered by a first supply voltage and a second supply voltage, the first supply voltage being greater than the second supply voltage; the first p-type transistor is configured to receive a voltage lower than the second supply voltage; and the first n-type transistor is configured to receive a voltage greater than the second supply voltage.

[0055] In another aspect of the disclosure, a semiconductor device includes a first complementary field effect transistor (CFET) pair including a first transistor having a first gate electrode coupled with a first input of an input pair. The first CFET pair includes a second transistor vertically stacked with the first transistor, having a same type as the first transistor, and a second gate electrode coupled with a second input of the input pair. The semiconductor device is configured to compare a first voltage received at the first input of the input pair with a second voltage received at the second input of the output pair.

[0056] In some embodiments, the first transistor is vertically spaced apart from and laterally overlapping the second transistor.

[0057] In some embodiments, the first transistor and the second transistor are n-type transistors of a differential input stage of a dynamic comparator or a sense amplifier, the n-type transistors coupled with a clock-gated positive feedback stage.

[0058] In some embodiments, the first transistor and the second transistor are symmetrically formed on opposite sides of a lateral plane separating the first transistor from the second p-type transistor.

[0059] In some embodiments, the first transistor and the second transistor include a same number of gate vias coupled with a metallization layer formed over the semiconductor device, the metallization layer including: a front side metallization layer coupled with the gate vias of the first transistor; and a back side metallization layer coupled with the gate vias of the second transistor.

[0060] In some embodiments, the first transistor and the second transistor are coupled with a same OD region.

[0061] In another aspect of the disclosure, a semiconductor device includes a differential input circuit including a first complementary field effect transistor (CFET) pair including a first transistor having a first gate electrode coupled with a first input of an input pair. The CFET pair includes a second transistor vertically stacked with the first transistor, having a second gate electrode coupled with a second input of the input pair. The differential input circuit is configured to compare a first voltage received at the first input of the input pair with a second voltage received at the second input of the output pair, and to communicate the comparison to a gate-gated positive feedback stage.

[0062] In some embodiments, the differential input circuitry is an input to one of the dynamic comparators or sense amplifiers; and the gating of the gating gated positive feedback stage is a clock.

[0063] In some embodiments, the first transistor and the second transistor are of the same type.

[0064] In some embodiments, the first transistor and the second transistor are symmetrically formed on a transverse plane separating the first transistor and the second transistor.

[0065] In some embodiments, the first transistor and the second transistor include the same number of gate vias coupled to a metallization layer formed over the semiconductor device, the metallization layer including: a front metallization layer coupled to the gate via of the first transistor; and a rear metallization layer coupled to the gate via of the second transistor.

[0066] As used herein, the terms “about” and “approximately” generally refer to the value of a given quantity that can vary depending on the specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term “about” can refer to a given quantity of value, for example, varying within a range of 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0067] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A semiconductor device, comprising: The first CFET pair includes: A first n-type transistor has a first gate electrode coupled to a first input terminal of a differential pair; and A first p-type transistor, stacked perpendicularly to the first n-type transistor, and having a second gate electrode coupled to the first input terminal of the differential pair; and The second CFET pair includes: The second n-type transistor has a third gate electrode coupled to the second input terminal of the differential pair; and The second p-type transistor is stacked vertically with the second n-type transistor and has a fourth gate electrode coupled to the second input terminal of the differential pair.

2. The semiconductor device according to claim 1, wherein, The first n-type transistor includes: A first gate structure, coupled to the first gate electrode, laterally overlaps with and vertically spaced from the second gate structure of the first p-type transistor; and The first source / drain region is coupled to the first gate structure and laterally overlaps with and is vertically spaced from the second gate structure of the first p-type transistor.

3. The semiconductor device according to claim 1, wherein, The first n-type transistor and the first p-type transistor are symmetrically formed on a lateral plane separating the first n-type transistor and the first p-type transistor.

4. The semiconductor device according to claim 1, wherein, The first n-type transistor and the first p-type transistor are each coupled to the same diffusion region.

5. The semiconductor device according to claim 1, wherein, The first input terminal and the second input terminal of the differential pair are each coupled to the same diffusion region.

6. The semiconductor device according to claim 1, wherein, The first n-type transistor and the first p-type transistor include the same number of gate vias coupled to a metallization layer formed above the semiconductor device.

7. The semiconductor device according to claim 6, wherein, The metallization layer includes: The front metallization layer is coupled to the gate via of one of the first n-type transistors or the first p-type transistor; and The rear metallization layer is coupled to the gate via of either the first n-type transistor or the first p-type transistor.

8. A semiconductor device, comprising: The first CFET pair includes: A first transistor having a first gate electrode coupled to a first input terminal of an input pair; and A second transistor, stacked perpendicularly to the first transistor, and having the same type as the first transistor and a second gate electrode coupled to a second input terminal of the input pair, wherein the semiconductor device is configured to compare a first voltage received at the first input of the input pair with a second voltage received at the second input terminal of the output pair.

9. The semiconductor device according to claim 8, wherein, The first transistor and the second transistor are n-type transistors of the differential input stage of a dynamic comparator or sense amplifier, and the n-type transistors are coupled to a clock-gated positive feedback stage.

10. A semiconductor device, comprising: Differential input circuit, including: The first CFET pair includes: A first transistor having a first gate electrode coupled to a first input terminal of an input pair; and The second transistor is stacked perpendicularly to the first transistor and has a second gate electrode coupled to the second input terminal of the input pair. The differential input circuit is configured to compare a first voltage received at the first input terminal of the input pair with a second voltage received at the second input terminal of the output pair, and transmit the comparison to a gating positive feedback stage.

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