Integrated circuit including backside wiring and method of designing same

Abstract

An example integrated circuit includes a plurality of cells located in a plurality of rows extending in a first horizontal direction. The plurality of cells includes a first cell disposed in a first row. The first cell includes a first active pattern extending in a first horizontal direction and a first backside pattern overlapping the first active pattern in a vertical direction and extending in the first horizontal direction in a first backside wiring layer below the first active pattern. The first backside pattern is removed from a first inspection region that overlaps the first active pattern and extends in the second horizontal direction.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0104127, filed with the Korean Intellectual Property Office on August 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to an integrated circuit and its design method, including back-side wiring and a structure that allows for easy inspection. Background Technology

[0003] Integrated circuits manufactured using semiconductor processes may contain defects due to various factors. Defective integrated circuits may lack the designed performance, fail to perform their intended functions, or have a shortened lifespan. Semiconductor processes can include procedures for inspecting integrated circuits to detect defects. As the device size included in integrated circuits decreases and their structure becomes more complex, the difficulty of inspecting integrated circuits may also increase. Summary of the Invention

[0004] In some embodiments, an integrated circuit includes: a plurality of cells arranged in a row extending along a first horizontal direction, wherein the plurality of cells includes a first cell disposed in the first row, wherein the first cell includes a first active pattern extending in the first horizontal direction and a first back-side pattern extending in the first horizontal direction in a first back-side wiring layer that overlaps with and is below the first active pattern in a vertical direction, wherein the first back-side pattern is removed from a first inspection region that overlaps with and extends in a second horizontal direction.

[0005] In some embodiments, an integrated circuit includes: a plurality of active patterns extending in a first horizontal direction and a plurality of back-side patterns extending below the plurality of active patterns, wherein the plurality of back-side patterns includes a first back-side pattern that overlaps with a first active pattern in the plurality of active patterns in a vertical direction and extends in a first back-side wiring layer along the first horizontal direction, wherein the first back-side pattern is removed from a first inspection region that overlaps with the first active pattern and extends in a second horizontal direction.

[0006] In some embodiments, a method of designing an integrated circuit includes: obtaining input data defining a plurality of cells included in the integrated circuit; placing the plurality of cells based on a cell library; and generating output data defining the placed plurality of cells, wherein the cell library defines a first layout and a second layout of a first cell among the plurality of cells, and placing the plurality of cells includes setting the first layout and replacing the first layout with the second layout, wherein the first layout includes a first backside pattern extending continuously from a first boundary of the first layout to a second boundary in a first backside wiring layer along a first horizontal direction, and the second layout includes a second backside pattern corresponding to the first backside pattern, wherein a portion of the first backside pattern is removed from a first inspection area. Attached Figure Description

[0007] The embodiments can be more clearly understood through the following detailed description in conjunction with the accompanying drawings.

[0008] Figure 1 This is a diagram showing an example of an integrated circuit layout.

[0009] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a diagram showing an example of the device.

[0010] Figure 3 This is a diagram showing an example of an integrated circuit layout.

[0011] Figure 4A , Figure 4B and Figure 4C This is a diagram showing an example of an integrated circuit layout.

[0012] Figure 5A and Figure 5B This is a diagram showing an example of an integrated circuit layout.

[0013] Figure 6A and Figure 6B This is a diagram showing an example of an integrated circuit layout.

[0014] Figure 7A and Figure 7B This is a diagram showing an example of an integrated circuit layout.

[0015] Figure 8 This is a diagram showing an example of an integrated circuit layout.

[0016] Figure 9A and Figure 9B This is a diagram showing an example of an integrated circuit layout.

[0017] Figure 10 This is a flowchart illustrating an example of a method for manufacturing integrated circuits.

[0018] Figure 11 This is a flowchart illustrating an example of a method for designing integrated circuits.

[0019] Figure 12 This is a flowchart illustrating an example of a method for designing integrated circuits.

[0020] Figure 13 This is a block diagram illustrating an example of an on-chip system.

[0021] Figure 14 This is a block diagram illustrating an example of a computing system that includes a stored program memory. Detailed Implementation

[0022] Figure 1 This is a diagram showing an example of integrated circuit layout 10. Figure 1 A plan view of layout 10 and a cross-sectional view of layout 10 taken along line X1-X1' are shown. Here, the X-axis direction and the Y-axis direction can be referred to as the first direction and the second direction, respectively, and the Z-axis direction can be referred to as the vertical direction or the third direction. The plane formed by the X-axis and the Y-axis can be referred to as the horizontal plane, and a component located in the +Z direction relative to other components can be referred to as above other components, and a component located in the -Z direction relative to other components can be referred to as below other components. Furthermore, the area of ​​a component can refer to the size occupied by the component in a plane parallel to the horizontal plane, and the width of a component can refer to its length in a direction orthogonal to the direction in which the component extends. The surface exposed in the +Z direction can be referred to as the upper surface, the surface exposed in the -Z direction can be referred to as the bottom surface, and the surface exposed in the ±X direction or ±Y direction can be referred to as the side surface. In the accompanying drawings, for ease of illustration, only some layers may be shown, and for ease of understanding, even if a via connecting the upper pattern and the lower pattern is located below the upper pattern, the via may be indicated. Furthermore, patterns including conductive materials, such as patterns of wiring layers, can be referred to as conductive patterns, or simply as patterns.

[0023] Integrated circuits can include devices, such as transistors, arranged on a substrate SUB. See below for reference. Figures 2A to 2D Examples of devices arranged on a substrate SUB are described. Integrated circuits may include patterns extending above the devices and patterns extending below the substrate SUB. For example, as... Figure 1As shown, layout 10 may include patterns extending in a front-side wiring layer (such as a first front-side wiring layer M1) above the substrate SUB and patterns extending in a back-side wiring layer (such as a first back-side wiring layer BM1) below the substrate SUB. Here, the pattern of the front-side wiring layer may be referred to as a front-side pattern, and the pattern of the back-side wiring layer may be referred to as a back-side pattern. In some embodiments, the back-side pattern may be used to power the device, and the back-side pattern used to power the device may be referred to as a back-side power delivery network. Due to the back-side pattern, routing resources in the front-side wiring layer can be increased, and the integrated circuit can have a reduced area and / or a highly efficient structure. In particular, when the back-side pattern is used to power the device, the power supply voltage supplied to the device does not decrease due to the reduction in IR voltage drop.

[0024] Reference Figure 1 Layout 10 may include a gate (or gate electrode) extending in the Y-axis direction and an active pattern extending in the X-axis direction. For example, as Figure 1 As shown, the active patterns of a p-channel field-effect transistor (PFET) and an n-channel field-effect transistor (NFET) can extend in the X-axis direction and intersect with a gate extending in the Y-axis direction. Sources / drains can be formed on each side of the gate, and a channel can be formed between the sources / drains. In some embodiments, the sources / drains can be referred to as diffusion regions.

[0025] The first back-side pattern BM11 and the second back-side pattern BM12 may extend in the X-axis direction within the first back-side wiring layer BM1, and a back-side interlayer dielectric (BILD) may be inserted between the first back-side pattern BM11 and the second back-side pattern BM12. In some embodiments, the first back-side pattern BM11 may provide a positive supply voltage to the PFET and may extend in the X-axis direction below the PFET active pattern, such as... Figure 1 As shown. In some embodiments, the second back-side pattern BM12 can provide a negative supply voltage to the NFET and can extend in the X direction below the NFET active pattern, such as... Figure 1 As shown.

[0026] Layout 10 may include a through-silicon via (TSV) penetrating the substrate SUB and a back-side contact BC connected to the lower surface of the source / drain. For example, as Figure 1 As shown, the first through-silicon via (TSV1) and the second through-silicon via (TSV2) can extend from the upper surface of the first back-side pattern BM11. A first back-side contact BC1 can be disposed on the first TSV1 and can be connected to the first source / drain SD1. Furthermore, a second back-side contact BC2 can be disposed on the second TSV2 and can be connected to the third source / drain SD3. In some embodiments, with... Figure 1Unlike the previous design, through-silicon vias (TSVs) can be omitted, and the back-side contacts can extend from the back-side pattern to the source / drain. When a positive supply voltage is applied to the first back-side pattern BM11, the first source / drain SD1 and the third source / drain SD3 can receive the positive supply voltage from the first back-side pattern BM11. For example... Figure 1 As shown, the first positive side pattern M11 can be connected to the second source / drain SD2 through the first via V01 of the first via layer V0 and the first contact (or the first source / drain contact) CA1.

[0027] Integrated circuits can be manufactured using semiconductor processes and may contain defects due to various factors. Physical failure analysis (PFA) refers to the analysis of defects in integrated circuits using analytical equipment. For example, optical fault isolation (OFI) refers to the use of various optical techniques (such as light emission and static laser stimulation) to detect defects in integrated circuits. Figure 1 As shown by the arrow, when the laser shines from bottom to top, i.e., along the +Z axis, for OFI, the laser may be blocked by the pattern of the back-side wiring layer and may not be able to reach the location to be inspected. For example, as... Figure 1 As shown, when the first back-side pattern BM11 is positioned below the PFET active pattern AP1, the laser may not be able to reach the PFET active pattern AP1, and it may be difficult to inspect the transistor junction.

[0028] As described below with reference to the accompanying drawings, integrated circuits can include a structure that facilitates easy inspection. Therefore, integrated circuits including back-side wiring can be inspected, and defects can be easily detected. Furthermore, integrated circuits containing defects can be easily rejected, thereby ensuring that integrated circuits delivering the designed performance and functionality are shipped.

[0029] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a diagram showing an example of the device. For example, Figure 2A FinFET 20a is shown. Figure 2B A full-ring gate field-effect transistor (GAAFET) 20b is shown. Figure 2C A multi-bridge channel field-effect transistor (MBCFET) 20c is shown, and Figure 2D A vertical field-effect transistor (VFET) 20d is shown. For ease of illustration, Figures 2A to 2C The diagram shows the state where one of the two source / drain regions has been removed, and Figure 2D A cross-section of VFET 20d is shown, cut along a plane parallel to the Y and Z axes and passing through the channel CH of VFET 20d.

[0030] Reference Figure 2AFinFET 20a can be formed from fin-shaped active patterns extending along the Y-axis between shallow trench isolation portions (STI) and a gate G extending along the Y-axis. Source / drain electrodes (SD) can be formed on both sides of the gate G, and thus the source and drain can be spaced apart from each other in the X-axis direction. An insulating film can be formed between the channel CH and the gate G. In some embodiments, FinFET 20a can be formed from multiple active patterns and gates G spaced apart from each other in the X-axis direction.

[0031] Reference Figure 2B The GAAFET 20b can be formed from an active pattern (i.e., nanowires) extending in the X-axis direction and spaced apart from each other in the Z-axis direction, and a gate G extending in the Y-axis direction. Source / drain electrodes SD can be formed on both sides of the gate G, and therefore, the source and drain can be spaced apart from each other in the X-axis direction. An insulating film can be formed between the channel CH and the gate G. It should be noted that the number of nanowires included in the GAAFET 20b is not limited to... Figure 2B The quantities shown.

[0032] Reference Figure 2C The MBCFET 20c can be formed from active patterns (i.e., nanosheets) extending in the X-axis direction and spaced apart from each other in the Z-axis direction, and a gate G extending in the Y-axis direction. Source / drain electrodes (SD) can be formed on both sides of the gate G, and therefore, the source and drain can be spaced apart from each other in the X-axis direction. An insulating film can be formed between the channel CH and the gate G. It should be noted that the number of nanosheets included in the MBCFET 20c is not limited to... Figure 2C The quantities shown.

[0033] Reference Figure 2D VFET 20d may include a top source / drain T_SD and a bottom source / drain B_SD spaced apart from each other in the Z-axis direction, wherein a channel CH is located between the top source / drain T_SD and the bottom source / drain B_SD. VFET 20d may include a gate G surrounding the channel CH between the top source / drain T_SD and the bottom source / drain B_SD. An insulating film may be formed between the channel CH and the gate G.

[0034] The following description primarily focuses on integrated circuits including FinFET 20a or MBCFET 20c; however, it should be noted that the devices included in the integrated circuits are not limited to those described herein. Figures 2A to 2DExamples include: For instance, an integrated circuit may include a ForkFET, in which nanosheets of P-type transistors and nanosheets of N-type transistors are separated by dielectric walls, allowing the N-type and P-type transistors to have a more closely spaced structure. Furthermore, integrated circuits may include bipolar junction transistors and FETs, such as complementary field-effect transistors (CFETs), negative capacitance field-effect transistors (NCFETs), and carbon nanotube (CNT) FETs.

[0035] Figure 3 This is a diagram illustrating an example of an integrated circuit layout. For example, Figure 3 A plan view of the layout of cells 30 included in the integrated circuit and a cross-sectional view of the layout of cells 30 taken along line X2-X2' are shown. For ease of explanation, Figure 3 The first back-side pattern BM11 and the second back-side pattern BM12 of the first back-side wiring layer BM1 extending to the outside of the cell 30 are shown.

[0036] Integrated circuits can include cells. A cell is a unit of layout included in an integrated circuit and may be referred to as a standard cell. A cell may include a transistor and may be designed to perform a predefined function. In an integrated circuit, cells can be arranged in rows. For example, cells can be arranged and aligned in multiple rows extending along the X-axis. Cells arranged in a row, for example... Figure 3 Unit 30 can be called a single-height unit, while units arranged in two or more consecutive rows, for example... Figure 8 The 80th unit can be called a multi-height unit.

[0037] Reference Figure 3 Unit 30 may include a PFET active pattern AP1 and an NFET active pattern AP2 extending in the X-axis direction. The PFET active pattern AP1 may form a PFET with a gate electrode extending in the Y-axis direction, and the NFET active pattern AP2 may form an NFET with a gate electrode extending in the Y-axis direction. The gate electrodes may extend parallel to each other along the Y-axis direction at a spacing CPP. Figure 3 As shown, a dummy gate can replace the gate electrode and extend along the cell boundary in the Y-axis direction. The back-side pattern can extend below the active pattern. For example, as... Figure 3 As shown, the first back-side pattern BM11 can extend in the X-axis direction below the PFET active pattern AP1, and the second back-side pattern BM12 can extend in the X-axis direction below the NFET active pattern AP2. That is, the first back-side pattern BM11 can overlap with the PFET active pattern AP1 in the Z-axis direction (i.e., the vertical direction), and the second back-side pattern BM12 can overlap with the NFET active pattern AP2 in the Z-axis direction.

[0038] like Figure 3As shown, the first through-silicon via (TSV1) and the first back-side contact (BC1) can be located between the first source / drain (SD1) and the first back-side pattern (BM11). In some embodiments, a positive supply voltage can be applied to the first back-side pattern (BM11), and the PFET can receive the positive supply voltage from the first back-side pattern (BM11). In some embodiments, a negative supply voltage can be applied to the second back-side pattern (BM12), and the NFET can receive the negative supply voltage from the second back-side pattern (BM12). (Refer to the above...) Figure 1 As mentioned above, due to the first back-side pattern BM11 and the second back-side pattern BM12, it may be difficult to inspect the junction of the transistor. An example of a cell including the following structure is described below with reference to the accompanying drawings, which provides... Figure 3 Unit 30 provides the same functionality and performance as the transistor junction while also providing the ability to check the transistor junction.

[0039] Figure 4A , Figure 4B and Figure 4C This is a diagram illustrating an example of an integrated circuit layout. For example, Figure 4A This is a plan view showing the layout of unit 40. Figure 4B It is a cross-sectional view showing the layout of unit 40 taken along line X2-X2', and Figure 4C This is a cross-sectional view showing the layout of element 40 taken along line X3-X3'. For ease of explanation, Figure 4A Only the gate electrode, back-side contact, and back-side pattern are shown in the reference. Figures 4A to 4C The description in this document omits any descriptions identical to those given above with reference to the accompanying drawings.

[0040] Reference Figure 4A Unit 40 may include unit region 41 and dummy region 42. Unit region 41 may have the same characteristics as... Figure 3 The same structure as unit 30, and therefore, Figure 4A Unit 40 can provide with Figure 3 The unit 30 has the same function and performance. The dummy region 42 may include an inspection region IR, from which the pattern of the first back-side wiring layer BM1 can be removed. For example, as... Figure 4AAs shown, the first back-side pattern BM11 and the second back-side pattern BM12 can extend in the X-axis direction and be removed from the inspection region IR extending in the Y-axis direction. Therefore, each of the first back-side pattern BM11 and the second back-side pattern BM12 can have a reduced width (length in the Y-axis direction) in the dummy region 42. As described above with reference to the accompanying drawings, the first back-side pattern BM11 and the second back-side pattern BM12 can overlap with the active pattern in the vertical direction. The inspection region IR can also include a portion that vertically overlaps with the active pattern, and therefore, the junction of the transistor can be inspected through the inspection region IR where the first back-side pattern BM11 and the second back-side pattern BM12 have been removed. The first back-side contact BC1 and the second back-side contact BC2 can be located above the first back-side pattern BM11 and the second back-side pattern BM12, respectively.

[0041] Reference Figure 4B The first back-side pattern BM11 can extend in the X-axis direction and is connected to the first source / drain SD1 through the first through-silicon via TSV1 and the first back-side contact BC1. See below. Figure 4C Unlike the description, the first back-side pattern BM11 can be continuous along the line X2-X2' between the boundaries of the unit 40 facing the X-axis direction.

[0042] Reference Figure 4C The first back-side pattern BM11 can extend in the X-axis direction and is connected to the first source / drain SD1 through the first through-silicon via TSV1 and the first back-side contact BC1. (Refer to the above.) Figure 4A The first back-side pattern BM11 can be removed from the inspection area IR, and the back-side interlayer dielectric BILD can be inserted between the first back-side pattern BM11 and the boundary of cell 40, as described above. Figure 4C As shown.

[0043] Unit 40 may include structures added via dummy region 42 for biasing transistors. For example, such as... Figure 4C As shown, the second source / drain SD2 can be connected to the third source / drain SD3 via the first contact CA1, the first via V01, the first positive side pattern M11, the second via V02, and the second contact CA2. The first positive side pattern M11 can extend in the X-axis direction. Therefore, the third source / drain SD3 included in the dummy region 42 can be biased to the potential of the second source / drain SD2 without affecting the operation of the cell 40.

[0044] Figure 5A and Figure 5B This is a diagram showing examples of the layouts 50a and 50b of integrated circuits. For example, Figure 5A and Figure 5BExamples of cross-sections for layouts 50a and 50b are shown. In the following text, with reference to... Figure 5A and Figure 5B In this description, descriptions identical to those given above with reference to the accompanying drawings have been omitted. In some embodiments, with Figure 5A and Figure 5B As shown, the integrated circuit may include back-side patterns formed on fewer than or more than four back-side wiring layers.

[0045] Reference Figure 5A Layout 50a may include back-side patterns extending in multiple back-side wiring layers, and may include back-side vias between the back-side patterns. For example, as... Figure 5A As shown, the first back-side pattern BM11 to the fourth back-side pattern BM41 can extend in the first back-side wiring layer to the fourth back-side wiring layer, respectively, and the first back-side via BV11 to the third back-side via BV31 can be arranged between the first back-side pattern BM11 to the fourth back-side pattern BM41, respectively. In some embodiments, all back-side patterns and back-side vias can be removed from the inspection area. For example, as... Figure 5A As shown, the back-side patterns and back-side vias of the first to fourth back-side wiring layers can be removed from the first inspection area IR1. Therefore, the active patterns, source / drain electrodes, and / or gate electrodes are not blocked by the back-side wiring layer patterns but are exposed to the laser from the back side of layout 50a. In other words, the laser can irradiate the first inspection area IR1 along the +Z axis direction, and the laser can reach the junction.

[0046] Reference Figure 5B Layout 50b may include back-side patterns extending in multiple back-side wiring layers, and may include back-side vias between the back-side patterns. For example, as... Figure 5B As shown, the first back-side pattern BM12 to the fourth back-side pattern BM42 can extend in the first back-side wiring layer to the fourth back-side wiring layer, respectively, and the first back-side via BV12 to the third back-side via BV32 can be respectively disposed between the first back-side pattern BM12 to the fourth back-side pattern BM42. In some embodiments, at least one back-side pattern can exist in the inspection area. For example, as... Figure 5B As shown, the second backside patterns BM22 to the fourth backside patterns BM42 of the second to fourth backside wiring layers can be removed from the second inspection area IR2, while the first backside pattern BM12 of the first backside wiring layer can be present in the second inspection area IR2. In some embodiments, despite the presence of one or more backside patterns, the laser used in OFI can still reach the junction, and therefore, at least one backside pattern that does not block the laser can be present in the second inspection area IR2. In some embodiments, with Figure 5BUnlike the previous example, the second back-side pattern BM22 of the second back-side wiring layer may additionally exist in the second inspection area IR2.

[0047] Figure 6A and Figure 6B This is a diagram illustrating an example of an integrated circuit layout. For example, Figure 6A and Figure 6B An example layout of cells 60a and 60b included in an integrated circuit is shown. For ease of illustration, Figure 6A and Figure 6B Only the gate electrode, back-side contact, and back-side pattern are shown in the reference. Figure 6A and Figure 6B The description in this document omits any descriptions identical to those given above with reference to the accompanying drawings.

[0048] Reference Figure 6A Unit 60a may include unit region 61 and dummy region 62. Unit region 61 may have the same characteristics as... Figure 3 The same structure as unit 30, and therefore, Figure 6A Unit 60a can provide with Figure 3 The unit 30 has the same function and performance. The dummy region 62 may include an inspection region IR, and the pattern of the first back-side wiring layer BM1 can be removed from the inspection region IR. For example, as... Figure 6A As shown, the first back-side pattern BM11 and the second back-side pattern BM12 can extend in the X-axis direction and be removed from the inspection area IR extending in the Y-axis direction. Figure 4A The units 40 are different; the first back-side pattern BM11 and the second back-side pattern BM12 can be terminated by the inspection area IR. For example... Figure 6A As shown, the inspection area IR may intersect with the boundary of cell 60a extending in the Y-axis direction, and therefore, the first back-side pattern BM11 and the second back-side pattern BM12 may be shortened due to the inspection area IR. In some embodiments, the cross-section of the layout of cell 60a cut along line X4-X4' may be consistent with... Figure 4C The cross sections are the same or similar. The first back-side contact BC1 and the second back-side contact BC2 can be respectively disposed above the first back-side pattern BM11 and the second back-side pattern BM12.

[0049] Reference Figure 6B Unit 60b may include unit region 63 and dummy region 64. Unit region 63 may have the same characteristics as... Figure 3 The same structure as unit 30, and therefore, Figure 6B Unit 60b can provide with Figure 3The unit 30 has the same function and performance. The dummy region 64 may include an inspection region IR, and the pattern of the first back-side wiring layer BM1 can be removed from the inspection region IR. For example, as... Figure 6B As shown, the first back-side pattern BM11 and the second back-side pattern BM12 can extend in the X-axis direction and be removed from the inspection area IR extending in the Y-axis direction. (Refer to the above text.) Figure 6A The first back-side pattern BM11 and the second back-side pattern BM12 may be terminated by the inspection area IR. The first back-side contact BC1 and the second back-side contact BC2 may be respectively disposed above the first back-side pattern BM11 and the second back-side pattern BM12.

[0050] In some implementations, the inspection region IR may have a width corresponding to the gate electrode spacing (i.e., CPP) or a width corresponding to a multiple of the gate electrode spacing. For example, as referenced above... Figure 4A and Figure 6A The inspection region IR can have a width corresponding to the spacing between adjacent gate electrodes and dummy gates. Furthermore, as... Figure 6B As shown, the width of the inspection area IR can correspond to twice the width of the gate electrode.

[0051] Figure 7A and Figure 7B This is a diagram illustrating an example of an integrated circuit layout. For example, Figure 7A and Figure 7B An example layout of cells 70a and 70b included in an integrated circuit is shown. For ease of illustration, Figure 7A and Figure 7B Only the gate electrode, back-side contact, and back-side pattern are shown. See below for reference. Figure 7A and Figure 7B The inspection region IR can exist within the cell boundary. Figure 7A and Figure 7B The description in this document omits any descriptions identical to those given above with reference to the accompanying drawings.

[0052] Reference Figure 7AUnit 70a may include a first back-side pattern BM11 and a second back-side pattern BM12 extending in the X-axis direction. An inspection region IR may extend in the Y-axis direction between the first gate electrode G71 and the second gate electrode G72, and a portion of each of the first back-side pattern BM11 and the second back-side pattern BM12 may be removed. Therefore, each of the first back-side pattern BM11 and the second back-side pattern BM12 may be continuous between the boundaries of unit 70a that face each other in the X-axis direction (or extend in the Y-axis direction), while having a reduced width (i.e., a length in the Y-axis direction) below the region between the first gate electrode G71 and the second gate electrode G72, and the second back-side pattern BM12 may also have a reduced width below the region between the first gate electrode G71 and the second gate electrode G72.

[0053] Reference Figure 7B Unit 70b may include a first back-side pattern BM11 and a second back-side pattern BM12 extending in the X-axis direction. An inspection region IR may extend in the Y-axis direction between the first gate electrode G71 and the second gate electrode G72, and may divide each of the first back-side pattern BM11 and the second back-side pattern BM12. For example, the first back-side pattern BM11 may be divided into two parts BM11_1 and BM11_2 by the inspection region IR, and the second back-side pattern BM12 may also be divided into two parts BM12_1 and BM12_2 by the inspection region IR. Therefore, the first back-side pattern BM11 and the second back-side pattern BM12 may be discontinuous between the boundaries of unit 70b that face each other in the X-axis direction (or extend in the Y-axis direction).

[0054] Figure 8 This is a diagram illustrating an example of an integrated circuit layout. For example, Figure 8 The layout of cell 80 included in the integrated circuit is shown. For ease of explanation, Figure 8 Only the gate electrode, back-side contact, and back-side pattern are shown in the reference. Figure 8 The description in this document omits any descriptions identical to those given above with reference to the accompanying drawings.

[0055] Reference Figure 8 Cell 80 can be a multi-height cell and can be continuous in the first row R1 and the second row R2. As described above with reference to the accompanying drawings, a single-height cell can include a PFET active pattern and an NFET active pattern, and for this purpose, the PFET active pattern and the NFET active pattern can extend in the X-axis direction in a row extending along the X-axis direction. The back-side pattern of the first back-side wiring layer BM1 can extend below the active pattern. For example, as... Figure 8As shown, in the first row R1, the first back side pattern BM11 and the second back side pattern BM12 can extend in the X-axis direction, and in the second row R2, the third back side pattern BM13 and the fourth back side pattern BM14 can extend in the X-axis direction.

[0056] As mentioned above Figure 2C As described above, when the width of the active pattern (i.e., nanosheet) in the MBCFET 20c is extended, the channel width can be extended, and therefore the current drive capability of the transistor can be increased. For cells with high current drive capability, active patterns extending in different rows can be combined. For example, as... Figure 8 As shown, the NFET active pattern AP81 can extend in the first row R1, and the NFET active pattern AP83 can extend in the second row R2. The PFET active pattern AP82 can be formed by combining the PFET active patterns extending in the first row R1 and the PFET active patterns extending in the second row R2. Therefore, the PFET active pattern AP82 can have an extended width (i.e., a length in the Y-axis direction), and the cell 80 can include a PFET with high current drive capability.

[0057] In some implementations, the inspection region IR can overlap with an extended active pattern. For example, as... Figure 8 As shown, the inspection region IR can overlap with the PFET active pattern AP82 in the Z-axis direction, and the back-side pattern can be removed from the inspection region IR. In some embodiments, such as Figure 8 As shown, when the inspection area IR is between the second back-side pattern BM12 and the third back-side pattern BM13, the inspection area IR can be set without removing the pattern of the first back-side wiring layer BM1.

[0058] Figure 9A and Figure 9B This is a diagram illustrating an example of an integrated circuit layout. For example, Figure 9A The plan view of layout 90a and the cross-sectional view of layout 90a taken along line X5-X5' are shown. Figure 9B The plan view of layout 90b and the cross-sectional view of layout 90b taken along line X6-X6' are shown. For ease of explanation, Figure 9A and Figure 9B Only the first back-side routing layer BM1, the second back-side routing layer BM2, and the first back-side via layer BV1 between the first back-side routing layer BM1 and the second back-side routing layer BM2 are shown. Figure 9A and Figure 9B The description in this document omits any descriptions identical to those given above with reference to the accompanying drawings.

[0059] Reference Figure 9ALayout 90a may include first units C11 to fourth units C14 arranged in the same row. In some embodiments, the integrated circuit may include a back-side power delivery network. For example, as... Figure 9A As shown, in the first back-side wiring layer BM1, the first back-side pattern BM11 can extend in the X-axis direction to provide a positive power supply voltage, and the second back-side pattern BM12 can extend in the X-axis direction to provide a negative power supply voltage. Furthermore, in the second back-side wiring layer BM2, the third back-side pattern BM21 and the fourth back-side pattern BM22 can extend in the Y-axis direction to provide a positive power supply voltage, and the fifth back-side pattern BM23 and the sixth back-side pattern BM24 can extend in the Y-axis direction to provide a negative power supply voltage. In some embodiments, such as... Figure 9A As shown, the spacing P11 between the third back-side pattern BM21 providing a positive power supply voltage and the fifth back-side pattern BM23 providing a negative power supply voltage can be smaller than the spacing P12 between the third back-side pattern BM21 and the fourth back-side pattern BM22 providing a positive power supply voltage. Figure 9A As shown, the first back-side pattern BM11 can be connected to the third back-side pattern BM21 through the first back-side via BV11, and can be connected to the fourth back-side pattern BM22 through the second back-side via BV12.

[0060] As mentioned above Figure 6A , Figure 6B and Figure 7B As stated, when the back-side pattern of the first back-side routing layer BM1 is divided into inspection areas, it is possible that the back-side pattern of the first back-side routing layer BM1 is not connected to the back-side pattern of the second back-side routing layer BM2 through the vias of the first back-side via layer BV1. For example, as... Figure 9A As shown, the first back-side pattern BM11 can be divided into a first portion BM11_1 to a third portion BM11_3 by a first inspection region IR1 and a second inspection region IR2, and the second portion BM11_2 between the first inspection region IR1 and the second inspection region IR2 can be connected to the back-side pattern of the second back-side wiring layer BM2 without passing through the vias of the first back-side via layer BV1. Therefore, an increased IR voltage drop may occur in the path of power supply to the transistors included in the second cell C12 and / or the third cell C13.

[0061] Reference Figure 9B Layout 90b may include first cells C21 to fourth cells C24 arranged in the same row. In some embodiments, the integrated circuit may include a back-side power delivery network. For example, as... Figure 9BAs shown, in the first back-side wiring layer BM1, the first back-side pattern BM11 can extend in the X-axis direction to provide a positive power supply voltage, and the second back-side pattern BM12 can extend in the X-axis direction to provide a negative power supply voltage. Furthermore, in the second back-side wiring layer BM2, the third back-side pattern BM21 and the fourth back-side pattern BM22 can extend in the Y-axis direction to provide a positive power supply voltage, and the fifth back-side pattern BM23 and the sixth back-side pattern BM24 can extend in the Y-axis direction to provide a negative power supply voltage. In some embodiments, such as... Figure 9B As shown, the spacing P11 between the third back-side pattern BM21 providing a positive power supply voltage and the fifth back-side pattern BM23 providing a negative power supply voltage can be smaller than the spacing P12 between the third back-side pattern BM21 and the fourth back-side pattern BM22 providing a positive power supply voltage. Figure 9B As shown, the first back-side pattern BM11 can be connected to the third back-side pattern BM21 through the first back-side via BV11, and can be connected to the fourth back-side pattern BM22 through the second back-side via BV12.

[0062] and Figure 9A The layout is different from that of 90a. Figure 9B In layout 90b, the back-side pattern of the first back-side wiring layer BM1 can be connected to the back-side pattern of the second back-side wiring layer BM2 via vias in the first back-side via layer BV1. For example, as Figure 9B As shown, each of the first back-side pattern BM11 and the second back-side pattern BM12 can be divided into three parts by the first inspection region IR1 and the second inspection region IR2, and each of these parts can be connected to the back-side pattern of the second back-side wiring layer BM2 through a via in the first back-side via layer BV1. Therefore, the path for powering the transistors included in the first unit C21 to the fourth unit C24 can have a low IR voltage drop. See below for reference. Figure 12 Describe an example of setting up a check area to provide a low IR drop.

[0063] Figure 10 This is a flowchart illustrating an example of a method for manufacturing an integrated circuit (IC). Specifically, Figure 10 The flowchart illustrates an example of a method for manufacturing an integrated circuit (IC) that includes cells. Figure 10 As shown, the method for manufacturing an integrated circuit (IC) may include multiple operations (S10, S30, S50, S70 and S90).

[0064] The cell library (or standard cell library) D12 may include information about the cells, such as their function, characteristics, and layout. In some implementations, the cell library D12 can define different layouts for the same cell. For example, the cell library D12 can define a single cell layout. Figure 3 , Figure 4A , Figure 6A and Figure 6B The layout is as described above with reference to the attached diagram. Figure 3 , Figure 4A , Figure 6A and Figure 6B The layout can correspond to units that provide the same functionality and performance.

[0065] Design rule D14 may include requirements that the layout of integrated circuits (ICs) must follow. For example, design rule D14 may include requirements for the space between patterns in the same layer, the minimum width of patterns, the routing direction in wiring layers, etc. In some implementations, design rule D14 may define the minimum length of the inspection region, the minimum area of ​​the inspection region, etc.

[0066] In operation S10, a logic synthesis operation can be performed to generate netlist data D13 from RTL data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) can perform logic synthesis from RTL data D11 written in a hardware description language (HDL) (e.g., VHSIC Hardware Description Language (VHDL) and Verilog) by referencing cell library D12, thereby generating netlist data D13, which includes a bitstream or a netlist. Netlist data D13 may correspond to the inputs for placement and routing described below. Here, netlist data D13 may be referred to as input data.

[0067] In operation S30, cells can be arranged. For example, a semiconductor design tool (e.g., a P&R tool) can place cells used in netlist data D13 by referring to the cell library D12 and design rule D14. In some embodiments, the semiconductor design tool can place power gating cells and place the back-side pattern in the back-side wiring layer. See below for further details. Figure 11 Describe an example of operation S30.

[0068] In operation S50, the pins of the cells can be routed. For example, the semiconductor design tool can generate interconnects that electrically connect output pins to the input pins of the configured functional cells. Furthermore, the semiconductor design tool can generate interconnects connecting to nodes to which a positive or negative power supply voltage is applied to provide power to the functional cells. Interconnects may include via patterns in via layers and / or wiring layers. The semiconductor design tool can generate layout data D15 defining the configured cells and the generated interconnects. Layout data D15 may have a format such as GDSII and may include geometric information of the cells and interconnects. The semiconductor design tool can refer to design rule D14 when routing the pins of the cells. The semiconductor design tool may not place the backside pattern in the inspection area, thereby allowing OFI through the inspection area. Layout data D15 may correspond to the output of the arrangement and routing. In some implementations, operations S30 and S50 may be repeated. Operation S50 alone, or a set of operations S30 and S50, may be referred to as a method for designing integrated circuits.

[0069] In operation S70, mask fabrication operations can be performed. For example, optical proximity correction (OPC) can be applied to the layout data D15 to correct distortions such as refraction caused by the properties of light in photolithography. Patterns on the mask can be defined based on the data to which OPC is applied to form patterns arranged in multiple layers, and at least one mask (or photomask) can be fabricated to form the pattern for each layer. In some embodiments, the layout of the integrated circuit IC can be modified to a limited extent in operation S70, and this limited modification of the integrated circuit IC in operation S70 can be referred to as design polishing as a post-processing step to optimize the integrated circuit IC structure.

[0070] In operation S90, operations for manufacturing an integrated circuit (IC) can be performed. For example, an IC can be manufactured by patterning multiple layers using at least one mask manufactured in operation S70. Front-end processes (FEOL) may include operations such as planarizing and cleaning the wafer, forming trenches, forming wells, forming gate electrodes, and forming source and drain electrodes. Through FEOL, individual devices such as transistors, capacitors, resistors, etc., can be formed on the substrate. Furthermore, back-end processes (BEOL) may include operations such as siliconizing gate, source and drain regions, adding dielectrics, planarizing, forming vias, adding metal layers, forming vias, forming passivation layers, etc. Through BEOL, individual devices such as transistors, capacitors, resistors, etc., can be interconnected. In some embodiments, middle-end processes (MOL) may be performed between FEOL and BEOL, and contacts may be formed on individual devices. Subsequently, the IC can be packaged into a semiconductor package and used as a component in various applications.

[0071] Figure 11 This is a flowchart illustrating an example of a method for designing integrated circuits. For example, Figure 11 The flowchart shows Figure 10 Example of operation S30. See above for reference. Figure 10 As mentioned above, it can be found in Figure 11 The units are arranged in operation S30'. For example... Figure 11 As shown, operation S30' may include multiple operations (S31 to S33). Referring below... Figure 10 right Figure 11 Describe it.

[0072] Reference Figure 11 Input data can be obtained in operation S31. For example, a semiconductor design tool can obtain netlist data D13 as input data. (See above for reference.) Figure 10 The netlist data D13 can define the cells included in the integrated circuit.

[0073] In operation S32, cells can be placed. For example, a semiconductor design tool can place cells defined in netlist data D13 using the reference cell library D12 and design rule D14. Figure 11 As shown, operation S32 can include operations S32_2 and S32_4. In operation S32_2, a first layout of the first unit can be set. Here, the first layout can refer to a layout that does not include the inspection area, such as... Figure 3 As shown. The semiconductor design tool can select the cell to be set from the netlist data D13, identify the first layout corresponding to the selected cell from the cell library D12, and set the identified first layout. In operation S32_4, the first layout can be replaced with a second layout. Here, the second layout can refer to a layout that includes the inspection area, such as... Figure 4A , Figure 6A and Figure 6B As shown. Therefore, the inspection area for OFI can be generated by replacing the first layout with a second layout that includes the inspection area.

[0074] In operation S33, output data can be generated. For example, the output data can define the arranged cells. The output data can be in... Figure 10 The operation is provided in S50.

[0075] Figure 12 This is a flowchart illustrating an example of a method for designing integrated circuits. For example, Figure 12 The flowchart shows Figure 11 Example of operation S32. See above for reference. Figure 11 As mentioned above, it can be found in Figure 12 The cells are arranged in operation S32'. For example... Figure 12As shown, operation S32' can include multiple operations S32_1 and S32_3.

[0076] In operation S32_1, a power delivery network can be configured. In some implementations, the semiconductor design tool can configure the back-side power delivery network. Therefore, as described above... Figure 9A and Figure 9B The back-side pattern extending in the Y-axis direction can be set in the second back-side wiring layer BM2.

[0077] In operation S32_3, the first unit can be identified. (See above for reference.) Figure 11 The first cell may refer to a cell that is replaced by a second layout after a first layout is established. In some embodiments, the semiconductor design tool may identify the first cell based on the back-side pattern of the second back-side wiring layer established in operation S32_1. For example, the semiconductor design tool may identify a first cell that vertically overlaps with at least one of the back-side patterns of the second back-side wiring layer established in operation S32_1. Referring to the above... Figure 9A The cells that do not vertically overlap with the back-side pattern of the second back-side wiring layer (e.g., Figure 9A If the C12 and C13 areas are included in the inspection area, an increased IR voltage drop may occur. Therefore, as mentioned above... Figure 9B The semiconductor design tool can identify cells that vertically overlap with the back-side pattern of the second back-side wiring layer (e.g., Figure 9B (C21 and C24), and replace the first layout of the identified cells with the second layout. Therefore, an increase in IR voltage drop can be prevented.

[0078] Figure 13 This is a block diagram illustrating an example of a System-on-Chip (SoC) 130. SoC 130 is a semiconductor device that may include integrated circuits according to an embodiment. SoC 130 is a device that implements complex blocks (e.g., intellectual property (IP) performing various functions) on a single chip. SoC 130 can be designed using methods for designing integrated circuits according to an embodiment, and therefore, SoC 130 can provide design performance and functionality with high reliability. (Refer to...) Figure 13 The SoC 130 may include a modem 132, a display controller 133, a memory 134, an external memory controller 135, a central processing unit (CPU) 136, a transaction unit 137, a PMIC 138, and a graphics processing unit (GPU) 139, and the various functional blocks of the SoC 130 may communicate with each other via a system bus 131.

[0079] The CPU 136, capable of controlling the operation of SoC 130 at the highest level, can also control the operation of other functional blocks 132 to 139. The modem 132 can demodulate signals received from outside the SoC 130, or modulate signals generated internally by the SoC 130 and send them externally. The external memory controller 135 can control the sending and receiving of data with external storage devices connected to the SoC 130. For example, under the control of the external memory controller 135, programs and / or data stored in external storage devices can be provided to the CPU 136 or GPU 139. The GPU 139 can execute program instructions related to graphics processing. The GPU 139 can receive graphics data through the external memory controller 135 and can send the graphics data processed by the GPU 139 to the outside of the SoC 130 through the external memory controller 135. The transaction unit 137 can monitor data transactions for each functional block, and the PMIC 138 can control the power supplied to each functional block under the control of the transaction unit 137. The display controller 133 can control an external display (or display device) of the SoC 130 to send data generated within the SoC 130 to the display. The memory 134 may include non-volatile memory, such as electrically erasable programmable read-only memory (EEPROM), flash memory, etc., or may include volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0080] Figure 14 This is a block diagram illustrating an example of a computing system 140 including a memory with a stored program. According to the method of designing integrated circuits according to embodiments, at least some of the operations in the above flowchart can be performed in the computing system (or computer) 140.

[0081] The computing system 140 can be a fixed computing system, such as a desktop computer, workstation, or server, or a portable computing system, such as a laptop computer. Figure 14 As shown, the computing system 140 may include a processor 141, an input / output (I / O) device 142, a network interface 143, a random access memory (RAM) 144, a read-only memory (ROM) 145, and a storage device 146. The processor 141, I / O device 142, network interface 143, RAM 144, ROM 145, and storage device 146 may be connected to a bus 147 and communicate with each other via the bus 147.

[0082] Processor 141 may be referred to as a processing unit and may include at least one core capable of executing any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit Extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.), such as a microprocessor, application processor (AP), digital signal processor (DSP), or GPU. For example, processor 141 may access memory, i.e., RAM 144 or ROM 145, via bus 147 and execute instructions stored in RAM 144 or ROM 145.

[0083] RAM 144 may store a program PGM or at least a portion thereof for a method of designing an integrated circuit according to an embodiment, and the program PGM may cause processor 141 to perform at least some operations included in the method of designing an integrated circuit, such as... Figure 11 The method. That is, the program PGM may include multiple instructions executable by the processor 141, and the instructions included in the program PGM can cause the processor 141 to perform at least some of the operations included in the flowchart above.

[0084] Even if the power supply to the computing system 140 is cut off, the storage device 146 will not lose the stored data. For example, the storage device 146 may include a non-volatile storage device, or may include a storage medium such as magnetic tape, optical disc, or magnetic disk. Furthermore, the storage device 146 can be removed from the computing system 140. The storage device 146 may store a program PGM according to an embodiment, and the program PGM or at least a portion thereof may be loaded from the storage device 146 into the RAM 144 before the processor 141 executes the program PGM. Alternatively, the storage device 146 may store a file written in a programming language, and a program PGM or at least a portion thereof generated from that file by a compiler, etc., may be loaded into the RAM 144. Furthermore, as... Figure 14 As shown, storage device 146 can store database DB, and database DB can include information required for designing integrated circuits, such as information about design blocks, Figure 10 The unit library D12 and / or design rule D14.

[0085] Storage device 146 can store data to be processed by processor 141 or data already processed by processor 141. That is, processor 141 can generate data by processing data stored in storage device 146 according to program PGM, and can also store the generated data in storage device 146. For example, storage device 146 can store... Figure 10 The RTL data D11, netlist data D13, and / or layout data D15.

[0086] I / O device 142 may include input devices such as a keyboard and pointers, and output devices such as a display and a printer. For example, a user can trigger processor 141 to execute program PGM through I / O device 142 to input... Figure 10 The RTL data D11 and / or netlist data D13, and checked. Figure 10 The layout data is D15.

[0087] Network interface 143 can provide access to networks outside computing system 140. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other form of link.

[0088] Although this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of the claims or any invention, but rather as descriptions of features that may be specific to particular embodiments of the invention. Some features described in this specification within the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from the combination in some cases, and combinations may be for sub-combinations or variations thereof.

[0089] Although this disclosure has been shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit comprising a plurality of cells located in a plurality of rows extending in a first horizontal direction, in, The plurality of units includes a first unit disposed in the first row. The first unit includes: The first active pattern extends in the first horizontal direction, and A first back-side pattern overlaps with the first active pattern in the vertical direction, and the first back-side pattern extends in the first horizontal direction and is located in a first back-side wiring layer below the first active pattern. The first backside pattern is removed from the first inspection area, and the first inspection area overlaps with the first active pattern and extends in the second horizontal direction.

2. The integrated circuit according to claim 1, wherein, The first unit includes: The second active pattern extends in the first horizontal direction, and A second back-side pattern overlaps with the second active pattern in the vertical direction and extends in the first back-side wiring layer along the first horizontal direction, wherein the second back-side pattern is removed from the first inspection area and the first inspection area overlaps with the second active pattern.

3. The integrated circuit according to claim 1, wherein The first inspection area contacts the boundary of the first unit, and The first back-side pattern terminates at the first inspection area.

4. The integrated circuit according to claim 1, wherein, The first inspection area divides the first back-side pattern into a first part and a second part.

5. The integrated circuit according to claim 1, wherein, The plurality of units includes a second unit, and the first unit and the second unit have the same preceding process FEOL.

6. The integrated circuit according to claim 1, wherein, The width of the first back-side pattern changes according to the first inspection area.

7. The integrated circuit according to claim 1, wherein, The first unit includes: The first source / drain contact overlaps with the first active pattern in the vertical direction. The second source / drain contact overlaps with the first inspection area, and A first positive side pattern is electrically connected to the first source / drain contact and the second source / drain contact, and the first positive side pattern extends along the first horizontal direction in the first positive side wiring layer.

8. The integrated circuit according to claim 1, wherein The first unit includes a plurality of gate electrodes, the plurality of gate electrodes extending in the second horizontal direction at a first spacing, and The width of the first inspection area corresponds to the first spacing or a multiple of the first spacing.

9. The integrated circuit according to claim 1, wherein, The first back-side pattern is configured to apply a power supply voltage to the first cell.

10. An integrated circuit, comprising: Multiple active patterns extend in the first horizontal direction; as well as Multiple back-side patterns extend beneath the multiple active patterns. The plurality of back-side patterns include a first back-side pattern, which overlaps with a first active pattern among the plurality of active patterns in the vertical direction. The first back-side pattern extends along the first horizontal direction in the first back-side wiring layer. The first backside pattern is removed from the first inspection area that overlaps with the first active pattern and extends in the second horizontal direction.

11. The integrated circuit according to claim 10, wherein The plurality of back-side patterns includes a second back-side pattern, which overlaps with a second active pattern among the plurality of active patterns in the vertical direction. The second active pattern is adjacent to the first active pattern, and the second back-side pattern extends along the first horizontal direction in the first back-side wiring layer. The second backside pattern is removed from the first inspection area that overlaps with the second active pattern.

12. The integrated circuit according to claim 10, wherein, The first inspection area divides the first back-side pattern into a first part and a second part.

13. The integrated circuit according to claim 12, wherein The plurality of back-side patterns include a third back-side pattern and a fourth back-side pattern. The third back-side pattern and the fourth back-side pattern extend parallel to each other along the second horizontal direction in the second back-side wiring layer below the first back-side wiring layer. The first portion is connected to the third back-side pattern via a first back-side via layer between the first back-side wiring layer and the second back-side wiring layer. The second part is connected to the fourth back-side pattern through the second back-side via of the first back-side via layer.

14. The integrated circuit according to claim 10, wherein, The width of the first back-side pattern changes according to the first inspection area.

15. The integrated circuit according to claim 10, further comprising: Multiple gate electrodes extend in the second horizontal direction at a first spacing. The width of the first inspection area corresponds to the first spacing or a multiple of the first spacing.

16. The integrated circuit according to claim 10, wherein, The plurality of back-side patterns and the first inspection area are separated from each other.

17. The integrated circuit according to claim 10, wherein The plurality of back-side patterns include a third back-side pattern and a fourth back-side pattern. The third back-side pattern and the fourth back-side pattern overlap with the second active pattern among the plurality of active patterns. The third back-side pattern and the fourth back-side pattern extend parallel to each other in the first back-side wiring layer along the first horizontal direction, and The plurality of back-side patterns are separated from each other by the second inspection area, which is located between the third and fourth back-side patterns.

18. The integrated circuit according to claim 10, wherein, The first back-side pattern is configured to apply a power supply voltage to the device formed by the first active pattern.

19. A method for designing an integrated circuit, the method comprising: Obtain input data for multiple units included in a defined integrated circuit; The multiple units are placed based on the unit library; as well as Generate output data for the defined and placed multiple units. The cell library defines a first layout and a second layout for a first cell among the plurality of cells, and The placement of the plurality of units includes: Set the first layout; and Replace the first layout with the second layout. The first layout includes a first back-side pattern extending continuously from a first boundary of the first layout to a second boundary along a first horizontal direction in a first back-side wiring layer. The second layout includes a second back-side pattern corresponding to the first back-side pattern, and a portion of the first back-side pattern is removed from the first inspection area.

20. The method of claim 19, further comprising: A power transmission network is set up to supply power to the multiple units. The power transmission network includes a plurality of third back-side patterns extending along a second horizontal direction in a second back-side wiring layer below the first back-side wiring layer, and The placement of the plurality of units includes: identifying the first unit among the placed plurality of units based on the plurality of third back-side patterns.

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