Data prefetching processing method, multi-level cache processor architecture and computer equipment

Abstract

The invention provides a data prefetching processing method, a multi-level cache processor architecture and computer equipment, the method is applied to the multi-level cache processor architecture, the multi-level cache processor architecture comprises a first cache and a second cache, a counter is arranged in the second cache, and the counter is connected with the first cache. The counting module is used for counting the hit times of the data request sent by the first cache in the second cache; the method comprises the following steps: when a second cache executes a request backfill operation to evict a first data request, determining the number of hit times of first data corresponding to the first data request; when the number of hit times of the first data is smaller than a first threshold value, the second cache sends the address of the first data and the number of hit times of the first data to a prefetcher of the first cache, so that the prefetcher of the first cache sends a prefetching request for the first data to the second cache. According to the method, the influence on the subsequent reading efficiency of the first data due to the fact that the first data is evicted by the second cache can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a data prefetching processing method, a multi-level cache processor architecture, and a computer device. BACKGROUND

[0002] In a multi-level cache processor architecture, an upper-level cache pre-fetches data that is likely to be used to a lower-level cache by sending a pre-fetch request, so that the data can be directly hit from the lower-level cache when the data is actually needed.

[0003] However, the cache space in the processor is limited, and any data that is likely to be used cannot be pre-fetched to the lower-level cache for storage without limit. Therefore, the lower-level cache will evict the pre-fetch request and the corresponding pre-fetched data from the cache when the storage space is full or a cleaning period is reached. At this time, it is possible that the data pre-fetched to the lower-level cache is not used up before being evicted, affecting the subsequent reading efficiency of the data. SUMMARY

[0004] To solve the above technical problem, the present application provides a data prefetching processing method, a multi-level cache processor architecture, and a computer device, which can avoid affecting the subsequent reading efficiency of the first data due to the evicting of the second cache.

[0005] The first aspect of the present application provides a data prefetching processing method applied to a multi-level cache processor architecture, wherein the multi-level cache processor architecture includes a first cache and a second cache, the second cache is provided with a counter, and the counter is used to count the number of times that a data request sent by the first cache is hit in the second cache; the data request includes a data pre-fetch request. The method includes: When the second cache performs a request backfill operation to evict a first data request, the second cache determines the number of times that the first data corresponding to the first data request is hit. When the number of times that the first data is hit is less than a first threshold, the second cache sends the address of the first data and the number of times that the first data is hit to a pre-fetcher of the first cache, so that the pre-fetcher of the first cache sends a pre-fetch request for the first data to the second cache.

[0006] In some implementations, each data stored in the second cache corresponds to a counter that is set to count the number of times that the data is hit; the method further includes: When a data request sent by the first cache hits the first data, the second cache increments the count value of the counter corresponding to the first data by 1.

[0007] The second aspect of the present application provides another data prefetching processing method, applied to a multi-level cache processor architecture, the multi-level cache processor architecture comprising a first cache and a second cache, the second cache being provided with a counter, the counter being configured to count a number of times that a data request sent by the first cache hits in the second cache; the data request comprising a data prefetching request; The method comprises: The first cache receives an address of the first data and a number of times that the first data hits, which are sent by the second cache to a prefetcher of the first cache in a case where the second cache determines that a number of times that the first data corresponding to the first data request is accessed is less than a first threshold value when the second cache evicts the first data request by performing a request backfill operation. The first cache sends a prefetch request for prefetching the first data to the second cache according to the address of the first data and the number of times that the first data hits.

[0008] In some implementations, the first cache sends a prefetch request for prefetching the first data to the second cache according to the address of the first data and the number of times that the first data hits, comprising: The first cache generates a first prefetch request corresponding to the first data according to the address of the first data. In a case where a prefetch queue in the prefetcher of the first cache is empty, the prefetcher of the first cache adds the first prefetch request corresponding to the first data to the prefetch queue.

[0009] In some implementations, the first cache stores a number of times that data of each prefetching address hits; The first cache sends a prefetch request for prefetching the first data to the second cache according to the address of the first data and the number of times that the first data hits, further comprising: In a case where the prefetcher of the first cache simultaneously adds a first prefetch request corresponding to the first data and a second prefetch request corresponding to second data to the prefetch queue, the number of times that the first data and the second data hit is compared. If the number of times that the first data hits is not less than the number of times that the second data hits, the prefetcher of the first cache adds the first prefetch request corresponding to the first data to the prefetch queue. Or, If the number of times that the first data hits is less than the number of times that the second data hits, the prefetcher of the first cache adds the second prefetch request corresponding to the second data to the prefetch queue.

[0010] The third aspect of the present application provides a multi-level cache processor architecture, comprising a first cache and a second cache, wherein a counter is arranged in the second cache, and the counter is used to count the number of times that a data request sent by the first cache hits in the second cache; the data request comprises a data prefetch request; When the second cache evicts the first data request by performing a request backfill operation, the second cache determines the number of times that first data corresponding to the first data request hits; When the number of times that the first data hits is less than a first threshold, the second cache sends the address of the first data and the number of times that the first data hits to a prefetcher of the first cache; The first cache sends a prefetch request for prefetching the first data to the second cache according to the address of the first data and the number of times that the first data hits.

[0011] In some implementations, a counter corresponding to each data stored in the buffer storage area of the second cache is arranged to count the number of times that the data hits; When the data request sent by the first cache hits the first data, the second cache adds 1 to the count value of the counter corresponding to the first data.

[0012] In some implementations, the first cache generates a first prefetch request corresponding to the first data according to the address of the first data; When the prefetch queue in the prefetcher of the first cache is empty, the prefetcher of the first cache adds the first prefetch request corresponding to the first data to the prefetch queue; In some implementations, the first cache stores the number of times that data corresponding to each prefetch address hits; When the prefetcher of the first cache simultaneously adds the first prefetch request corresponding to the first data and a second prefetch request corresponding to second data to the prefetch queue, the number of times that the first data and the second data hit is compared; If the number of times that the first data hits is not less than the number of times that the second data hits, the prefetcher of the first cache adds the first prefetch request corresponding to the first data to the prefetch queue; Alternatively, If the number of times that the first data hits is less than the number of times that the second data hits, the prefetcher of the first cache adds the second prefetch request corresponding to the second data to the prefetch queue.

[0013] The fourth aspect of the present application provides a computer device comprising the multi-level cache processor architecture described above.

[0014] The data prefetching method proposed in this application sets a counter in the second cache of a multi-level cache processor architecture to count the number of times data requests sent by the first cache are hit in the second cache. When the second cache evicts the first data request during a request backfilling operation, it determines the number of times the first data corresponding to the first data request is hit. When the number of hits for the first data is less than a first threshold, the second cache sends the address of the first data and the number of hits to the prefetcher of the first cache, so that the prefetcher of the first cache sends a prefetch request for the first data to the second cache. In the above scheme, when the number of hits for the first data corresponding to the first data request is less than the first threshold, it indicates that the first data may be used again later. At this time, the second cache sends the address of the first data and the number of hits to the prefetcher of the first cache, so that the prefetcher of the first cache sends a prefetch request for the first data to the second cache. This allows the first data to be prefetched into the second cache again, thereby avoiding the impact on the subsequent reading efficiency of the first data due to the second cache evicting the first data. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a multi-level cache processor architecture provided in an embodiment of this application.

[0017] Figure 2 This is a flowchart illustrating a data prefetching processing method provided in an embodiment of this application. Detailed Implementation

[0018] The technical solution of this application embodiment is applicable to application scenarios of cache data prefetching in a multi-level cache processor architecture. The technical solution of this application embodiment can avoid the impact on the reading efficiency of prefetched data due to the prefetched data being evicted from the buffer.

[0019] In the hierarchical structure of a computer storage system, cache is a high-speed, small-capacity memory located between the central processing unit (CPU) and main memory. It consists of static RAM chips, which have a relatively small capacity but are faster than main memory, approaching the speed of the CPU.

[0020] The working principle of caching is as follows: When the CPU needs to read data, it first searches for it in the CPU cache. If found, it reads the data immediately and sends it to the CPU for processing. If not found, it reads the data from the relatively slower main memory and sends it to the CPU for processing. Simultaneously, the data block containing this data is loaded into the cache. This allows subsequent reads of the entire data block to be performed from the cache, avoiding further access to main memory. This reading mechanism increases the CPU's cache hit rate, meaning that the data the CPU needs to read next is more likely to be in the CPU cache, with only a small amount of data needing to be read from main memory. This significantly saves the time the CPU spends directly reading from main memory and essentially eliminates waiting time when reading data.

[0021] The data in the cache is only a copy of a portion of the data in memory. Therefore, when the CPU searches for data in the cache, it may encounter situations where it cannot find the data (because some data has not been copied from memory to the cache). In this case, the CPU will still read the data from memory, thus slowing down the CPU's data read speed. However, the CPU will copy the read data into the cache for future use. Therefore, the more frequently data is accessed, the longer it remains in the cache. Furthermore, the most frequently accessed data changes over time, so the data in the cache needs to be frequently updated according to a specific algorithm to ensure that the data in the cache always represents the most frequently accessed data.

[0022] The technical solution of this application embodiment is applicable to a multi-level cache processor architecture, which includes multiple levels of cache, such as two-level cache, three-level cache, four-level cache, or any number of other cache levels.

[0023] In the multi-level cache described above, based on their distance from the processor core, the caches can be defined as Level 1 cache, Level 2 cache, Level 3 cache, and so on. The earlier the cache level, the closer it is to the processor core, and the faster the processor core can read data from it. Conversely, the later the cache level, the farther it is from the processor core, and the slower the processor core can read data from it. For example, the processor core can read data from the Level 1 cache faster than from the Level 2 cache, and from the Level 2 cache faster than from the Level 3 cache.

[0024] Generally, the earlier a cache is in the cache hierarchy, the more frequently the stored data is accessed by the processor core; conversely, the later a cache is in the cache hierarchy, the less frequently the stored data is accessed by the processor core. Furthermore, caches at earlier tiers typically have smaller storage spaces, while caches at later tiers generally have larger storage spaces.

[0025] Figure 1This is a schematic diagram of a multi-level cache processor architecture provided in an embodiment of this application. In this multi-level cache processor architecture, three levels of cache are exemplarily shown, namely the first level cache L1, the second level cache L2, and the third level cache L3.

[0026] The first-level cache (L1) is further divided into instruction cache (L1I) and data cache (L1D). Instruction cache (L1I) is used to cache instructions, and data cache (L1D) is used to cache data.

[0027] The first-level cache L1 mentioned above, which includes instruction cache L1I and data cache L1D, shares the second-level cache L2.

[0028] See Figure 1 As shown, this multi-level cache processor architecture includes multiple processor cores. Each processor core is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. Multiple processor cores share a single Level 3 cache L3.

[0029] See also Figure 1 For multiple processor cores, different regions can be defined. Each processor core in each region is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. All processor cores in this region share a single Level 3 cache L3. Processor cores in multiple regions share the system main memory through an on-chip network.

[0030] In the processor architecture described above, when a LOAD instruction misses the required data in L1D, L1D sends a read request to L2 to read the data. If the data is still not found in L2, a read request is sent to L3 to read the data. If the data is still not found in L3, it needs to be read from main memory. During this process, if the required data is found in a certain level of cache, it is sequentially returned to the upper-level caches until it is returned to the processor. For example, if the data is read from L2, the cache line containing that data is returned to L1, where it is stored, and L1 then returns the cache line to the processor.

[0031] Data prefetching refers to storing the data needed by the processor core in the cache in advance, so that when the processor core actually needs to read this data, it can directly retrieve it from the cache, instead of having to read the data from main memory when needed. Data prefetching can also reduce the probability of data requests missing in the cache.

[0032] For example in Figure 1In the multi-level cache processor architecture shown, L1D sends a prefetch request to L2C, causing L2C to prefetch and load the target data into L2C. When the processor core actually needs the target data, L1D sends a data request to L2C, and the data can be obtained from L2C.

[0033] However, the storage space of each cache level in the processor is limited, and it is not possible to prefetch and store all potentially needed data indefinitely. Therefore, when the cache is full or the cleanup cycle is reached, prefetch requests and their corresponding prefetched data will be evicted from the cache. At this point, it is possible that data prefetched into the cache may be evicted before it has been fully used, affecting the efficiency of subsequent reads of that data.

[0034] For example, in Figure 1 In the multi-level cache processor architecture shown, L1D sends a prefetch request to L2C, causing L2C to prefetch and load the target data. Subsequently, other data will be stored in L2C during system operation. Due to the limited space of L2C, the target data prefetched to L2C cannot be stored indefinitely. When L2C space is full and other data needs to be stored, L2C will evict some historical data and requests to make room for new data or requests. This may involve evicting the prefetched target data. If the use of this target data is not yet complete, meaning the processor will use it again later, it will cause a miss in L2C when the processor subsequently reads this target data, requiring the processor to read the corresponding target data from L3 or main memory, thus reducing the efficiency of reading this target data.

[0035] To address the aforementioned technical problems, this application provides a novel data prefetching scheme. This scheme can count the number of times prefetched data is hit in the cache. When prefetched data is evicted from the cache, if the number of hits for the prefetched data is less than a first threshold, the upper-level cache is instructed to resend the prefetch request for the prefetched data. Thus, after the prefetched data is evicted, it is re-prefetched into the cache so that subsequent requests for the prefetched data can be directly hit in the cache, thereby improving the efficiency of reading prefetched data.

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] This application first provides a data prefetching processing method applied to a multi-level cache processor architecture, which includes a first cache and a second cache. The first cache is located at the upper level of the second cache; that is, the first cache is the upper-level cache of the second cache, and similarly, the second cache is the lower-level cache of the first cache. Furthermore, the first cache and the second cache are different caches at adjacent levels, wherein the storage space of the second cache is larger than the storage space of the first cache.

[0038] The aforementioned multi-level cache processor architecture can be as follows: Figure 1 The multi-level cache processor architecture shown can be configured such that the first cache and the second cache are respectively... Figure 1 The first level cache (L1, specifically L1C or L1D) and the second level cache (L2) can be used, or the first and second caches can be respectively... Figure 1 The second-level cache (L2) and the third-level cache (L3) are used in the system.

[0039] In this embodiment, the second cache in the multi-level cache processor architecture is equipped with a counter to count the number of times a data request sent from the first cache to the second cache is hit in the second cache. A data request being hit in the second cache means that the requested data is found in the second cache. This data request includes data prefetch requests and may also include other data requests.

[0040] In some embodiments, a counter is set in the second cache, specifically, a counter is set for each piece of data in the second cache, used to count the number of times that piece of data is hit. Based on the above counter settings, when a data request sent from the first cache to the second cache hits any piece of data in the second cache, the count value of the counter corresponding to that piece of data is incremented by 1.

[0041] Based on the multi-level cache processor architecture described above, this application provides a data prefetching processing method, which can be implemented by the interaction of the first cache and the second cache in the multi-level cache processor architecture described above.

[0042] See Figure 2 As shown, the data prefetching processing method provided in this application embodiment includes: S101. When the data request sent by the first cache hits the first data, the second cache increments the counter value corresponding to the first data by 1.

[0043] The aforementioned first data refers to the data loaded into the second cache in response to the first data request. This first data request is used to retrieve the first data. For example, when the second cache receives the first data request from the first cache, if the first data is not present locally in the second cache, the second cache stores the first data request in a buffer. Simultaneously, it retrieves the first data from a lower-level cache or main memory, populates the second cache's buffer with the first data, and returns the first data to the first cache. After this process, the second cache contains both the first data and the first data request.

[0044] Subsequently, during system operation, if a data request sent from the first cache to the second cache is used to request the reading of the first data, the data request will be able to hit the first data in the second cache. At this time, the second cache will increment the counter value corresponding to the first data by 1.

[0045] Through the above processing, the second cache can accurately count the number of times the data requests sent by the first cache hit the first data.

[0046] S102. When the second cache performs a request backfilling operation and evicts the first data request, it determines the number of times the first data corresponding to the first data request is hit.

[0047] Specifically, when the second cache reads new data from the lower-level cache or main memory and fills the data back into the buffer storage area by performing a request backfill operation, if there is no free storage space in the buffer storage area, the existing data requests in the buffer storage area need to be evicted before the request backfill operation is performed.

[0048] When the second cache evicts the first data request, it first determines the number of times the first data corresponding to the first data request is hit. That is, by reading the count value of the counter of the first data corresponding to the first data request, the number of times the first data corresponding to the first data request is hit can be determined.

[0049] S103. When the number of times the first data is hit is less than the first threshold, the second cache sends the address of the first data and the number of times the first data is hit to the prefetcher of the first cache.

[0050] Typically, once cached data has been accessed a certain number of times, it will no longer be accessed. Therefore, the cache needs to periodically clean up historical data to keep the data in the cache as frequently accessed as possible, thereby improving the space utilization of the cache.

[0051] Conversely, if cached data is accessed less frequently, it can be assumed that the data is likely to be accessed again later.

[0052] Based on the above pattern, this application embodiment sets a first threshold in the second cache to determine whether the data in the second cache will continue to be accessed.

[0053] Specifically, when the second cache needs to evict the first data request during the backfill operation, it first determines the number of times the first data corresponding to the first data request is hit, that is, the number of times the first data is accessed.

[0054] If the number of times the first data is hit is not less than the first threshold, it can be considered that the first data has been accessed multiple times, and the probability of the first data being accessed again in subsequent runs is small. If the number of times the first data is hit is less than the first threshold, it can be considered that the first data has been accessed less often, and the probability of the first data being accessed again in subsequent runs is relatively high.

[0055] Based on the above judgment, when the number of times the first data is hit is less than the first threshold, the second cache sends the address of the first data and the number of times the first data is hit to the prefetcher of the first cache.

[0056] S104, the first cache receives the address of the first data sent by the second cache and the number of times the first data is hit.

[0057] Correspondingly, when the second cache sends the address of the first data and the number of times the first data has been hit to the first cache, the prefetcher of the first cache can receive the address of the first data and the number of times the first data has been hit.

[0058] After receiving the address of the first data and the number of times the first data was hit, the first cache stores this information. Furthermore, during system operation, whenever the first cache receives the data address and the number of times the data was hit from the second cache, it stores the received information.

[0059] S105. The first cache sends a prefetch request to the second cache to prefetch the first data based on the address of the first data and the number of times the first data is hit.

[0060] In this embodiment, when the first cache receives the address of the first data sent by the second cache and the number of times the data was hit, the prefetcher of the first cache can generate a prefetch request to request the first data to be prefetched into the second cache based on the address of the first data and the number of times the first data was hit, and send the prefetch request to the second cache, so that the second cache, upon receiving the prefetch request, responds to the prefetch request and prefetches the first data into the second cache again.

[0061] Through the above processing, although the second cache evicts the first data request, the second cache prefetches the first data again because the first cache sends a prefetch request to the second cache. Therefore, the second cache still stores the first data. When the first cache sends another data request for the corresponding first data to the second cache, it can find the first data in the second cache.

[0062] As described above, the data prefetching method proposed in this application sets a counter in the second cache of a multi-level cache processor architecture to count the number of times data requests sent by the first cache are hit in the second cache. When the second cache evicts a first data request during a request backfilling operation, it determines the number of times the first data corresponding to the first data request is hit. When the number of hits for the first data is less than a first threshold, the second cache sends the address of the first data and the number of hits for the first data to the prefetcher of the first cache, so that the prefetcher of the first cache sends a prefetch request for the first data to the second cache. In the above scheme, when the number of hits for the first data corresponding to the first data request is less than the first threshold, it indicates that the first data may be used again later. At this time, the second cache sends the address of the first data and the number of hits for the first data to the prefetcher of the first cache, so that the prefetcher of the first cache sends a prefetch request for the first data to the second cache. This allows the first data to be prefetched into the second cache again, thereby avoiding the impact on the subsequent reading efficiency of the first data due to the second cache evicting the first data.

[0063] In another embodiment, it is also disclosed that the first cache sends a prefetch request to the second cache for prefetching the first data based on the address of the first data and the number of times the first data is hit, specifically including the steps shown in A1 and A2 below: A1. The first cache generates a first prefetch request corresponding to the first data based on the address of the first data.

[0064] Specifically, the prefetcher of the first cache generates a first prefetch request based on the address of the first data, requesting that the data at that address be prefetched into the second cache. This first prefetch request carries the storage address of the first data in main memory.

[0065] A2. If the prefetch queue in the prefetcher of the first cache is free, the prefetcher of the first cache will add the first prefetch request corresponding to the first data to the prefetch queue.

[0066] The prefetch queue in the prefetcher of the first cache is used to store the prefetch requests generated by the prefetcher of the first cache. The prefetch requests in the prefetch queue are sent out sequentially according to the order in which they enter the prefetch queue.

[0067] After the prefetcher in the first cache generates a first prefetch request for prefetching the first data, if there is a free storage location in the prefetch queue of the first cache, the first prefetch request can be added to the free storage location of the prefetch queue.

[0068] In another embodiment, it is disclosed that after the prefetcher of the first cache generates a first prefetch request for prefetching the first data, if there is no free storage space in the prefetch queue of the first cache prefetcher, the first cache may discard the first prefetch request.

[0069] In another embodiment, priorities can be set for different prefetch requests. For example, in this embodiment, the priority of the data expectation request generated based on the data address sent by the second cache and the number of times the data is hit is set to be higher than the priority of the prefetch request generated by the first cache based on other information. Based on the above priority setting, after the prefetcher of the first cache generates a first prefetch request for prefetching the first data, if there is no free storage space in the prefetch queue of the first cache prefetcher, the first cache prefetcher filters prefetch requests with a priority lower than that of the first prefetch request from the prefetch queue and removes the filtered prefetch requests from the prefetch queue. At this time, a free storage space is generated in the prefetch queue, and the first prefetch request can be stored in the free storage space of the prefetch queue.

[0070] In another embodiment, it is also disclosed that the first cache stores the number of times the data at each prefetch address is hit, wherein the number of times the data at each prefetch address is hit can be obtained by a counter in the second buffer.

[0071] In other words, during system operation, the first cache sends a prefetch request to the second cache to prefetch data from a specific address. The second cache counts the number of times the prefetched data is accessed and feeds the results back to the first cache. Correspondingly, the first cache can store the number of times data at each prefetch address is hit.

[0072] In addition to generating a first prefetch request for the first data based on the address of the first data sent from the second cache and the number of times the first data was hit, the prefetcher of the first cache also generates prefetch requests based on other prefetch algorithms.

[0073] Based on the above operations, the prefetcher in the first cache generates a first prefetch request corresponding to the first data based on the address of the first data and the number of times the first data is hit, and generates a second prefetch request to request the second data to be prefetched into the second cache. When the first prefetch request and the second prefetch request are added to the prefetch queue at the same time, the number of times the first data and the second data are hit is compared.

[0074] The number of times the first data is hit is sent from the second cache to the first cache, while the number of times the second data is hit is obtained by the first cache during operation by storing the number of times the data at each prefetch address is hit.

[0075] If the number of hits for the first data is not less than the number of hits for the second data, then the prefetcher of the first cache will add the first prefetch request corresponding to the first data to the prefetch queue.

[0076] or, If the number of hits for the first data is less than the number of hits for the second data, then the prefetcher of the first cache will add the second prefetch request corresponding to the second data to the prefetch queue.

[0077] That is, when the space of the prefetch queue of the first cache is limited, and there are multiple prefetch requests that need to be added to the prefetch queue, the first cache will add the prefetch requests corresponding to the data with more hits to the prefetch queue, while the prefetch requests corresponding to the data with fewer hits can be discarded.

[0078] In another embodiment, if the number of hits for the first data is the same as the number of hits for the second data, and the space of the prefetch queue of the first cache is limited and cannot simultaneously accommodate the first prefetch request corresponding to the first data and the second prefetch request corresponding to the second data, the first cache prioritizes adding the first prefetch request corresponding to the first data to the prefetch queue. Because the first data is data that has already been accessed and may be accessed again, adding the first prefetch request corresponding to the first data to the prefetch queue prioritizes sending the first prefetch request to the second cache, allowing the second cache to prefetch the first data.

[0079] Based on the scheme of this embodiment, the first cache can send prefetch requests corresponding to data with a high probability of being accessed to the second cache first, so that the second cache can prefetch data with a high probability of being accessed in order to meet the data reading needs of the system in a timely manner.

[0080] Another embodiment of this application provides a multi-level cache processor architecture, which includes a first cache and a second cache. The first cache is located at the upper level of the second cache, that is, the first cache is the upper-level cache of the second cache, and similarly, the second cache is the lower-level cache of the first cache. Furthermore, the first cache and the second cache are different caches at adjacent levels, wherein the storage space of the second cache is larger than the storage space of the first cache.

[0081] The aforementioned multi-level cache processor architecture can be as follows: Figure 1 The multi-level cache processor architecture shown can be configured such that the first cache and the second cache are respectively... Figure 1The first level cache (L1, specifically L1C or L1D) and the second level cache (L2) can be used, or the first and second caches can be respectively... Figure 1 The second-level cache (L2) and the third-level cache (L3) are used in the system.

[0082] A counter is set in the second cache to count the number of times a data request sent from the first cache is hit in the second cache; the data request includes a data prefetch request.

[0083] In the multi-level cache processor architecture described above, when the second cache performs a request backfilling operation and evicts the first data request, it determines the number of times the first data corresponding to the first data request is hit. When the number of times the first data is hit is less than the first threshold, the second cache sends the address of the first data and the number of times the first data is hit to the prefetcher of the first cache. The first cache sends a prefetch request to the second cache to prefetch the first data based on the address of the first data and the number of times the first data has been hit.

[0084] In another embodiment, each piece of data stored in the buffer storage area of ​​the second cache is respectively set with a counter to count the number of times the data is hit; When a data request sent by the first cache hits the first data, the second cache increments the counter value corresponding to the first data by 1.

[0085] In another embodiment, the first cache generates a first prefetch request corresponding to the first data based on the address of the first data; If the prefetch queue in the prefetcher of the first cache is free, the prefetcher of the first cache will add the first prefetch request corresponding to the first data to the prefetch queue. In another embodiment, the first cache stores the number of times data at each prefetch address is hit; When the prefetcher of the first cache adds the first prefetch request corresponding to the first data and the second prefetch request corresponding to the second data to the prefetch queue at the same time, the number of hits of the first data and the second data are compared. If the number of times the first data is hit is not less than the number of times the second data is hit, then the prefetcher of the first cache will add the first prefetch request corresponding to the first data to the prefetch queue; or, If the number of hits for the first data is less than the number of hits for the second data, then the prefetcher of the first cache will add the second prefetch request corresponding to the second data to the prefetch queue.

[0086] The multi-level cache processor architecture provided in this embodiment belongs to the same application concept as the data prefetching processing method provided in the above embodiments of this application. It can execute the data prefetching processing method provided in any of the above embodiments of this application and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment can be found in the specific processing content of the data prefetching processing method provided in the above embodiments of this application, and will not be repeated here.

[0087] Furthermore, another embodiment of this application provides a computer device including the multi-level cache processor architecture described in the above embodiments. This multi-level cache processor architecture is configured to implement the data prefetching processing method described in any of the above embodiments. The specific structure and function of the multi-level cache processor architecture in this computer device, as well as the specific processing procedure for implementing the above data prefetching processing method and the corresponding beneficial effects, can be found in the descriptions of the above embodiments and will not be repeated here.

[0088] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0089] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0090] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0091] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0092] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0093] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0094] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0095] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0096] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0097] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0098] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data prefetching processing method, characterized in that, The method is applied to a multi-level cache processor architecture, which includes a first cache and a second cache. A counter is set in the second cache to count the number of times a data request sent by the first cache is hit in the second cache. The data request includes a data prefetch request; The method includes: When the second cache performs a request backfilling operation and evicts the first data request, it determines the number of times the first data corresponding to the first data request is hit; When the number of times the first data is hit is less than the first threshold, the second cache sends the address of the first data and the number of times the first data is hit to the prefetcher of the first cache, so that the prefetcher of the first cache sends a prefetch request for the first data to the second cache.

2. The method according to claim 1, characterized in that, Each piece of data stored in the second cache is assigned a counter to count the number of times the data is hit; the method further includes: When a data request sent by the first cache hits the first data, the second cache increments the counter value corresponding to the first data by 1.

3. A data prefetching processing method, characterized in that, The method is applied to a multi-level cache processor architecture, which includes a first cache and a second cache. A counter is set in the second cache to count the number of times a data request sent by the first cache is hit in the second cache. The data request includes a data prefetch request; The method includes: The first cache receives the address of the first data sent by the second cache and the number of times the first data has been hit; wherein, the address of the first data and the number of times the first data has been hit are sent to the prefetcher of the first cache when the second cache performs a request backfilling operation and evicts the first data request, and determines that the number of times the first data corresponding to the first data request has been accessed is less than a first threshold. The first cache sends a prefetch request to the second cache to prefetch the first data based on the address of the first data and the number of times the first data is hit.

4. The method according to claim 3, characterized in that, The first cache sends a prefetch request to the second cache for prefetching the first data based on the address of the first data and the number of times the first data has been hit, including: The first cache generates a first prefetch request corresponding to the first data based on the address of the first data; If the prefetch queue in the prefetcher of the first cache is free, the prefetcher of the first cache will add the first prefetch request corresponding to the first data to the prefetch queue.

5. The method according to claim 4, characterized in that, The first cache stores the number of times the data at each prefetch address is hit; The first cache sends a prefetch request to the second cache for prefetching the first data based on the address of the first data and the number of times the first data has been hit, and further includes: When the prefetcher of the first cache adds the first prefetch request corresponding to the first data and the second prefetch request corresponding to the second data to the prefetch queue at the same time, the number of hits of the first data and the second data are compared. If the number of times the first data is hit is not less than the number of times the second data is hit, then the prefetcher of the first cache will add the first prefetch request corresponding to the first data to the prefetch queue; or, If the number of hits for the first data is less than the number of hits for the second data, then the prefetcher of the first cache will add the second prefetch request corresponding to the second data to the prefetch queue.

6. A multi-level cache processor architecture, characterized in that, It includes a first cache and a second cache. The second cache is equipped with a counter, which is used to count the number of times a data request sent from the first cache is hit in the second cache. The data request includes a data prefetch request. When the second cache performs a request backfilling operation and evicts the first data request, it determines the number of times the first data corresponding to the first data request is hit; When the number of times the first data is hit is less than the first threshold, the second cache sends the address of the first data and the number of times the first data is hit to the prefetcher of the first cache. The first cache sends a prefetch request to the second cache to prefetch the first data based on the address of the first data and the number of times the first data is hit.

7. The multi-level cache processor architecture according to claim 6, characterized in that, Each piece of data stored in the buffer storage area of ​​the second cache is assigned a counter to count the number of times the data is hit; When a data request sent by the first cache hits the first data, the second cache increments the counter value corresponding to the first data by 1.

8. The multi-level cache processor architecture according to claim 6, characterized in that, The first cache generates a first prefetch request corresponding to the first data based on the address of the first data; If the prefetch queue in the prefetcher of the first cache is free, the prefetcher of the first cache will add the first prefetch request corresponding to the first data to the prefetch queue.

9. The multi-level cache processor architecture according to claim 8, characterized in that, The first cache stores the number of times the data at each prefetch address is hit; When the prefetcher of the first cache adds the first prefetch request corresponding to the first data and the second prefetch request corresponding to the second data to the prefetch queue at the same time, the number of hits of the first data and the second data are compared. If the number of times the first data is hit is not less than the number of times the second data is hit, then the prefetcher of the first cache will add the first prefetch request corresponding to the first data to the prefetch queue; or, If the number of hits for the first data is less than the number of hits for the second data, then the prefetcher of the first cache will add the second prefetch request corresponding to the second data to the prefetch queue.

10. A computer device, characterized in that, Including the multi-level cache processor architecture as described in any one of claims 6 to 9.

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