Data prefetching processing method and multi-level cache processor architecture

Abstract

The invention provides a data prefetching processing method and a multi-level cache processor architecture, the method is applied to the multi-level cache processor architecture, the multi-level cache processor architecture comprises a first cache and a second cache, and a counter is arranged in the second cache. The counter is used for counting the number of hit times of the data request sent by the first cache in the second cache; the data request comprises a data prefetching request; the method comprises the steps that when the number of continuous hit times of a data prefetching request sent by a first cache in a second cache is larger than a first threshold value, the second cache sends a first feedback signal to a prefetching device of the first cache, so that the prefetching device of the first cache reduces the prefetching request sending frequency. According to the method, waste of prefetching resources caused by repeated prefetching can be avoided, so that the cache performance is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data prefetching processing method and a multi-level cache processor architecture. Background Technology

[0002] In a multi-level cache processor architecture, the upper-level cache sends prefetch requests to the lower-level cache to prefetch potentially needed data so that the data can be directly retrieved from the lower-level cache when it is actually needed.

[0003] Caching typically employs multiple prefetch algorithms, each generating a prefetch request and sending it to the lower-level cache, enabling the lower-level cache to perform data prefetching operations. Different prefetch algorithms have varying prefetch accuracy, and the accuracy of prefetch requests sent by the upper-level cache may also change depending on the scenario. If the upper-level cache frequently generates and sends prefetch requests to the lower-level cache, duplicate prefetching may occur, wasting prefetch resources and impacting cache performance. Summary of the Invention

[0004] To address the aforementioned technical issues, this application provides a data prefetching processing method and a multi-level cache processor architecture, which can avoid the waste of prefetching resources caused by repeated prefetching, thereby improving cache performance.

[0005] The first aspect of this application provides a data prefetching processing method applied to a multi-level cache processor architecture, the multi-level cache processor architecture including a first cache and a second cache, the second cache being provided with a counter, the counter being used to count the number of times a data request sent by the first cache is hit in the second cache; the data request includes a data prefetching request. The method includes: When the number of consecutive hits of the data prefetch requests sent by the first cache in the second cache exceeds a first threshold, the second cache sends a first feedback signal to the prefetcher of the first cache to reduce the frequency of sending prefetch requests.

[0006] In some implementations, after the second cache sends the first feedback signal to the prefetcher of the first cache, the method further includes: If a data request or data prefetch request sent by the first cache misses in the second cache, the second cache resets the number of consecutive hits of the data prefetch request sent by the first cache to zero and sends a second feedback signal to the prefetcher of the first cache to increase the frequency of sending prefetch requests.

[0007] In some implementations, the method further includes: The second cache sends out-of-core bandwidth occupancy information and / or the number of times prefetched data in the second cache is hit to the prefetcher of the first cache, so that the prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm; The prefetched data includes data cached in the second cache based on prefetch requests sent by the prefetcher of the first cache.

[0008] The second aspect of this application provides another data prefetching processing method applied to a multi-level cache processor architecture, wherein the multi-level cache processor architecture includes a first cache and a second cache, wherein a counter is provided in the second cache, the counter being used to count the number of times a data request sent by the first cache is hit in the second cache; the data request includes a data prefetching request. The method includes: Upon receiving a first feedback signal from the second cache, the prefetcher of the first cache reduces the frequency of prefetch request transmission. The first feedback signal is sent by the second cache to the prefetcher of the first cache when the number of consecutive hits of the data prefetch requests sent by the first cache in the second cache exceeds a first threshold.

[0009] In some implementations, after the prefetcher of the first cache reduces the prefetch request sending frequency, the method further includes: Upon receiving a second feedback signal from the second cache, the prefetcher of the first cache increases the frequency of prefetch request transmission. The second feedback signal is sent by the second cache to the prefetcher of the first cache when a data request or data prefetch request sent by the first cache is not found in the second cache.

[0010] In some implementations, the method further includes: The prefetcher of the first cache receives out-of-core bandwidth usage information sent by the second cache and / or the number of times prefetched data in the second cache is hit, wherein the prefetched data includes data cached in the second cache based on prefetch requests sent by the prefetcher of the first cache; The prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm based on the off-core bandwidth occupancy information and / or the number of times the prefetched data in the second cache is hit.

[0011] In some implementations, the prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm based on the off-core bandwidth occupancy information, including: When the off-core bandwidth occupancy information indicates that the off-core bandwidth occupancy rate is higher than a set threshold, the prefetcher of the first cache will reduce the prefetch frequency of the prefetch algorithm. or, When the off-core bandwidth occupancy information indicates that the off-core bandwidth occupancy rate is not higher than a set threshold, the prefetcher of the first cache will increase the prefetch frequency of the prefetch algorithm.

[0012] In some implementations, the prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm based on the number of times the prefetched data in the second cache is hit, including: The prefetcher of the first cache determines the prefetch accuracy of each prefetch algorithm based on the number of times the prefetched data in the second cache is hit, and determines the priority of each prefetch algorithm based on the prefetch accuracy of each prefetch algorithm. The prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm according to the priority of each prefetch algorithm; wherein the prefetch frequency of the prefetch algorithm is proportional to the priority of the prefetch algorithm.

[0013] In some implementations, the method further includes: If the difference between the first statistical value and the second statistical value corresponding to the high-priority prefetch algorithm is greater than a set difference, the prefetcher of the first cache will reduce the prefetch frequency of the low-priority prefetch algorithm; the first statistical value represents the number of prefetch requests that are discarded after being generated by the high-priority algorithm, and the second statistical value represents the number of hit prefetch requests issued by the high-priority algorithm; wherein, when the prefetch request issued by the high-priority algorithm prefetches data in the second cache and is hit, the prefetch request is the hit prefetch request.

[0014] A third aspect of this application provides a multi-level cache processor architecture, which includes a first cache and a second cache. The second cache is equipped with a counter, which is used to count the number of times a data request sent by the first cache is hit in the second cache. The data request includes a data prefetch request. The multi-level cache processor architecture is configured to implement the data prefetching processing method described above.

[0015] In the data prefetching method provided in this application, the second cache counts the number of times the data prefetch requests sent by the first cache hit in the second cache. When the number of consecutive hits of the data prefetch requests sent by the first cache in the second cache exceeds a first threshold, the second cache sends a first feedback signal to the first cache. Upon receiving the first feedback signal from the second cache, the first cache reduces the frequency of sending prefetch requests. In the above scheme, the second cache monitors the hit status of the data prefetch requests sent by the first cache in real time, that is, it monitors the repetition rate of the data prefetch requests sent by the first cache. If the number of consecutive hits of the data prefetch requests sent by the first cache in the second cache exceeds the first threshold, it indicates that the data prefetch requests sent by the first cache are consecutively repeated. At this time, the second cache sends a first feedback signal to the first cache, causing the first cache to reduce the frequency of sending prefetch requests, thereby reducing the repetition rate of the data prefetch requests sent by the first cache. This avoids wasting prefetch resources and helps improve cache performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a multi-level cache processor architecture provided in an embodiment of this application.

[0018] Figure 2 This is a flowchart illustrating a data prefetching processing method provided in an embodiment of this application. Detailed Implementation

[0019] The technical solution of this application embodiment is applicable to application scenarios of cache data prefetching in multi-level cache processor architecture. The technical solution of this application embodiment can dynamically adjust the cache prefetching frequency, thereby avoiding waste of prefetching resources and avoiding the impact of frequent prefetching on cache performance.

[0020] In the hierarchical structure of a computer storage system, cache is a high-speed, small-capacity memory located between the central processing unit (CPU) and main memory. It consists of static RAM chips, which have a relatively small capacity but are faster than main memory, approaching the speed of the CPU.

[0021] The working principle of caching is as follows: When the CPU needs to read data, it first searches for it in the CPU cache. If found, it reads the data immediately and sends it to the CPU for processing. If not found, it reads the data from the relatively slower main memory and sends it to the CPU for processing. Simultaneously, the data block containing this data is loaded into the cache. This allows subsequent reads of the entire data block to be performed from the cache, avoiding further access to main memory. This reading mechanism increases the CPU's cache hit rate, meaning that the data the CPU needs to read next is more likely to be in the CPU cache, with only a small amount of data needing to be read from main memory. This significantly saves the time the CPU spends directly reading from main memory and essentially eliminates waiting time when reading data.

[0022] The data in the cache is only a copy of a portion of the data in memory. Therefore, when the CPU searches for data in the cache, it may encounter situations where it cannot find the data (because some data has not been copied from memory to the cache). In this case, the CPU will still read the data from memory, thus slowing down the CPU's data read speed. However, the CPU will copy the read data into the cache for future use. Therefore, the more frequently data is accessed, the longer it remains in the cache. Furthermore, the most frequently accessed data changes over time, so the data in the cache needs to be frequently updated according to a specific algorithm to ensure that the data in the cache always represents the most frequently accessed data.

[0023] The technical solution of this application embodiment is applicable to a multi-level cache processor architecture, which includes multiple levels of cache, such as two-level cache, three-level cache, four-level cache, or any number of other cache levels.

[0024] In the multi-level cache described above, based on their distance from the processor core, the caches can be defined as Level 1 cache, Level 2 cache, Level 3 cache, and so on. The earlier the cache level, the closer it is to the processor core, and the faster the processor core can read data from it. Conversely, the later the cache level, the farther it is from the processor core, and the slower the processor core can read data from it. For example, the processor core can read data from the Level 1 cache faster than from the Level 2 cache, and from the Level 2 cache faster than from the Level 3 cache.

[0025] Generally, the earlier a cache is in the cache hierarchy, the more frequently the stored data is accessed by the processor core; conversely, the later a cache is in the cache hierarchy, the less frequently the stored data is accessed by the processor core. Furthermore, caches at earlier tiers typically have smaller storage spaces, while caches at later tiers generally have larger storage spaces.

[0026] Figure 1This is a schematic diagram of a multi-level cache processor architecture provided in an embodiment of this application. In this multi-level cache processor architecture, three levels of cache are exemplarily shown, namely the first level cache L1, the second level cache L2, and the third level cache L3.

[0027] The first-level cache (L1) is further divided into instruction cache (L1I) and data cache (L1D). Instruction cache (L1I) is used to cache instructions, and data cache (L1D) is used to cache data.

[0028] The first-level cache L1 mentioned above, which includes instruction cache L1I and data cache L1D, shares the second-level cache L2.

[0029] See Figure 1 As shown, this multi-level cache processor architecture includes multiple processor cores. Each processor core is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. Multiple processor cores share a single Level 3 cache L3.

[0030] See also Figure 1 For multiple processor cores, different regions can be defined. Each processor core in each region is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. All processor cores in this region share a single Level 3 cache L3. Processor cores in multiple regions share the system main memory through an on-chip network.

[0031] In the processor architecture described above, when a LOAD instruction misses the required data in L1D, L1D sends a read request to L2 to read the data. If the data is still not found in L2, a read request is sent to L3 to read the data. If the data is still not found in L3, it needs to be read from main memory. During this process, if the required data is found in a certain level of cache, it is sequentially returned to the upper-level caches until it is returned to the processor. For example, if the data is read from L2, the cache line containing that data is returned to L1, where it is stored, and L1 then returns the cache line to the processor.

[0032] Data prefetching refers to storing the data needed by the processor core in the cache in advance, so that when the processor core actually needs to read this data, it can directly retrieve it from the cache, instead of having to read the data from main memory when needed. Data prefetching can also reduce the probability of data requests missing in the cache.

[0033] For example in Figure 1In the multi-level cache processor architecture shown, L1D sends a prefetch request to L2C, causing L2C to prefetch and load the target data into L2C. When the processor core actually needs the target data, L1D sends a data request to L2C, and the data can be obtained from L2C.

[0034] Multiple prefetching algorithms typically coexist in a cache. Each algorithm generates a data prefetch request and sends it to the lower-level cache, enabling the lower-level cache to perform the corresponding data prefetching operation. However, different prefetching algorithms have varying degrees of accuracy. Some algorithms accurately prefetch the data needed by the processor into the lower-level cache, while others do not. Furthermore, the prefetching frequency also differs, meaning different algorithms send data prefetch requests at different intervals. If the upper-level cache frequently sends data prefetch requests to the lower-level cache, the lower-level cache's storage space may quickly become full of prefetched data. Alternatively, if the data prefetched into the lower-level cache is not the data needed by the processor, and the upper-level cache still frequently sends data prefetch requests, it will waste prefetching resources. Conversely, if the data needed by the processor has already been prefetched into the lower-level cache, and the upper-level cache continues to send data prefetch requests to instruct the lower-level cache to prefetch this data, it will also result in wasted prefetching resources.

[0035] Therefore, in multi-level caching, if the data prefetching operation is not controlled and managed, it may lead to wasted prefetching resources or cache space, thereby affecting cache performance.

[0036] To address the aforementioned technical issues, this application provides a data prefetching processing scheme that enables effective management and control of cached data prefetching operations, thereby avoiding wasting prefetching resources and improving cache performance.

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] This application first provides a data prefetching processing method applied to a multi-level cache processor architecture, which includes a first cache and a second cache. The first cache is located at the upper level of the second cache; that is, the first cache is the upper-level cache of the second cache, and similarly, the second cache is the lower-level cache of the first cache. Furthermore, the first cache and the second cache are different caches at adjacent levels, wherein the storage space of the second cache is larger than the storage space of the first cache.

[0039] The aforementioned multi-level cache processor architecture can be as follows: Figure 1 The multi-level cache processor architecture shown can be configured such that the first cache and the second cache are respectively... Figure 1 The first level cache (L1, specifically L1C or L1D) and the second level cache (L2) can be used, or the first and second caches can be respectively... Figure 1 The second-level cache (L2) and the third-level cache (L3) are used in the system.

[0040] In this embodiment, the second cache in the multi-level cache processor architecture is equipped with a counter to count the number of times a data request sent from the first cache to the second cache is hit in the second cache. A data request being hit in the second cache means that the requested data is found in the second cache. This data request includes data prefetch requests and may also include other data requests.

[0041] Based on the above counter settings, when a data prefetch request sent from the first cache to the second cache hits the target data requested for prefetching in the second cache, that is, when the data requested for prefetching by the data prefetch request sent from the first cache already exists in the second cache, the counter value is incremented by 1. When any data prefetch request sent from the first cache misses in the second cache, the counter value is reset to zero.

[0042] In some embodiments, data prefetch requests issued by the cache are divided into data prefetch requests based on load instructions and data prefetch requests based on store instructions. Data prefetch requests issued by the cache prefetcher based on load instructions carry a load flag to indicate that they are data prefetch requests issued based on load instructions; data prefetch requests issued by the cache prefetcher based on store instructions carry a store flag to indicate that they are data prefetch requests issued based on store instructions.

[0043] Correspondingly, counters can be set in the cache for data prefetch requests generated based on load instructions and data prefetch requests generated based on store instructions, respectively, to count the number of times data prefetch requests generated based on load instructions are hit in the cache and the number of times data prefetch requests generated based on store instructions are hit in the cache.

[0044] When a data prefetch request generated by a load instruction is hit in the cache, the corresponding counter is incremented by 1; when any data prefetch request generated by a load instruction is not hit in the cache, the corresponding counter is reset to zero.

[0045] Similarly, when a data prefetch request generated based on a store instruction is hit in the cache, the corresponding counter is incremented by 1, and when any data prefetch request generated based on a store instruction is not hit in the cache, the corresponding counter is reset to zero.

[0046] Based on the multi-level cache processor architecture described above, this application provides a data prefetching processing method, which can be implemented by the interaction of the first cache and the second cache in the multi-level cache processor architecture described above.

[0047] See Figure 2 As shown, the data prefetching processing method provided in this application embodiment includes: S101. When the number of consecutive hits of the data prefetch request sent from the first cache in the second cache exceeds the first threshold, the second cache sends a first feedback signal to the prefetcher of the first cache.

[0048] Specifically, based on the aforementioned counter in the second cache, when a data prefetch request sent by the first cache hits the target data in the second cache, the counter value is incremented by 1, and when any data prefetch request sent by the first cache misses in the second cache, the counter value is cleared to zero.

[0049] Therefore, by reading the count value of the aforementioned counter, the second cache can determine the number of consecutive hits in the second cache of the data prefetch requests sent by the first cache.

[0050] If the number of consecutive hits of data prefetch requests sent by the first cache in the second cache exceeds a first threshold, it means that before the current time, at least a number of consecutive data prefetch requests sent by the first cache that are not less than the first threshold have all hit in the second cache. In this case, it can be concluded that before the current time, at least a number of data prefetch requests sent by the first cache that are not less than the first threshold were all duplicate data prefetch requests. If the first cache continues to send data prefetch requests, it may also send duplicate data prefetch requests, thus wasting prefetch resources. In order to avoid wasting prefetch resources, the second cache sends a first feedback signal to the first cache, which is used to instruct the first cache to reduce the frequency of sending prefetch requests.

[0051] In some embodiments, counters can be set in the second cache for data prefetch requests generated based on load instructions and data prefetch requests generated based on store instructions, respectively, to count the number of times data prefetch requests generated based on load instructions from the first cache are hit in the second cache, and to count the number of times data prefetch requests generated based on store instructions from the first cache are hit in the second cache.

[0052] When the number of times the data prefetch requests generated by the load instruction sent by the first cache hit the second cache is greater than the first threshold, the second cache sends a first feedback signal to the first cache indicating a reduction in the frequency of expected load requests. At this time, the first feedback signal is used to instruct the first cache to reduce the frequency of data prefetch requests generated by the load instruction.

[0053] When the number of times the data prefetch requests generated by the store instruction sent by the first cache hit the second cache is greater than the first threshold, the second cache sends a first feedback signal to the first cache indicating a reduction in the expected frequency of store requests. At this time, the first feedback signal is used to instruct the first cache to reduce the frequency of data prefetch requests generated by the store instruction.

[0054] S102. Upon receiving the first feedback signal from the second cache, the prefetcher of the first cache reduces the frequency of prefetch request transmission.

[0055] Specifically, there may be multiple prefetching algorithms in the first cache. When the first cache receives the first feedback signal sent by the second cache, it can reduce the frequency of data prefetching requests generated by each prefetching algorithm. Alternatively, the first cache can select a prefetching algorithm with lower priority or lower importance from multiple prefetching algorithms based on the priority and importance of each prefetching algorithm, and reduce the frequency of data prefetching requests generated by it or control it to stop generating data prefetching requests.

[0056] In some embodiments, when the first feedback signal sent by the second cache is used to instruct the first cache to reduce the sending frequency of data prefetch requests generated based on load instructions, the first cache will reduce the frequency of data prefetch requests generated by the prefetch algorithm that generates data prefetch requests based on load instructions.

[0057] When the first feedback signal sent by the second cache is used to instruct the first cache to reduce the frequency of sending data prefetch requests based on the store instruction, the first cache will reduce the frequency of data prefetch requests generated by the prefetch algorithm based on the store instruction.

[0058] As can be seen from the above processing, in the data prefetching method provided in this application embodiment, the second cache counts the number of times the data prefetch requests sent by the first cache hit in the second cache. When the number of consecutive hits of the data prefetch requests sent by the first cache in the second cache exceeds a first threshold, the second cache sends a first feedback signal to the first cache. Upon receiving the first feedback signal from the second cache, the first cache reduces the frequency of sending prefetch requests. In the above scheme, the second cache monitors the hit status of the data prefetch requests sent by the first cache in real time, that is, it monitors the repetition rate of the data prefetch requests sent by the first cache. If the number of consecutive hits of the data prefetch requests sent by the first cache in the second cache exceeds the first threshold, it can be said that the data prefetch requests sent by the first cache are continuously repeated. At this time, the second cache sends a first feedback signal to the first cache, causing the first cache to reduce the frequency of sending prefetch requests, thereby reducing the repetition rate of the data prefetch requests sent by the first cache, thus avoiding waste of prefetch resources and helping to improve cache performance.

[0059] See also Figure 2 As shown, another embodiment of the data prefetching processing method further includes: S103. If a data request or data prefetch request sent from the first cache is not hit in the second cache, the second cache clears the number of consecutive hits of the data prefetch request sent from the first cache in the second cache and sends a second feedback signal to the prefetcher of the first cache.

[0060] Specifically, if the second cache receives any data request or data prefetch request from the first cache but misses it, it means the second cache does not contain the corresponding data. In this case, the second cache needs to request the corresponding data from the next level of storage, i.e., send a data request to the next level of storage. At the same time, the second cache resets the number of consecutive hits of the data prefetch requests sent by the first cache to zero, i.e., resets the counter value to zero, and sends a second feedback signal to the first cache. This second feedback signal is used to instruct the first cache to increase the frequency of prefetch request sending.

[0061] In some embodiments, counters can be set in the second cache for data prefetch requests generated based on load instructions and data prefetch requests generated based on store instructions, respectively, to count the number of times data prefetch requests generated based on load instructions from the first cache are hit in the second cache, and to count the number of times data prefetch requests generated based on store instructions from the first cache are hit in the second cache.

[0062] When the number of times the data prefetch requests generated by the load instruction sent by the first cache hit the second cache is greater than the first threshold, the second cache sends a first feedback signal to the first cache indicating a reduction in the frequency of expected load requests. At this time, the first feedback signal is used to instruct the first cache to reduce the frequency of data prefetch requests generated by the load instruction.

[0063] After the second cache sends the first feedback signal to the first cache, which instructs the first cache to reduce the sending frequency of data prefetch requests generated based on load instructions, if any load request sent by the first cache or any data prefetch request generated based on load instructions is missed by the second cache, the second cache sends a second feedback signal to the first cache indicating that the sending frequency of data prefetch requests generated based on load instructions should be increased.

[0064] When the number of times the data prefetch requests generated by the store instruction sent by the first cache hit the second cache is greater than the first threshold, the second cache sends a first feedback signal to the first cache indicating a reduction in the expected frequency of store requests. At this time, the first feedback signal is used to instruct the first cache to reduce the frequency of data prefetch requests generated by the store instruction.

[0065] After the second cache sends the first feedback signal to the first cache, which instructs the first cache to reduce the sending frequency of data prefetch requests generated based on store instructions, if any store request sent by the first cache or any data prefetch request generated based on store instructions is missed by the second cache, the second cache sends a second feedback signal to the first cache indicating that the sending frequency of data prefetch requests generated based on store instructions should be increased.

[0066] S104. Upon receiving the second feedback signal from the second cache, the prefetcher of the first cache increases the frequency of prefetch request transmission.

[0067] Specifically, there may be multiple prefetching algorithms in the first cache. When the first cache receives the first feedback signal sent by the second cache, it can reduce the frequency of data prefetching requests generated by each prefetching algorithm. Alternatively, the first cache can select a prefetching algorithm with lower priority or lower importance from multiple prefetching algorithms based on the priority and importance of each prefetching algorithm, and reduce the frequency of data prefetching requests generated by it or control it to stop generating data prefetching requests.

[0068] When the first cache receives the second feedback signal sent by the second cache, the prefetch request sending frequency of the prefetch algorithm that has had its data prefetch request sending frequency reduced during step S102 can be increased. Alternatively, based on the current prefetch requirements, the frequency of data prefetch requests generated by the prefetch algorithm that can meet the current data requirements of the processor can be increased.

[0069] In some embodiments, when the first feedback signal sent by the second cache is used to instruct the first cache to reduce the sending frequency of data prefetch requests generated based on load instructions, the first cache will reduce the frequency of data prefetch requests generated by the prefetch algorithm that generates data prefetch requests based on load instructions.

[0070] When the first cache receives a second feedback signal from the second cache indicating an increase in the sending frequency of data prefetch requests based on the load instruction, the first cache will increase the frequency of data prefetch requests generated by the prefetch algorithm based on the load instruction.

[0071] When the first feedback signal sent by the second cache is used to instruct the first cache to reduce the frequency of sending data prefetch requests based on the store instruction, the first cache will reduce the frequency of data prefetch requests generated by the prefetch algorithm based on the store instruction.

[0072] When the first cache receives a second feedback signal from the second cache indicating an increase in the frequency of sending data prefetch requests based on store instructions, the first cache will increase the frequency of data prefetch requests generated by the prefetch algorithm based on store instructions.

[0073] In this embodiment, when the second cache detects that any data request or data prefetch request sent by the first cache is not hit in the second cache, the second cache sends a second feedback signal to the first cache, causing the first cache to increase the frequency of sending data prefetch requests. At this time, more data will be prefetched into the second cache, which can increase the probability of the data request sent by the first cache hitting the second cache, thereby improving the data reading efficiency of the processor.

[0074] In another embodiment, the second cache also sends out-of-core bandwidth occupancy information and / or the number of times prefetched data in the second cache is hit to the prefetcher of the first cache.

[0075] The aforementioned external bandwidth usage information includes bandwidth usage for cache access to lower-level storage, and may also include interconnect usage, such as routing between nodes and whether channels are congested due to resources. For example, in Figure 1In the multi-level cache processor architecture shown, multiple processor cores share the L3 cache. Therefore, the off-core bandwidth usage information includes the bandwidth usage of each processor core accessing the L3 cache. During data prefetching operations between different levels of cache within each processor core, data may be prefetched from L3. Therefore, conflicts or congestion may occur when processor cores access L3. The off-core bandwidth usage information accurately reflects the bandwidth usage of each processor core accessing L3.

[0076] If the external bandwidth usage information indicates that the external bandwidth is busy, then data prefetching operations should be reduced to prevent excessive data prefetching requests from causing congestion on the external bandwidth. If the external bandwidth usage information indicates that the external bandwidth is idle, then the data prefetching frequency can be increased to prefetch more data.

[0077] In another embodiment, it is disclosed that when the prefetch mode of the first cache is conservative prefetch mode, the second cache does not send a prefetch request to cache data from main memory into the buffer in advance, thereby reducing the occupation of off-core bandwidth. When the prefetch mode of the first cache is aggressive prefetch mode, the second cache can send a prefetch request to cache data from main memory into the buffer in advance, thereby storing data from main memory into the buffer in advance and reducing the time spent accessing main memory when reading data.

[0078] The aforementioned prefetched data includes data cached in the second cache based on prefetch requests sent by the prefetcher of the first cache. When the first cache sends a data prefetch request to the second cache, the second cache performs the data prefetch operation corresponding to the data prefetch request, prefetching the target data into the second cache; this target data is then the prefetched data. In another embodiment, the aforementioned prefetched data also includes data prefetched into the second cache by prefetch requests generated by read requests of the second cache.

[0079] The number of times the prefetched data in the second cache is hit is the number of times the prefetched data is prefetched into the second cache in response to the data prefetch request sent by the first cache, and the number of times the prefetched data in the second cache is read by the first cache.

[0080] In the second cache, a counter can be set to count the number of times prefetched data in the second cache is hit by data requests sent from the first cache. In some embodiments, a counter can be set for each prefetching algorithm of the first cache to count the number of times data prefetched into the second cache is hit in response to expected data requests sent by that prefetching algorithm. Therefore, the second cache can determine the number of times prefetched data corresponding to each prefetching algorithm is hit by reading the count values ​​of the aforementioned counters.

[0081] The second cache sends the aforementioned out-of-core bandwidth usage information and / or the number of times the prefetched data in the second cache is hit to the first cache, so that the first cache can adjust the prefetch frequency of each prefetch algorithm based on this information.

[0082] Accordingly, after receiving the off-core bandwidth occupancy information sent by the second cache and / or the number of times the prefetched data in the second cache is hit, the prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm according to the off-core bandwidth occupancy information and / or the number of times the prefetched data in the second cache is hit.

[0083] For example, if the prefetcher of the first cache receives off-core bandwidth occupancy information from the second cache, and this information indicates that the off-core bandwidth occupancy rate is higher than a set threshold, it means that the off-core bandwidth is busy. In this case, the prefetcher of the first cache will lower the prefetch frequency of its prefetch algorithm, thus reducing the number of data prefetch requests generated. In some embodiments, if the prefetch frequency of the prefetch algorithm in the first cache is already relatively low when the prefetcher receives the off-core bandwidth occupancy information from the second cache, no adjustment is needed.

[0084] If the received off-core bandwidth occupancy information indicates that the off-core bandwidth occupancy rate is not higher than the aforementioned set threshold, it means that the off-core bandwidth is not busy at this time. In this case, the prefetcher of the first cache will increase the prefetch frequency of the prefetch algorithm, that is, control the prefetch algorithm to generate data prefetch requests at a higher frequency. This allows data prefetching operations to be performed in a timely manner when the off-core bandwidth is not busy, prefetching the data that the processor may need into the second cache in a timely manner, so that the processor can hit the required data in the second cache when it needs to read data. In some embodiments, if the prefetch frequency of the prefetch algorithm in the first cache is already relatively high when the off-core bandwidth occupancy information sent by the second cache is received by the first cache prefetcher, no adjustment is needed.

[0085] Based on the scheme in this embodiment, the first cache can dynamically adjust the prefetch frequency of each prefetch algorithm in combination with the off-core bandwidth usage, thereby improving data prefetch efficiency and cache prefetch performance.

[0086] If the prefetcher of the first cache receives the number of times the prefetched data in the second cache has been hit, it adjusts the prefetch frequency of each prefetch algorithm based on the number of times the prefetched data in the second cache has been hit.

[0087] The number of times prefetched data in the second cache is hit includes the number of times data prefetched into the second cache in response to data prefetch requests sent to the second cache by various prefetch algorithms in the first cache is hit. In other words, for each prefetch algorithm in the first cache, the second cache will count the number of times data prefetched into the second cache based on a prefetch request sent to the second cache by that algorithm is hit by data requests sent to the first cache.

[0088] The prefetcher of the first cache determines the prefetch accuracy of each prefetch algorithm based on the number of times data in the second cache is hit by the data prefetch requests sent to the second cache based on each prefetch algorithm in the first cache, and determines the priority of each prefetch algorithm based on the prefetch accuracy of each prefetch algorithm.

[0089] The more times the data in the second cache is hit by the data prefetching request sent from the prefetching algorithm in the first cache to the second cache, the higher the prefetching accuracy of the prefetching algorithm; conversely, the fewer times the data in the second cache is hit by the data prefetching request sent from the prefetching algorithm in the first cache to the second cache, the lower the prefetching accuracy of the prefetching algorithm.

[0090] According to the above rules, the prefetcher of the first cache can determine the prefetch accuracy of each prefetch algorithm, and further, based on the prefetch accuracy of each prefetch algorithm, set a priority for each prefetch algorithm. The higher the prefetch accuracy of a prefetch algorithm, the higher its priority; conversely, the lower the prefetch accuracy of a prefetch algorithm, the lower its priority.

[0091] After determining the priority of each prefetching algorithm, the prefetcher of the first cache adjusts the prefetching frequency of each prefetching algorithm according to its priority.

[0092] The prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm according to the relationship between the prefetch frequency and the priority of the prefetch algorithm. That is, the higher the priority of the prefetch algorithm, the higher the prefetch frequency adjusted by the prefetcher of the first cache; the lower the priority of the prefetch algorithm, the lower the prefetch frequency adjusted by the prefetcher of the first cache.

[0093] Based on the scheme of this embodiment, the prefetcher of the first cache can reasonably adjust the prefetch frequency of each prefetch algorithm according to the prefetch accuracy of each prefetch algorithm, thereby improving the data prefetch accuracy and improving the data prefetch performance of the cache.

[0094] In some embodiments, the prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm, which can be achieved through an arbitration algorithm. For example, the prefetcher of the first cache can allow each prefetch algorithm to generate data prefetch requests according to existing rules, but the prefetcher of the first cache arbitrates and controls the sending of data prefetch requests generated by each prefetch algorithm to the second cache. If the prefetch algorithm has a higher priority, the prefetcher of the first cache can arbitrate to send the data prefetch request generated by that prefetch algorithm to the second cache; if the prefetch algorithm has a lower priority, the prefetcher of the first cache can arbitrate not to send the data prefetch request generated by that prefetch algorithm to the second cache.

[0095] In another embodiment, the prefetcher of the first cache counts the number of data prefetch requests that are discarded after being generated by each prefetch algorithm, obtaining a first statistical value corresponding to each prefetch algorithm. Also, the prefetcher of the first cache counts the number of hit prefetch requests sent to the second cache by each prefetch algorithm, obtaining a second statistical value corresponding to each prefetch algorithm. Specifically, when a data prefetch request from a prefetch algorithm in the first cache prefetches data in the second cache and is then hit by a data request sent from the first cache, that data prefetch request becomes a hit prefetch request.

[0096] In some embodiments, the first statistical value corresponding to the prefetching algorithm in the first cache can be determined by the arbitration and control results of the data prefetch requests generated by each prefetching algorithm in the first cache's prefetcher. The second statistical value corresponding to the prefetching algorithm in the first cache can be determined by the number of times the prefetched data in the second cache sent from the second cache to the first cache is hit. For example, based on the number of times the prefetched data in the second cache is hit, it can be determined whether each prefetched data was hit; that is, it can be determined whether the data prefetched by the data prefetch request sent by the prefetching algorithm in the first cache was hit by the data request sent by the first cache, and thus whether the data prefetch request sent by the prefetching algorithm in the first cache is a hit prefetch request.

[0097] The prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm based on the first and second statistical values ​​corresponding to each prefetch algorithm, as well as the priority of each prefetch algorithm.

[0098] Specifically, for high-priority prefetching algorithms, if the difference between the first and second statistical values ​​corresponding to the high-priority algorithm is greater than a set difference (i.e., the first statistical value is much larger than the second statistical value), it indicates that the number of data prefetch requests discarded by the high-priority algorithm is much greater than the number of hit prefetch requests. In this case, it can be determined that too many data prefetch requests are being discarded by the high-priority algorithm. In this situation, the prefetcher of the first cache lowers the prefetch frequency of the low-priority prefetching algorithm, thus reducing the number of data prefetch requests sent to the second cache by the low-priority prefetching algorithm, while simultaneously increasing the prefetch frequency of the high-priority prefetching algorithm. Because the required accuracy of the high-priority prefetching algorithm is higher than that of the low-priority prefetching algorithm, adjusting it in the above manner allows the high-priority prefetching algorithm to more accurately prefetch the data needed by the processor into the second cache.

[0099] Another embodiment of this application provides a multi-level cache processor architecture, which includes a first cache and a second cache. The first cache is located at the upper level of the second cache, that is, the first cache is the upper-level cache of the second cache, and similarly, the second cache is the lower-level cache of the first cache. Furthermore, the first cache and the second cache are different caches at adjacent levels, wherein the storage space of the second cache is larger than the storage space of the first cache.

[0100] The aforementioned multi-level cache processor architecture can be as follows: Figure 1 The multi-level cache processor architecture shown can be configured such that the first cache and the second cache are respectively... Figure 1 The first level cache (L1, specifically L1C or L1D) and the second level cache (L2) can be used, or the first and second caches can be respectively... Figure 1 The second-level cache (L2) and the third-level cache (L3) are used in the system.

[0101] In this embodiment, the second cache in the multi-level cache processor architecture is equipped with a counter to count the number of times a data request sent from the first cache to the second cache is hit in the second cache. A data request being hit in the second cache means that the requested data is found in the second cache. This data request includes data prefetch requests and may also include other data requests.

[0102] Based on the above counter settings, when a data prefetch request sent from the first cache to the second cache hits the target data requested for prefetching in the second cache, that is, when the data requested for prefetching by the data prefetch request sent from the first cache already exists in the second cache, the counter value is incremented by 1. When any data prefetch request sent from the first cache misses in the second cache, the counter value is reset to zero.

[0103] The multi-level cache processor architecture provided in this embodiment is configured to implement the data prefetching processing method described in any of the above embodiments. The specific processing steps and corresponding beneficial effects of this multi-level cache processor architecture in implementing the above data prefetching processing method can be found in the descriptions of the above method embodiments, and will not be repeated here.

[0104] In another embodiment, a computer device is also provided, which includes the multi-level cache processor architecture described above. The multi-level cache processor architecture in the computer device provided in this embodiment is configured to implement the data prefetching processing method described in any of the above embodiments. The specific processing steps and corresponding beneficial effects of the multi-level cache processor architecture in this computer device implementing the data prefetching processing method can be found in the descriptions of any of the above method embodiments, and will not be repeated here.

[0105] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0106] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0107] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0108] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0109] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0110] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0111] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0112] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0113] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0114] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0115] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data prefetching processing method, characterized in that, The method is applied to a multi-level cache processor architecture, which includes a first cache and a second cache. A counter is set in the second cache to count the number of times a data request sent by the first cache is hit in the second cache. The data request includes a data prefetch request; The method includes: When the number of consecutive hits of the data prefetch requests sent by the first cache in the second cache exceeds a first threshold, the second cache sends a first feedback signal to the prefetcher of the first cache to reduce the frequency of sending prefetch requests.

2. The method according to claim 1, characterized in that, After the second cache sends the first feedback signal to the prefetcher of the first cache, the method further includes: If a data request or data prefetch request sent by the first cache misses in the second cache, the second cache resets the number of consecutive hits of the data prefetch request sent by the first cache to zero and sends a second feedback signal to the prefetcher of the first cache to increase the frequency of sending prefetch requests.

3. The method according to claim 1 or 2, characterized in that, The method further includes: The second cache sends out-of-core bandwidth occupancy information and / or the number of times prefetched data in the second cache is hit to the prefetcher of the first cache, so that the prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm; The prefetched data includes data cached in the second cache based on prefetch requests sent by the prefetcher of the first cache.

4. A data prefetching processing method, characterized in that, The method is applied to a multi-level cache processor architecture, which includes a first cache and a second cache. A counter is set in the second cache to count the number of times a data request sent by the first cache is hit in the second cache. The data request includes a data prefetch request; The method includes: Upon receiving a first feedback signal from the second cache, the prefetcher of the first cache reduces the frequency of prefetch request transmission. The first feedback signal is sent by the second cache to the prefetcher of the first cache when the number of consecutive hits of the data prefetch requests sent by the first cache in the second cache exceeds a first threshold.

5. The method according to claim 4, characterized in that, After the prefetcher of the first cache reduces the prefetch request sending frequency, the method further includes: Upon receiving a second feedback signal from the second cache, the prefetcher of the first cache increases the frequency of prefetch request transmission. The second feedback signal is sent by the second cache to the prefetcher of the first cache when a data request or data prefetch request sent by the first cache is not found in the second cache.

6. The method according to claim 4 or 5, characterized in that, The method further includes: The prefetcher of the first cache receives out-of-core bandwidth usage information sent by the second cache and / or the number of times prefetched data in the second cache is hit, wherein the prefetched data includes data cached in the second cache based on prefetch requests sent by the prefetcher of the first cache; The prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm based on the off-core bandwidth occupancy information and / or the number of times the prefetched data in the second cache is hit.

7. The method according to claim 6, characterized in that, The prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm based on the off-core bandwidth occupancy information, including: When the off-core bandwidth occupancy information indicates that the off-core bandwidth occupancy rate is higher than a set threshold, the prefetcher of the first cache will reduce the prefetch frequency of the prefetch algorithm. or, When the off-core bandwidth occupancy information indicates that the off-core bandwidth occupancy rate is not higher than a set threshold, the prefetcher of the first cache will increase the prefetch frequency of the prefetch algorithm.

8. The method according to claim 6, characterized in that, The prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm based on the number of times the prefetched data in the second cache is hit, including: The prefetcher of the first cache determines the prefetch accuracy of each prefetch algorithm based on the number of times the prefetched data in the second cache is hit, and determines the priority of each prefetch algorithm based on the prefetch accuracy of each prefetch algorithm. The prefetcher of the first cache adjusts the prefetch frequency of each prefetch algorithm according to the priority of each prefetch algorithm; wherein the prefetch frequency of the prefetch algorithm is proportional to the priority of the prefetch algorithm.

9. The method according to claim 8, characterized in that, The method further includes: If the difference between the first statistical value and the second statistical value corresponding to the high-priority prefetch algorithm is greater than a set difference, the prefetcher of the first cache will reduce the prefetch frequency of the low-priority prefetch algorithm; the first statistical value represents the number of prefetch requests that are discarded after being generated by the high-priority algorithm, and the second statistical value represents the number of hit prefetch requests issued by the high-priority algorithm; wherein, when the prefetch request issued by the high-priority algorithm prefetches data in the second cache and is hit, the prefetch request is the hit prefetch request.

10. A multi-level cache processor architecture, characterized in that, The multi-level cache processor architecture includes a first cache and a second cache. The second cache is equipped with a counter, which is used to count the number of times a data request sent by the first cache is hit in the second cache. The data request includes a data prefetch request. The multi-level cache processor architecture is configured to implement the data prefetching processing method as described in any one of claims 1 to 9.

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