AES encryption and decryption hardware implementation method based on RISCV encryption and decryption vector extension architecture
By designing seven dedicated instructions on the RISCV vector extension architecture, the flexibility and scalability issues of existing AES hardware acceleration solutions are solved, realizing an efficient and low-cost AES encryption and decryption hardware design suitable for multiple platforms.
Patent Information
- Application Number
- CN202511679361.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-17
- Publication Date
- 2026-02-10
AI Technical Summary
Existing AES hardware acceleration solutions rely on custom scalar instructions, which make it difficult to fully utilize the parallel computing capabilities of modern processors, resulting in poor flexibility and scalability, as well as large chip area and increased costs.
A hardware implementation method for AES encryption and decryption based on RISCV vector extension architecture is adopted. By adding Zvkng/Zvkned extension instruction set, seven instructions are designed for different AES operations. Combining the advantages of vector computing and customized instruction mechanism, a modular encryption and decryption process is realized, reducing chip area and improving flexibility.
It achieves a flexible encryption and decryption process design, reduces hardware costs, enhances the flexibility of software programming, is applicable to different platforms, and provides a solid foundation for the future evolution of cryptographic algorithms.
Smart Images
Figure CN121502835A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of data encryption technology, specifically, it relates to a hardware implementation method for AES encryption and decryption based on the RISCV encryption and decryption vector extension architecture. Background Technology
[0002] With the increasing demand for data encryption, AES has become the core algorithm in the field of data security. As an international standard for symmetric block cipher algorithms, it is widely used in the protection of sensitive data in various industries such as government, finance, communications, and cloud computing. AES supports key lengths of 128 bits, 192 bits, and 256 bits, and adopts block cipher. Each data block is 128 bits long. Its core operations include byte substitution, row shifting, column obfuscation, and round key addition. It has the advantages of high efficiency and strong resistance to attacks.
[0003] Traditional AES hardware acceleration solutions often rely on dedicated instruction set extensions, such as Intel's AES-NI or ARM's Cryptography Extension. These solutions typically use custom scalar instructions and are mainly designed to accelerate single data blocks, making it difficult to fully utilize the parallel computing capabilities of modern processors.
[0004] The existing Intel solution uses a fixed, bundled extension. AES-NI relies on the SSE / AVX vector instruction set, abstracts high-level behavior through aggregated instructions, and key expansion is automatically completed by hardware. The instructions encapsulate all operations in one round of AES into an atomic operation, which greatly reduces flexibility and scalability. The physical implementation will occupy more chip area and greatly increase costs. Summary of the Invention
[0005] To address the aforementioned problems and technical deficiencies, this application adopts the following technical solution: a hardware implementation method for AES encryption and decryption based on the RISCV vector encryption and decryption extension architecture, comprising the following steps: The RISCV instruction set features a vector extension for AES encryption and decryption; In the AES encryption process, the initial round corresponds to the vaesz.vs instruction, the middle round corresponds to the vaesem.[vv,vs] instruction, and the final round corresponds to the vaesef.[vv,vs] instruction; During AES decryption, the initial round corresponds to the vaesz.vs instruction, the intermediate round corresponds to the vaesdm.[vv,vs] instruction, and the final round corresponds to the vaesdf.[vv,vs] instruction.
[0006] Preferably, the vector extension of the RISCV instruction set is supplemented with Zvkng / Zvkned extensions, adding a total of 7 instructions. Each instruction corresponds to a different AES encryption / decryption operation. Different combinations of these instructions are used to implement different AES encryption / decryption operations. The 7 instructions include: The vaesz.vs instruction is used for the XOR operation in round 0 of vector AES; The vaesem.[vv,vs] instruction is used for vector AES intermediate round encryption; The vaesef.[vv,vs] instruction is used for the final round of vector AES encryption; The vaesdm.[vv,vs] instruction is used for vector AES intermediate round decryption; The vaesdf.[vv,vs] instruction is used for the final round of vector AES decryption; The vaeskf1.vi command is used for vector AES-128 key expansion; The vaeskf2.vi command is used for vector AES-256 key expansion.
[0007] Preferably, in the initial round of the AES encryption and decryption process, the encrypted data block is XORed with the round key.
[0008] Furthermore, in the AES encryption process, the intermediate round includes four operations: byte substitution, row shifting, column obfuscation, and round key addition; The final round consists of three operations: byte substitution, row shifting, and round key addition.
[0009] Furthermore, the AES-128 encryption consists of 10 rounds, including 9 intermediate rounds and 1 final round. The intermediate and final rounds of the AES encryption process are defined and implemented in an RTL module. In the final round, the column obfuscation operation is bypassed. The bypassing function is implemented based on the round number information given in the vaesef and vaesem instructions.
[0010] Furthermore, in the AES decryption process, the intermediate wheel includes four operations: reverse shift, reverse byte substitution, wheel key addition, and reverse column obfuscation. The final round consists of three operations: reverse shift, reverse byte substitution, and round key addition.
[0011] Furthermore, the AES-128 decryption process consists of 10 rounds, including 9 intermediate rounds and 1 final round. The functions of the intermediate and final rounds in the AES encryption process can be implemented in a single RTL module.
[0012] Furthermore, in the final round, the reverse column obfuscation operation is bypassed. This bypass functionality is achieved based on the round number information given in the vaesdf and vaesdm instructions. An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the program, it implements the content of an AES encryption and decryption hardware implementation method based on a RISCV vector encryption and decryption extension architecture as described above.
[0013] A computer-readable storage medium storing a computer program thereon, characterized in that, when executed by a processor, the computer program implements the content of an AES encryption and decryption hardware implementation method based on a RISCV vector encryption and decryption extended architecture as described above.
[0014] Compared to existing technologies, the beneficial effects of this application are as follows: This application combines the algorithmic characteristics, vector computation advantages, and customized instruction mechanism of the zvkned extended instruction set. Leveraging the highly atomic nature of the zvkned extended instruction set, each instruction performs only basic operations, decomposing the entire AES encryption / decryption process into different instruction combinations. This allows developers to flexibly combine and adjust the various steps of the encryption process according to different application requirements, increasing the flexibility of software programming. It also facilitates hardware RTL design, requiring only the implementation of the most basic functional modules, significantly reducing chip area and cost. Furthermore, it enhances hardware and software flexibility. The modular and scalable architecture design can easily adapt to different platforms, from embedded systems to high-performance computing, and provides a solid foundation for the future evolution and customized implementation of cryptographic algorithms, driving the development of encryption processor architecture towards greater efficiency, openness, and customizability. Attached Figure Description
[0015] In the attached diagram: Figure 1 This is a schematic diagram of the method steps in an embodiment of this application; Figure 2 This is a list of extended instructions for embodiments of this application; Figure 3 This is a schematic diagram of the AES-128 encryption and decryption steps in an embodiment of this application; Figure 4 This is a schematic diagram of the AES encryption process in an embodiment of this application. Figure 5 This is a schematic diagram of the AES decryption process according to an embodiment of this application; Figure 6 This is a schematic diagram of the encryption / decryption module structure according to an embodiment of this application; Figure 7 This is a schematic diagram of the device structure according to an embodiment of this application. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments. Generally, the components of the embodiments of this application described and shown in the accompanying drawings can be arranged and designed in various different configurations.
[0017] Example 1 like Figure 1 As shown, a hardware implementation method for AES encryption and decryption based on the RISC-CV vector encryption and decryption extension architecture includes the following steps: The RISCV instruction set has approved a vector extension scheme for AES encryption and decryption, and proposed the zvkned extension instruction set. Based on the characteristics of the RISCV zvkned extension, we propose our modular solution. The RISCCV instruction set vector extension is supplemented with Zvkng / Zvkned extensions, adding a total of 7 instructions. Each instruction corresponds to a different AES encryption / decryption operation. Different combinations of these instructions are used to implement different AES encryption / decryption operations. The 7 instructions include: The vaesz.vs instruction is used for the XOR operation in round 0 of vector AES; The vaesem.[vv,vs] instruction is used for vector AES intermediate round encryption; The vaesef.[vv,vs] instruction is used for the final round of vector AES encryption; The vaesdm.[vv,vs] instruction is used for vector AES intermediate round decryption; The vaesdf.[vv,vs] instruction is used for the final round of vector AES decryption; The vaeskf1.vi command is used for vector AES-128 key expansion; The vaeskf2.vi command is used for vector AES-256 key expansion.
[0018] In the AES encryption process, the initial round corresponds to the vaesz.vs instruction, the middle round corresponds to the vaesem.[vv,vs] instruction, and the final round corresponds to the vaesef.[vv,vs] instruction; In the initial rounds of the AES encryption and decryption process, the encrypted data block is XORed with the round key.
[0019] In the AES encryption process, the intermediate rounds include four operations: byte substitution, row shifting, column obfuscation, and round key addition. The final round consists of three operations: byte substitution, row shifting, and round key addition.
[0020] AES-128 encryption consists of 10 rounds, including 9 intermediate rounds and 1 final round. The intermediate and final rounds of the AES encryption process are defined and implemented in an RTL module. In the final round, the column obfuscation operation is bypassed. The bypass function is implemented based on the round number information given in the vaesef and vaesem instructions.
[0021] During AES decryption, the initial round corresponds to the vaesz.vs instruction, the intermediate round corresponds to the vaesdm.[vv,vs] instruction, and the final round corresponds to the vaesdf.[vv,vs] instruction.
[0022] In the AES decryption process, the intermediate round includes four operations: reverse shift, reverse byte substitution, round key addition, and reverse column obfuscation. The final round consists of three operations: reverse shift, reverse byte substitution, and round key addition.
[0023] AES-128 decryption consists of 10 rounds, including 9 intermediate rounds and 1 final round. The functions of the intermediate and final rounds of the AES encryption process can be implemented in a single RTL module. In the final round, the reverse obfuscation operation is bypassed. This bypassing function is achieved based on the round number information given in the vaesdf and vaesdm instructions.
[0024] The RTL module includes 5 multiplexers. The multiplexers select different input branches according to the input instructions to complete the functions of different instructions.
[0025] Example 2 like Figure 2 As shown, the vector extension of the RISCV instruction set specifically adds the Zvkng / Zvkned extension for AES, adding a total of 7 instructions. Each instruction corresponds to a different AES encryption and decryption operation. Different combinations of these instructions can be used to implement different AES encryption and decryption operations, such as encryption, decryption, and key expansion.
[0026] Figure 3 The steps for AES-128 encryption and decryption are given. It can be seen that the AES encryption process mainly includes the following steps: 1. The initial round (AddRoundKey) corresponds to the vaesz.vs instruction, which performs a bitwise XOR operation on the encrypted data block (called the "state") and the round key.
[0027] 2. Middle Rounds correspond to the vaesem.[vv,vs] instruction. AES-128 encryption has 10 rounds, including 9 middle rounds and one final round. Each middle round includes the following four operations: Byte substitution (SubBytes); Row shifting (ShiftRows); MixColumns; Add RoundKey.
[0028] 3. The final round corresponds to the vaesef.[vv,vs] instruction. The final round omits the column mixing operation, and the final output state is the encrypted ciphertext.
[0029] Byte substitution (SubBytes); Row shifting (ShiftRows); Add RoundKey.
[0030] The AES decryption process is similar to the encryption process, except that the order and transformation of each step are reversed: 1. The initial round (AddRoundKey) corresponds to the vaesz.vs instruction, which performs an XOR operation between the ciphertext and the round key.
[0031] 2. Middle Rounds correspond to the vaesdm.[vv,vs] instruction. AES-128 decryption also has 10 rounds, including 9 middle rounds and one final round. Each middle round includes the following four inverse operations: InvShiftRows; Inverse byte substitution (InvSubBytes); Add Round Key; Inverse Column Confusion (InvMixColumns).
[0032] 3. The final round corresponds to the vaesdf.[vv,vs] instruction. The final round omits the inverse column obfuscation (InvMixColumns) operation, and the final output state is the decrypted plaintext.
[0033] InvShiftRows; Inverse byte substitution (InvSubBytes); Add RoundKey.
[0034] from Figure 4As can be seen, the intermediate and final rounds of the AES encryption process perform essentially the same operations. We define them within an RTL module, simply by bypassing the column obfuscation operation in the final round. This bypass functionality is achieved based on the round number information provided in the vaesef and vaesem instructions. Thus, a single module can implement 10 rounds of encryption. Similarly, from Figure 5 As can be seen, the intermediate and final rounds of the AES decryption process perform essentially the same operations. They can be implemented within a single RTL module. The only requirement is to bypass the inverse obfuscation operation in the final round. This bypass functionality is achieved based on the round number information provided in the vaesdf and vaesdm instructions. Thus, a single module can implement 10 rounds of decryption.
[0035] The initial stages of both encryption and decryption use an XOR operation between the ciphertext and the round key. This function is shared. Ultimately, AES encryption, decryption, and XOR operations are all defined and implemented in a single RTL module. This allows for 10 rounds of encryption and decryption operations to be performed in one module, significantly reducing the chip area.
[0036] The final encryption / decryption module is as follows: Figure 6 As shown 1. AES encryption and decryption involves a large number of table lookups and operations such as shifting and XOR. Considering timing issues, each round of operations can be completed in one or two clock cycles.
[0037] 2. Each module uses multiple multiplexers (MUX) to select different input branches based on the input instruction (inst_type) to complete the function of different instructions.
[0038] Example 3 like Figure 7 As shown, from a hardware perspective, this application provides an embodiment of an electronic device that includes all or part of an AES encryption / decryption hardware implementation method based on a RISCV vector encryption / decryption extension architecture. The electronic device includes a service processor and a distributed memory. The service processor is connected to the memory. The distributed memory stores a service self-management program configured to store machine-readable instructions. The service processor executes the service self-management program. When the instructions are executed by the processor, they implement the AES encryption / decryption hardware implementation method based on a RISCV vector encryption / decryption extension architecture as described above.
[0039] From a hardware perspective, in order to effectively improve the flexibility, versatility, and efficiency of data acquisition, this application provides an embodiment of an electronic device that includes all or part of an AES encryption / decryption hardware implementation method based on the RISCV vector encryption / decryption extension architecture. The electronic device specifically includes the following components: The system comprises a processor, memory, a communications interface, and a bus; wherein the processor, memory, and communications interface communicate with each other via the bus; the communications interface is used to implement information transmission between core business systems, user terminals, and related databases and other related devices using a hardware implementation method for AES encryption and decryption based on a RISCV vector encryption and decryption extended architecture; the logic controller can be a desktop computer, tablet computer, or mobile terminal, etc., but this embodiment is not limited to these.
[0040] In this embodiment, the logic controller can be implemented with reference to an embodiment of an AES encryption and decryption hardware implementation method based on a RISCV vector encryption and decryption extension architecture, the content of which is incorporated herein and repeated parts will not be described again.
[0041] It is understood that the user terminal may include smartphones, tablet electronic devices, network set-top boxes, portable computers, desktop computers, personal digital assistants (PDAs), in-vehicle devices, smart wearable devices, etc., wherein the smart wearable devices may include smart glasses, smartwatches, smart bracelets, etc.
[0042] In practical applications, a portion of an AES encryption / decryption hardware implementation method based on the RISCV vector encryption / decryption extension architecture can be executed on the electronic device side as described above, or all operations can be completed in the client device. The choice can be made based on the processing power of the client device and the limitations of the user's usage scenario, and this application does not impose any limitations on this. If all operations are completed in the client device, the client device may further include a processor.
[0043] The aforementioned client device may have a communication module (i.e., a communication unit) that can communicate with a remote server to achieve data transmission with the server. The server may include a server on the task scheduling center side, and in other implementation scenarios, it may also include a server on an intermediate platform, such as a server on a third-party server platform that has a communication link with the task scheduling center server. The server may include a single computer device, a server cluster composed of multiple servers, or a server structure of a distributed device.
[0044] Example 4 The embodiments of this application also provide a computer-readable storage medium capable of implementing an AES encryption and decryption hardware implementation method based on a RISCV vector encryption and decryption extension architecture, where the execution subject is a server or client, as described in the above embodiments. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements all the contents of the AES encryption and decryption hardware implementation method based on a RISCV vector encryption and decryption extension architecture, where the execution subject is a server or client, as described in the above embodiments.
[0045] The embodiments of this application may be provided as methods, apparatus, or computer program products. Therefore, this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0046] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0047] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0048] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0049] The embodiments described above are merely preferred embodiments of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications, improvements, and substitutions without departing from the concept of this application, and these all fall within the protection scope of this application.
Claims
1. A hardware implementation method for AES encryption and decryption based on the RISC-CV vector encryption and decryption extension architecture, characterized in that, Includes the following steps: The RISCV instruction set features a vector extension for AES encryption and decryption; In the AES encryption process, the initial round corresponds to the vaesz.vs instruction, the middle round corresponds to the vaesem.[vv,vs] instruction, and the final round corresponds to the vaesef.[vv,vs] instruction; During AES decryption, the initial round corresponds to the vaesz.vs instruction, the intermediate round corresponds to the vaesdm.[vv,vs] instruction, and the final round corresponds to the vaesdf.[vv,vs] instruction.
2. The hardware implementation method for AES encryption and decryption based on the RISC-CV vector encryption and decryption extension architecture according to claim 1, characterized in that, The RISCV instruction set adds Zvkng / Zvkned extensions to its vector extension, resulting in 7 additional instructions. Each instruction corresponds to a different AES encryption / decryption operation. Different combinations of these instructions are used to implement different AES encryption / decryption operations. The 7 instructions include: The vaesz.vs instruction is used for the XOR operation in round 0 of vector AES; The vaesem.[vv,vs] instruction is used for vector AES intermediate round encryption; The vaesef.[vv,vs] instruction is used for the final round of vector AES encryption; The vaesdm.[vv,vs] instruction is used for vector AES intermediate round decryption; The vaesdf.[vv,vs] instruction is used for the final round of vector AES decryption; The vaeskf1.vi command is used for vector AES-128 key expansion; The vaeskf2.vi command is used for vector AES-256 key expansion.
3. The hardware implementation method for AES encryption and decryption based on the RISC-CV vector encryption and decryption extension architecture according to claim 1, characterized in that, In the initial rounds of the AES encryption and decryption processes, the encrypted data block is XORed with the round key.
4. The hardware implementation method for AES encryption and decryption based on the RISCV vector encryption and decryption extension architecture according to claim 3, characterized in that, In the AES encryption process, the intermediate round includes four operations: byte substitution, row shifting, column obfuscation, and round key addition. The final round consists of three operations: byte substitution, row shifting, and round key addition.
5. A hardware implementation method for AES encryption and decryption based on a RISCV vector encryption and decryption extension architecture according to claim 4, characterized in that, The AES-128 encryption process consists of 10 rounds, including 9 intermediate rounds and 1 final round. The intermediate and final rounds of the AES encryption process are defined and implemented in an RTL module. In the final round, the column obfuscation operation is bypassed. The bypassing function is implemented based on the round number information given in the vaesef and vaesem instructions.
6. The hardware implementation method for AES encryption and decryption based on the RISCV vector encryption and decryption extension architecture according to claim 3, characterized in that, The intermediate wheel in the AES decryption process includes four operations: reverse shift, reverse byte substitution, wheel key addition, and reverse column obfuscation. The final round consists of three operations: reverse shift, reverse byte substitution, and round key addition.
7. The hardware implementation method for AES encryption and decryption based on the RISC-CV vector encryption and decryption extension architecture according to claim 6, characterized in that, The AES-128 decryption process consists of 10 rounds, including 9 intermediate rounds and 1 final round. The functions of the intermediate and final rounds in the AES encryption process can be implemented in a single RTL module.
8. A hardware implementation method for AES encryption and decryption based on a RISCV vector encryption and decryption extension architecture according to claim 7, characterized in that, In the final round, the reverse column obfuscation operation is bypassed. This bypass function is achieved based on the round number information given in the vaesdf and vaesdm instructions.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the AES encryption and decryption hardware implementation method based on the RISCV vector encryption and decryption extension architecture as described in claim 1.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the AES encryption and decryption hardware implementation method based on the RISCV vector encryption and decryption extension architecture as described in claim 1.