ISO automatic verification method and computer program product
By creating a normalized document and parsing tool to generate an isolation check module, the problem of automating the functional verification of chip isolation units was solved, the verification efficiency was improved and human error was reduced, and the automated checking of isolation signal values was realized.
Patent Information
- Application Number
- CN202511532306.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-24
- Publication Date
- 2026-02-10
AI Technical Summary
The lack of automated methods in existing technologies for verifying the functionality of isolation units in chips leads to low efficiency, high error rates, and difficulty in ensuring comprehensiveness and consistency in manual verification.
By creating normalized documents to record the attribute information of isolated signals, and using parsing tools to generate an isolation check module, automated verification is achieved and the module is integrated into the simulation environment for testing.
It enables automated verification of isolation signal values, improves verification efficiency, avoids human error, saves manpower and resources, and supports direct reuse in different projects.
Smart Images
Figure CN121503369A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip detection, and in particular to an ISO automatic verification method and a computer program product. BACKGROUND
[0002] Modern chip design often contains multiple power domains to achieve independent power management of different modules, for example, the Bluetooth module can be powered off when the CPU core is working to save power consumption. However, when a module (such as module A) is powered off, its output signal may enter an indefinite state (such as high impedance state 'Z' or unknown value 'X'), and if these signals are transmitted to other modules (such as module B) that are still working, it may cause logic errors or short circuit currents and other serious consequences. To solve this problem, an isolation unit is usually inserted between the power domains, which functions to clamp the output signal of the module to a certain logic value (such as 0 or 1) when the module is powered off, thereby ensuring the stability of the input signal of the receiving module. The operation of the isolation unit is controlled by an isolation enable signal (ISO_EN), which is turned on by the power management unit before the module is powered off and turned off after power-on.
[0003] Currently, the verification of the function of the isolation unit mainly relies on manual inspection or indirect verification methods, and there is a lack of automatic verification means. Because the number of signals that need to be isolated in the chip is large, and involves multiple design modules and engineers, the manual verification method is inefficient, prone to errors, and difficult to ensure comprehensiveness and consistency. SUMMARY
[0004] The purpose of the present application is to overcome the shortcomings of the prior art and provide an ISO automatic verification method and a computer program product, which automatically analyzes the standardized document and generates an isolation signal check module (iso_checker) through a script tool, and finally realizes the automatic verification of the isolation function.
[0005] The purpose of the present application is achieved by the following technical solutions: In a first aspect, the present application discloses an ISO automatic verification method, comprising: creating a normalized document, the normalized document recording at least attribute information of a signal that needs to be isolated, the attribute information including: an isolation enable signal, a signal level, a signal name, and an expected isolation value; using an analysis tool to read and analyze the normalized document to extract the attribute information; based on the extracted attribute information, automatically generating an isolation check module; and integrating the isolation check module into a verification environment for simulation testing.
[0006] The application can realize automatic verification of whether the isolated signal value meets the expectation.
[0007] Further, the reading and parsing of the normalized document by the parsing tool further includes: performing a specification check on the content of the normalized document, and performing an error prompt when a format error is found; wherein the specification check includes at least one of the following: checking whether the content is blank, whether it contains special punctuation marks, whether it contains white spaces, and whether the isolated value meets a specific binary format.
[0008] Further, the step of automatically generating an isolation check module based on the extracted attribute information includes: generating corresponding check logic for each isolated signal recorded in the normalized document.
[0009] Further, the check logic includes: the isolation check module is used to check whether the corresponding isolated signal value is the expected isolated value when the isolation enable signal is valid, and is turned off when the signal is invalid.
[0010] Further, the check logic is implemented by SystemVerilog assertion; the assertion is configured to check whether the value of the corresponding isolated signal is equal to the expected isolated value as soon as the isolation enable signal is monitored to be valid, and report an error when the check fails.
[0011] Further, the isolation check module further includes: an enable control switch, which is implemented by a one-bit variable, for controlling whether the entire check is effective.
[0012] Further, the simulation test includes: power consumption simulation combined with UPF, CPF power supply intent files or power ground netlists.
[0013] In a second aspect, the application discloses a computer program product, which stores computer program instructions, and the computer program instructions are executed by a processor to realize the ISO automatic verification method. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figure 1 The ISO automatic verification method flowchart in some embodiments of the application. DETAILED DESCRIPTION
[0015] The technical solutions of the present application will be described clearly and completely below in combination with embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.
[0016] Referring to Figure 1 The present application provides an ISO automation verification method and a computer program product.
[0017] Before the specific solutions are described, some specific names are explained: Power Domains: Power domains, modern chips have multiple power domains, and different modules can independently switch power supplies (for example: when the CPU core is working, the Bluetooth module can be powered off to save power).
[0018] ISO: Isolation, which is essentially to separate two or more parts physically or logically, so that they cannot directly affect each other. The key purpose is to avoid interference (one part problem does not affect other parts), security control (prevent dangerous spread, such as current, data error), and functional independence (modules can be independently designed / tested / operated).
[0019] ISO_EN: Isolation enable signal.
[0020] checker: checker is a commonly used term in the verification field, which is a component of a verification environment, and is specially used to check the functional correctness of the design (DUT) in real time or after the fact. It is not part of the DUT, but a "supervisor" in the verification environment.
[0021] Iso_checker: Iso_checker is a checker that specifically checks the correctness of ISO, and its function is a component for checking whether the ISO is correct.
[0022] Hierarchy: Signal Hierarchy refers to the hierarchical path structure of signals in modular design.
[0023] CPF: A tool-independent standardized language for explicitly describing the power management architecture of a chip at the RTL (Register Transfer Level) design stage, including power domain division, power switch control, signal isolation rules, state retention strategies, etc. CPF is one of the core standards of low-power design flow, and competes with another mainstream format UPF (Unified Power Format, IEEE 1801), both of which have similar functions but different syntax and ecosystems.
[0024] PG netlist: Power / Ground Netlist, is a key data file describing the physical connection relationship of the chip power supply network, mainly used for power integrity verification and power consumption analysis after physical design.
[0025] Filelist: file list used by simulation tools.
[0026] sv: systemverilog programming language.
[0027] sv assertion: assertion implemented in systemverilog.
[0028] Modern chips have multiple power domains (Power Domains), and different modules can independently switch power supply (for example: when the CPU core is working, the Bluetooth module can be powered off to save power). When a module (such as module A) is powered off (Power Off), its output signal will become an indeterminate state (floating, high impedance state 'Z') or unknown value ('X'). In order to separate two or more parts physically or logically so that they cannot directly affect each other, an isolation cell (Isolation Cell) is inserted between different power domains.
[0029] Among them, the role of the isolation cell is: when module A is powered off, the Isolation Cell forces its output signal to be a safe and determined value (usually 0 or 1); and ensure that module B receives a valid logic level (not X / Z) to avoid system crash. The working logic of the isolation cell is: in normal mode (module A is powered on), the Isolation Cell transmits the signal transparently. In power saving mode (module A is powered off), the Isolation Cell clamps the output to a preset value (such as 0) and ignores input changes. And it is used for isolation enable signal (ISO_EN): controlled by the power management controller (Power Manager), indicating when to enable isolation. Usually, isolation is enabled before module power-off and disabled after module power-on.
[0030] Therefore, it is necessary to confirm that the ISO_EN signal is in the correct timing (enabled before power-off / disabled after power-on). Check if the isolated signal value meets the expectations (0 or 1).
[0031] According to the ISO automated verification method of the embodiment of the application, the method specifically comprises the following steps: First, enter all signals requiring isolation and their attribute information into a standardized document with a uniform format, such as Excel, TXT, or HTML. Normalization can be performed after entry or before entry. This document should include the isolation enable signal ISO_EN, the signal's hierarchy, the signal name, and its expected isolation value (e.g., 0 or 1). This standardized management ensures consistent descriptions of ISO signals across different projects, facilitating subsequent automated processing.
[0032] Then, a parsing tool is written using a scripting language such as Python or Perl. This tool reads the content of the normalized document and extracts information such as ISO_EN, level, signal name, and isolation value line by line, converting it into a data structure that the program can process. Specifically, this includes: Read and parse the normalized ISO document content, and extract information such as ISO_EN, level, signal name and isolation value line by line, and convert it into a data structure that the program can process.
[0033] Taking an Excel spreadsheet as an example: The script first retrieves the content of each row of the table according to the ISO table format, such as ISO_EN, Hierarchy, signal name, and ISO value, and saves the content of each row as a list to prepare for the subsequent script to reference and retrieve the table content.
[0034] Furthermore, the script checks the document content for standardization, including whether the content is blank, whether it contains special punctuation marks, whether it contains whitespace characters, whether the ISO value is filled in correctly according to the specific base, and whether the capitalization is correct. If a formatting error is found, an error message will be displayed to ensure the validity of the input data.
[0035] Understandably, the script checks whether every item entered in the document conforms to the document specifications, reporting errors for non-compliance and omissions. Therefore, the script itself doesn't need to check the correctness of the ISO values; it only needs to check whether the document conforms to the specifications.
[0036] The script then generates the corresponding isolation check module, `iso_checker`, based on the parsed ISO document content. This ISO check module can be implemented using SystemVerilog modules, interfaces, or assertions. Internally, it includes an enable / disable switch for global control of the check function, including logic for monitoring the ISO_EN signal. Before and after chip power-up, a one-bit ISO_EN signal is raised. When the ISO_EN signal is raised, if the isolation enable signal is valid, a check of the ISO value is immediately initiated to determine if the corresponding isolation signal value is the expected isolation value. If the ISO_EN signal is invalid, it is disabled. The check logic can be implemented using SystemVerilog assertions or always blocks, enabling real-time monitoring of whether the signal value meets expectations and outputting error messages when errors are detected. In addition, this module can also integrate coverage collection functionality, utilizing the coverage characteristics built into assertions or the code coverage statistics function of simulation tools to comprehensively evaluate the verification integrity.
[0037] In some preferred embodiments, checking the ISO value for correctness via sv assertion includes: Based on the ISO table content, each row describes the ISO value of a signal. Then, for each signal, an assertion check is generated based on ISO_EN and ISO value to determine if it is correct. This process is repeated to generate an svassertion checker for the entire ISO signal. These svassertion checkers are then placed into the module. This action is also implemented by a script (or an interface, or simply an assertion).
[0038] It's worth noting that using SV assertions makes it very convenient to assign coverage metrics. Based on the characteristics of SV assertions, coverage metrics can be directly written for each assertion, eliminating the need for engineers to write them manually. Similarly, if using always statements, coverage metrics are also unnecessary, as EDA tools collect code coverage data, achieving 100% coverage through these metrics alone.
[0039] In some examples, it is necessary to check immediately upon encountering ISO_EN. In this example, the check is not a one-time event, but is repeated continuously.
[0040] Of course, both of the methods mentioned above can achieve continuous repeated checks.
[0041] After generating the iso_checker according to the aforementioned steps, integrate it into the verification environment. This can be done via a filelist or by direct instantiation. During the power consumption simulation phase, combine it with a UPF (Unified Power Format) or CPF (Common Power Format) power intent file, or use a power ground netlist (PG netlist) for simulation testing. During simulation, if any isolation signal value does not conform to the preset value, the simulation log will automatically report the error, thereby achieving automated and comprehensive verification of the isolation function.
[0042] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. An ISO automated verification method, characterized in that, include: Create a normalized document, which records at least the attribute information of the signal to be isolated, including: isolation enable signal, signal level, signal name, and expected isolation value; The normalized document is read and parsed using a parsing tool to extract the attribute information; Based on the extracted attribute information, an isolation check module is automatically generated; The isolation check module is integrated into the verification environment for simulation testing.
2. The ISO automated verification method according to claim 1, characterized in that, The process of using parsing tools to read and parse the normalized document also includes: The content of the normalized document is checked for standardization, and an error message is displayed when a formatting error is found; The normative checks include at least one of the following: checking whether the content is blank, whether it contains special punctuation marks, whether it contains whitespace characters, and whether the isolation value conforms to a specific number base format.
3. The ISO automated verification method according to claim 2, characterized in that, The steps for automatically generating the isolation check module based on the extracted attribute information include: For each signal that needs to be isolated recorded in the normalized document, generate the corresponding inspection logic.
4. The ISO automated verification method according to claim 3, characterized in that: The inspection logic includes: The isolation check module is used to check whether the corresponding isolation signal value is the expected isolation value when the isolation enable signal is valid, and to shut down when the signal fails.
5. The ISO automated verification method according to claim 4, characterized in that: The inspection logic is implemented using SystemVerilog assertions; The assertion is configured to: when the isolation enable signal is detected to be valid, immediately check whether the value of the corresponding isolation signal is equal to the expected isolation value, and report an error if the check fails.
6. The ISO automated verification method according to claim 2, characterized in that: The isolation inspection module also includes: The enable control switch, implemented by a one-bit variable, controls whether the entire check is active.
7. The ISO automated verification method according to claim 1, characterized in that: The simulation tests include: power consumption simulation using UPF, CPF power intent files or power ground network tables.
8. A computer program product, characterized in that, The device stores computer program instructions that, when executed by a processor, implement the ISO automated verification method according to any one of claims 1 to 7.