Storage device and operating method of storage device

Abstract

A memory device and an operating method of the memory device are provided. The storage device includes a plurality of non-volatile memory devices; and a memory controller commonly connected to the plurality of non-volatile memory devices through a first signal line and commonly connected to the plurality of non-volatile memory devices through a second signal line. Each of the plurality of non-volatile memory devices receives a command and an address through a first signal line, and communicates data bits with the memory controller through a second signal line. When a command and an address are not received through the first signal line, the plurality of nonvolatile memory devices exchange information through the first signal line without control of the memory controller.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0106186, filed on August 8, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The disclosure relates to a semiconductor device, and more specifically, to a memory device and a method of operating the memory device. Background Technology

[0003] The storage device may include a memory controller and multiple non-volatile memory devices. Multiple non-volatile memory devices connected to the memory controller via a common signal line may correspond to one channel. The multiple non-volatile memory devices may communicate with the memory controller based on a communication standard.

[0004] Multiple non-volatile memory devices can share information with each other, which helps in managing them. However, when multiple non-volatile memory devices share information, it can hinder control over them. Therefore, the throughput of the memory device may decrease, leading to undesirable and / or suboptimal operation. Furthermore, multiple non-volatile memory devices sharing information may not meet communication standards, resulting in undesirable technologies that do not meet those standards. Summary of the Invention

[0005] The disclosed aspect provides apparatus and methods for allowing non-volatile memory devices to share information with each other without impeding the memory controller's control over the operation of the non-volatile memory devices.

[0006] According to the disclosed aspects, a storage device is provided, the storage device comprising: a plurality of non-volatile memory devices; and a memory controller, which is connected to the plurality of non-volatile memory devices via a first signal line and to the plurality of non-volatile memory devices via a second signal line, wherein each of the plurality of non-volatile memory devices is configured to: transmit data bits to the memory controller via a second signal line corresponding to the command and address received via the first signal line based on receiving a command and address via the first signal line; and exchange information with one or more other non-volatile memory devices among the plurality of non-volatile memory devices via the first signal line based on not receiving a command via the first signal line.

[0007] According to another aspect of the disclosure, a method for operating a storage device is provided. The storage device includes a plurality of non-volatile memory devices and a memory controller. The method includes: configuring the plurality of non-volatile memory devices to operate in a first mode via the memory controller; transmitting a first clock signal and commands and addresses synchronized with the first clock signal to the plurality of non-volatile memory devices via a first signal line via the memory controller; transmitting data strobe signals and data bits synchronized with the data strobe signals to the plurality of non-volatile memory devices based on the commands and addresses; and exchanging information synchronously with the data strobe signals via the first signal line in the first mode of the plurality of non-volatile memory devices without the control of the memory controller when the memory controller does not transmit the first clock signal via the first signal line.

[0008] According to another aspect of the disclosure, a storage device is provided, the storage device comprising: a plurality of first non-volatile memory devices connected to a first channel; a plurality of second non-volatile memory devices connected to a second channel; and a memory controller connected to the first channel and the second channel, wherein the memory controller is configured to: set the plurality of first non-volatile memory devices to operate in one of a first mode and a second mode; and, independently of the mode set for the plurality of first non-volatile memory devices, set the plurality of second non-volatile memory devices to operate in one of a first mode and a second mode, wherein each of the first channel and the second channel includes: a first signal line configured to transmit commands and addresses; and a second signal line configured to transmit data bits, wherein, in the first mode, the plurality of first non-volatile memory devices are configured to exchange information via the first signal line based on the absence of a command received via the first signal line, and wherein, in the second mode, the plurality of first non-volatile memory devices are configured to omit the exchange of information via the first signal line. Attached Figure Description

[0009] The above and other objects and features disclosed will become clear from the detailed description of the disclosed embodiments with reference to the accompanying drawings.

[0010] Figure 1 A storage device according to a disclosed embodiment is shown.

[0011] Figure 2 An example of control logic and data buffers is shown.

[0012] Figure 3 This is a flowchart illustrating a method of operating a storage device according to a disclosed embodiment.

[0013] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E An example of a storage device operating in SCA mode with inter-device communication based on data strobe signals is shown.

[0014] Figure 5 Examples of request and response packets according to the disclosed embodiments are shown.

[0015] Figure 6A , Figure 6B , Figure 6C and Figure 6D Examples of data bits in non-volatile memory devices that transmit data synchronously with data strobe signals, as well as data bits in request and response packets, are shown.

[0016] Figure 7 This shows another example of control logic and data buffers.

[0017] Figure 8A and Figure 8B An example of a storage device operating in SCA mode with inter-device communication based on a second clock signal is shown.

[0018] Figure 9A and Figure 9B An example is shown of a first non-volatile memory device, a second non-volatile memory device, a third non-volatile memory device, and a fourth non-volatile memory device transmitting a second clock signal and data bits of a request packet or a response packet.

[0019] Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E This shows an example of a storage device operating in conventional mode.

[0020] Figure 11 This illustrates an example of a memory controller using inter-device communication.

[0021] Figure 12 This is a flowchart illustrating a method of operating a non-volatile memory device according to a disclosed embodiment.

[0022] Figure 13 A storage device according to another disclosed embodiment is shown.

[0023] Figure 14 This is a block diagram illustrating a non-volatile memory device according to a disclosed embodiment.

[0024] Figure 15 This is a block diagram illustrating a system according to a disclosed embodiment. Detailed Implementation

[0025] The disclosed embodiments will now be described in detail and clearly to the extent that they are readily implemented by those skilled in the art.

[0026] Figure 1 A storage device 100 according to a disclosed embodiment is shown. (See also...) Figure 1 The storage device 100 may include a first non-volatile memory device 110_1, a second non-volatile memory device 110_2, a third non-volatile memory device 110_3, a fourth non-volatile memory device 110_4, and a memory controller 120. However, the disclosure is not limited thereto, and therefore, according to embodiments, the number of non-volatile memory devices may be different from four. In another embodiment, the storage device 100 may include one or more other components.

[0027] The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be connected to the memory controller 120. For example, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be connected to the memory controller 120 via a first signal line SIGL1 and a second signal line SIGL2. The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 connected to the memory controller 120 can form a channel.

[0028] The first signal line SIGL1 can send or transmit j control signals CS[1:j] (j is a positive integer) to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. For example, the first signal line SIGL1 can send or transmit control signals CS[1:j] in one direction.

[0029] The second signal line SIGL2 can transmit or transmit m data strobe signals DQS[1:m] (m is a positive integer) and n data signals DQ[1:n] (n is a positive integer) between the memory controller 120 and the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. For example, the second signal line SIGL2 can transmit or transmit data strobe signals DQS[1:m] and data signals DQ[1:n] in both directions.

[0030] Each of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may include control logic CL, a data buffer DTB, and a temperature sensor TS.

[0031] The control logic CL receives control signals CS[1:j] from the memory controller 120 via the first signal line SIGL1. The control logic CL can control the operation of non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 based on the control signals CS[1:j]. For example, based on the control signals CS[1:j], the control logic CL can control the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 to perform write, read, or erase operations.

[0032] The data buffer DTB can transmit (or exchange) the data strobe signal DQS[1:m] and the data signal DQ[1:n] with the memory controller 120 via the second signal line SIGL2.

[0033] During a write operation, the data buffer DTB can latch data bits transmitted via the data signals DQ[1:n] based on or in response to the data strobe signals DQS[1:m]. For example, during a write operation, the data buffer DTB can latch data bits transmitted via the data signals DQ[1:n] synchronously with the data strobe signals DQS[1:m]. The data buffer DTB can transfer the latched data bits to the core circuitry of the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4, so that the data bits are written into the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4.

[0034] During a read operation, the data buffer DTB may output data bits transferred from the core circuitry of non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 as a data signal DQ[1:n] based on or in response to the data strobe signal DQS[1:m]. For example, during a read operation, the data buffer DTB may output data bits transferred from the core circuitry of non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 as a data signal DQ[1:n] synchronously with the data strobe signal DQS[1:m].

[0035] The temperature sensor TS can measure the temperature of non-volatile memory devices 110_1, 110_2, 110_3, or 110_4. For example, the temperature sensor TS can be located at a specific location (e.g., the location with the greatest heat generation) within the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4. The temperature sensor TS can periodically (e.g., based on a first time period) measure the ambient temperature (e.g., the temperature of the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4) and can store (or update) the temperature information. The temperature sensor TS can periodically (e.g., based on a second time period) provide the temperature information to the control logic CL.

[0036] According to an embodiment, based on certain conditions being met, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can exchange information with each other without the control of the memory controller 120. For example, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can exchange information via the first signal line SIGL1. In this case, the first signal line SIGL1 can exchange information in both directions.

[0037] Information exchange between two or more of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may include at least one of peak current information, temperature information, and status information.

[0038] For example, peak current information may include, but is not limited to, information about the current peak current or information about the peak current within a given time window. For example, temperature information may include, but is not limited to, temperature information obtained from a temperature sensor TS. For example, status information may include, but is not limited to, information indicating the status of an operation. For example, status information may include information indicating whether a write operation, read operation, or erase operation has failed or succeeded. According to embodiments, the memory devices may be managed or controlled based on information exchanged between two or more of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4.

[0039] In one embodiment, the exchange of information between the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 without the control of the memory controller 120 can be referred to as inter-device communication or "inter-device comm". In another example, because multiple semiconductor dies integrated in a package form a channel, the exchange of information between the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 without the control of the memory controller 120 can be referred to as inter-die communication or "inter-die comm".

[0040] In one embodiment, additional signal lines may be provided between the memory controller 120 and the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. The additional signal lines may include, but are not limited to, chip enable signal lines and ready-busy signal lines. For example, chip enable signal lines may be provided between the memory controller 120 and the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4, respectively. The memory controller 120 can select a non-volatile memory device as the access target by activating one of the chip enable signal lines connected to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 and deactivating the signals of the remaining chip enable signal lines.

[0041] For example, ready-busy signal lines can be respectively provided between the memory controller 120 and the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. Each of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can notify the memory controller 120 whether its own state is ready or busy by activating or deactivating the signal of the corresponding ready-busy signal line.

[0042] In one embodiment, at least one of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may not include a temperature sensor TS. In this case, the temperature information of the portion of the non-volatile memory devices including the temperature sensor TS in the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be exchanged.

[0043] Figure 2 An example of control logic (CL) and data buffer (DTB) is shown. (See reference...) Figure 1 and Figure 2 The control logic CL may include, but is not limited to, a pattern storage device MS, a first latch LC1, a delay-locked loop DLL, a first driver DRV1, a command parser CMDP, a packet generator PKG, a packet parser PKP, and a voltage and current generator VCG.

[0044] The mode storage device MS may include information about various operating modes of the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4. For example, the mode storage device MS may store information about whether the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 are currently operating in normal mode conforming to the communication standards of the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4, or in legacy mode conforming to an earlier version of the communication standards. The mode storage device MS may store information about whether inter-device communication (or inter-die communication) of the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 is activated or deactivated. The mode storage device MS may store information about the manner (e.g., the method or technique used) for exchanging information based on the activation of inter-device communication (or inter-die communication). The control logic CL can control the operation of non-volatile memory devices 110_1, 110_2, 110_3 or 110_4 based on information stored in the pattern storage device MS.

[0045] In addition to the information above, the mode storage device MS may store various information regarding the operating modes of the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4. In one embodiment, the mode storage device MS may include non-volatile memory elements or volatile memory elements (such as static random access memory (SRAM) cells or dynamic random access memory (DRAM) cells). Non-volatile memory elements may include, but are not limited to, electrical fuses. Volatile memory elements may include, but are not limited to, SRAM cells or DRAM cells.

[0046] The first latch LC1 latches a signal received via the first signal line SIGL1. The first latch LC1 is used to latch a synchronization signal, and the signal latched by the first latch LC1 can be changed. For example, the inputs of the first latch LC1 can be multiplexed. In one example, the first latch LC1 can latch a first signal synchronously with a second signal. When the first and second signals are multiplexed (or changed), the first latch LC1 can latch a second signal synchronously with the first signal. The control logic CL can operate based on the signal latched by the first latch LC1.

[0047] The delay-locked loop (DLL) receives a clock signal, adjusts the delay of the clock signal, and outputs a delayed clock signal. The clock signal received by the DLL can be changed. For example, the inputs of the DLL can be multiplexed. In one example, the DLL can latch a third signal synchronously with a fourth signal. When the third and fourth signals are multiplexed (or changed), the DLL can latch the fourth signal synchronously with the third signal. The control logic (CL) can operate based on the clock signal output from the DLL.

[0048] The first driver DRV1 can be used to control the logic CL to send signals to the first signal line SIGL1 during inter-device communication.

[0049] The command parser CMDP can parse commands received from the memory controller 120 and output the parsed results. The control logic CL can operate based on the parsed results and can control non-volatile memory devices 110_1, 110_2, 110_3 or 110_4.

[0050] In an example scenario of performing inter-device communication, the packet generator PKG can generate packets for inter-device communication based on information about the method of exchange, which is stored in the pattern storage device MS. The generated packets can be output to the first signal line SIGL1 via the first driver DRV1.

[0051] In the example scenario where inter-device communication is activated and packets are received via the first signal line SIGL1 based on inter-device communication, the packet parser PKP can parse the received packets and output the parsing result. Control logic CL can store the parsing result. For example, the parsing result may include information transmitted from any other non-volatile memory device 110_1, 110_2, 110_3, or 110_4. Information transmitted from other non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 may include, but is not limited to, peak current information, temperature information, or status information.

[0052] A voltage and current generator (VCG) generates voltages and currents used in non-volatile memory devices 110_1, 110_2, 110_3, or 110_4. The VCG detects peak currents and provides information about the detected peak currents (peak current information) to the control logic (CL). The control logic (CL) stores the peak current information along with information parsed by the packet parser (PKP). Furthermore, the control logic (CL) stores temperature and status information of the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4, along with the peak current information and the parsed information.

[0053] The data buffer DTB may include, but is not limited to, a second driver DRV2 and a second latch LC2. The second driver DRV2 can be used to send data strobe signals DQS[1:m] and data signals DQ[1:n] to the second signal line SIGL2. For example, the data buffer DTB uses the second driver DRV2 to send data strobe signals DQS[1:m] and data signals DQ[1:n] to the second signal line SIGL2. The second latch LC2 can be used to latch the data strobe signals DQS[1:m] and data signals DQ[1:n] received from the second signal line SIGL2. For example, the data buffer DTB uses the second latch to latch the data strobe signals DQS[1:m] and data signals DQ[1:n] received from the second signal line SIGL2.

[0054] According to the disclosed embodiments, the control logic CL may include a first driver DRV1 for inter-device communication. However, the disclosed embodiments are not limited thereto. For example, the control logic CL may transmit packets generated by the packet generator PKG to the data buffer DTB, and the second driver DRV2 of the data buffer DTB may output the packets to the first signal line SIGL1. The output of the second driver DRV2 may be demultiplexed to be output to either the first signal line SIGL1 or the second signal line SIGL2. In this case, the first driver DRV1 of the control logic CL may be omitted.

[0055] Figure 3 This is a flowchart illustrating an operation method of a storage device 100 according to a disclosed embodiment. (Refer to...) Figure 1 , Figure 2 and Figure 3 In operation S110, the method (operation method) may include setting an operation mode. For example, the storage device 100 may set a mode. For example, the memory controller 120 may set the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 to operate in a mode associated with inter-device communication.

[0056] In one embodiment, a description will be given of the memory controller 120 setting one of a first mode, a second mode, a third mode, and a fourth mode to a first non-volatile memory device 110_1, a second non-volatile memory device 110_2, a third non-volatile memory device 110_3, and a fourth non-volatile memory device 110_4, but the modes in the disclosed embodiments are not limited to the number or order of modes.

[0057] In the example case where the memory controller 120 is powered on, the memory controller 120 can set or change modes based on requests from external host devices or internal policies.

[0058] In operation S120, the method may include determining whether a non-volatile memory device 110_1, 110_2, 110_3, or 110_4 is set to a first mode. For example, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and / or the fourth non-volatile memory device 110_4 may determine whether the corresponding non-volatile memory device 110_1, 110_2, 110_3, or 110_4 is set to the first mode. For example, the control logic CL of the corresponding non-volatile memory device 110_1, 110_2, 110_3, or 110_4 may identify the set mode based on mode information stored in the mode storage device MS.

[0059] In an example where non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 are configured in a first mode, in operation S130, the method may include configuring non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 in a separate command and address (SCA) mode based on the data strobe signal DQS (e.g., an SCA mode with DQS-based inter-device communication). For example, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 may be configured in a separate command and address (SCA) mode based on the data strobe signal DQS.

[0060] In SCA mode, the memory controller 120 can send clock signals, commands, and addresses as control signals CS[1:j] to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 via the first signal line SIGL1. In SCA mode, the memory controller 120 can send data bits as data signals DQ[1:n] to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 via the second signal line SIGL2.

[0061] When the memory controller 120 does not send clock signals, commands, and addresses through the first signal line SIGL1, and when the memory controller 120 sends or receives data signals DQ[1:n] synchronously with the data strobe signal DQS[1:m], the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can perform inter-device communication synchronously with the data strobe signal DQS.

[0062] According to an embodiment, based on determining in operation S120 that the non-volatile memory device 110_1, 110_2, 110_3 or 110_4 is not set to a first mode, in operation S140, the method may include determining whether the non-volatile memory device 110_1, 110_2, 110_3 or 110_4 is set to a second mode.

[0063] In an example where non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 are configured in a second mode, in operation S150, the method may include configuring non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 in a separate command and address (SCA) mode without inter-device communication. For example, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 may be configured in an SCA mode without inter-device communication (or where inter-device communication is not performed or omitted).

[0064] According to an embodiment, based on determining in operation S140 that the non-volatile memory device 110_1, 110_2, 110_3 or 110_4 is not set to the second mode, in operation S160, the method may include determining whether the non-volatile memory device 110_1, 110_2, 110_3 or 110_4 is set to the third mode.

[0065] In an example where non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 are configured in a third mode, in operation S170, the method may include configuring non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 in a separate command and address (SCA) mode with inter-device communication based on a second clock signal CLK2. For example, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 may be configured in an SCA mode with inter-device communication based on the second clock signal CLK2 (or configured to perform inter-device communication based on the second clock signal CLK2). In one embodiment, the second clock signal CLK2 may be different from the clock signals sent to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. For example, the second clock signal CLK2 can be generated by any one of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4.

[0066] According to an embodiment, based on the determination in operation S160 that non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 are not set to a third mode, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 are identified as being set to a fourth mode. In operation S180, the method may include determining that non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can be set to a fourth mode without inter-device communication. According to an embodiment, the fourth mode may be a conventional mode.

[0067] In conventional mode, the memory controller 120 can send the write enable signal and the address latch enable signal as control signals CS[1:j] to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 via the first signal line SIGL1. In conventional mode, the memory controller 120 can send the data bits, commands, and addresses as data signals DQ[1:n] to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 via the second signal line SIGL2.

[0068] Figure 4A , Figure 4B , Figure 4C , Figure 4Dand Figure 4E An example of storage device 100 operating in SCA mode with inter-device communication based on data strobe signals is shown. In one embodiment, in Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E The middle shows Figure 3 An example of the first pattern, in Figure 3 In the first mode, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3 and the fourth non-volatile memory device 110_4 perform inter-device communication based on any one of the data strobe signals DQS[1:m] without the control of the memory controller 120.

[0069] Reference Figure 4A The control signal CS[1:j] may include a clock signal CLK, a first command address signal CA1, a second command address signal CA2, and a read enable signal RE. The first signal line SIGL1 may be configured to transmit the clock signal CLK, the first command address signal CA1, the second command address signal CA2, and the read enable signal RE.

[0070] Figure 4B This illustrates an example of a storage device 100 performing a write operation in SCA mode with inter-device communication. (Refer to...) Figure 2 and Figure 4B In the example scenario where the memory controller 120 intends to send commands and addresses CA to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4, the memory controller 120 may first generate and output a clock signal CLK. The memory controller 120 may then output the commands and addresses CA synchronously with the clock signal CLK as a first command address signal CA1 and a second command address signal CA2.

[0071] According to an embodiment, a non-volatile memory device among the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be selected via a chip enable signal of the memory controller 120. The first latch LC1 of the control logic CL of the selected non-volatile memory device 110_1, 110_2, 110_3, or 110_4 can latch commands and addresses CA synchronously with a clock signal CLK. The command parser CMDP of the control logic CL can parse commands and addresses CA.

[0072] According to an embodiment, while outputting the command and address CA, the memory controller 120 can generate and output a data strobe signal DQS[1:m]. The memory controller 120 can synchronously send data DQ as a data signal DQ[1:n] with the data strobe signal DQS[1:m].

[0073] The second latch LC2 of the data buffer DTB of the selected non-volatile memory device 110_1, 110_2, 110_3 or 110_4 can latch the latched data DQ synchronously with the data strobe signal DQS[1:m].

[0074] The first signal line SIGL1 and the second signal line SIGL2 can be separated from each other. For example, the signal of the first signal line SIGL1 can be synchronized with the clock signal CLK, and the signal of the second signal line SIGL2 can be synchronized with the data strobe signal DQS. Therefore, the memory controller 120 can output signals simultaneously through the first signal line SIGL1 and the second signal line SIGL2.

[0075] In one embodiment, the data DQ may be data corresponding to the current command and address CA or data corresponding to a previous command and address. In another embodiment, the memory controller 120 may receive the data DQ corresponding to a previous read command from a selected non-volatile memory device 110_1, 110_2, 110_3, or 110_4.

[0076] In one embodiment, when the memory controller 120 outputs one of the first command address signal CA1, the second command address signal CA2, and the clock signal CLK, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may not attempt inter-device communication.

[0077] Figure 4C This illustrates an example of a storage device 100 performing a read operation in SCA mode with inter-device communication. (Refer to...) Figure 4C In the example scenario where the memory controller 120 intends to send commands and addresses CA to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4, the memory controller 120 may first generate and output a clock signal CLK. The memory controller 120 may then output the command and address signals CA synchronously with the clock signal CLK as a first command address signal CA1 and a second command address signal CA2.

[0078] According to an embodiment, a non-volatile memory device among the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be selected via a chip enable signal of the memory controller 120. The first latch LC1 of the control logic CL of the selected non-volatile memory device 110_1, 110_2, 110_3, or 110_4 can latch commands and addresses CA synchronously with a clock signal CLK. The command parser CMDP of the control logic CL can parse commands and addresses CA.

[0079] According to an embodiment, at the same time (or at a similar time) as the output command and address CA, the memory controller 120 may generate a read enable signal RE, and may send the read enable signal RE to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4.

[0080] A non-volatile memory device 110_1, 110_2, 110_3, or 110_4 selected from the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may delay reading the enable signal RE to generate a data strobe signal DQS[1:m]. For example, the delay-locked loop DLL of the control logic CL may delay reading the enable signal RE to generate the data strobe signal DQS[1:m]. The data strobe signal DQS[1:m] may be transmitted to the data buffer DTB. The second driver DRV2 of the data buffer DTB may output the data strobe signal DQS[1:m]. In addition, the second driver DRV2 of the data buffer DTB may output the data DQ transmitted from the core circuitry.

[0081] After outputting the command and address CA, the memory controller 120 may receive a data strobe signal DQS[1:m] from the selected non-volatile memory device 110_1, 110_2, 110_3, or 110_4. The memory controller 120 may receive data DQ as a data signal DQ[1:n] from the selected non-volatile memory device 110_1, 110_2, 110_3, or 110_4 in synchronization with the data strobe signal DQS[1:m].

[0082] The first signal line SIGL1 and the second signal line SIGL2 can be separated from each other. The signal of the first signal line SIGL1 can be synchronized with the clock signal CLK, and the signal of the second signal line SIGL2 can be synchronized with the data strobe signal DQS. Therefore, the memory controller 120 can output a signal through the first signal line SIGL1 and receive a signal through the second signal line SIGL2 at the same time.

[0083] In one embodiment, the data DQ may be data corresponding to the current command and address CA or data corresponding to a previous command and address. In another embodiment, the memory controller 120 may send the data DQ corresponding to a previous write command to a selected non-volatile memory device 110_1, 110_2, 110_3, or 110_4.

[0084] Figure 4D An example is shown of a first non-volatile memory device 110_1, a second non-volatile memory device 110_2, a third non-volatile memory device 110_3, and a fourth non-volatile memory device 110_4 performing inter-device communication based on a data strobe signal DQS without the control of a memory controller 120. (Refer to...) Figure 2 and Figure 4D It can perform inter-device communication when the memory controller 120 does not output the clock signal CLK, the first command address signal CA1, and the second command address signal CA2.

[0085] In one embodiment, inter-device communication can be performed when the memory controller 120 transmits a data strobe signal DQS[1:m] and a data signal DQ[1:n] to a selected non-volatile memory device 110_1, 110_2, 110_3 or 110_4.

[0086] In one embodiment, one of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may be designated as a "primary non-volatile memory device," and one or more of the remaining non-volatile memory devices among the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may be designated as "auxiliary non-volatile memory devices." According to an example embodiment, the primary non-volatile memory device may be referred to as the main non-volatile memory device, and the auxiliary non-volatile memory device may be referred to as the sub-non-volatile memory device.

[0087] For example, the primary non-volatile memory device can be determined based on the internal policy of the memory controller 120 or based on the serial numbers of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. In one embodiment, the first non-volatile memory device 110_1 may be the primary non-volatile memory device. Therefore, in some example embodiments described below, the first non-volatile memory device 110_1 may be the primary non-volatile memory device.

[0088] In an example where the clock signal CLK is not received from the memory controller 120 (e.g., when a threshold time has elapsed after the clock signal CLK has been deactivated and when the primary nonvolatile memory device 110_1 communicates with the memory controller 120 using the data strobe signal DQS[1:m]), the primary nonvolatile memory device 110_1 may initiate inter-device communication. The threshold time may include, but is not limited to, a time determined during manufacturing or a time determined by the memory controller 120. In one embodiment, the read enable signal RE may also be switched based on the memory controller 120 receiving data DQ from nonvolatile memory devices 110_1, 110_2, 110_3, or 110_4.

[0089] The packet generator PKG of the control logic CL of the main nonvolatile memory device 110_1 can generate a request packet PKR for requesting inter-device communication (e.g., requesting information). The first driver DRV1 of the control logic CL of the main nonvolatile memory device 110_1 can synchronously output the request packet PKR to the signal line through which the "first command address signal CA1 and the second command address signal CA2 are transmitted" in the first signal line SIGL1, in conjunction with any of the data strobe signals DQS[1:m].

[0090] The request packet PKR can be transmitted to the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, the fourth non-volatile memory device 110_4, and the memory controller 120. The memory controller 120 may ignore the request packet PKR.

[0091] Each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can receive the request packet PKR via a first latch LC1 using control logic CL. For example, the first latch LC1 can latch the request packet PKR synchronously with any of the data strobe signals DQS[1:m].

[0092] In one embodiment, based on the activation of the chip enable signal line corresponding to each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4, the first latch LC1 of the control logic CL can latch the first command address signal CA1 and the second command address signal CA2 synchronously with the clock signal CLK. Each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can parse commands sent from the memory controller 120 using the command parser CMDP of the control logic CL.

[0093] In the example case where the clock signal CLK is not received and the data strobe signals DQS[1:m] are active (e.g., in a positive switching state), the first latch LC1 of the control logic CL of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can latch the signal of the signal line transmitting the first command address signal CA1 and the signal of the signal line transmitting the second command address signal CA2 synchronously with any of the data strobe signals DQS[1:m]. Each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can parse the request packet PKR sent from the main non-volatile memory device 110_1 using the packet parser PKP of the control logic CL.

[0094] In an example scenario where the memory controller 120 outputs a clock signal CLK while performing inter-device communication, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be configured to stop inter-device communication. For example, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can be configured to stop inter-device communication and complete preparation for receiving commands and addresses CA from the memory controller 120 before a threshold number of cycles of the clock signal CLK has elapsed since the clock signal was received (e.g., a threshold number of cycles during manufacturing or set by the memory controller 120).

[0095] Figure 4E An example is shown where a first non-volatile memory device 110_1, a second non-volatile memory device 110_2, a third non-volatile memory device 110_3, and a fourth non-volatile memory device 110_4 perform inter-device communication based on a data strobe signal DQS without the control of a memory controller 120. In one embodiment, in Figure 4E The text is a jumbled collection of characters and phrases, seemingly from different sources and lacking coherent sentences. A direct translation wouldn Figure 4D Example of the operations performed afterwards. See reference. Figure 2 and Figure 4E Inter-device communication can continue even when the memory controller 120 does not output the clock signal CLK, the first command address signal CA1, or the second command address signal CA2.

[0096] In one embodiment, inter-device communication can continue when the memory controller 120 transmits data strobe signals DQS[1:m] and data signals DQ[1:n] to the selected non-volatile memory devices 110_1, 110_2, 110_3, or 110_4. In another embodiment, the read enable signal RE can also be switched based on the memory controller 120 receiving data DQ from the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4.

[0097] In an example where the clock signal CLK is not received from the memory controller 120, each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may send a response packet PKS to the main non-volatile memory device 110_1 based on the request packet PKR. For example, in response to the request packet PKR, each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may send a response packet PKS to the main non-volatile memory device 110_1.

[0098] The packet generator PKG of the control logic CL of each of the second non-volatile memory devices 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can generate a response packet PKS to provide device information in response to a request packet PKR. The first driver DRV1 of the control logic CL of each of the second non-volatile memory devices 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can output the response packet PKS synchronously with any of the data strobe signals DQS[1:m] to the signal line through which the "first command address signal CA1 and the second command address signal CA2 are transmitted" in the first signal line SIGL1. In one example, one or more of the signal lines in the first signal line SIGL1, excluding the signal lines for transmitting the clock signal CLK and the read enable signal RE, can be used to exchange information (e.g., sending request packets PKR and response packets PKS) of the non-volatile memory devices 110_1, 110_2, 110_3 and 110_4.

[0099] The response packet PKS can be transmitted to the main non-volatile memory device 110_1 and the memory controller 120. The memory controller 120 may ignore the response packet PKS.

[0100] In one embodiment, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may sequentially output response packets PKS. The order in which the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 output response packets PKS may be determined by the memory controller 120, for example, based on a sequence number.

[0101] The main non-volatile memory device 110_1 can receive the response packet PKS via a first latch LC1 using control logic CL. For example, the first latch LC1 can latch the response packet PKS synchronously with any of the data strobe signals DQS[1:m].

[0102] In one embodiment, based on the activation of the chip enable signal corresponding to the main non-volatile memory device 110_1, the first latch LC1 of the control logic CL can latch the first command address signal CA1 and the second command address signal CA2 synchronously with the clock signal CLK. The main non-volatile memory device 110_1 can parse commands sent from the memory controller 120 using the command parser CMDP of the control logic CL.

[0103] In the example case where the clock signal CLK is not received and the data strobe signals DQS[1:m] are active (e.g., in a positive switching state), the first latch LC1 of the control logic CL of the main non-volatile memory device 110_1 can latch the signal of the signal line transmitting the first command address signal CA1 and the signal of the signal line transmitting the second command address signal CA2 synchronously with any of the data strobe signals DQS[1:m]. The main non-volatile memory device 110_1 can parse the response packets PKS sent from the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 by using the packet parser PKP of the control logic CL.

[0104] According to an embodiment, based on the parsed response packet PKS, the main non-volatile memory device 110_1 may include information from the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. The control logic CL of the main non-volatile memory device 110_1 can store and manage the information from the main non-volatile memory device 110_1 together with the information from the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4.

[0105] In an example scenario where the memory controller 120 outputs a clock signal CLK while performing inter-device communication, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be configured to stop inter-device communication. For example, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can be configured to stop inter-device communication and complete preparation for receiving commands and addresses CA from the memory controller 120 before a threshold number of cycles of the clock signal CLK has elapsed (e.g., a threshold number of cycles during manufacturing or set by the memory controller 120).

[0106] In an example where inter-device communication is stopped, the main non-volatile memory device 110_1 may discard information collected during the stopped inter-device communication. In another example where inter-device communication is stopped, the main non-volatile memory device 110_1 may store information from non-volatile memory devices that have been fully received so far (e.g., information from non-volatile memory devices that have completed the exchange), and may discard information from non-volatile memory devices that have been partially received (e.g., information from non-volatile memory devices that have not completed the exchange).

[0107] In one embodiment, such as in Figure 3 As described in the second mode, storage device 100 can be configured to an SCA mode in which inter-device communication is not performed. For example, when operations requiring frequent access are performed, inter-device communication can be deactivated to maximize throughput. For example, operations requiring frequent access may include, but are not limited to, scrub operations that verify the integrity of data stored in storage device 100.

[0108] In another example scenario where access frequency is relatively low, the changes in information of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be expected to be small based on historical data over time or user access patterns; in this case, inter-device communication can be deactivated. The activation and deactivation of inter-device communication can be determined by the memory controller 120 or an external host device communicating with the memory controller 120.

[0109] Figure 5 Examples of request packets (PKR) and response packets (PKS) according to disclosed embodiments are shown. (See also...) Figure 4D , Figure 4E and Figure 5 The information packet, including the request packet PKR or the response packet PKS, may include: a start mode including at least two start bits "S", an opcode mode including at least two opcode bits "OP", an identifier mode including at least two identifier bits "ID", a message mode including at least two message bits "M", and an end mode including at least two end bits "E".

[0110] A start mode including at least two start bits "S" can indicate the start of a packet. The second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can identify that a packet has been received by recognizing the start mode. The main non-volatile memory device 110_1 can also recognize that a packet has been received by recognizing the start mode.

[0111] An opcode pattern, including at least two opcode bits (OP), indicates whether the packet is a request packet (PKR) or a response packet (PKS). An identifier pattern, including at least two identifier bits (ID), indicates the non-volatile memory device that sent the packet.

[0112] A message pattern including at least two message bits "M" may include information. For example, the message pattern of a request packet PKR may indicate information requested or needed by the primary nonvolatile memory device 110_1. For example, the message pattern of a request packet PKR may indicate the kind (or type) of information needed or requested by the primary nonvolatile memory device 110_1. For example, the memory controller 120 may send a signal indicating the kind of information to be transmitted via a second signal line SIGL2 through a first signal line SIGL1 to a plurality of nonvolatile memory devices 110_1, 110_2, 110_3, and 110_4. The message pattern of a response packet PKS may include information from each of the second nonvolatile memory device 110_2, the third nonvolatile memory device 110_3, and the fourth nonvolatile memory device 110_4 requested via the request packet PKR.

[0113] An end pattern that includes at least two end bits "E" can indicate the end of a packet.

[0114] Figure 6A , Figure 6B , Figure 6C and Figure 6D Examples are shown of non-volatile memory devices 110_1, 110_2, 110_3 or 110_4 transmitting data bits DB of data DQ and data bits DB of request packet PKR and response packet PKS synchronously with data strobe signal DQS (e.g., any one of data strobe signal DQS[1:m]).

[0115] Reference Figure 4D , Figure 4E and Figure 6A The memory controller 120 can align the center of the data bit DB of the data DQ with the rising and falling edges of the data strobe signal DQS. For example, based on a double data rate (DDR) scheme, the data bit DB of the data DQ can be sent from the memory controller 120 to a first non-volatile memory device 110_1, a second non-volatile memory device 110_2, a third non-volatile memory device 110_3, and a fourth non-volatile memory device 110_4.

[0116] The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can align the center of the request packet PKR and the response packet PKS with the rising edge of the data strobe signal DQS. The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can transmit the request packet PKR and the response packet PKS based on a single data rate (SDR) scheme.

[0117] For example, the delay-locked loop (DLL) of the data buffer DTB in the control logic CL of non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can generate an internal clock signal aligned with the center of the data bits DB of the request packet PKR or response packet PKS, and can provide the internal clock signal to the first driver DRV1 of the control logic CL. The first driver DRV1 can output the data bits DB of the request packet PKR and response packet PKS synchronously with the internal clock signal. For example, the first driver DRV1 of the control logic CL can output the data bits DB of the request packet PKR or response packet PKS synchronously with the falling edge of the data strobe signal DQS.

[0118] The first latch LC1 of the control logic CL of the non-volatile memory device 110_1, 110_2, 110_3 or 110_4 can latch the data bits DB of the request packet PKR or the response packet PKS synchronously with the rising edge of the data strobe signal DQS.

[0119] Reference Figure 4D , Figure 4E and Figure 6B Non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can align the edges of the data bits DB of data DQ with the rising and falling edges of the data strobe signal DQS. For example, based on a double data rate (DDR) scheme, the data bits DB of data DQ can be sent from the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 to the memory controller 120.

[0120] The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can align the center of the request packet PKR and the response packet PKS with the rising edge of the data strobe signal DQS. The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can transmit the request packet PKR and the response packet PKS based on a single data rate (SDR) scheme.

[0121] For example, the delay-locked loop (DLL) of the data buffer DTB in the control logic CL of non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can generate an internal clock signal aligned with the center of the data bits DB of the request packet PKR or response packet PKS, and can provide the internal clock signal to the first driver DRV1 of the control logic CL. The first driver DRV1 can output the data bits DB of the request packet PKR and response packet PKS synchronously with the internal clock signal. For example, the first driver DRV1 of the control logic CL can output the data bits DB of the request packet PKR or response packet PKS synchronously with the falling edge of the data strobe signal DQS.

[0122] The first latch LC1 of the control logic CL of the non-volatile memory device 110_1, 110_2, 110_3 or 110_4 can latch the data bits DB of the request packet PKR or the response packet PKS synchronously with the rising edge of the data strobe signal DQS.

[0123] Reference Figure 4D , Figure 4E and Figure 6C The memory controller 120 can align the center of the data bit DB of the data DQ with the rising and falling edges of the data strobe signal DQS. For example, based on a double data rate (DDR) scheme, the data bit DB of the data DQ can be sent from the memory controller 120 to a first non-volatile memory device 110_1, a second non-volatile memory device 110_2, a third non-volatile memory device 110_3, and a fourth non-volatile memory device 110_4.

[0124] The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can align the edges of the request packet PKR and the response packet PKS with the rising edge of the data strobe signal DQS. For example, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can transmit the data bits DB of the request packet PKR or the response packet PKS synchronously with the rising edge of the data strobe signal DQS. The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can transmit the request packet PKR and the response packet PKS based on a single data rate (SDR) scheme.

[0125] For example, the delay-locked loop (DLL) of the data buffer DTB included in the control logic CL of the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can generate an internal clock signal aligned with the center of the data bits DB of the request packet PKR or response packet PKS, and can provide the internal clock signal to the first latch LC1 of the control logic CL. The first latch LC1 can latch the data bits DB of the request packet PKR and the response packet PKS synchronously with the internal clock signal. In another example, the first latch LC1 of the control logic CL can latch the data bits DB of the request packet PKR or the response packet PKS synchronously with the falling edge of the data strobe signal DQS.

[0126] Reference Figure 4D , Figure 4E and Figure 6DThe first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can align the edges of the data bits DB of data DQ with the rising and falling edges of the data strobe signal DQS. For example, based on a double data rate (DDR) scheme, the data bits DB of data DQ can be sent from the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 to the memory controller 120.

[0127] The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can align the edges of the request packet PKR and the response packet PKS with the rising edge of the data strobe signal DQS. For example, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can transmit the data bits DB of the request packet PKR or the response packet PKS synchronously with the rising edge of the data strobe signal DQS. The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can transmit the request packet PKR and the response packet PKS based on a single data rate (SDR) scheme.

[0128] For example, the delay-locked loop (DLL) of the data buffer DTB included in the control logic CL of the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can generate an internal clock signal aligned with the center of the data bits DB of the request packet PKR or response packet PKS, and can provide the internal clock signal to the first latch LC1 of the control logic CL. The first latch LC1 can latch the data bits DB of the request packet PKR and the response packet PKS synchronously with the internal clock signal. In another example, the first latch LC1 of the control logic CL can latch the data bits DB of the request packet PKR or the response packet PKS synchronously with the falling edge of the data strobe signal DQS.

[0129] Figure 7 The control logic CL and data buffer DTB according to another embodiment are shown. (See also...) Figure 1 and Figure 7 The control logic CL may include a pattern storage device MS, a first latch LC1, a delay-locked loop DLL, a first driver DRV1, a command parser CMDP, a packet generator PKG, a packet parser PKP, a voltage and current generator VCG, and a phase-locked loop PLL.

[0130] The configuration and operation of the pattern storage device MS, first latch LC1, delay-locked loop DLL, first driver DRV1, command parser CMDP, packet generator PKG, packet parser PKP, and voltage and current generator VCG can be similar to those described in the reference. Figure 2 The configuration and operation of the pattern storage device MS, the first latch LC1, the delay-locked loop DLL, the first driver DRV1, the command parser CMDP, the packet generator PKG, the packet parser PKP, and the voltage and current generator VCG are described. Therefore, additional descriptions will be omitted to avoid redundancy.

[0131] and Figure 2 Compared to the control logic CL, the control logic CL may further include a phase-locked loop (PLL). The control logic CL can generate a second clock signal for inter-device communication using the PLL. The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can perform inter-device communication using the second clock signal, without relying on the data strobe signal DQS. Therefore, the time window during which the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can perform inter-device communication can be extended.

[0132] The data buffer DTB may include a second driver DRV2 and a second latch LC2. The configuration and operation of the second driver DRV2 and the second latch LC2 can be similar to those described in the reference. Figure 2 The configuration and operation of the second driver DRV2 and the second latch LC2 are described. Therefore, additional descriptions will be omitted to avoid redundancy.

[0133] According to the disclosed embodiments, the control logic CL may include a first driver DRV1 for inter-device communication and a phase-locked loop (PLL). However, the disclosed embodiments are not limited thereto. For example, the control logic CL may transmit packets generated by the packet generator PKG to the data buffer DTB, and the second driver DRV2 of the data buffer DTB may output the packets to the first signal line SIGL1. The output of the second driver DRV2 may be demultiplexed to be output to either the first signal line SIGL1 or the second signal line SIGL2. In this case, the first driver DRV1 of the control logic CL may be omitted.

[0134] In one embodiment, the memory controller 120 can be referenced Figure 4B and Figure 4CThe first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 are accessed in the same manner as described. Therefore, additional descriptions will be omitted to avoid redundancy.

[0135] Figure 8A and Figure 8B An example of storage device 100 operating in SCA mode with inter-device communication based on a second clock signal CLK2 is shown. For example, in Figure 3 In the third mode shown, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3 and / or the fourth non-volatile memory device 110_4 perform inter-device communication based on the second clock signal CLK2 without the control of the memory controller 120.

[0136] Reference Figure 2 and Figure 8A It can perform inter-device communication when the memory controller 120 does not output the clock signal CLK, the first command address signal CA1, and the second command address signal CA2.

[0137] In one embodiment, one of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may be designated as the "primary non-volatile memory device". For example, the primary non-volatile memory device may be determined based on the internal policy of the memory controller 120 or based on the identification information of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. The identification information may include, but is not limited to, the serial numbers of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. In one embodiment, the first non-volatile memory device 110_1 may be the primary non-volatile memory device.

[0138] In an example where the clock signal CLK is not received from the memory controller 120 (e.g., when a threshold time has elapsed after the clock signal CLK has been deactivated), the primary non-volatile memory device 110_1 may initiate inter-device communication regardless of whether the primary non-volatile memory device 110_1 is transmitting the data strobe signal DQS[1:m] with the memory controller 120. The threshold time may include, but is not limited to, a time during manufacturing or determined by the memory controller 120.

[0139] The phase-locked loop (PLL) of the control logic CL of the primary non-volatile memory device 110_1 can generate a second clock signal CLK2. The PLL can send the second clock signal CLK2 to the signal line in the first signal line SIGL1 that transmits the first command address signal CA1. The second clock signal CLK2 can be transmitted to the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, the fourth non-volatile memory device 110_4, and the memory controller 120. The memory controller 120 can ignore the second clock signal CLK2. In one example, at least one signal line in the first signal line SIGL1, excluding the signal lines for transmitting the clock signal CLK and the read enable signal RE, can be used to transmit the second clock signal CLK2.

[0140] The packet generator PKG of the control logic CL of the main nonvolatile memory device 110_1 can generate a request packet PKR for requesting inter-device communication. The first driver DRV1 of the control logic CL of the main nonvolatile memory device 110_1 can output the request packet PKR synchronously with the second clock signal CLK2 to the signal line through which the second command address signal CA2 is transmitted in the first signal line SIGL1. In one embodiment, regardless of inter-device communication, the memory controller 120 can transmit a read enable signal RE, a data signal DQ[1:m], or a data DQ to the nonvolatile memory devices 110_1, 110_2, 110_3, or 110_4. In one example, at least one of the signal lines in the first signal line SIGL1 other than the signal lines transmitting the clock signal CLK, the read enable signal RE, and the second clock signal CLK2 can be used to transmit the request packet PKR.

[0141] The request packet PKR can be transmitted to the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, the fourth non-volatile memory device 110_4, and the memory controller 120. The memory controller 120 may ignore the request packet PKR.

[0142] Each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can receive the request packet PKR via a first latch LC1 using control logic CL. For example, the first latch LC1 can latch the request packet PKR synchronously with a second clock signal CLK2.

[0143] In one embodiment, based on the activation of the chip enable signal line corresponding to each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4, the first latch LC1 of the control logic CL can latch the first command address signal CA1 and the second command address signal CA2 synchronously with the clock signal CLK. Each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can parse commands sent from the memory controller 120 using the command parser CMDP of the control logic CL.

[0144] In the example case where the clock signal CLK is not received, regardless of whether the data strobe signal DQS[1:m] is active, the first latch LC1 of the control logic CL of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can latch the signal line transmitting the second command address signal CA2 synchronously with the second clock signal CLK2. Each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can parse the request packet PKR sent from the memory controller 120 using the packet parser PKP of the control logic CL.

[0145] In an example scenario where the memory controller 120 outputs a clock signal CLK while performing inter-device communication, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be configured to stop inter-device communication. For example, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can be configured to stop inter-device communication and complete preparation for receiving commands and addresses CA from the memory controller 120 before a threshold number of cycles of the clock signal CLK has elapsed. For example, the threshold number of cycles can be set during manufacturing or can be set by the memory controller 120.

[0146] Figure 8B An example is shown of a first non-volatile memory device 110_1, a second non-volatile memory device 110_2, a third non-volatile memory device 110_3, and a fourth non-volatile memory device 110_4 performing inter-device communication based on a second clock signal CLK2 without the control of a memory controller 120. Figure 8B In, according to the embodiment shown in Figure 8A The subsequent operations. (Refer to...) Figure 2 and Figure 8BInter-device communication can continue even when the memory controller 120 does not output the clock signal CLK, the first command address signal CA1, or the second command address signal CA2.

[0147] In an example where the clock signal CLK is not received from the memory controller 120, in response to a request packet PKR, each of the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may send a response packet PKS to the main non-volatile memory device 110_1. In one embodiment, regardless of inter-device communication, the memory controller 120 may pass a read enable signal RE, a data signal DQ[1:m], or data DQ to the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4.

[0148] The packet generator PKG of the control logic CL of each of the second non-volatile memory devices 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can generate a response packet PKS to provide device information in response to a request packet PKR. The first driver DRV1 of the control logic CL of each of the second non-volatile memory devices 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can output the response packet PKS synchronously with the second clock signal CLK2 received from the main non-volatile memory device 110_1 to the signal line through which the "second command address signal CA2 is transmitted" in the first signal line SIGL1.

[0149] The response packet PKS can be transmitted to the main non-volatile memory device 110_1 and the memory controller 120. The memory controller 120 may ignore the response packet PKS.

[0150] In one embodiment, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 may sequentially output response packets PKS. The order in which the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 output response packets PKS may be determined by the memory controller 120, for example, based on a sequence number.

[0151] The main non-volatile memory device 110_1 can receive the response packet PKS via a first latch LC1 using control logic CL. For example, the first latch LC1 can latch the response packet PKS synchronously with a second clock signal CLK2.

[0152] In one embodiment, based on the activation of the chip enable signal corresponding to the main non-volatile memory device 110_1, the first latch LC1 of the control logic CL can latch the first command address signal CA1 and the second command address signal CA2 synchronously with the clock signal CLK. The main non-volatile memory device 110_1 can parse commands sent from the memory controller 120 using the command parser CMDP of the control logic CL.

[0153] In the example case where the clock signal CLK is not received and the data strobe signal DQS[1:m] is active (e.g., the data strobe signal DQS[1:m] is toggling), the first latch LC1 of the control logic CL of the main non-volatile memory device 110_1 can latch the response packet PKS synchronously with the second clock signal CLK2. The main non-volatile memory device 110_1 can parse the response packet PKS sent from the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 by using the packet parser PKP of the control logic CL.

[0154] According to an embodiment, based on the parsed response packet PKS, the main non-volatile memory device 110_1 may include information from the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. The control logic CL of the main non-volatile memory device 110_1 can store and manage the information from the main non-volatile memory device 110_1 together with the information from the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4.

[0155] In an example scenario where the memory controller 120 outputs a clock signal CLK while performing inter-device communication, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be configured to stop inter-device communication. For example, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can be configured to stop inter-device communication and complete preparation for receiving commands and addresses CA from the memory controller 120 before a threshold number of cycles of the clock signal CLK has elapsed (e.g., a threshold number of cycles during manufacturing or set by the memory controller 120).

[0156] In an example where inter-device communication is stopped, the main non-volatile memory device 110_1 may discard information collected during the stopped inter-device communication. In another example where inter-device communication is stopped, the main non-volatile memory device 110_1 may store information from non-volatile memory devices that have been fully received so far, and may discard information from non-volatile memory devices that have been partially received.

[0157] In one embodiment, such as in Figure 3 As described in the second mode, storage device 100 can be configured to SCA mode, where inter-device communication is not performed. In example cases where operations requiring frequent access are performed, inter-device communication can be deactivated to maximize throughput. Operations requiring frequent access may include, but are not limited to, cleanup operations that verify the integrity of data stored in storage device 100.

[0158] In another example scenario where access frequency is relatively low, the changes in information of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can be expected to be small based on historical data over time or user access patterns; in this case, inter-device communication can be deactivated. The activation and deactivation of inter-device communication can be determined by the memory controller 120 or an external host device communicating with the memory controller 120.

[0159] Figure 9A and Figure 9B An example is shown of how the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 transmit the second clock signal CLK2 and the data bits DB of the request packet PKR or the response packet PKS.

[0160] Reference Figure 8A , Figure 8B and Figure 9A The center of the data bit DB of the main non-volatile memory device 110_1, which is sent to the signal line that transmits the second command address signal CA2, is aligned with the rising edge of the second clock signal CLK2, which is sent to the signal line that transmits the first command address signal CA1.

[0161] Reference Figure 8A , Figure 8B and Figure 9B The main non-volatile memory device 110_1 may align the edge of the data bit DB sent to the signal line that transmits the second command address signal CA2 with the rising edge of the second clock signal CLK2 sent to the signal line that transmits the first command address signal CA1.

[0162] Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E An example of storage device 100 operating in conventional mode is shown. Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E The diagram shows a first non-volatile memory device 110_1, a second non-volatile memory device 110_2, a third non-volatile memory device 110_3, and a fourth non-volatile memory device 110_4. Figure 3 An example of operation in the fourth mode.

[0163] Reference Figure 10A The control signal CS[1:j] may include the write enable signal WE, the address latch enable signal ALE, the command latch enable signal CLE, and the read enable signal RE. The first signal line SIGL1 may be configured to transmit the write enable signal WE, the address latch enable signal ALE, the command latch enable signal CLE, and the read enable signal RE.

[0164] Figure 10B This is a diagram illustrating an example of a storage device 100 performing a command input operation in conventional mode. (Refer to...) Figure 2 and Figure 10B The memory controller 120 can switch the write enable signal WE during a given time period and can activate the command latch enable signal CLE (e.g., to logic low). During the given time period, the memory controller 120 can send the command CMD to the transfer data signal DQ[1:n] in the second signal line SIGL2 in sync with the write enable signal WE.

[0165] The non-volatile memory device 110_1, 110_2, 110_3 or 110_4 among the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3 and the fourth non-volatile memory device 110_4 activated by the chip enable signal can receive the command CMD synchronously with the write enable signal WE.

[0166] In one embodiment, a signal line configured to transmit a write enable signal WE in conventional mode (or fourth mode) may correspond to a signal line configured to transmit a clock signal CLK in a first mode, second mode, or third mode.

[0167] In one embodiment, the signal line configured to transmit the command latch enable signal CLE in the conventional mode (or the fourth mode) may correspond to the signal line configured to transmit the first command address signal CA1 or the second command address signal CA2 in the first mode, the second mode, or the third mode.

[0168] Figure 10C This is a diagram illustrating an example of the storage device 100 performing an address input operation in conventional mode. (Refer to...) Figure 2 and Figure 10C The memory controller 120 can switch the write enable signal WE and activate the address latch enable signal ALE (e.g., to logic low) during a given time period. During the given time period, the memory controller 120 can send the address ADD to the transfer data signal DQ[1:n] in the second signal line SIGL2 in sync with the write enable signal WE.

[0169] The non-volatile memory device 110_1, 110_2, 110_3 or 110_4 among the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3 and the fourth non-volatile memory device 110_4 activated by the chip enable signal can receive address ADD synchronously with the write enable signal WE.

[0170] In one embodiment, a signal line configured to transmit the address latch enable signal ALE in conventional mode (or fourth mode) may correspond to a signal line configured to transmit the first command address signal CA1 or the second command address signal CA2 in a first mode, second mode, or third mode.

[0171] Figure 10D This is a diagram illustrating an example of a storage device 100 performing a data input operation in conventional mode. (Refer to...) Figure 2 and Figure 10D The memory controller 120 can switch the data strobe signal DQS[1:m] and can transmit data DQ synchronously with the data strobe signal DQS[1:m].

[0172] Figure 10E This is a diagram illustrating an example of a storage device 100 performing a data output operation in conventional mode. (Refer to...) Figure 2 and Figure 10E The memory controller 120 can switch the read enable signal RE. Non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can delay the read enable signal RE to generate a data strobe signal DQS[1:m]. Non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can transmit data DQ synchronously with the data strobe signal DQS[1:m].

[0173] Figure 11 This illustrates an example of memory controller 120 using inter-device communication. (See reference...) Figure 1 and Figure 11 In operation S210, the memory controller 120 may execute a communication COMM with the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. For example, the memory controller 120 may command any one of the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 to perform a write operation, a read operation, or an erase operation.

[0174] In operation S220, the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 can perform inter-device communication to exchange information INFO. For example, through inter-device communication, the main non-volatile memory device 110_1 can collect peak current information, temperature information, or status information from the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4.

[0175] In operation S230, the main non-volatile memory device 110_1 can report the collected information to the memory controller 120 (see reference). Figure 11 (as in "RPT"). For example, the memory controller 120 may send a status read command to the primary nonvolatile memory device 110_1 that requires information from the first nonvolatile memory device 110_1, the second nonvolatile memory device 110_2, the third nonvolatile memory device 110_3, and the fourth nonvolatile memory device 110_4. For example, based on the status read command, the primary nonvolatile memory device 110_1 may report the collected information to the memory controller 120.

[0176] In operation S240, the memory controller 120 may perform the next operation POST based on information from the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 provided from the main non-volatile memory device 110_1.

[0177] For example, based on peak current information, the memory controller 120 can perform load balancing to adjust access to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4.

[0178] For example, based on temperature information, the memory controller 120 may perform thermal throttling to adjust access to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4.

[0179] For example, based on the status information, the memory controller 120 may again perform access to the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4, or may provide a notification message to an external host device.

[0180] As described above, the memory controller 120 can access the main non-volatile memory device 110_1 to collect all information in the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4. Therefore, the memory controller 120 can easily manage the first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4.

[0181] Figure 12 This is a flowchart illustrating the operation method of a non-volatile memory device 110_1, 110_2, 110_3, or 110_4 according to a disclosed embodiment. (Refer to...) Figure 1 and Figure 12 In operation S310, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can perform inter-device communication. (See reference...) Figures 1 to 11 As described, in the example case where no clock signal CLK or command and address CA is received from memory controller 120 (or in the example case where no clock signal CLK or command and address CA is received from memory controller 120 during the threshold time), non-volatile memory devices 110_1, 110_2, 110_3 or 110_4 may initiate inter-device communication.

[0182] In operation S315, the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 may determine whether a clock signal CLK has been received. For example, the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 may determine whether a clock signal CLK has been received from the memory controller 120.

[0183] In the example case where the clock signal CLK is not received, it is expected that no command and address CA synchronized with the clock signal CLK will be received. In the example case where the clock signal CLK is not received, in operation S320, the non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can determine whether communication has ended.

[0184] In the example case where a response packet PKS is output based on (or in response to) a request packet PKR, the non-volatile memory device (e.g., 110_2, 110_3, or 110_4) that is not the primary non-volatile memory device among non-volatile memory devices 110_1, 110_2, 110_3, and 110_4 can determine the end of the communication.

[0185] In an example scenario where a request packet PKR sent to auxiliary nonvolatile memory devices 110_2, 110_3, and 110_4 has been received sequentially from auxiliary nonvolatile memory devices 110_2, 110_3, and 110_4, the primary nonvolatile memory device (e.g., 110_1) among the nonvolatile memory devices 110_1, 110_2, 110_3, and 110_4 can determine the end of communication.

[0186] In the example case where the clock signal CLK is not received ("No" in operation S315) and when communication has not ended ("No" in operation S320), in operation S325, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can continue inter-device communication. That is, in operations S315, S320, and S325, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can perform inter-device communication while monitoring the clock signal CLK.

[0187] In the example case where communication ends ("Yes" in operation S320), in operation S330, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 can complete inter-device communication. For example, the main non-volatile memory device 110_1 can store information collected from auxiliary non-volatile memory devices 110_2, 110_3, and 110_4 together with the information in the main non-volatile memory device 110_1.

[0188] For example, the main non-volatile memory device 110_1 can update previously stored information so that the latest information is stored. Optionally, the main non-volatile memory device 110_1 can add timestamp information so that information from two or more different times is stored.

[0189] In the example case of receiving clock signal CLK, it is expected that command and address CA will be received synchronously with clock signal CLK. In the example case of receiving clock signal CLK, in operation S335, non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 may terminate inter-device communication. For example, within a given number of clock cycles of clock signal CLK (e.g., within three cycles), non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 may terminate inter-device communication. Non-volatile memory devices 110_1, 110_2, 110_3, or 110_4 may terminate inter-device communication regardless of whether inter-device communication has been completed.

[0190] In operation S340, different operations can be determined based on the mode of non-volatile memory devices 110_1, 110_2, 110_3, or 110_4. In the example case where the main non-volatile memory device 110_1 is in the first mode, in operation S345, the main non-volatile memory device 110_1 may discard information associated with the terminated inter-device communication (e.g., information collected from auxiliary non-volatile memory devices 110_2, 110_3, and 110_4).

[0191] In the example case where the main non-volatile memory device 110_1 is in the second mode, during operation S365, the main non-volatile memory device 110_1 may store the information that has been fully received from the information collected from the auxiliary non-volatile memory devices 110_2, 110_3, and 110_4. Then, during operation S355, the main non-volatile memory device 110_1 may discard the information that was not fully received from the information collected from the auxiliary non-volatile memory devices 110_2, 110_3, and 110_4.

[0192] For example, the main non-volatile memory device 110_1 can update previously stored information so that the latest information is stored. Optionally, the main non-volatile memory device 110_1 can add timestamp information so that information from two or more different times is stored.

[0193] Figure 13 A storage device 200 according to another embodiment of the disclosure is shown. (See also...) Figure 13The storage device 200 may include a first non-volatile memory device 210_1, a second non-volatile memory device 210_2, a third non-volatile memory device 210_3, a fourth non-volatile memory device 210_4, a fifth non-volatile memory device 210_5, a sixth non-volatile memory device 210_6, a seventh non-volatile memory device 210_7, an eighth non-volatile memory device 210_8, and a memory controller 220.

[0194] The configuration and operation of the first non-volatile memory device 210_1, the second non-volatile memory device 210_2, the third non-volatile memory device 210_3, and the fourth non-volatile memory device 210_4 can be compared with... Figure 1 The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 are configured and operate identically. The first non-volatile memory device 210_1, the second non-volatile memory device 210_2, the third non-volatile memory device 210_3, and the fourth non-volatile memory device 210_4 can communicate with the memory controller 220 through the first channel CH1.

[0195] The configuration and operation of the fifth non-volatile memory device 210_5, the sixth non-volatile memory device 210_6, the seventh non-volatile memory device 210_7, and the eighth non-volatile memory device 210_8 can be compared with... Figure 1 The first non-volatile memory device 110_1, the second non-volatile memory device 110_2, the third non-volatile memory device 110_3, and the fourth non-volatile memory device 110_4 are configured and operate identically. The fifth non-volatile memory device 210_5, the sixth non-volatile memory device 210_6, the seventh non-volatile memory device 210_7, and the eighth non-volatile memory device 210_8 can communicate with the memory controller 220 via the second channel CH2.

[0196] Each of the first channel CH1 and the second channel CH2 may include a first signal line SIGL1 and a second signal line SIGL2. The first signal line SIGL1 may be configured to transmit a control signal CS[1:j]. The second signal line SIGL2 may be configured to transmit a data strobe signal DQS[1:m] and a data signal DQ[1:n].

[0197] The memory controller 220 can independently access and configure the first non-volatile memory device 210_1, the second non-volatile memory device 210_2, the third non-volatile memory device 210_3 and the fourth non-volatile memory device 210_4 of the first channel CH1, and the fifth non-volatile memory device 210_5, the sixth non-volatile memory device 210_6, the seventh non-volatile memory device 210_7 and the eighth non-volatile memory device 210_8 of the second channel CH2.

[0198] For example, the memory controller 220 can independently set the first non-volatile memory device 210_1, the second non-volatile memory device 210_2, the third non-volatile memory device 210_3, and the fourth non-volatile memory device 210_4 of the first channel CH1 as references. Figure 3 One of the described first, second, third, and fourth modes. Regardless of the mode of the first non-volatile memory device 210_1, second non-volatile memory device 210_2, third non-volatile memory device 210_3, and fourth non-volatile memory device 210_4 of the first channel CH1, the memory controller 220 can independently set the fifth non-volatile memory device 210_5, sixth non-volatile memory device 210_6, seventh non-volatile memory device 210_7, and eighth non-volatile memory device 210_8 of the second channel CH2 as a reference. Figure 3 One of the described first, second, third, and fourth modes. In one example, storage device 200 may also include random access memory (RAM).

[0199] Figure 14 This is a block diagram illustrating a non-volatile memory device 300 according to a disclosed embodiment. (Refer to...) Figure 14 The non-volatile memory device 300 includes a memory cell array 310, a row decoder block 320, a page data buffer block (page buffer block) 330, a pass / fail check block (PFC) 340, a data input and output block 350, a data buffer block 360, a control logic block 370, and a temperature sensor TS.

[0200] Memory cell array 310 includes multiple memory blocks BLK1 to BLKz. Each of memory blocks BLK1 to BLKz includes multiple memory cells. Each of memory blocks BLK1 to BLKz is connected to line decoder block 320 via at least one ground select line GSL, a word line WL, and at least one string select line SSL. A portion of the word line WL can be used as a dummy word line. Each of memory blocks BLK1 to BLKz is connected to page data buffer block 330 via multiple bit lines BL. Multiple memory blocks BLK1 to BLKz can be jointly connected to multiple bit lines BL.

[0201] In one embodiment, each of the plurality of memory blocks BLK1 to BLKz may correspond to a cell in an erase operation. Memory cells belonging to each memory block can be erased simultaneously. In another example, each of the memory blocks BLK1 to BLKz may be divided into multiple sub-blocks. Each of the multiple sub-blocks may correspond to a cell in an erase operation.

[0202] The row decoder block 320 is connected to the memory cell array 310 via the ground select line GSL, the word line WL, and the serial select line SSL. The row decoder block 320 operates under the control of the control logic block 370.

[0203] The row decoder block 320 can decode the row address RA received from the data buffer block 360, and can control the voltages to be applied to the serial select line SSL, word line WL and ground select line GSL based on the decoded row address.

[0204] Page data buffer block 330 is connected to memory cell array 310 via multiple bit lines BL. Page data buffer block 330 is connected to data input and output block 350 via multiple data lines DL. Page data buffer block 330 operates under the control of control logic block 370.

[0205] During programming operations, page data buffer block 330 can store data to be written into memory cells. Page data buffer block 330 can apply voltage to multiple bit lines BL based on the stored data. During read operations or verification read operations performed during programming or erase operations, page data buffer block 330 can sense the voltage of bit lines BL and store the sensing results.

[0206] In a verification read operation associated with a programming or erasing operation, pass / fail check block 340 verifies the sensing results of page data buffer block 330. For example, in a verification read operation performed during a programming operation, pass / fail check block 340 counts the number of values ​​(e.g., the number of 0s) corresponding to conduction units that are not programmed to a target threshold voltage or higher.

[0207] In the verification read operation performed during the erase operation, the pass / fail check block 340 can count the number (e.g., the number of 1s) of cutoff cells that were not erased to a target threshold voltage or lower. According to an embodiment, based on a count result greater than or equal to the threshold, the pass / fail check block 340 can output a failure signal to the control logic block 370. According to an embodiment, based on a count result less than the threshold, the pass / fail check block 340 can output a pass signal to the control logic block 370. Based on the verification result of the pass / fail check block 340, the programming loop of the programming operation or the erasure loop of the erase operation can also be executed.

[0208] Data input / output block 350 is connected to page data buffer block 330 via multiple data lines DL. Data input / output block 350 can receive column addresses CLA from data buffer block 360. Data input / output block 350 can output data read from page data buffer block 330 to data buffer block 360 based on column addresses CLA. Data input / output block 350 can also provide data received from data buffer block 360 to page data buffer block 330 based on column addresses CLA.

[0209] Data buffer block 360 can transmit data strobe signals DQS[1:m] and data signals DQ[1:n] to memory controller 120 or 220 via the second signal line SIGL2. Data buffer block 360 can operate under the control of control logic block 370. Data buffer block 360 can be connected to a reference... Figures 1 to 13 The described data buffer DTB corresponds to this.

[0210] Control logic block 370 can receive control signals CS[1:j] from memory controller 120 or 220 via the first signal line SIGL1. Control logic block 370 can be referenced... Figures 1 to 13 The control logic CL described corresponds to this.

[0211] The temperature sensor TS can sense the temperature of the non-volatile memory device 300 and generate temperature information. The temperature sensor TS can provide the temperature information to the control logic block 370. The temperature sensor TS can be disposed on the semiconductor die of the non-volatile memory device 300.

[0212] In one embodiment, the non-volatile memory device 300 can be manufactured using a bonding method. The memory cell array 310 can be manufactured using a first wafer, and the line decoder block 320, page data buffer block 330, pass / fail check block 340, data input and output block 350, data buffer block 360, and control logic block 370 can be manufactured using a second wafer. The non-volatile memory device 300 can be implemented by bonding the first wafer and the second wafer such that the upper surfaces of the first wafer and the second wafer face each other.

[0213] In another example, the non-volatile memory device 300 can be fabricated using a cell-on-periphery (COP) approach. Peripheral circuitry, including a line decoder block 320, a page data buffer block 330, a pass / fail check block 340, a data input and output block 350, a data buffer block 360, and a control logic block 370, can be implemented on the substrate. The memory cell array 310 can be implemented on the peripheral circuitry. The peripheral circuitry and the memory cell array 310 can be connected using through-vias.

[0214] Figure 15 This is a diagram of a system 1000 that utilizes a storage device according to an embodiment. Figure 15 System 1000 can essentially be a mobile system (such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device). However, Figure 15 The system 1000 is not limited to a mobile system and can be a PC, laptop computer, server, media player, or automotive device (e.g., navigation device).

[0215] Reference Figure 15 System 1000 may include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b). Furthermore, system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0216] The main processor 1100 controls all operations of the system 1000 (more specifically, including the operation of other components in the system 1000). The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0217] The main processor 1100 may include at least one CPU core 1110 and a controller 1120 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator 1130, which is dedicated circuitry for high-speed data operations, such as artificial intelligence (AI) data operations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU) and may be implemented as a chip physically separate from other components of the main processor 1100.

[0218] Memory 1200a and 1200b may be used as the main memory device of system 1000. Although each of memory 1200a and 1200b may include volatile memory (such as static random access memory (SRAM) and / or dynamic RAM (DRAM)), each of memory 1200a and 1200b may include non-volatile memory (such as flash memory, phase-change RAM (PRAM) and / or resistive RAM (RRAM)). Memory 1200a and 1200b may be implemented in the same package as main processor 1100.

[0219] Storage devices 1300a and 1300b can be used as non-volatile memory devices configured to store data regardless of whether they are powered, and have a larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b may each include storage controllers 1310a and 1310b and NVMs (non-volatile memory) 1320a and 1320b, which are configured to store data via the control of storage controllers 1310a and 1310b. Although NVMs 1320a and 1320b may include flash memory with a two-dimensional (2D) or three-dimensional (3D) V-NAND structure, NVMs 1320a and 1320b may include other types of NVMs (such as PRAM and / or RRAM).

[0220] Storage devices 1300a and 1300b may be physically separate from the main processor 1100 and included in the system 1000, or may be implemented in the same package as the main processor 1100. Furthermore, storage devices 1300a and 1300b may be various types of solid-state drives (SSDs) or memory cards, and may be removably combined with other components of the system 1000 via interfaces such as connection interface 1480, which will be described below. Storage devices 1300a and 1300b may be devices employing standard protocols such as Universal Flash Storage (UFS), embedded multimedia card (eMMC), or Non-Volatile Memory Fast (NVMe), but are not limited to these.

[0221] Image capture device 1410 can capture still images or moving images. Image capture device 1410 may include a camera, a portable video camera, and / or a webcam.

[0222] User input device 1420 can receive various types of data input by the user of system 1000, and includes a touchpad, keypad, keyboard, mouse and / or microphone.

[0223] Sensor 1430 can detect various types of physical quantities that can be obtained from outside the system 1000 and convert the detected physical quantities into electrical signals. Sensor 1430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0224] The communication device 1440 can send and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, and / or a modem.

[0225] The display 1450 and speaker 1460 can be used as output devices for a user configured to output visual and auditory information to the system 1000, respectively.

[0226] The power supply device 1470 can suitably convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000.

[0227] The connection interface 1480 provides a connection between the system 1000 and an external device that connects to the system 1000 and is able to send and receive data from the system 1000. The connection interface 1480 can be implemented using various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0228] In one embodiment, refer to Figures 1 to 14 The described storage device 100 or 200 can be implemented using storage devices 1300a and 1300b. The non-volatile memory (NVM) included in each of storage devices 1300a and 1300b may include multiple non-volatile memory devices. The multiple non-volatile memory devices can receive commands and addresses via a first signal line and transmit data bits to the memory controller via a second signal line. When commands and addresses are not received via the first signal line (e.g., when a command is not received via the first signal line), the multiple non-volatile memory devices can be configured to exchange information via the first signal line without the control of the memory controller.

[0229] In the above embodiments, the components according to the disclosure are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc., can be used to distinguish the components from each other and do not limit the disclosure. For example, the terms "first," "second," "third," etc., do not imply any form of order or numerical meaning.

[0230] In the above embodiments, components according to the disclosed embodiments are referenced by using blocks. These blocks can be implemented using various hardware devices (such as integrated circuits (ICs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven in the hardware devices, software (such as applications), or a combination of hardware devices and software. Furthermore, blocks may include circuits implemented using semiconductor elements in integrated circuits, or circuits registered as intellectual property (IP).

[0231] According to the disclosed embodiments, when no clock signal and commands and addresses synchronized with the clock signal are received, the non-volatile memory device can share information by using the signal lines through which commands and addresses are transmitted. Therefore, a storage device and a method of operating the storage device are provided that enable easier management of the non-volatile memory device.

[0232] Although the disclosure has been described with reference to the disclosed embodiments, it will be clear to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: Multiple non-volatile memory devices; as well as The memory controller is connected to the plurality of non-volatile memory devices via multiple first signal lines and also via multiple second signal lines. Each of the plurality of non-volatile memory devices is configured as follows: Based on the commands and addresses received through the plurality of first signal lines, the data bits corresponding to the commands and addresses received through the plurality of second signal lines are transmitted to the memory controller via the plurality of second signal lines. Based on the absence of a command received through the plurality of first signal lines, information is exchanged with one or more other non-volatile memory devices among the plurality of non-volatile memory devices through the plurality of first signal lines.

2. The storage device as claimed in claim 1, wherein, The information includes at least one of the peak current information, temperature information, and status information of the respective non-volatile memory device among the plurality of non-volatile memory devices.

3. The storage device as claimed in claim 1, wherein, The first of the plurality of first signal lines is configured to transmit a clock signal synchronized with the command and address in a first mode. In the second mode, based on the absence of a clock signal received via the first-first signal line, the plurality of non-volatile memory devices are configured to exchange information via one or more of the first signal lines and second-first signal lines. The one or more second-first signal lines are configured to transmit commands and addresses in a first mode.

4. The storage device as claimed in claim 3, wherein, At least one of the plurality of second signal lines is configured to transmit a data strobe signal synchronized with the data bits, and Specifically, when the memory controller transmits the data bits and data strobe signals to the plurality of non-volatile memory devices, the plurality of non-volatile memory devices are configured to exchange the information synchronously with the data strobe signals.

5. The storage device as claimed in claim 4, wherein, The primary non-volatile memory device among the plurality of non-volatile memory devices is configured to send a packet requesting the information to one or more remaining non-volatile memory devices among the plurality of non-volatile memory devices in synchronization with a data strobe signal via one or more second-first signal lines.

6. The storage device as claimed in claim 5, wherein, The packet includes at least two start bits, at least two opcode bits, at least two identifier bits, at least two message bits, and at least two end bits.

7. The storage device as claimed in claim 5, wherein, Based on the packet requesting the information, the one or more remaining non-volatile memory devices are configured to sequentially send response packets including the information to the main non-volatile memory device, synchronously with the data strobe signal, via the one or more second-first signal lines.

8. The storage device as claimed in claim 3, wherein, The plurality of non-volatile memory devices are configured to stop exchanging the information upon receiving a clock signal.

9. The storage device as claimed in claim 8, wherein, Based on the receipt of a clock signal, the plurality of non-volatile memory devices are configured to stop exchanging the information within a certain number of cycles of the clock signal starting from the start of the clock signal reception.

10. The storage device of claim 8, wherein, If the exchange of information is stopped before it is completed, the information in the exchange is discarded.

11. The storage device as claimed in claim 8, wherein, Since the exchange of information is stopped before it is completed, the information of the non-volatile memory devices that have completed the exchange is stored, and the information of the non-volatile memory devices that have not completed the exchange is discarded.

12. The storage device as claimed in claim 3, wherein, When no clock signal is received, the primary non-volatile memory device among the plurality of non-volatile memory devices outputs a second clock signal through at least one of the one or more second-first signal lines, and The plurality of non-volatile memory devices are configured to exchange information synchronously with a second clock signal via at least one of the one or more second-first signal lines.

13. The storage device of claim 12, wherein, The primary nonvolatile memory device is configured to send a packet requesting the information to the remaining nonvolatile memory devices among the plurality of nonvolatile memory devices, synchronously with a second clock signal via the additional at least one signal line.

14. The storage device of claim 13, wherein, Based on the packet requesting the information, the remaining non-volatile memory device is configured to sequentially send response packets including the information to the main non-volatile memory device via the additional at least one signal line, in synchronization with the second clock signal.

15. The storage device as claimed in claim 1, wherein, Based on a request from the memory controller, the plurality of non-volatile memory devices are configured to activate or deactivate the exchange of the information.

16. The storage device of claim 15, wherein, After the exchange of information is deactivated, in conventional mode, the memory controller is configured to transmit commands, addresses, and data bits to the plurality of non-volatile memory devices via the plurality of second signal lines, and The memory controller is configured to send a signal indicating the type of data to be transmitted through the plurality of second signal lines to the plurality of non-volatile memory devices via the plurality of first signal lines.

17. A method of operating a storage device, the storage device comprising a plurality of non-volatile memory devices and a memory controller, the method comprising: The memory controller configures the plurality of non-volatile memory devices to operate in a first mode; The memory controller transmits a first clock signal, along with commands and addresses synchronized with the first clock signal, to the plurality of non-volatile memory devices via a first signal line. In the plurality of non-volatile memory devices, data strobe signals and data bits synchronized with the data strobe signals are transmitted to the memory controller based on commands and addresses; as well as In the plurality of non-volatile memory devices, in a first mode, when the memory controller does not send a first clock signal through the first signal line, information is exchanged synchronously with the data strobe signal through the first signal line without the control of the memory controller.

18. The operating method as described in claim 17, further comprising: The memory controller configures the plurality of non-volatile memory devices to operate in a second mode; as well as With the plurality of non-volatile memory devices configured to operate in a second mode, the exchange of information via the first signal line is omitted.

19. The operating method as described in claim 17, further comprising: In the memory controller, the plurality of non-volatile memory devices are configured into a second mode; as well as In the second mode of the plurality of non-volatile memory devices, when the memory controller does not send the first clock signal through the first signal line, the information is exchanged synchronously with the second clock signal through the first signal line without the control of the memory controller.

20. A storage device, comprising: Multiple first non-volatile memory devices are connected to the first channel; Multiple second non-volatile memory devices are connected to the second channel; as well as The memory controller is connected to the first and second channels. The memory controller is configured as follows: The plurality of first non-volatile memory devices are configured to operate in one of a first mode and a second mode; and Independent of the modes configured for the plurality of first non-volatile memory devices, the plurality of second non-volatile memory devices are configured to operate in one of the first and second modes. Each of the first and second channels includes: The first signal line is configured to transmit commands and addresses; and The second signal line is configured to transmit data bits. In the first mode, the plurality of first non-volatile memory devices are configured to exchange information via the first signal line when no command is received via the first signal line, and In the second mode, the plurality of first non-volatile memory devices are configured to omit exchanging the information via the first signal line.

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