Amplification circuit and amplifier

Abstract

The embodiment of the invention provides an amplifying circuit and an amplifier. The amplifying circuit comprises an amplifying unit and a gain adjusting unit, the amplifying unit is electrically connected with a signal input end and a signal output end, and the gain adjusting unit is electrically connected with the amplifying unit; the amplification unit is used for amplifying an input signal of the signal input end and outputting the amplified signal to the signal output end; and the gain adjusting unit is used for adjusting the input impedance of the amplifying unit according to the frequency of the input signal, so that the gain of the amplifying unit is positively correlated with the frequency. The amplifying circuit provided by the invention can reduce the low-frequency-band gain and improve the high-frequency-band gain, so that the problem that the low-frequency-band gain is much higher than the high-frequency-band gain can be solved, and the gain flatness is improved.

Description

TECHNICAL FIELD

[0001] The embodiments of the present application relate to the technical field of signal amplification, in particular to an amplification circuit and an amplifier. BACKGROUND

[0002] The amplification circuit can amplify weak signals to an amplitude suitable for subsequent processing, and is a key component in low-noise amplifiers, mixers and other various amplifiers. Currently, some amplification circuits have a wide working frequency band, and there is a problem that the gain of the low frequency band is much higher than that of the high frequency band, which may cause system calibration errors and other problems.

[0003] Currently, an RC high-pass filter is added to the output end of the amplification circuit. The RC high-pass filter attenuates the gain of the high frequency band signal to a smaller extent and attenuates the gain of the low frequency band signal to a larger extent, thereby improving the problem that the gain of the low frequency band is much higher than that of the high frequency band to a certain extent.

[0004] However, the RC high-pass filter attenuates the gain of the full frequency band, which makes the high frequency band signal, which originally has a relatively low gain, even lower, and makes the signal less usable. SUMMARY

[0005] Therefore, the embodiments of the present application provide an amplification circuit and an amplifier to at least partially solve the above problems.

[0006] According to a first aspect of the embodiments of the present application, an amplification circuit includes: an amplification unit and a gain adjustment unit; the amplification unit is electrically connected with a signal input end and a signal output end respectively, and the gain adjustment unit is electrically connected with the amplification unit; the amplification unit is configured to amplify an input signal of the signal input end and output the amplified signal to the signal output end; and the gain adjustment unit is configured to adjust an input impedance of the amplification unit according to a frequency of the input signal, so that the gain of the amplification unit is positively related to the frequency.

[0007] In a possible implementation manner, the amplification unit includes: an input matching unit, a gain unit and an output matching unit; the input matching unit is electrically connected with the signal input end and an input end of the gain unit respectively, and the output matching unit is electrically connected with an output end of the gain unit and the signal output end respectively; the input matching unit is configured to output a first signal after impedance matching according to the input signal; the gain unit is configured to amplify the first signal to generate a second signal and output the second signal to the output matching unit; and the output matching unit is configured to output an output signal after impedance matching according to the second signal.

[0008] In a possible implementation, the input matching unit comprises: a first inductor and a first capacitor; a first end of the first inductor is electrically connected with the signal input end, a second end of the first inductor is electrically connected with a first end of the first capacitor, and a second end of the first capacitor is electrically connected with an input end of the gain unit.

[0009] In a possible implementation, the output matching unit comprises: a second inductor and a second capacitor; a first end of the second inductor is electrically connected with an output end of the gain unit and a first end of the second capacitor, a second end of the second inductor is electrically connected with a power supply, and a second end of the second capacitor is electrically connected with the signal output end.

[0010] In a possible implementation, the gain unit comprises: a first NMOS tube and a third inductor; a gate of the first NMOS tube is electrically connected with the second end of the first capacitor, a drain of the first NMOS tube is electrically connected with the output matching unit, a source of the first NMOS tube is electrically connected with a first end of the third inductor, and a second end of the third inductor is grounded.

[0011] In a possible implementation, the gain unit further comprises: a first bias signal source; the gate of the first NMOS tube is electrically connected with the first bias signal source.

[0012] In a possible implementation, the gain adjustment unit comprises: a third capacitor and a fourth inductor; a first end of the third capacitor is electrically connected with a first end of the third inductor, a second end of the third capacitor is electrically connected with a first end of the fourth inductor, and a second end of the fourth inductor is electrically connected with a second end of the third inductor.

[0013] In a possible implementation, the gain unit further comprises: a second NMOS tube and a fourth capacitor; a gate of the second NMOS tube is electrically connected with a first end of the fourth capacitor, a drain of the second NMOS tube is electrically connected with the output matching unit, a source of the second NMOS tube is electrically connected with the drain of the first NMOS tube, and a second end of the fourth capacitor is grounded.

[0014] In a possible implementation, the gain unit further comprises: a second bias signal source; the gate of the second NMOS tube is electrically connected with the second bias signal source.

[0015] According to a second aspect of the present application, an amplifier is provided, comprising the amplification circuit according to the first aspect of the present application.

[0016] According to the embodiment of this application, the amplifier circuit includes an amplification unit and a gain adjustment unit. The amplification unit is electrically connected to both the signal input terminal and the signal output terminal, and the gain adjustment unit is electrically connected to the amplification unit. The amplification unit amplifies the input signal at the signal input terminal and outputs the amplified signal to the signal output terminal. The gain adjustment unit adjusts the input impedance of the amplification unit according to the frequency of the input signal, so that the gain of the amplification unit is positively correlated with the frequency. By reducing the gain in the low-frequency band and increasing the gain in the high-frequency band to adjust the gain of the amplifier circuit, the problem that the gain in the low-frequency band is much higher than the gain in the high-frequency band can be improved, thereby improving the gain flatness and reducing the calibration complexity and error caused by the gain difference. Compared with the prior art, the amplifier circuit provided in this application embodiment can avoid the synchronous deterioration of the high-frequency band signal when attenuating the low-frequency band signal, can maintain the strength of the high-frequency signal, and improve the signal fidelity and availability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0018] Figure 1 This is a schematic diagram of an amplifier circuit provided in an embodiment of this application; Figure 2 This is a circuit diagram of an amplifier circuit provided in an embodiment of this application; Figure 3 This is an equivalent circuit diagram of an amplifier circuit provided in an embodiment of this application; Figure 4 This is a graph showing the impedance of the gain adjustment unit as a function of frequency. Figure 5 This is a simulation result graph showing the inductance value as a function of frequency for an amplifier circuit that does not include a gain adjustment unit. Figure 6 This is a simulation result diagram of the inductance value of the amplifier circuit provided in the embodiment of this application changing with frequency; Figure 7 This is a circuit diagram of another amplifier circuit provided in an embodiment of this application; Figure 8 This is a schematic diagram of an amplifier provided in an embodiment of this application. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0020] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0021] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0022] As mentioned earlier, amplifier circuits amplify weak signals to a suitable amplitude for subsequent processing, making them key components in low-noise amplifiers, mixers, and various other amplifiers. Currently, some amplifier circuits operate with wide bandwidths, exhibiting significantly higher gain in the low-frequency range than in the high-frequency range, potentially causing system calibration errors. Currently, this is addressed by adding an RC high-pass filter at the amplifier circuit's output. This RC high-pass filter attenuates the gain of high-frequency signals less and the gain of low-frequency signals more, thus mitigating the problem of significantly higher gain in the low-frequency range to some extent. However, attenuating the gain across the entire frequency band with an RC high-pass filter can further reduce the already low gain of high-frequency signals, decreasing signal usability.

[0023] In this embodiment, the amplification circuit includes an amplification unit and a gain adjustment unit. The amplification unit is electrically connected to both the signal input terminal and the signal output terminal, and the gain adjustment unit is electrically connected to the amplification unit. The amplification unit amplifies the input signal at the signal input terminal and outputs the amplified signal to the signal output terminal. The gain adjustment unit adjusts the input impedance of the amplification unit according to the frequency of the input signal, making the gain of the amplification unit positively correlated with the frequency. By reducing the gain in the low-frequency band and increasing the gain in the high-frequency band to adjust the gain of the amplification circuit, the problem of the low-frequency band gain being significantly higher than the high-frequency band gain can be improved, thereby improving gain flatness and reducing calibration complexity and errors caused by gain differences. Compared with the prior art, the amplification circuit provided in this embodiment can avoid the synchronous deterioration of the high-frequency band signal when attenuating the low-frequency band signal, maintain the strength of the high-frequency signal, and improve the signal fidelity and availability.

[0024] The amplifier circuit provided in this application is illustrated below through embodiments.

[0025] Figure 1 This is a schematic diagram of an amplifier circuit provided in an embodiment of this application, such as... Figure 1 As shown, the amplifier circuit 100 includes an amplification unit 101 and a gain adjustment unit 102. The amplification unit 101 is electrically connected to both the signal input terminal 10 and the signal output terminal 20, and the gain adjustment unit 102 is electrically connected to the amplification unit 101. The amplification unit 101 amplifies the input signal at the signal input terminal 10 and outputs the amplified signal to the signal output terminal 20. The gain adjustment unit 102 adjusts the input impedance of the amplification unit 101 according to the frequency of the input signal, so that the gain of the amplification unit 101 is positively correlated with the frequency.

[0026] The amplification unit 101 includes one or more transistors, which can be bipolar transistors or field-effect transistors, etc. The amplification circuit 100 amplifies the signal to be amplified input to the signal input terminal 10 through one or more transistors, and outputs the amplified signal to the signal output terminal 20.

[0027] The gain adjustment unit 102 can adjust the gain of the amplification unit 101 according to the frequency of the signal to be amplified input to the signal input terminal 10. Specifically, when the input signal frequency is low, the gain adjustment unit 102 can increase the input impedance of the amplification unit 101, thereby reducing the gain of the amplification unit 101; when the input signal frequency is high, the gain adjustment unit 102 can decrease the input impedance of the amplification unit 101, thereby increasing the gain of the amplification unit 101.

[0028] In this embodiment, the amplifier circuit 100 includes an amplification unit 101 and a gain adjustment unit 102. The amplification unit 101 is electrically connected to the signal input terminal 10 and the signal output terminal 20, respectively, and the gain adjustment unit 102 is electrically connected to the amplification unit 101. The amplification unit 101 amplifies the input signal at the signal input terminal 10 and outputs the amplified signal to the signal output terminal 20. The gain adjustment unit 102 adjusts the input impedance of the amplification unit 101 according to the frequency of the input signal, so that the gain of the amplification unit 101 is positively correlated with the frequency. By reducing the gain in the low-frequency band and increasing the gain in the high-frequency band to adjust the gain of the amplifier circuit 100, the problem that the gain in the low-frequency band is much higher than the gain in the high-frequency band can be improved, thereby improving the gain flatness and reducing the calibration complexity and error caused by the gain difference. Compared with the prior art, the amplifier circuit 100 provided in this embodiment can avoid the synchronous deterioration of the high-frequency band signal when attenuating the low-frequency band signal, can maintain the strength of the high-frequency signal, and improve the signal fidelity and availability.

[0029] Figure 2 This is a circuit diagram of an amplifier circuit 100 provided in an embodiment of this application, such as... Figure 2 As shown, the amplification unit 101 includes an input matching unit 201, a gain unit 202, and an output matching unit 203. The input matching unit 201 is electrically connected to both the signal input terminal 10 and the input terminal of the gain unit 202. The output matching unit 203 is electrically connected to both the output terminal of the gain unit 202 and the signal output terminal 20. The input matching unit 201 outputs a first signal after impedance matching based on the input signal. The gain unit 202 amplifies the first signal, generates a second signal, and outputs it to the output matching unit 203. The output matching unit 203 outputs an output signal after impedance matching based on the second signal.

[0030] Input matching unit 201 matches the impedance between the input terminal of gain unit 202 and signal input terminal 10, performs impedance matching processing on the received signal to be amplified input at signal input terminal 10, and outputs the impedance-matched input signal, i.e., the first signal, to gain unit 202. Gain unit 202 receives the first signal, amplifies it to generate an amplified first signal, i.e., the second signal, and outputs the second signal to output matching unit 203. Output matching unit 203 matches the impedance between the output terminal of gain unit 202 and signal output terminal 20, performs impedance matching processing on the received second signal, and outputs the impedance-matched second signal, i.e., the output signal, to gain unit 202.

[0031] In this embodiment, the amplification unit 101 includes an input matching unit 201, a gain unit 202, and an output matching unit 203. The input matching unit 201 is electrically connected to both the signal input terminal 10 and the input terminal of the gain unit 202. The output matching unit 203 is electrically connected to both the output terminal of the gain unit 202 and the signal output terminal 20. The input matching unit 201 outputs a first signal after impedance matching based on the input signal. The gain unit 202 amplifies the first signal, generates a second signal, and outputs it to the output matching unit 203. The output matching unit 203 outputs an output signal after impedance matching based on the second signal. By matching the impedance between the input terminal of the gain unit 201 and the signal input terminal 10, and between the input terminal of the gain unit 202 and the signal output terminal 20, respectively, impedance matching units 201 and 203 can reduce signal loss during transmission, thereby improving signal transmission efficiency. Furthermore, the matching network can avoid gain fluctuations caused by impedance mismatch, ensuring that the amplification unit 101 has a stable gain throughout the entire operating frequency band, thus improving gain stability.

[0032] In one possible implementation, such as Figure 2 As shown, the input matching unit 201 includes a first inductor Lg and a first capacitor C1. The first end of the first inductor Lg is electrically connected to the signal input terminal 10, the second end of the first inductor Lg is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is electrically connected to the input terminal of the gain unit 202.

[0033] The first inductor Lg and the first capacitor C1 form an LC matching network. The first inductor Lg provides inductive reactance in the LC matching network, and the first capacitor C1 provides capacitive reactance. By adjusting the parameters of the first inductor Lg and the first capacitor C1, the total impedance of the input matching unit 201 can be adjusted to achieve impedance matching between the output impedance of the signal input terminal 10 and the input impedance of the gain unit 202. At a specific operating frequency, the inductive reactance of the first inductor Lg and the capacitive reactance of the first capacitor C1 cancel each other out, and the total impedance of the input matching unit 201 becomes a pure resistance, the magnitude of which is equal to the output impedance of the signal input terminal 10.

[0034] In this embodiment, the input matching unit 201 includes a first inductor Lg and a first capacitor C1. A first end of the first inductor Lg is electrically connected to the signal input terminal 10, a second end of the first inductor Lg is electrically connected to the first end of the first capacitor C1, and a second end of the first capacitor C1 is electrically connected to the input terminal of the gain unit 202. By reasonably adjusting the parameters of the first inductor Lg and the first capacitor C1 to achieve impedance matching, signal transmission efficiency can be significantly improved, ensuring that the signal is transmitted from the signal input terminal 10 to the gain unit 202 to the maximum extent, reducing reflections and energy loss caused by impedance mismatch, thereby improving signal integrity and quality.

[0035] In one possible implementation, such as Figure 2 As shown, the output matching unit 203 includes a second inductor Ld and a second capacitor C2. The first end of the second inductor Ld is electrically connected to the output terminal of the gain unit 202 and the first end of the second capacitor C2. The second end of the second inductor Ld is electrically connected to the power supply, and the second end of the second capacitor C2 is electrically connected to the signal output terminal 20.

[0036] The second inductor Ld is electrically connected to both the output terminal of the gain unit 202 and the power supply, providing a DC bias path for the gain unit 202 while also providing inductive reactance in the AC signal path. The second capacitor C2 provides a low-impedance path for the AC signal, allowing the AC signal to pass while blocking DC components. By adjusting the parameters of the second inductor Ld and the second capacitor C2, the total impedance of the output matching unit 203 can be adjusted to match the output impedance of the gain unit 202 with the input impedance of the signal output terminal 20.

[0037] In this embodiment, the output matching unit 203 includes a second inductor Ld and a second capacitor C2. The first end of the second inductor Ld is electrically connected to the output terminal of the gain unit 202 and the first end of the second capacitor C2. The second end of the second inductor Ld is electrically connected to the power supply, and the second end of the second capacitor C2 is electrically connected to the signal output terminal 20. By reasonably adjusting the parameters of the second inductor Ld and the second capacitor C2, impedance matching can be achieved between the output impedance of the gain unit 202 and the input impedance of the signal output terminal 20. This ensures that the amplified signal can be transmitted to the load or subsequent circuits to the maximum extent, improving signal transmission efficiency. Furthermore, good impedance matching can reduce signal reflection and distortion during transmission, thereby improving signal integrity and quality.

[0038] In one possible implementation, such as Figure 2As shown, the gain unit 202 includes a first NMOS transistor M1 and a third inductor Ls. The gate of the first NMOS transistor M1 is electrically connected to the second terminal of the first capacitor C1, the drain of the first NMOS transistor M1 is electrically connected to the output matching unit 203, the source of the first NMOS transistor M1 is electrically connected to the first terminal of the third inductor Ls, and the second terminal of the third inductor Ls is grounded.

[0039] The first NMOS transistor M1 has a common-source configuration. A first signal is input to the gate of the first NMOS transistor M1 in voltage form. The first NMOS transistor M1 amplifies the input voltage signal through its transconductance and converts it into a second signal in current form. This second signal is then output to the output matching unit 203 through the drain of the first NMOS transistor M1. The source of the first NMOS transistor M1 is connected to ground through a third inductor Ls. The third inductor Ls resonates with the parasitic capacitance between the gate and source of the first NMOS transistor M1, generating an equivalent resistance at the gate of the first NMOS transistor M1. This provides the real part of the input impedance, achieving better input impedance matching.

[0040] In this embodiment, the gain unit 202 includes a first NMOS transistor M1 and a third inductor Ls. The gate of the first NMOS transistor M1 is electrically connected to the second terminal of the first capacitor C1, the drain of the first NMOS transistor M1 is electrically connected to the output matching unit 203, the source of the first NMOS transistor M1 is electrically connected to the first terminal of the third inductor Ls, and the second terminal of the third inductor Ls is grounded. Through the transconductance mechanism of the first NMOS transistor M1, signal amplification and gain can be achieved. Furthermore, by optimizing input impedance matching through the third inductor Ls, signal transmission efficiency and circuit performance can be improved.

[0041] In one possible implementation, such as Figure 2 As shown, the gain unit 202 also includes a first bias signal source Vb1. The gate of the first NMOS transistor M1 is electrically connected to the first bias signal source Vb1.

[0042] The first bias signal source Vb1 is electrically connected to the gate of the first NMOS transistor M1. The first bias signal source Vb1 can provide a stable DC voltage or current to the gate of the first NMOS transistor M1, enabling it to operate in the saturation region. Furthermore, by setting a suitable bias signal source, the DC level of the input signal to the gate of the first NMOS transistor M1 can be adjusted to a suitable range, matching the bias requirements of the first NMOS transistor M1.

[0043] In this embodiment, the gain unit 202 further includes a first bias signal source Vb1. The gate of the first NMOS transistor M1 is electrically connected to the first bias signal source Vb1. The stable bias signal provided by the first bias signal source Vb1 allows the first NMOS transistor M1 to operate at a suitable static operating point, maintaining its input and output impedances within the expected range. This ensures that the amplifier circuit 100 has a relatively stable gain at different input signal frequencies, improving the circuit's stability and reliability.

[0044] In one possible implementation, such as Figure 2 As shown, the gain adjustment unit 102 includes a third capacitor Cs1 and a fourth inductor Ls1. The first terminal of the third capacitor Cs1 is electrically connected to the first terminal of the third inductor Ls1, the second terminal of the third capacitor Cs1 is electrically connected to the first terminal of the fourth inductor Ls1, and the second terminal of the fourth inductor Ls1 is electrically connected to the second terminal of the third inductor Ls1.

[0045] Figure 3 This is an equivalent circuit diagram of an amplifier circuit provided in an embodiment of this application, such as... Figure 3 As shown, L L R L C L These are the equivalent output matching inductors, resistors, and capacitors, respectively. From the equivalent circuit structure, the input impedance of amplifier circuit 100 can be obtained. , where g m L is the transconductance of the first NMOS transistor M1. g Let L be the inductance value of the first inductor Lg. z Let C be the equivalent inductance of the third inductor Ls, the third capacitor Cs1, and the fourth inductor Ls1. gs This is the parasitic capacitance between the gate and source of the first NMOS transistor M1.

[0046] Figure 4 This is a graph showing the impedance of the gain adjustment unit as a function of frequency, such as... Figure 4 As shown, ω0 is the resonant point of the resonant circuit formed by the third inductor Ls and the parasitic capacitance of the first NMOS transistor M1.

[0047] When the frequency is below the resonant point ω0, the impedance of the LC series resonant structure formed by the third capacitor Cs1 and the fourth inductor Ls1 in series exhibits capacitive characteristics. According to the impedance formula of a capacitor... When the frequency is below and close to the resonant point ω0, the impedance of the LC series resonant structure is close to zero. At this time, the LC series resonant structure is equivalent to a large capacitor, which resonates in parallel with the third inductor Ls, and the overall impedance is... Because it is close to the resonance point, ,Right now Therefore, the overall impedance will be a large jωL. At this time, the third capacitor Cs1 and the fourth inductor Ls1 are equivalent to the third inductor Ls as a large inductor, which increases the real part of the input impedance and thus reduces the gain in the low-frequency range.

[0048] When the frequency is above the resonant point ω0, the impedance of the LC series resonant structure exhibits inductive behavior. According to the impedance formula for an inductor, jωL, when the frequency is above and close to the resonant point ω0, the impedance of the LC series resonant structure approaches a positive zero value. At this time, the LC series resonant structure is equivalent to a small inductor, which is connected in parallel with the Ls inductor. The total inductance in parallel is less than any single inductor in parallel. In this case, the third capacitor Cs1 and the fourth inductor Ls1 are equivalent to a small inductor as a whole with the third inductor Ls, which reduces the real part of the input impedance and thus improves the gain in the high-frequency band.

[0049] By selecting appropriate device dimensions, the overall equivalent inductance values ​​of the third capacitor Cs1 and the fourth inductor Ls1 and the third inductor Ls can be adjusted at different frequencies. This allows the gain in the low-frequency band to be the same as the gain in the high-frequency band, or the gain in the low-frequency band to be lower than the gain in the high-frequency band.

[0050] To more intuitively demonstrate the effect of the amplifier circuit 100 in the embodiments of this application on the equivalent adjustment of the amplification gain, simulations were performed on the amplifier circuit without the gain adjustment unit 102 and the amplifier circuit provided in the embodiments of this application. Figure 5 This is a simulation result graph showing the inductance value as a function of frequency for an amplifier circuit without a gain adjustment unit. Figure 6 This is a simulation result graph showing the inductance value of the amplifier circuit provided in this application as a function of frequency. Figure 5 and Figure 6 The data is summarized in the table below:

[0051] The amplifier circuit without gain adjustment unit 102 and the amplifier circuit provided in this embodiment are simulated using an EVB board + package + die_EM (removing the Ls and Ld inductors of the die and using inductor element indq). The amplifier circuit without gain adjustment unit 102 has a gain of 18.8dB at 2.0GHz and a gain of 16.2dB at 2.5GHz, with a gain difference of 2.6Hz between 2.0GHz and 2.5GHz. The amplifier circuit provided in this embodiment has a gain of 18.0dB at 2.0GHz and a gain of 16.5dB at 2.5GHz, with a gain difference of 1.5Hz between 2.0GHz and 2.5GHz.

[0052] As can be seen from the table above, the gain adjustment unit can effectively adjust the inductance value of the amplifier circuit according to the frequency, thereby increasing the inductance value at low frequencies and decreasing the inductance value at high frequencies. The simulation results of the complete circuit show that the amplifier circuit provided in this embodiment achieves improved high-frequency gain and reduces the difference between high and low frequency gains.

[0053] It should be noted that this application embodiment uses an LC series resonant structure as an example to illustrate one circuit structure design of the gain adjustment unit 102. In addition, the gain adjustment unit 102 can also be configured as an LC parallel resonant, RC resonant, or other circuit structures. Any scheme that changes the inductance value presented by the source feedback inductor (third inductor Ls) through a resonant network is within the protection scope of this application embodiment.

[0054] In this embodiment, the gain adjustment unit 102 includes a third capacitor Cs1 and a fourth inductor Ls1. The first terminal of the third capacitor Cs1 is electrically connected to the first terminal of the third inductor Ls, the second terminal of the third capacitor Cs1 is electrically connected to the first terminal of the fourth inductor Ls1, and the second terminal of the fourth inductor Ls1 is electrically connected to the second terminal of the third inductor Ls. Through the resonance of the third capacitor Cs1 and the fourth inductor Ls1, the inductance value of the third inductor Ls (i.e., the source feedback inductor) at different frequencies is effectively adjusted, thereby effectively adjusting the input impedance. This makes the gain of the amplifier circuit 100 positively correlated with the frequency, which can improve the problem that the gain in the low-frequency band is much higher than the gain in the high-frequency band, improve the gain flatness, and thus improve the system performance and stability.

[0055] Figure 7 This is a circuit diagram of another amplifier circuit provided in the embodiments of this application, such as... Figure 7 As shown, the gain unit 202 also includes a second NMOS transistor M2 and a fourth capacitor C4. The gate of the second NMOS transistor M2 is electrically connected to the first terminal of the fourth capacitor C4, the drain of the second NMOS transistor M2 is electrically connected to the output matching unit 203, the source of the second NMOS transistor M2 is electrically connected to the drain of the first NMOS transistor M1, and the second terminal of the fourth capacitor C4 is grounded.

[0056] The second NMOS transistor M2 has a common-gate structure. Utilizing the low input impedance characteristic of the common-gate second NMOS transistor M2, the second signal output from the drain of the first NMOS transistor M1 to the source of the second NMOS transistor M2 is buffered and then output to the output matching unit 203 through the drain of the second NMOS transistor M2. Furthermore, the common-gate structure has a certain noise suppression capability, which can reduce the noise figure of the circuit and improve the signal-to-noise ratio of the entire amplifier circuit 100.

[0057] The fourth capacitor, C4, is connected between the gate of the second NMOS transistor M2 and ground. This effectively isolates the DC potential of the gate of the second NMOS transistor M2 from ground, preventing the DC component of the ground potential from directly entering the gate of the second NMOS transistor M2 and affecting the normal bias of the circuit. This maintains a stable DC bias voltage at the gate of the second NMOS transistor M2. Furthermore, the fourth capacitor, C4, can filter out some high-frequency noise and interference signals, making the signal input to the second NMOS transistor M2 cleaner and more complete.

[0058] In this embodiment, the gain unit 202 further includes a second NMOS transistor M2 and a fourth capacitor C4. The gate of the second NMOS transistor M2 is electrically connected to the first terminal of the fourth capacitor C4, the drain of the second NMOS transistor M2 is electrically connected to the output matching unit 203, the source of the second NMOS transistor M2 is electrically connected to the drain of the first NMOS transistor M1, and the second terminal of the fourth capacitor C4 is grounded. Through the further transmission and processing of the second signal by the second NMOS transistor M2, the preceding common-source amplifier and the subsequent circuit can be effectively buffered and isolated, preventing the load effect of the subsequent circuit on the common-source amplifier, thereby ensuring the stability of the gain of the amplifier circuit 100. Furthermore, the fourth capacitor C4 can stabilize the gate voltage of the second NMOS transistor M2, thereby improving the stability of the amplifier circuit 100.

[0059] In one possible implementation, such as Figure 7 As shown, the gain unit 202 also includes a second bias signal source Vb2. The gate of the second NMOS transistor M2 is electrically connected to the second bias signal source Vb2.

[0060] The second bias signal source Vb2 can provide a stable bias voltage to the gate of the second NMOS transistor M2, enabling it to operate in its linear amplification region and thus amplify and transmit signals normally. By adjusting the magnitude of the bias voltage, the gain of the common-gate second NMOS transistor M2 can be adjusted, thereby indirectly affecting the gain of the entire circuit.

[0061] In this embodiment, the gain unit 202 further includes a second bias signal source Vb2. The gate of the second NMOS transistor M2 is electrically connected to the second bias signal source Vb2. The stable bias signal provided by the second bias signal source Vb2 ensures that the common-gate power transistor operates at a suitable current and voltage level under static conditions, stabilizing the static operating point of the entire circuit, providing a stable foundation for signal amplification and transmission, and improving the stability of the circuit.

[0062] Figure 8 This is a schematic diagram of an amplifier provided in an embodiment of this application, as shown below. Figure 8 As shown, the amplifier 80 includes the amplifier circuit 100 in any of the above embodiments.

[0063] Specifically, amplifier 80 can be a low-noise amplifier, a mixer, or other amplifiers.

[0064] In the embodiments of this application, the amplifier circuit 100 can be the amplifier circuit 100 in any of the above embodiments. Since it is based on the same inventive concept as the foregoing embodiments, it can achieve the same effect. The specific implementation process can be found in the description of the foregoing embodiments, and will not be repeated here.

[0065] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0066] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0067] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. An amplifier circuit, characterized in that, include: Amplification unit and gain adjustment unit; The amplification unit is electrically connected to the signal input terminal and the signal output terminal respectively, and the gain adjustment unit is electrically connected to the amplification unit; The amplification unit is used to amplify the input signal at the signal input terminal and output the amplified signal to the signal output terminal. The gain adjustment unit is used to adjust the input impedance of the amplification unit according to the frequency of the input signal, so that the gain of the amplification unit is positively correlated with the frequency.

2. The amplifier circuit according to claim 1, characterized in that, The amplification unit includes: an input matching unit, a gain unit, and an output matching unit; The input matching unit is electrically connected to the signal input terminal and the input terminal of the gain unit, respectively, and the output matching unit is electrically connected to the output terminal of the gain unit and the signal output terminal, respectively. The input matching unit is used to output a first signal after impedance matching based on the input signal; The gain unit is used to amplify the first signal, generate a second signal, and output it to the output matching unit; The output matching unit is used to output an impedance-matched output signal based on the second signal.

3. The amplifier circuit according to claim 2, characterized in that, The input matching unit includes: a first inductor and a first capacitor; The first end of the first inductor is electrically connected to the signal input terminal, the second end of the first inductor is electrically connected to the first end of the first capacitor, and the second end of the first capacitor is electrically connected to the input terminal of the gain unit.

4. The amplifier circuit according to claim 2, characterized in that, The output matching unit includes: a second inductor and a second capacitor; The first end of the second inductor is electrically connected to the output end of the gain unit and the first end of the second capacitor, the second end of the second inductor is electrically connected to the power supply, and the second end of the second capacitor is electrically connected to the signal output end.

5. The amplifier circuit according to claim 3, characterized in that, The gain unit includes: a first NMOS transistor and a third inductor; The gate of the first NMOS transistor is electrically connected to the second terminal of the first capacitor, the drain of the first NMOS transistor is electrically connected to the output matching unit, the source of the first NMOS transistor is electrically connected to the first terminal of the third inductor, and the second terminal of the third inductor is grounded.

6. The amplifier circuit according to claim 5, characterized in that, The gain unit further includes: a first bias signal source; The gate of the first NMOS transistor is electrically connected to the first bias signal source.

7. The amplifier circuit according to claim 5 or 6, characterized in that, The gain adjustment unit includes: a third capacitor and a fourth inductor; The first terminal of the third capacitor is electrically connected to the first terminal of the third inductor, the second terminal of the third capacitor is electrically connected to the first terminal of the fourth inductor, and the second terminal of the fourth inductor is electrically connected to the second terminal of the third inductor.

8. The amplifier circuit according to claim 7, characterized in that, The gain unit further includes: a second NMOS transistor and a fourth capacitor; The gate of the second NMOS transistor is electrically connected to the first terminal of the fourth capacitor, the drain of the second NMOS transistor is electrically connected to the output matching unit, the source of the second NMOS transistor is electrically connected to the drain of the first NMOS transistor, and the second terminal of the fourth capacitor is grounded.

9. The amplifier circuit according to claim 8, characterized in that, The gain unit further includes: a second bias signal source; The gate of the second NMOS transistor is electrically connected to the second bias signal source.

10. An amplifier, characterized in that, Includes the amplifier circuit described in any one of claims 1-9.

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