Clock phase calibration device, clock phase calibration method and chip

Abstract

The invention relates to a clock phase calibration device, a clock phase calibration method and a chip. The clock phase calibration device comprises a clock management module, a phase analysis module and a phase interpolator. The signal input end of the clock management module is used for receiving a clock signal, the output end of the clock management module is connected with the input end of the phase analysis module and the input end of the phase interpolator, and the output end of the phase analysis module is connected with the control end of the clock management module; the phase analysis module is used for generating a phase adjustment control code of the clock signal according to the in-phase clock signal and the orthogonal clock signal output by the clock management module; the clock management module is used for adjusting the phase between the in-phase clock signal and the orthogonal clock signal according to the phase adjustment control code to obtain a phase adjustment clock signal; and the phase interpolator is used for generating and outputting a calibration clock signal of the clock signal according to the phase adjustment clock signal. By adopting the device, the calibration effect of the clock phase calibration device can be improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a clock phase calibration device, a clock phase calibration method, and a chip. Background Technology

[0002] As data transmission rates in chips continue to increase, clock and data recovery (CDR) circuits require increasingly higher quadrature accuracy of the input I / Q clock signals. However, due to factors such as process variations, temperature fluctuations, power supply noise, and layout mismatch, there is usually a phase error between the in-phase (I) and quadrature (Q) clock signals, which makes it impossible to meet the quadrature accuracy requirements.

[0003] In related technologies, adjustable delay lines and capacitive loads are commonly used to design clock phase calibration devices to calibrate the phase error between the I and Q clock signals.

[0004] However, the clock phase calibration device in the related technology has poor calibration effect. Summary of the Invention

[0005] Therefore, it is necessary to provide a clock phase calibration device, clock phase calibration method, and chip to address the aforementioned technical problems, thereby improving the calibration effect of clock phase calibration devices in related technologies.

[0006] In a first aspect, this application provides a clock phase calibration device, which includes a clock management module, a phase analysis module, and a phase interpolator; the signal input terminal of the clock management module is used to receive clock signals, the output terminal of the clock management module is connected to the input terminal of the phase analysis module and the input terminal of the phase interpolator, and the output terminal of the phase analysis module is connected to the control terminal of the clock management module;

[0007] The phase analysis module is used to generate a phase adjustment control code for the clock signal based on the in-phase clock signal and quadrature clock signal output by the clock management module.

[0008] The clock management module is used to adjust the phase between the in-phase clock signal and the quadrature clock signal according to the phase adjustment control code to obtain a phase-adjusted clock signal;

[0009] The phase interpolator is used to adjust the clock signal according to the phase, and generate and output a calibration clock signal of the clock signal.

[0010] In one embodiment, the phase analysis module includes a deviation detection module and a digital control module; the output of the clock management module is connected to the input of the deviation detection module, the output of the deviation detection module is connected to the input of the digital control module, and the output of the digital control module is connected to the control terminal of the clock management module.

[0011] The deviation detection module is used to detect the phase difference between the in-phase clock signal and the quadrature clock signal to obtain the deviation detection result;

[0012] The digital control module is used to generate the phase adjustment control code based on at least one of the deviation detection results.

[0013] In one embodiment, the deviation detection module includes an XOR gate; the input of the XOR gate is connected to the output of the clock management module, and the output of the XOR gate is connected to the input of the digital control module.

[0014] In one embodiment, the digital control module is further configured to:

[0015] Within a preset calibration period, multiple deviation detection results are received, and an initial control code is obtained;

[0016] Compare the number of high-level signals and the number of low-level signals in the multiple deviation detection results;

[0017] If the number of high levels is greater than the number of low levels, the initial control code is adjusted in reverse to generate the phase adjustment control code;

[0018] If the number of high levels is less than the number of low levels, the initial control code is positively adjusted to generate the phase adjustment control code.

[0019] In one embodiment, the clock management module includes a buffer and a phase interpolation circuit; the signal input terminal of the buffer is used to receive a clock signal, the output terminal of the buffer is connected to the signal input terminal of the phase interpolation circuit, the control terminal of the phase interpolation circuit is connected to the output terminal of the phase analysis module, and the output terminal of the phase interpolation circuit is connected to the input terminal of the phase analysis module and the input terminal of the phase interpolator.

[0020] In one embodiment, the phase interpolation circuit includes a first phase interpolation unit and a second phase interpolation unit;

[0021] The control terminal of the first phase interpolation unit is connected to the output terminal of the phase analysis module, the signal input terminal of the first phase interpolation unit is connected to the buffer, and the output terminal of the first phase interpolation unit is connected to the input terminal of the phase analysis module and the input terminal of the phase interpolator.

[0022] The control terminal of the second phase interpolation unit is connected to the output terminal of the phase analysis module, the signal input terminal of the second phase interpolation unit is connected to the buffer, and the output terminal of the second phase interpolation unit is connected to the input terminal of the phase analysis module and the input terminal of the phase interpolator.

[0023] In one embodiment, the first phase interpolation unit includes a first field-effect transistor (FET), a second field-effect transistor (FET), and a first power supply. The drains of the first FET and the second FET are both connected to the buffer, the input terminal of the phase analysis module, and the input terminal of the phase interpolator. The sources of the first FET and the second FET are both connected to the first terminal of the first power supply. The second terminal of the first power supply is grounded, and the third terminal of the first power supply is connected to the output terminal of the phase analysis module.

[0024] In one embodiment, the second phase interpolation unit includes a third field-effect transistor, a fourth field-effect transistor, and a second power supply; the drains of the third and fourth field-effect transistors are both connected to the buffer, the input terminal of the phase analysis module, and the input terminal of the phase interpolator; the sources of the third and fourth field-effect transistors are both connected to the first terminal of the second power supply; the second terminal of the second power supply is grounded; and the third terminal of the second power supply is connected to the output terminal of the phase analysis module.

[0025] Secondly, this application provides a clock phase calibration method, applied to the phase analysis module of a clock phase calibration device as described in any one of the first aspects above, the method comprising:

[0026] The clock management module in the clock phase calibration device performs phase analysis on the in-phase clock signal and quadrature clock signal output by the clock signal, and generates the phase adjustment control code of the clock signal.

[0027] The phase adjustment control code is sent to the clock management module, instructing the clock management module to adjust the phase between the in-phase clock signal and the quadrature clock signal, and outputs the obtained phase-adjusted clock signal to the phase interpolator so that the phase interpolator generates a calibration clock signal for the clock signal.

[0028] In one embodiment, the clock management module in the clock phase calibration device performs phase analysis based on the in-phase clock signal and the quadrature clock signal output by the clock signal, and generates a phase adjustment control code for the clock signal, including:

[0029] The phase difference between the in-phase clock signal and the quadrature clock signal is detected to obtain the deviation detection result;

[0030] The phase adjustment control code is generated based on at least one deviation detection result output by the deviation detection module.

[0031] In one embodiment, generating the phase adjustment control code based on at least one deviation detection result output by the deviation detection module includes:

[0032] Within a preset calibration period, multiple deviation detection results are received, and an initial control code is obtained;

[0033] Compare the number of high-level signals and the number of low-level signals in the multiple deviation detection results;

[0034] If the number of high levels is greater than the number of low levels, the initial control code is adjusted in reverse to generate the phase adjustment control code;

[0035] If the number of high levels is less than the number of low levels, the initial control code is positively adjusted to generate the phase adjustment control code.

[0036] Thirdly, this application also provides a chip, the chip comprising: a clock phase calibration device as described in any one of the first aspects above.

[0037] The aforementioned clock phase calibration device, clock phase calibration method, and chip include a clock phase calibration device comprising a clock management module, a phase analysis module, and a phase interpolator. The signal input terminal of the clock management module receives clock signals, and its output terminal is connected to the input terminals of the phase analysis module and the phase interpolator. The output terminal of the phase analysis module is connected to the control terminal of the clock management module. The phase analysis module generates a phase adjustment control code for the clock signal based on the in-phase and quadrature clock signals output by the clock management module. The clock management module adjusts the phase between the in-phase and quadrature clock signals according to the phase adjustment control code to obtain a phase-adjusted clock signal. The phase interpolator generates and outputs a calibration clock signal based on the phase-adjusted clock signal. The embodiments of this application can accurately generate the phase adjustment control code of the clock signal through the phase analysis module, and adjust the phase deviation between the in-phase clock signal and the quadrature clock signal according to the accurate phase adjustment control code through the clock management module, so as to accurately obtain the calibrated I / Q clock signal. Therefore, the clock phase calibration device in the embodiments of this application does not need to use adjustable delay lines and capacitive loads, etc., and can achieve high-precision, low-power, real-time and adaptive calibration of the input I / Q clock signal of the CDR circuit. Thus, it can improve the calibration effect of the clock phase calibration device in related technologies to cope with the clock mismatch challenge in high-speed SERDES systems. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the clock phase calibration device in one embodiment;

[0040] Figure 2 This is a schematic diagram of the phase analysis module in one embodiment;

[0041] Figure 3 This is a schematic diagram of the clock phase calibration device in another embodiment;

[0042] Figure 4 This is a schematic diagram illustrating the impact of high-speed I / Q clock phase deviation in one embodiment;

[0043] Figure 5 This is a schematic diagram illustrating the generation of control codes in one embodiment;

[0044] Figure 6 This is a flowchart illustrating a clock phase calibration method in one embodiment;

[0045] Figure 7 This is an internal structural diagram of a computer device in one embodiment.

[0046] Explanation of reference numerals in the attached figures:

[0047] Clock management module 11; phase analysis module 12; phase interpolator 13; deviation detection module 121; digital control module 122; buffer 111; phase interpolation circuit 112; first phase interpolation unit 112a; second phase interpolation unit 112b; first field-effect transistor Q1; second field-effect transistor Q2; first power supply V1; third field-effect transistor Q3; fourth field-effect transistor Q4; second power supply V2. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0050] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0051] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0052] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0053] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0054] In high-speed SERDES (Serializer / Deserializer Parallel Converter Systems), the Clock and Data Recovery (CDR) circuit is a crucial component for ensuring reliable data reception. With the continuous increase in data transmission rates within chips, the Clock and Data Recovery (CDR) circuit demands increasingly higher quadrature accuracy from the input I / Q clock signals. Only by sampling the input data of the CDR circuit with precise in-phase (I) and quadrature (Q) clock signals can accurate clock information be output. However, due to factors such as process variations, temperature fluctuations, power supply noise, and layout mismatches, phase errors typically exist between the in-phase (I) and quadrature (Q) clock signals, leading to sampling time errors, increased bit error rate, and ultimately failing to meet the quadrature accuracy requirements.

[0055] In related technologies, analog tuning techniques are typically relied upon, such as using adjustable delay lines and capacitive loads, to design clock phase calibration devices to calibrate the phase error between the I and Q clock signals. However, clock phase calibration devices in these technologies suffer from the following technical problems: First, the calibration accuracy is limited by the minimum step size of the delay line, typically on the order of a few picoseconds, making it difficult to meet the requirements of high-speed applications; second, analog circuits are sensitive to changes in PVT (Process-Voltage-Temperature Sensitivity). Therefore, the calibration effect of clock phase calibration devices in these technologies is unsatisfactory.

[0056] After introducing the background technology of the clock phase calibration device provided in the embodiments of this application, the technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0057] In one embodiment, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a clock phase calibration device in one embodiment. A clock phase calibration device is provided, which includes a clock management module 11, a phase analysis module 12, and a phase interpolator 13. The signal input terminal of the clock management module 11 is used to receive clock signals, the output terminal of the clock management module 11 is connected to the input terminal of the phase analysis module 12 and the input terminal of the phase interpolator 13, and the output terminal of the phase analysis module 12 is connected to the control terminal of the clock management module 11.

[0058] The phase analysis module 12 is used to generate a phase adjustment control code for the clock signal based on the in-phase clock signal and quadrature clock signal output by the clock management module 11.

[0059] Clock management module 11 is used to adjust the phase between in-phase clock signal and quadrature clock signal according to phase adjustment control code to obtain phase-adjusted clock signal;

[0060] Phase interpolator 13 is used to adjust the clock signal according to the phase, generate and output a calibration clock signal of the clock signal.

[0061] The input clock signal can be four clock signals with a 90-degree phase difference. The phase adjustment control code refers to the phase interpolation control code, used to adjust the clock phase. The phase adjustment clock signal is the calibrated I / Q clock signal. The calibration clock signal is the precise, high-speed clock required by the SERDES system to ensure its normal operation.

[0062] In this embodiment, the clock phase calibration device includes a clock management module 11 (Input Buf), a phase analysis module 12, and a phase interpolator 13. The clock management module 11 (Input Buf), also known as the input delay adjustment module, processes the clock signal received at the input terminal to obtain an in-phase clock signal (I) and a quadrature clock signal (Q), and outputs the in-phase clock signal (I) and the quadrature clock signal (Q) to the phase analysis module 12. The phase analysis module 12 generates a phase adjustment control code for the clock signal based on the in-phase clock signal (I) and the quadrature clock signal (Q), and transmits the phase adjustment control code to the clock management module 11. Therefore, the clock management module 11 also adjusts the phase between the in-phase clock signal (I) and the quadrature clock signal (Q) using a phase interpolation-based structure and based on the phase adjustment control code, obtaining a phase-adjusted clock signal, and outputs the phase-adjusted clock signal to the phase interpolator 13. The phase interpolator 13 is the core component of the clock data recovery (CDR) circuit in the SERDE parallel converter system. The phase interpolator 13 is used to adjust the clock signal according to the phase, generate and output a calibration clock signal of the clock signal.

[0063] Optionally, the phase analysis module 12 can be a single chip; or, the phase analysis module 12 can be a structure employing part of a chip and part of a circuit; or, the phase analysis module 12 can be implemented entirely with circuitry. Of course, this application does not limit the specific structure of the phase analysis module 12.

[0064] The aforementioned clock phase calibration device includes a clock management module, a phase analysis module, and a phase interpolator. The signal input terminal of the clock management module receives clock signals, and its output terminal is connected to the input terminals of the phase analysis module and the phase interpolator. The output terminal of the phase analysis module is connected to the control terminal of the clock management module. The phase analysis module generates a phase adjustment control code for the clock signal based on the in-phase and quadrature clock signals output by the clock management module. The clock management module adjusts the phase between the in-phase and quadrature clock signals according to the phase adjustment control code to obtain a phase-adjusted clock signal. The phase interpolator generates and outputs a calibration clock signal based on the phase-adjusted clock signal. The embodiments of this application can accurately generate the phase adjustment control code of the clock signal through the phase analysis module, and adjust the phase deviation between the in-phase clock signal and the quadrature clock signal according to the accurate phase adjustment control code through the clock management module, so as to accurately obtain the calibrated I / Q clock signal. Therefore, the clock phase calibration device in the embodiments of this application does not need to use adjustable delay lines and capacitive loads, etc., and can achieve high-precision, low-power, real-time and adaptive calibration of the input I / Q clock signal of the CDR circuit in the SERDE system. Thus, it can improve the calibration effect of the clock phase calibration device in related technologies to cope with the clock mismatch challenge in high-speed SERDE systems.

[0065] In one embodiment, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the phase analysis module in one embodiment. The phase analysis module 12 includes a deviation detection module 121 and a digital control module 122. The output terminal of the clock management module 11 is connected to the input terminal of the deviation detection module 121, the output terminal of the deviation detection module 121 is connected to the input terminal of the digital control module 122, and the output terminal of the digital control module 122 is connected to the control terminal of the clock management module 11.

[0066] The deviation detection module 121 is used to detect the phase difference between the in-phase clock signal and the quadrature clock signal to obtain the deviation detection result;

[0067] The digital control module 122 is used to generate a phase adjustment control code based on at least one deviation detection result.

[0068] In this embodiment, the deviation detection module 121 (Xor comp) is responsible for detecting the phase difference between the I and Q clock signals in real time or at regular intervals. Specifically, the deviation detection module 121 (Xor comp) is used in a high-speed clock circuit based on XOR logic to detect the phase difference between in-phase and quadrature clock signals, and converts the phase deviation into a digital error signal to obtain the deviation detection result. Testing shows that the measurement resolution of the deviation detection module 121 reaches 0.15 ps. The digital error signal is either high or low level, and can also be referred to as the deviation detection result (cal_results).

[0069] The digital control module 122 (calibration logic) receives the digital error signal output by the deviation detection module 121 (Xor comp) in real time or at regular intervals. It employs a state machine-based adaptive algorithm to perform real-time background processing based on at least one deviation detection result, generating a phase adjustment control code (Cali_bus). A state machine (finite state automaton) is a mathematical model or design pattern used to describe the transition rules between a system or object and its finite number of states. The core of a state machine is to abstract the operating rules of real-world phenomena and clarify the relationships between states, events, transitions, and actions.

[0070] In this embodiment, the phase analysis module includes a deviation detection module and a digital control module. The deviation detection module can convert the phase information of the I / Q clock into a lead-lag binary logic, i.e., a digital error signal. Thus, the digital control module can generate a phase adjustment control code to control the clock management module based on the digital error signal. The clock delay can be adjusted according to the phase adjustment control code, thereby effectively adjusting the phase error between clock signals.

[0071] In one embodiment, such as Figure 3 As shown, Figure 3 The diagram below shows the structure of the clock phase calibration device in another embodiment. The deviation detection module 121 includes an XOR gate. The input of the XOR gate is connected to the output of the clock management module 11, and the output of the XOR gate is connected to the input of the digital control module 122.

[0072] In this embodiment, the deviation detection module can accurately detect the phase error between the in-phase clock signal and the quadrature clock signal based on the high-speed clock circuit of XOR logic. The measurement resolution of the deviation detection module 121 reaches 0.15ps.

[0073] In one embodiment, combined Figure 3 As shown, the aforementioned digital control module 122 is also used for:

[0074] Within a preset calibration period, multiple deviation detection results are received, and an initial control code is obtained;

[0075] Compare the number of high-level and low-level signals in multiple deviation detection results;

[0076] If the number of high levels is greater than the number of low levels, the initial control code is reversed to generate a phase adjustment control code.

[0077] If the number of high levels is less than the number of low levels, the initial control code is positively adjusted to generate a phase adjustment control code.

[0078] Generally, such as Figure 4 As shown, Figure 4 This is a schematic diagram illustrating the impact of high-speed I / Q clock phase deviation in one embodiment. For a CDR circuit, when there is a phase deviation in the high-speed I / Q input clock signals (i.e., clk_i and clk_q), it will cause the input clock coordinate axis to shift, degrade the linearity of the output clock, and increase the deterministic jitter (Dj) of the output clock.

[0079] In this embodiment of the application, the digital control module can pre-set a preset calibration period, an initial control code, a function relationship between delay (phase delay) and Cali_bus (the value of the control code). For example, the preset calibration period can be 100ns, the initial control code can be 000000 or 100000, and the function relationship between delay (phase delay) and Cali_bus (the value of the control code) can be a direct proportional relationship.

[0080] Therefore, the digital control module can receive multiple deviation detection results within a preset calibration period. For example, such as... Figure 5 As shown, Figure 5 This is a schematic diagram illustrating the generation of control codes in one embodiment. If the phase difference between any two clock signals is greater than 90 degrees, i.e. Figure 5 As shown in the timing diagram on the left, the deviation detection module can output 1, i.e., cal_results=1, indicating that delay is greater than 0, and the digital control module can receive a deviation detection result of 1. If the phase difference between any two clock signals is less than 90 degrees, the deviation detection module can output 0, i.e., cal_results=0, indicating that delay is less than 0, and the digital control module can receive a deviation detection result of 0. If the phase difference between any two clock signals is equal to 90 degrees, indicating that there is no phase deviation between any two clock signals, the deviation detection module can output 0, or it can output 1, indicating that delay is equal to 0, and the digital control module can receive a deviation detection result of 1 or 0.

[0081] The digital control module can compare the number of high-level (1) and low-level (0) signals in multiple deviation detection results within a preset calibration period. Combined with... Figure 5 As shown, if the number of high levels is greater than the number of low levels, the digital control module can adjust the initial control code in the opposite direction of the delay in the above functional relationship to generate a phase adjustment control code. For example, if the initial control code is 100000, then the phase adjustment control code can be 100001. If the number of high levels is less than the number of low levels, the digital control module can adjust the initial control code in the positive direction of the delay in the above functional relationship to generate a phase adjustment control code. For example, if the initial control code is 000000, then the phase adjustment control code can be 000001. The first digit of the phase adjustment control code (i.e.,...) Figure 5 The red number in the text indicates the direction of the delay.

[0082] Furthermore, if the number of high levels is equal to the number of low levels within the preset calibration period, it indicates that the distribution of high and low levels is uniform. In this case, the digital control module does not need to adjust the initial control code and can directly determine the initial control code as the phase adjustment control code.

[0083] In this embodiment, the digital control module can use adaptive calibration technology based on a state machine software background to adjust the initial control code and generate a phase adjustment control code. Thus, the calibration process can be performed in real time during data transmission without interrupting the normal operation of the system, greatly improving the availability of the system.

[0084] In one embodiment, combined Figure 3 As shown, the clock management module 11 includes a buffer 111 and a phase interpolation circuit 112. The signal input terminal of the buffer 111 is used to receive the clock signal, the output terminal of the buffer 111 is connected to the signal input terminal of the phase interpolation circuit 112, the control terminal of the phase interpolation circuit 112 is connected to the output terminal of the phase analysis module 12, and the output terminal of the phase interpolation circuit 112 is connected to the input terminal of the phase analysis module 12 and the input terminal of the phase interpolator 13.

[0085] In one embodiment, combined with Figure 3 As shown, the phase interpolation circuit 112 includes a first phase interpolation unit 112a and a second phase interpolation unit 112b.

[0086] The control terminal of the first phase interpolation unit 112a is connected to the output terminal of the phase analysis module 12, the signal input terminal of the first phase interpolation unit 112a is connected to the buffer 111, and the output terminal of the first phase interpolation unit 112a is connected to the input terminal of the phase analysis module 12 and the input terminal of the phase interpolator 13.

[0087] The control terminal of the second phase interpolation unit 112b is connected to the output terminal of the phase analysis module 12, the signal input terminal of the second phase interpolation unit 112b is connected to the buffer 111, and the output terminal of the second phase interpolation unit 112b is connected to the input terminal of the phase analysis module 12 and the input terminal of the phase interpolator 13.

[0088] In one embodiment, combined with Figure 3 As shown, the first phase interpolation unit 112a includes a first field-effect transistor Q1, a second field-effect transistor Q2, and a first power supply V1. The drains of the first field-effect transistor Q1 and the second field-effect transistor Q2 are both connected to the buffer 111, the input terminal of the phase analysis module 12, and the input terminal of the phase interpolator 13. The sources of the first field-effect transistor Q1 and the second field-effect transistor Q2 are both connected to the first terminal of the first power supply V1. The second terminal of the first power supply V1 is grounded, and the third terminal of the first power supply V1 is connected to the output terminal of the phase analysis module 12.

[0089] In one embodiment, combined with Figure 3 As shown, the second phase interpolation unit 112b includes a third field-effect transistor Q3, a fourth field-effect transistor Q4, and a second power supply V2. The drains of the third field-effect transistor Q3 and the fourth field-effect transistor Q4 are connected to the buffer 111, the input terminal of the phase analysis module 12, and the input terminal of the phase interpolator 13. The sources of the third field-effect transistor Q3 and the fourth field-effect transistor Q4 are connected to the first terminal of the second power supply V2. The second terminal of the second power supply V2 is grounded, and the third terminal of the second power supply V2 is connected to the output terminal of the phase analysis module 12.

[0090] Buffer 111 is used to receive and buffer externally input clock signals, and to output differential signals to the clkim and clkip, clkqm and clkqp ports of each interpolation unit. The first phase interpolation unit 112a and the second phase interpolation unit 112b each contain two sets of symmetrical MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistors) or diode structures, corresponding to the four input clock signals respectively. The first power supply V1 and the second power supply V2 can both be current sources or voltage sources.

[0091] In this embodiment, the gates of each field-effect transistor are connected to the input clock signal, and the sources and drains of each field-effect transistor are cross-coupled to form a current distribution network. The output of the phase analysis module 12 is the signal control terminal of the clock management module 11 (i.e., the control terminal in the above embodiment). By adjusting the control signal output by the phase analysis module 12, the weights of the two clock signals can be changed through the corresponding power supply, thereby changing the conduction degree of each device in the two phase interpolation units, and thus controlling the current ratio of each clock signal, thereby realizing continuous adjustment of the output phase.

[0092] In this embodiment, the clock management module 11 can use a phase interpolation-based tuning technique to precisely control the phase adjustment step size, which can reach 0.05ps. Thus, the phase adjustment accuracy in this embodiment is at least twice as high as that in related technologies.

[0093] As can be seen from the above embodiments, the clock phase calibration device in this application achieves high-precision compensation for I / Q clock phase errors through phase interpolation tuning technology and software adaptive calibration algorithm, significantly improving the stability of the clock data recovery (CDR) system. Compared with related technologies, this application embodiment has high calibration accuracy, reducing the phase error of the I / Q clock signal from the traditional 0.4ps level to within 0.15ps, an improvement of up to 62%; and, by adopting adaptive background calibration technology, it is robust to PVT variations, thereby improving the performance stability of high-speed SERDES systems and is applicable to data transmission systems with speeds of 112Gbps and above.

[0094] For example, the embodiments of this application are implemented using a 7nm CMOS process. Experiments show that the performance comparison between the CDR system in the embodiments of this application and the calibration methods in related technologies is shown in Table 1 below:

[0095] Table 1

[0096]

[0097] Based on the aforementioned clock phase calibration device, a clock phase calibration method is also provided. The clock phase calibration method will be described in detail below.

[0098] In one embodiment, a clock phase calibration method is provided, such as Figure 6 As shown, this method is applied to Figure 1 Taking the phase analysis module in the clock phase calibration device as an example, the following steps are included:

[0099] S201, the clock management module in the clock phase calibration device performs phase analysis on the in-phase clock signal and quadrature clock signal output by the clock signal, and generates the phase adjustment control code of the clock signal.

[0100] S202, the phase adjustment control code is sent to the clock management module, instructing the clock management module to adjust the phase between the in-phase clock signal and the quadrature clock signal, and output the obtained phase-adjusted clock signal to the phase interpolator so that the phase interpolator can generate a calibration clock signal for the clock signal.

[0101] In one embodiment, the clock management module in the clock phase calibration device performs phase analysis on the in-phase clock signal and the quadrature clock signal output by the clock signal, and generates a phase adjustment control code for the clock signal, including:

[0102] The phase difference between in-phase clock signals and quadrature clock signals is detected to obtain the deviation detection result;

[0103] A phase adjustment control code is generated based on at least one deviation detection result output by the deviation detection module.

[0104] In one embodiment, a phase adjustment control code is generated based on at least one deviation detection result output by the deviation detection module, including:

[0105] Within a preset calibration period, multiple deviation detection results are received, and an initial control code is obtained;

[0106] Compare the number of high-level and low-level signals in multiple deviation detection results;

[0107] If the number of high levels is greater than the number of low levels, the initial control code is reversed to generate a phase adjustment control code.

[0108] If the number of high levels is less than the number of low levels, the initial control code is positively adjusted to generate a phase adjustment control code.

[0109] The specific implementation methods and beneficial effects of each step in the above clock phase calibration method can be found in the descriptions in the above embodiments, and will not be repeated here.

[0110] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0111] In one exemplary embodiment, a phase analysis module is provided. This phase analysis module can be a computer device, which can be a terminal. Its internal structure diagram can be as follows: Figure 7 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a clock phase calibration method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0112] Those skilled in the art will understand that Figure 7The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0113] In one embodiment, a chip is provided, the chip including: a clock phase calibration device as described in any of the embodiments above.

[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0115] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A clock phase calibration device, characterized in that, The clock phase calibration device includes a clock management module, a phase analysis module, and a phase interpolator; the signal input terminal of the clock management module is used to receive clock signals, the output terminal of the clock management module is connected to the input terminal of the phase analysis module and the input terminal of the phase interpolator, and the output terminal of the phase analysis module is connected to the control terminal of the clock management module. The phase analysis module is used to generate a phase adjustment control code for the clock signal based on the in-phase clock signal and quadrature clock signal output by the clock management module. The clock management module is used to adjust the phase between the in-phase clock signal and the quadrature clock signal according to the phase adjustment control code to obtain a phase-adjusted clock signal; The phase interpolator is used to adjust the clock signal according to the phase, and generate and output a calibration clock signal of the clock signal.

2. The apparatus according to claim 1, characterized in that, The phase analysis module includes a deviation detection module and a digital control module; the output terminal of the clock management module is connected to the input terminal of the deviation detection module, the output terminal of the deviation detection module is connected to the input terminal of the digital control module, and the output terminal of the digital control module is connected to the control terminal of the clock management module. The deviation detection module is used to detect the phase difference between the in-phase clock signal and the quadrature clock signal to obtain the deviation detection result; The digital control module is used to generate the phase adjustment control code based on at least one of the deviation detection results.

3. The apparatus according to claim 2, characterized in that, The deviation detection module includes an XOR gate; the input of the XOR gate is connected to the output of the clock management module, and the output of the XOR gate is connected to the input of the digital control module.

4. The apparatus according to claim 2, characterized in that, The digital control module is also used for: Within a preset calibration period, multiple deviation detection results are received, and an initial control code is obtained; Compare the number of high-level signals and the number of low-level signals in the multiple deviation detection results; If the number of high levels is greater than the number of low levels, the initial control code is adjusted in reverse to generate the phase adjustment control code; If the number of high levels is less than the number of low levels, the initial control code is positively adjusted to generate the phase adjustment control code.

5. The apparatus according to any one of claims 1-4, characterized in that, The clock management module includes a buffer and a phase interpolation circuit; the signal input terminal of the buffer is used to receive clock signals, the output terminal of the buffer is connected to the signal input terminal of the phase interpolation circuit, the control terminal of the phase interpolation circuit is connected to the output terminal of the phase analysis module, and the output terminal of the phase interpolation circuit is connected to the input terminal of the phase analysis module and the input terminal of the phase interpolator.

6. The apparatus according to claim 5, characterized in that, The phase interpolation circuit includes a first phase interpolation unit and a second phase interpolation unit; The control terminal of the first phase interpolation unit is connected to the output terminal of the phase analysis module, the signal input terminal of the first phase interpolation unit is connected to the buffer, and the output terminal of the first phase interpolation unit is connected to the input terminal of the phase analysis module and the input terminal of the phase interpolator. The control terminal of the second phase interpolation unit is connected to the output terminal of the phase analysis module, the signal input terminal of the second phase interpolation unit is connected to the buffer, and the output terminal of the second phase interpolation unit is connected to the input terminal of the phase analysis module and the input terminal of the phase interpolator.

7. The apparatus according to claim 6, characterized in that, The first phase interpolation unit includes a first field-effect transistor, a second field-effect transistor, and a first power supply; the drains of the first and second field-effect transistors are connected to the buffer, the input terminal of the phase analysis module, and the input terminal of the phase interpolator; the sources of the first and second field-effect transistors are connected to the first terminal of the first power supply; the second terminal of the first power supply is grounded; and the third terminal of the first power supply is connected to the output terminal of the phase analysis module.

8. The apparatus according to claim 6, characterized in that, The second phase interpolation unit includes a third field-effect transistor, a fourth field-effect transistor, and a second power supply; the drains of the third and fourth field-effect transistors are connected to the buffer, the input terminal of the phase analysis module, and the input terminal of the phase interpolator; the sources of the third and fourth field-effect transistors are connected to the first terminal of the second power supply; the second terminal of the second power supply is grounded; and the third terminal of the second power supply is connected to the output terminal of the phase analysis module.

9. A clock phase calibration method, characterized in that, The method, applied to the phase analysis module in a clock phase calibration device as described in any one of claims 1-8, comprises: The clock management module in the clock phase calibration device performs phase analysis on the in-phase clock signal and quadrature clock signal output by the clock signal, and generates the phase adjustment control code of the clock signal. The phase adjustment control code is sent to the clock management module, instructing the clock management module to adjust the phase between the in-phase clock signal and the quadrature clock signal, and outputs the obtained phase-adjusted clock signal to the phase interpolator so that the phase interpolator generates a calibration clock signal for the clock signal.

10. The method according to claim 9, characterized in that, The step of the clock management module in the clock phase calibration device performing phase analysis on the in-phase clock signal and quadrature clock signal output by the clock signal, and generating the phase adjustment control code of the clock signal, includes: The phase difference between the in-phase clock signal and the quadrature clock signal is detected to obtain the deviation detection result; The phase adjustment control code is generated based on at least one deviation detection result output by the deviation detection module.

11. The method according to claim 10, characterized in that, The step of generating the phase adjustment control code based on at least one deviation detection result output by the deviation detection module includes: Within a preset calibration period, multiple deviation detection results are received, and an initial control code is obtained; Compare the number of high-level signals and the number of low-level signals in the multiple deviation detection results; If the number of high levels is greater than the number of low levels, the initial control code is adjusted in reverse to generate the phase adjustment control code; If the number of high levels is less than the number of low levels, the initial control code is positively adjusted to generate the phase adjustment control code.

12. A chip, characterized in that, The chip includes: a clock phase calibration device as described in any one of claims 1-8.

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