Output switching signal using capacitive element discharge

Abstract

The invention relates to an output switching signal using capacitive element discharge. A circuit for generating an output switching signal includes switching circuitry and comparison circuitry. The switching circuitry is configured to discharge the first capacitive element in response to detecting a first phase of the input switching signal, and to connect the first capacitive element in parallel with the second capacitive element in response to detecting a second phase of the input switching signal. The comparison circuitry is configured to generate an output switching signal based on a voltage at the second capacitive element.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to circuits and techniques for generating an output switching signal. BACKGROUND

[0002] Clock generators generate switching signals to support operation of circuits. For example, clock generators generate clock signals to synchronize operation of software and / or hardware components of a circuit. SUMMARY

[0003] Generally, the present disclosure is directed to techniques for low-power frequency dividers. The techniques described herein use analog frequency dividers, rather than relying solely on digital frequency dividers (e.g., cascaded D flip-flops). For example, a switching circuit device can be configured to discharge a first capacitive element in response to detecting a first phase (e.g., a logic 0) of an input switching signal, and to connect the first capacitive element and a second capacitive element (C lb ) in parallel in response to detecting a second phase (e.g., a logic 1) of the input switching signal. In this example, a comparison circuit device generates an output switching signal based on a voltage at the second capacitive element. For example, the comparison circuit device can generate an output signal having the first phase (e.g., a logic 1) when the voltage at the second capacitive element is greater than a comparison voltage, and the comparison circuit device can generate an output signal having the second phase (e.g., a logic 0) when the voltage at the second capacitive element is less than the comparison voltage. In this way, analog components can generate an output switching signal having a reduced frequency, which can reduce the amount of power consumed to generate the output switching frequency compared to systems that rely solely on digital frequency dividers.

[0004] In one example, the present disclosure describes a circuit for generating an output switching signal, the circuit comprising a switching circuit device and a comparison circuit device. The switching circuit device is configured to discharge a first capacitive element in response to detecting a first phase of an input switching signal, and to connect the first capacitive element and a second capacitive element in parallel in response to detecting a second phase of the input switching signal. The comparison circuit device is configured to generate the output switching signal based on a voltage at the second capacitive element.

[0005] In another example, the present disclosure describes a system for generating an output switching signal, the system comprising a first capacitive element, a second capacitive element, a switching circuit device, and a comparison circuit device. The switching circuit device is configured to discharge the first capacitive element in response to detecting a first phase of an input switching signal, and to connect the first capacitive element and the second capacitive element in parallel in response to detecting a second phase of the input switching signal. The comparison circuit device is configured to generate the output switching signal based on a voltage at the second capacitive element.

[0006] In one example, the disclosure describes a method for generating an output switch signal, the method comprising: discharging a first capacitive element in response to detecting a first phase of an input switch signal; connecting the first capacitive element in parallel with a second capacitive element in response to detecting a second phase of the input switch signal; and generating the output switch signal based on a voltage at the second capacitive element.

[0007] These and other examples are set forth in the following detailed description of the application. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 FIG. 1 is a block diagram illustrating an example first system for generating an output switch signal, in accordance with one or more techniques of the present disclosure.

[0009] Figure 2A FIG. 2 is a circuit diagram illustrating an example current-limited complementary metal-oxide-semiconductor (CMOS) inverter, in accordance with one or more techniques of the present disclosure.

[0010] Figure 2B FIG. 3 is a circuit diagram illustrating an example current-limited NAND gate for reducing power consumption of a digital frequency divider, in accordance with one or more techniques of the present disclosure.

[0011] Figure 3 FIG. 4 is a block diagram illustrating an example digital frequency divider, in accordance with one or more techniques of the present disclosure.

[0012] Figure 4 FIG. 5 is a block diagram illustrating an example second system for generating an output switch signal, in accordance with one or more techniques of the present disclosure.

[0013] Figure 5 FIG. 6 is a circuit diagram illustrating an example second system for generating an output switch signal, in accordance with one or more techniques of the present disclosure. Figure 4

[0014] Figure 6 FIG. 7 is a plot illustrating an input switch signal, a voltage at a second capacitive element, a voltage at a fourth capacitive element, an output switch signal, and a sample signal, in accordance with one or more techniques of the present disclosure.

[0015] Figure 7 FIG. 8 is a conceptual diagram illustrating an example system for generating an output switch signal using both an analog frequency divider and a digital frequency divider, in accordance with one or more techniques of the present disclosure.

[0016] Figure 8 FIG. 9 is a flow diagram illustrating an example process for generating an output switch signal, in accordance with one or more techniques of the present disclosure. DETAILED DESCRIPTION​

[0017] Figure 1 is a block diagram illustrating an example first system for generating an output switch signal according to one or more techniques of the present disclosure. As Figure 1 As shown in the example, the system 100 can include a circuit 102. The circuit 102 includes a switching circuit device 110, a first capacitive element 112, a second capacitive element 114, and a comparison circuit device 116.

[0018] The first capacitive element 112 and the second capacitive element 114 can each include an electrical component configured to store electrical energy in an electric field. Examples of electrical components configured to store electrical energy in an electric field can include, but are not limited to, ceramic capacitors, film capacitors, electrolytic capacitors (e.g., aluminum, tantalum, niobium, etc.), supercapacitors (e.g., double layer capacitors, pseudo capacitors, hybrid capacitors), mica capacitors, etc. Although the first capacitive element 112 and the second capacitive element 114 can each be described as an element, the first capacitive element 112 and / or the second capacitive element 114 can each be an array of capacitive elements. For example, the first capacitive element 112 can be an array of capacitive elements coupled in parallel and / or in series. Each of the capacitive elements can be included in a single chip implementation of the circuit 102 (e.g., a monolithic integrated circuit). However, in some examples, one or more of the capacitive elements can be formed using one or more discrete components (e.g., capacitor arrays) that are discrete from other components of the circuit 102.

[0019] The switching circuit device 110 can be configured to electrically connect a node of the first capacitive element 112 and a node of the second capacitive element 114 based on the input switch signal. For example, the switching circuit device 110 can cause the first capacitive element 112 to discharge in response to detecting a first phase (e.g., a logic 0 or a logic 1) of the input switch signal. For example, the switching circuit device 110 can couple the nodes (e.g., positive and negative nodes) of the first capacitive element 112 to a power node (e.g., a voltage node or a ground node) in response to detecting the first phase of the input switch signal.

[0020] The switching circuit device 110 can connect the first capacitive element 112 and the second capacitive element 114 in parallel in response to detecting a second phase (e.g., a logic 1 or a logic 0) of the input switch signal. Connecting the first capacitive element 112 and the second capacitive element 114 in parallel transfers the charge stored at the second capacitive element 114 to the first capacitive element 112. As described in further detail with respect to Figure 6 The switching circuit device 110 causing the first capacitive element 112 to discharge and connecting the first capacitive element 112 and the second capacitive element 114 in parallel can result in an exponential transient behavior of the voltage at the second capacitive element 114, as described in further detail.

[0021] Examples of switching elements can include, but are not limited to, silicon controlled rectifiers (SCRs), field effect transistors (FETs), and bipolar junction transistors (BJTs). Examples of FETs can include, but are not limited to, junction field effect transistors (JFETs), metal oxide semiconductor FETs (MOSFETs), dual gate MOSFETs, insulated gate bipolar transistors (IGBTs), any other type of FET, or any combination of the same. Examples of MOSFETs can include, but are not limited to, depletion mode p-channel MOSFETs (PMOS), enhancement mode PMOS, depletion mode n-channel MOSFETs (NMOS), enhancement mode NMOS, double-diffused MOSFETs (DMOS), any other type of MOSFET, or any combination of the same. Examples of BJTs can include, but are not limited to, PNP, NPN, heterojunction, or any other type of BJT, or any combination of the same. The switching elements can be high-side switching elements or low-side switching elements.

[0022] The comparison circuitry 116 can be configured to generate an output switching signal based on the voltage at the second capacitive element 114. For example, when the voltage at the second capacitive element 114 is greater than a reference voltage (e.g., a preconfigured voltage), the comparison circuitry 116 can generate the output switching signal to indicate a first phase (e.g., a logic 1 or a logic 0). In this example, when the voltage at the second capacitive element 114 is not greater than the reference voltage, the comparison circuitry 116 can generate the output switching signal to indicate a second phase. In this way, the system 100 can generate an output switching signal having a lower frequency than the input switching signal, which can reduce the amount of power consumed by the system 100 as compared to systems that rely solely on digital frequency dividers (e.g., cascaded D flip-flops) to generate the output switching signal.

[0023] Figure 2A is a circuit diagram illustrating an example current limited complementary metal oxide semiconductor (CMOS) inverter 200 in accordance with one or more techniques of the present disclosure. As shown, the CMOS inverter 200 includes transistors 230-233.

[0024] Power consumption is an important parameter for efficient or battery operated systems, such as, for example, automotive systems, when the car is off. In some systems, for example when the car is off, several blocks (e.g., frequency dividers) can remain active and consume a significant amount of power. To help reduce power consumption, the CMOS inverter 200 can limit current during a cross-over. The examples described herein that use D flip-flops can optionally include a current limiting device (e.g., the CMOS inverter 200).

[0025] Figure 2Bis a circuit diagram illustrating an example current limited NAND gate 201 for reducing power consumption of a digital frequency divider in accordance with one or more techniques of this disclosure. As shown, the NAND gate 201 includes transistors 240-245, which can be configured to limit current during a cross-over to help reduce power consumption. Examples described herein that use D flip-flops can optionally include a current limited device (e.g., the NAND gate 201).

[0026] Figure 3 is a block diagram illustrating an example digital frequency divider 300 in accordance with one or more techniques of this disclosure. As shown, the digital frequency divider 300 includes cascaded D flip-flops 301-310. The D flip-flops 301-310 can use one or more of the current limiting blocks of Figure 2A or Figure 2B Examples described herein that use an analog digital frequency divider can optionally include a digital frequency divider. For example, the output switch signal of the circuit 102 of Figure 1 may be used as a clock input (e.g., f in ) of the D flip-flops 301. While Figure 3 Examples illustrate ten D flip-flops, other examples of a digital frequency divider can include fewer than ten or more than ten D flip-flops.

[0027] Figure 4 is a block diagram illustrating an example second system for generating an output switch signal in accordance with one or more techniques of this disclosure. As Figure 4 illustrated by the example of Figure 1 , the system 400 can include a circuit 402. The circuit 402 includes a switching circuitry 410, a first capacitive element 412, a second capacitive element 414, and a comparison circuitry 416, which can be similar to the switching circuitry 110, the first capacitive element 112, the second capacitive element 114, and the comparison circuitry 116 of

[0028] Similar to Figure 1The switching circuit device 410 can discharge the first capacitive element 412 in response to detecting the first phase of the input switching signal. For example, the switching circuit device 110 can couple the nodes (e.g., positive and negative nodes) of the first capacitive element 112 to a power supply node (e.g., a voltage node or a ground node) in response to detecting the first phase of the input switching signal. The switching circuit device 410 can connect the first capacitive element 412 and the second capacitive element 414 in parallel in response to detecting the second phase of the input switching signal (e.g., a logic 1 or a logic 0). The switching circuit device 410 discharges the first capacitive element 412 and connects the first capacitive element 412 and the second capacitive element 414 in parallel, which can cause the voltage at the second capacitive element 414 to have an exponential behavior (e.g., exponentially increase or decrease).

[0029] In Figure 4 In this example, the switching circuit device 410 can discharge the third capacitive element 420 in response to detecting the first phase of the input switching signal. In this example, the switching circuit device 410 can connect the third capacitive element 420 and the fourth capacitive element 422 in parallel in response to detecting the second phase of the input switching signal. The switching circuit device 410 discharges the third capacitive element 420 and connects the third capacitive element 420 and the fourth capacitive element 422 in parallel, which can cause the voltage at the fourth capacitive element 422 to have an exponential behavior (e.g., exponentially decrease or increase). In this way, the comparison of the voltage at the second capacitive element 414 to the voltage at the fourth capacitive element 422 depends only on the capacitor ratio and is independent of both the absolute capacitance and the source voltage (e.g., the voltage used to charge the second capacitive element 141 and / or the fourth capacitive element 422), which can facilitate improved accuracy of the system 400 compared to systems that rely on a reference voltage (e.g., a pre-defined voltage).

[0030] The comparison circuit device 416 can generate the output signal based on the voltage at the second capacitive element 414 and also based on the voltage at the fourth capacitive element 422. For example, the comparison circuit device 416 can generate the output switching signal to indicate the first phase when the voltage at the second capacitive element 414 is greater than the voltage at the fourth capacitive element 422. In this example, the comparison circuit device 416 can generate the output switching signal to indicate the second phase when the voltage at the second capacitive element 414 is not greater than the voltage at the fourth capacitive element 422.

[0031] Figure 5 is a circuit diagram illustrating an example second system according to one or more techniques of the present disclosure. Figure 4 The circuit 500 can represent an analog frequency divider. In this example, the circuit 500 can include a first switching circuit device 510, a second switching circuit device 512, a first capacitive element 514, a second capacitive element 516, a third capacitive element 518, a fourth capacitive element 520, and a comparison circuit device 522.Figure 5 In the example, circuit 500 may include a first power node 559 (e.g., a voltage node) and a second power node 561 (e.g., a ground node or a reference node), a first capacitive element 512, a second capacitive element 514, a third capacitive element 520, a fourth capacitive element 522, a comparator circuit arrangement 516, and a time delay module 518. Figure 5 In the example, the switching circuit device 510 includes a first switching element 560, a second switching element 562, a third switching element 570, a fourth switching element 572, a first sampling switching element 564, and a second sampling switching element 566. The second capacitive element 514 and the fourth capacitive element 522 may have relatively large capacitances and may be referred to herein as “large capacitors” or simply “C”. LB “C” LA For example, the second capacitive element 514 may have a larger capacitance than the first capacitive element 512. Similarly, the fourth capacitive element 522 may have a larger capacitance than the third capacitive element 520.

[0032] like Figure 5 As shown, the first capacitive element 512 includes a second node and a first node coupled to the power supply node 559. The second capacitive element 514 includes a second node and a first node coupled to the power supply node 559. In this example, the first switching element 560 includes a first node coupled to the power supply node 559 and a second node coupled to the second node of the first capacitive element 512. The second switching element 562 includes a first node coupled to the second node of the first capacitive element 512 and a second node coupled to the second node of the second capacitive element 514.

[0033] The switching circuit device 510, or more specifically, the first sampling switching element 564, can be configured to charge the second capacitive element 514 to the supply voltage (e.g., the voltage at power node 559). Similarly, the switching circuit device 510, or more specifically, the second sampling switching element 566, can be configured to charge the fourth capacitive element 522 to the supply voltage (e.g., the voltage at power node 559). For example, in response to a sampling phase ('S'), the first sampling switching element 564 can charge the second capacitive element 514, and the second sampling switching element 566 can charge the fourth capacitive element 522. Regarding Figure 6 Let's discuss the sampling phase in more detail.

[0034] In response to detecting the first phase of the input switch signal ('1'), the switch circuit arrangement 510, or more specifically, the first switch element 560 can discharge the first capacitive element 512. For example, in response to detecting the first phase of the input switch signal ('1'), the first switch element 560 can connect both the first node of the first capacitive element 512 and the second node of the first capacitive element 512 to the power supply node 559. For example, the first switch element 560 can be configured to operate in an open state during the second phase of the input switch signal and operate in a closed state during the first phase of the input switch signal. In this example, the second switch element 562 can be configured to operate in a closed state during the second phase of the input switch signal ('2') and operate in an open state during the first phase of the input switch signal.

[0035] Similarly, the third capacitive element 520 includes a second node and a first node coupled to the power supply node 561. The fourth capacitive element 522 includes a second node and a first node coupled to the power supply node 561. In this example, the third switch element 570 includes a first node coupled to the power supply node 561 and a second node coupled to the second node of the third capacitive element 520. The fourth switch element 572 includes a first node coupled to the second node of the first capacitive element 512 and a second node coupled to the second node of the second capacitive element 514. Although Figure 5 Examples of the first capacitive element and the second capacitive element are referred to as being coupled to the power supply node 559 (e.g., a voltage node) in some examples, the first capacitive element and the second capacitive element are coupled to the power supply node 561 (e.g., a ground node or a reference node).

[0036] In response to detecting the first phase of the input switch signal, the switch circuit arrangement 510, or more specifically, the third switch element 570 can connect both the first node of the third capacitive element 520 and the second node of the third capacitive element 520 to the power supply node 561. For example, the third switch element 570 can be configured to operate in an open state during the second phase of the input switch signal and operate in a closed state during the first phase of the input switch signal.

[0037] In response to detecting the second phase of the input switch signal, the switch circuit 510, or more specifically, the fourth switch element 572 can connect the first capacitive element and the second capacitive element in parallel. For example, the fourth switch element 572 can be configured to operate in a closed state during the second phase of the input switch signal and operate in an open state during the first phase of the input switch signal.

[0038] The comparator circuit 516 can generate an output signal based on the voltage at the second capacitive element 514 and also based on the voltage at the fourth capacitive element 522. For example, when the voltage at the second capacitive element 514 is greater than the voltage at the fourth capacitive element 522, the comparator circuit 516 can generate an output switching signal to indicate a first stage. In this example, when the voltage at the second capacitive element 514 is not greater than the voltage at the fourth capacitive element 522, the comparator circuit 516 can generate an output switching signal to indicate a second stage. The comparator circuit 516 may include a comparator 515 and a time delay module 617. The time delay module 617 can reset the output switching signal after a time delay (e.g., the reciprocal of the frequency of the input switching signal).

[0039] Figure 6 The diagram illustrates the voltage at the input switch signal 602 and the second capacitive element 604 according to one or more techniques of this disclosure (see Figure 1). Figure 5 V b (t)), the voltage at the fourth capacitive element 606 (for example, see Figure 5 V a The graph shows the time (t), the output switch signal 608, and the sampling signal 610. The horizontal axis (i.e., the x-axis or horizontal coordinate axis) represents time (t).

[0040] For illustrative purposes only, see reference. Figures 1-5 discuss Figure 6 Circuit 500 may operate in sampling phase 620 in response to the detection of a pulse (e.g., logic '1') or a voltage exceeding a threshold in sampling signal 610. During sampling phase 620, first sampling switching element 564 may precharge second capacitive element 514. For example, first switching element 560 may connect first capacitive element 512 to power node 559 (e.g., VDD) during sampling phase 620. During sampling phase 620, second switching element 562 may prevent first capacitive element 512 from being connected in parallel with second capacitive element 514. For example, second switching element 562 may operate in an off state during sampling phase 620.

[0041] Similarly, the second sampling switch element 566 can precharge the fourth capacitive element 522. In some examples, the third switch element 570 can connect the third capacitive element 520 to the power node 561 (e.g., GND) during the sampling phase 620. During the sampling phase 620, the fourth switch element 572 can avoid connecting the third capacitive element 520 and the fourth capacitive element 522 in parallel. For example, the fourth switch element 572 can operate in an off state during the sampling phase 620.

[0042] After sampling phase 620 and during analog divider phase 622, the first sampling switch element 564 and the second sampling switch element 566 can be turned off (e.g., operated in an off state) until another sampling phase (e.g., sampling phase 624). During analog divider phase 622, the switching circuit device 510 can be based on the input switching signal 602 (e.g., f...). in It operates in the first stage ('1') and the second stage ('2'). For example, the frequency f of the input switch signal 602. in The sequence of clock phases 1 and 2 can control the switching of the switching circuit device 510 in the next operation phase as follows. As shown in the figure, there can be multiple first and second phase operations during the analog frequency divider phase 622. Figure 6 The analog divider stage 622 with four first stages and four second stages is illustrated for illustrative purposes only. In some examples, the analog divider stage 622 may include more or fewer than four first stages and / or the analog divider stage 622 may include more or fewer than four second stages.

[0043] During the first phase of the input switch signal 602, the switch circuit device 510 can cause the first capacitive element 512 and the third capacitive element 520 (e.g., C) to... Sa,b Discharge. For example, the first switching element 560 may connect both the first node and the second node of the first capacitive element 512 to the power supply node 559 (e.g., VDD) during the first phase ('1') of the input switching signal 602. Similarly, the third switching element 570 may connect both the first node and the second node of the third capacitive element 520 to the power supply node 561 (e.g., GND) during the first phase ('1') of the input switching signal 602.

[0044] During the second phase of the input switch signal 602, the switching circuit device 510 may connect a first capacitive element 512 and a second capacitive element 514 in parallel. In this way, the switching circuit device 510 can transfer charge from the second capacitive element 514 to the first capacitive element 512, which will cause the second capacitive element 514 to discharge slightly and thus reduce the voltage at the second capacitive element 514. Similarly, the switching circuit device 510 may connect a third capacitive element 520 and a fourth capacitive element 522 in parallel. In this way, the switching circuit device 510 can transfer charge from the fourth capacitive element 522 to the third capacitive element 520, which will cause the fourth capacitive element 522 to discharge slightly and thus reduce the voltage at the fourth capacitive element 522.

[0045] like Figure 6As shown, the switching process during the first stage of the input switching signal 602 and the switching process during the second stage of the input switching signal 602 can continue until the comparator circuit device 516 generates a pulse at the output signal. For example, during the analog frequency divider stage 622, the switching circuit device 510 can discharge the second capacitive element 514 and the fourth capacitive element 522 until the voltage at the second capacitive element 514 (e.g., V) is discharged. b The voltage becomes higher than that at the fourth capacitive element 522 (V). a The comparison circuit device 516 commutates and generates an output pulse (e.g., S). out ).

[0046] Switched capacitor (C) Sa,b The first switching element 560 and the third switching element 570 can operate as "resistors", and their values ​​can be approximated as R. eq =1 / (f in ×C Sa,b ), where R eq f represents the equivalent resistance of the switched capacitor. in It is the frequency of the input switch signal 602, and C Sa,b It is the absolute capacitance of the switched capacitor. In this way, the evolution of the voltage (Va(t)) at the second capacitive element 514 and the voltage (Vb(t)) at the fourth capacitive element 522 can have exponential behavior, and it can be written as Equations 1 and 2.

[0047] V a (t)=V DD ×exp[-t / T S ×C La / C Sa Equation 1

[0048] Where V a (t) represents the voltage at the fourth capacitive element 522, V DD The voltage at power node 559 is represented by exp(), which represents the natural exponential function, and t represents time, T. s Indicates the time period (e.g., 1 / f) in ), C La This represents the absolute capacitance of the fourth capacitive element 522, and C Sa This represents the absolute capacitance of the third capacitive element 520.

[0049] V b (t)=V DD Equation 2: ×[1-exp[-t / (TS×CLb / CSb)]]

[0050] Where V b(t) represents the voltage at the second capacitive element 514, V DD The voltage at power node 559 is represented by exp(), which represents the natural exponential function, and t represents time, T. s Indicates the time period (e.g., 1 / f) in ), C Lb This represents the absolute capacitance of the second capacitive element 514, and C Sb This represents the absolute capacitance of the first capacitive element 512.

[0051] Equation 3 gives the result at t x The occurrence at V a (t x ) = V b (t x ) switch point.

[0052] t x =T S ×(C L / C S Equation 3: ) × ln(2)

[0053] Where t x It is the switch point, T S It is a time period (e.g., 1 / f) in ), C L / C S It is the capacitor ratio between the capacitance of the second capacitive element 514 and the capacitance of the first capacitive element 512, or between the capacitance of the fourth capacitive element 522 and the capacitance of the third capacitive element 520, and ln(2) is the natural logarithm of 2. As shown in Equation 3, the switching point is independent of the voltage supplied at power node 559 (e.g., V). DD ).

[0054] At the switching point, the comparator circuit 516 can generate a pulse, and the voltage (e.g., C) across the second capacitive element 514 and the fourth capacitive element 522... La,b It can be reset at 624 during the sampling phase.

[0055] The output pulse sequence of the output switch signal 608 is at a frequency f as shown in Equation 4. out Place.

[0056] f in =f out ×(C L / C S )×ln(2)=f out ×D F Equation 4

[0057] Where f inIt is the frequency at input switch signal 602, f out It is the frequency of the output switch signal at 608, C L / C S It is the capacitor ratio between the capacitance of the second capacitive element 514 and the capacitance of the first capacitive element 512, or between the capacitance of the fourth capacitive element 522 and the capacitance of the third capacitive element 520, where ln(2) is the natural logarithm of 2, and D F Let D represent the frequency division factor. Equation 5 gives the frequency division factor D. F =f in / f out .

[0058] D F =(C L / C S Equation 5: ) × ln(2)

[0059] Assume the scheme achieves a frequency division factor of 100 (D) F The technique described herein, using an analog frequency divider (using four capacitive elements), is as follows (e.g., Figure 4 System 400 or Figure 5 Circuit 500) may include information on using only such Figure 3 The cascaded D flip-flops shown offer one or more of the following advantages. The division factor is given by Equation 5 (e.g., D...). F =(C L / C S )×ln(2)), resulting in a frequency division factor independent of the voltage at the power supply node (e.g., V DD And the absolute value of the capacitor. For example, the frequency division factor depends on the capacitor ratio rather than the absolute capacitance value, and therefore capacitance matching can be used.

[0060] Furthermore, compared to systems that rely solely on cascaded D flip-flops, Figure 1 , Figures 3-5 The analog frequency divider shown in the diagram consumes less power. Figure 1 , Figures 3-5 The power consumption of the analog frequency divider shown in the diagram may be due to the C at the beginning of the slow cycle. L This is caused by the pre-charge of the capacitor and the backup comparator current. For example, compared to a system using only a D flip-flop chain, Figure 1 , Figures 3-5 The power consumption of the analog frequency divider illustrated can be approximately 50%. In another example of its benefits, Figure 1 , Figures 3-5 The analog frequency divider illustrated can be used in a circuit (e.g., a chip) with a much smaller area than if it relied solely on a chain of D flip-flops.

[0061] Figure 7This is a conceptual diagram illustrating an example system 700 for generating an output switching signal using both an analog frequency divider 702 and a digital frequency divider 704, according to one or more techniques of this disclosure. Examples of the analog frequency divider 702 may include... Figure 1 System 100 Figure 4 System 400 or Figure 5 The circuit 500. The digital frequency divider 704 includes D flip-flops 780-783. Although Figure 7 The illustration shows a digital divider 704 with four D flip-flops, but other examples may include fewer or more than four D flip-flops.

[0062] As shown in the figure, D flip-flops 780-783 can be cascaded. For example, the clock input of D flip-flop 781 receives the inverted output (inv Q) from the previous D flip-flop (e.g., D flip-flop 780), and outputs the clock input to the next D flip-flop (e.g., D flip-flop 782) at the inverted output, where the D input of D flip-flop 781 is coupled to the inverted output of D flip-flop 781.

[0063] exist Figure 7 In the example, analog frequency divider 702 can receive an input switching signal and output a first output switching signal. For example, the first output switching signal can have a reduced frequency (e.g., a reduced frequency division factor in Equation 5). In this example, digital frequency divider 704 can represent a set of D flip-flops (e.g., D flip-flops 780-783) configured to receive the first output switching signal at a clock input and output a second output switching signal.

[0064] One or more benefits of using the combination of analog divider 702 and digital divider 704 may include: system 700 reduces power consumption compared to using D flip-flops alone. For example, higher power consumption in a D flip-flop chain can occur in the first block, which exchanges at a higher frequency than subsequent blocks in the chain. In this example, the last block in the D flip-flop chain exchanges at a lower frequency, which may consume less power than previous blocks in the chain. Another benefit may include: the first output switching signal output by analog divider 702 can be implemented as a pulse (e.g., Figure 6 S out In this example, the digital frequency divider 704 can generate a second output switching signal with a square wave having both a reduced frequency and a 50% duty cycle, which simplifies the implementation of the analog frequency divider 702.

[0065] Figure 8 This is a flowchart illustrating an example process for generating an output switching signal according to one or more techniques of this disclosure. Reference is made for illustrative purposes only. Figures 1-7 discuss Figure 8 .

[0066] In some examples, the switching circuit device 110 may be configured to charge (e.g., precharge) the second capacitive element 114 to the supply voltage (e.g., V). DD For example, in response to the sampling phase ('S'), the switching circuit device 110 can charge the second capacitive element 114.

[0067] The switching circuit device 110 can, in response to the detection of an input switching signal in the first stage, cause the first capacitive element 112 (e.g., C) to... SB Or C SA Discharge (802). For example, the switching circuit device 110 may, in response to the detection of a first stage of an input switching signal (e.g., logic 0 or logic 1), couple the nodes (e.g., positive and negative nodes) of the first capacitive element 112 to a power supply node (e.g., a voltage node or a ground node).

[0068] Switching circuit device 110 can, in response to the second stage of detecting an input switching signal, connect a first capacitive element 112 (e.g., C) in parallel. SB Or C SA ) and the second capacitive element 114 (e.g., C LB Or C LA (804). For example, in response to the detection of a second stage of the input switch signal (e.g., logic 1 or logic 0), the switching circuit device 110 may connect a first node (e.g., a positive node) of the first capacitive element 112 to a first node (e.g., a positive node) of the second capacitive element 114, and connect a second node (e.g., a positive node) of the first capacitive element 112 to a second node (e.g., a positive node) of the second capacitive element 114. In this way, the charge stored at the second capacitive element 114 is transferred to the first capacitive element 112, which may cause the voltage at the second capacitive element 114 to decay or rise exponentially.

[0069] Switching circuit device 110 can generate an output switching signal (806) based on the voltage at the second capacitive element 114. For example, when the voltage at the second capacitive element 114 is greater than a reference voltage, comparator circuit device 416 can generate an output switching signal to indicate a first stage (e.g., logic 1). In this example, when the voltage at the second capacitive element 114 is not greater than the reference voltage, comparator circuit device 416 can generate an output switching signal to indicate a second stage. In this way, switching circuit device 110 can generate an output switching signal with a reduced frequency from the input switching signal, while consuming less power compared to a system that relies solely on D flip-flops.

[0070] In some examples, the system can compare the voltage at the second capacitive element with the voltages at both capacitive elements. For example... Figure 4 As shown in the example, the switching circuit device 410 may be further configured to, in response to a first stage of detecting an input switching signal, cause the third capacitive element 420 (e.g., C) to... SA Discharge. In this example, the switching circuit device 410 can be configured to connect the third capacitive element 420 and the fourth capacitive element 422 (e.g., C) in parallel in response to the detection of the input switching signal in the second stage. LA In this way, the charge stored at the fourth capacitive element 422 is transferred to the third capacitive element 420, which can cause the voltage at the fourth capacitive element 422 to rise or fall exponentially.

[0071] The comparator circuit 416 can be configured to generate an output switching signal based on the voltage at the second capacitive element 414 and also based on the voltage at the fourth capacitive element 422. For example, when the voltage at the second capacitive element 414 is greater than the voltage at the fourth capacitive element 422, the comparator circuit 416 can generate an output switching signal to indicate a first stage. In this example, when the voltage at the second capacitive element 414 is not greater than the voltage at the fourth capacitive element 422, the comparator circuit 416 can generate an output switching signal to indicate a second stage. Comparing the voltages at the two capacitive switching elements that discharge using switched capacitors results in both the voltage at the second capacitive element 414 and the voltage at the fourth capacitive element 422 exhibiting exponential behavior, which allows the division factor to be independent of the voltage at the power supply node (e.g., V). DD ) and the absolute value of the capacitor. This allows the frequency division factor to be independent of the voltage at the power supply node (e.g., V). DD The absolute value of the capacitor can help simplify the implementation of the frequency division (e.g., allow for less precise components) and / or improve the accuracy of the frequency division.

[0072] In some examples, the output switch signal (which may be referred to as the first output switch signal) can be output to, for example... Figure 7 The example shows a set of D flip-flops. In this example, the set of D flip-flops can be configured to receive a first output switching signal at the clock input and output a second output switching signal. In this way, the set of D flip-flops can generate a second output switching signal with both a reduced frequency and a 50% duty cycle square wave, which can improve the accuracy of the second output switching signal (e.g., more precise frequency control and / or a more precise duty cycle form) and / or reduce power consumption compared to a system using only D flip-flops.

[0073] In various examples, the techniques and circuitry of this disclosure can be used to create long clock signals (e.g., greater than 100 milliseconds) for any of a variety of applications. In some specific examples, the techniques and circuitry of this disclosure can be used to generate long clock signals for controlling sample-and-hold operations performed by sample-and-hold circuitry. In some systems (e.g., vehicle systems), there may be several circuit elements or blocks (such as a reference voltage generator) that can remain active and consume a considerable amount of power to produce a constant or stable voltage, for example, even when the system is off. Sample-and-hold circuitry can be used to control such circuit elements or blocks (such as a reference voltage generator), and the techniques of this disclosure can be used to efficiently and effectively create long clock signals for controlling such sample-and-hold circuitry.

[0074] The following clauses may describe one or more aspects of this disclosure.

[0075] Clause 1: A circuit for generating an output switching signal, comprising: a switching circuit means configured to: discharge a first capacitive element in response to a first stage of detecting an input switching signal; and connect the first capacitive element and a second capacitive element in parallel in response to a second stage of detecting the input switching signal; and a comparison circuit means configured to generate the output switching signal based on the voltage at the second capacitive element.

[0076] Clause 2: The circuit of Clause 1, wherein the switching circuit device is further configured to: discharge the third capacitive element in response to a first stage of detecting an input switching signal; and connect the third capacitive element and the fourth capacitive element in parallel in response to a second stage of detecting an input switching signal, wherein the comparator circuit device is configured to generate an output switching signal based on the voltage at the second capacitive element and also based on the voltage at the fourth capacitive element.

[0077] Clause 3: The circuit of Clause 2, wherein, in order to generate an output switching signal, the comparator circuit is configured to: generate an output switching signal to indicate a first stage when the voltage at the second capacitive element is greater than the voltage at the fourth capacitive element; and generate an output switching signal to indicate a second stage when the voltage at the second capacitive element is not greater than the voltage at the fourth capacitive element.

[0078] Clause 4: The circuit of Clauses 1-3, wherein the first capacitive element includes a first node and a second node; and wherein, in order to discharge the first capacitive element, the switching circuit device is configured to connect both the first node and the second node of the first capacitive element to a power supply node.

[0079] Clause 5: The circuit of Clause 4, wherein the power supply node includes a ground node or a voltage node.

[0080] Clause 6: The circuit of Clauses 1-5, wherein the first capacitive element includes a second node and a first node coupled to a power supply node; wherein the second capacitive element includes a second node and a first node coupled to a power supply node; and wherein the switching circuit device includes: a first switching element, which includes a first node coupled to a power supply node and a second node coupled to a second node of the first capacitive element; and a second switching element, which includes a first node coupled to a second node of the first capacitive element and a second node coupled to a second node of the second capacitive element.

[0081] Clause 7: The circuit of Clause 6, wherein a first switching element is configured to operate in an open state during a second phase of an input switching signal and in a closed state during a first phase of an input switching signal; and wherein a second switching element is configured to operate in a closed state during the second phase of an input switching signal and in an open state during the first phase of an input switching signal.

[0082] Clause 8: Circuits of Clauses 6-7, wherein power supply nodes include ground nodes or voltage nodes.

[0083] Clause 9: The circuits of Clauses 1 and 4-8, wherein, in order to generate an output switching signal, the comparator circuit is configured to: generate an output switching signal to indicate a first stage when the voltage at the second capacitive element is greater than a reference voltage; and generate an output switching signal to indicate a second stage when the voltage at the second capacitive element is not greater than a reference voltage.

[0084] Clause 10: The circuit of Clauses 1-9, wherein the output switch signal is a first output switch signal, further comprising: a set of D flip-flops configured to receive the first output switch signal at a clock input and output a second output switch signal.

[0085] Clause 11: The circuit as described in Clauses 1-10, wherein the switching circuit device is configured to charge the second capacitive element to the supply voltage.

[0086] Clause 12: A system for generating an output switching signal, the system comprising: a first capacitive element; a second capacitive element; a switching circuit arrangement configured to: discharge the first capacitive element in response to a first stage of detecting an input switching signal; and connect the first capacitive element and the second capacitive element in parallel in response to a second stage of detecting the input switching signal; and a comparison circuit arrangement configured to generate the output switching signal based on the voltage at the second capacitive element.

[0087] Clause 13: The system of Clause 12, wherein the switching circuit device is a first switching circuit device, the circuit further comprising: a third capacitive element; a fourth capacitive element; and a second switching circuit device configured to: discharge the third capacitive element in response to a first stage of detecting an input switching signal; and connect the third capacitive element and the fourth capacitive element in parallel in response to a second stage of detecting an input switching signal, wherein the comparator circuit device is configured to generate an output switching signal based on the voltage at the second capacitive element and also based on the voltage at the fourth capacitive element.

[0088] Clause 14: The system of Clause 13, wherein, in order to generate an output switching signal, the comparator circuit is configured to: generate an output switching signal to indicate a first stage when the voltage at the second capacitive element is greater than the voltage at the fourth capacitive element; and generate an output switching signal to indicate a second stage when the voltage at the second capacitive element is not greater than the voltage at the fourth capacitive element.

[0089] Clause 15: The system of Clauses 12-14, wherein the second capacitive element includes a first node and a second node; and wherein, in order to discharge the second capacitive element, a switching circuit device is configured to connect both the first node of the first capacitive element and the second node of the first capacitive element to a power supply node.

[0090] Clause 16: The system of Clause 15, wherein the power supply node includes a ground node or a voltage node.

[0091] Clause 17: The system of Clauses 12-16, wherein a first capacitive element includes a second node and a first node coupled to a power supply node; wherein a second capacitive element includes a second node and a first node coupled to a power supply node; and wherein a switching circuit device includes: a first switching element that includes a first node coupled to a power supply node and a second node coupled to a second node of the first capacitive element; and a second switching element that includes a first node coupled to a second node of the first capacitive element and a second node coupled to a second node of the second capacitive element.

[0092] Clause 18: The system according to Clause 17, wherein the first switching element is configured to operate in an open state during a second phase of the input switching signal and in a closed state during a first phase of the input switching signal; and wherein the second switching element is configured to operate in a closed state during the second phase of the input switching signal and in an open state during the first phase of the input switching signal.

[0093] Clause 19: Systems of Clauses 17-18, wherein the power supply node includes a ground node or a voltage node.

[0094] Clause 20: A method for generating an output switching signal, the method comprising: discharging a first capacitive element in response to a first stage of detecting an input switching signal; connecting the first capacitive element and a second capacitive element in parallel in response to a second stage of detecting the input switching signal; and generating the output switching signal based on the voltage at the second capacitive element.

[0095] Various aspects are described in this disclosure. These and other aspects are within the scope of the appended claims.

Claims

1. A circuit for generating an output switching signal, the circuit comprising: The switching circuit device is configured as follows: In response to the detection of an input switch signal in the first stage, the first capacitive element is discharged; as well as In response to the detection of the input switch signal in the second stage, the first capacitive element and the second capacitive element are connected in parallel; as well as The comparison circuit is configured to generate the output switching signal based on the voltage at the second capacitive element.

2. The circuit according to claim 1, wherein the switching circuit device is further configured as follows: In response to the first stage of detecting the input switch signal, the third capacitive element is discharged; and In response to the second stage of detecting the input switch signal, the third capacitive element and the fourth capacitive element are connected in parallel. The comparison circuit is configured to generate the output switching signal based on the voltage at the second capacitive element and also based on the voltage at the fourth capacitive element.

3. The circuit according to claim 2, wherein, in order to generate the output switching signal, the comparator circuit is configured as follows: When the voltage at the second capacitive element is greater than the voltage at the fourth capacitive element, the output switching signal is generated to indicate the first stage; and When the voltage at the second capacitive element is not greater than the voltage at the fourth capacitive element, the output switching signal is generated to indicate the second stage.

4. The circuit according to claim 1, The first capacitive element includes a first node and a second node; and In order to discharge the first capacitive element, the switching circuit device is configured to connect both the first node and the second node of the first capacitive element to a power supply node.

5. The circuit according to claim 4, wherein the power supply node includes a ground node or a voltage node.

6. The circuit according to claim 1, The first capacitive element includes a second node and a first node coupled to a power supply node; The second capacitive element includes a second node and a first node coupled to the power supply node; as well as The switching circuit device includes: The first switching element includes a first node coupled to the power node and a second node coupled to the second node of the first capacitive element; by The second switching element includes a first node coupled to a second node of the first capacitive element and a second node coupled to a second node of the second capacitive element.

7. The circuit according to claim 6, The first switching element is configured to operate in an open state during the second phase of the input switching signal and in a closed state during the first phase of the input switching signal; and The second switching element is configured to operate in a closed state during the second phase of the input switching signal and in an open state during the first phase of the input switching signal.

8. The circuit of claim 6, wherein the power supply node includes a ground node or a voltage node.

9. The circuit of claim 1, wherein, in order to generate the output switching signal, the comparator circuit is configured as follows: When the voltage at the second capacitive element is greater than the reference voltage, the output switching signal is generated to indicate the first stage; and When the voltage at the second capacitive element is not greater than the reference voltage, the output switching signal is generated to indicate the second stage.

10. The circuit according to claim 1, wherein the output switch signal is a first output switch signal, and the circuit further comprises: A set of D flip-flops is configured to receive the first output switch signal at the clock input and output the second output switch signal.

11. The circuit of claim 1, wherein the switching circuit device is configured to charge the second capacitive element to a power supply voltage.

12. A system for generating an output switching signal, the system comprising: First capacitive element; Second capacitive element; The switching circuit device is configured as follows: In response to the detection of an input switch signal in the first stage, the first capacitive element is discharged; as well as In response to the second stage of detecting the input switch signal, the first capacitive element and the second capacitive element are connected in parallel; as well as The comparison circuit is configured to generate the output switching signal based on the voltage at the second capacitive element.

13. The system of claim 12, wherein the switching circuit device is a first switching circuit device, and the circuit further comprises: Third capacitive element; Fourth capacitive element; as well as The second switching circuit device is configured as follows: In response to the first stage of detecting the input switch signal, the third capacitive element is discharged; and In response to the second stage of detecting the input switch signal, the third capacitive element and the fourth capacitive element are connected in parallel. The comparison circuit is configured to generate the output switching signal based on the voltage at the second capacitive element and also based on the voltage at the fourth capacitive element.

14. The system of claim 13, wherein, in order to generate the output switching signal, the comparator circuit is configured to: When the voltage at the second capacitive element is greater than the voltage at the fourth capacitive element, the output switching signal is generated to indicate the first stage; and When the voltage at the second capacitive element is not greater than the voltage at the fourth capacitive element, the output switching signal is generated to indicate the second stage.

15. The system according to claim 12, The second capacitive element includes a first node and a second node; and In order to discharge the second capacitive element, the switching circuit device is configured to connect both the first node of the first capacitive element and the second node of the first capacitive element to a power supply node.

16. The system of claim 15, wherein the power node includes a ground node or a voltage node.

17. The system according to claim 12, The first capacitive element includes a second node and a first node coupled to a power supply node; The second capacitive element includes a second node and a first node coupled to the power supply node; as well as The switching circuit device includes: The first switching element includes a first node coupled to the power node and a second node coupled to the second node of the first capacitive element; as well as The second switching element includes a first node coupled to a second node of the first capacitive element and a second node coupled to a second node of the second capacitive element.

18. The system according to claim 17, The first switching element is configured to operate in an open state during the second phase of the input switching signal and in a closed state during the first phase of the input switching signal; and The second switching element is configured to operate in a closed state during the second phase of the input switching signal and in an open state during the first phase of the input switching signal.

19. The system of claim 17, wherein the power node includes a ground node or a voltage node.

20. A method for generating an output switching signal, the method comprising: In response to the detection of an input switch signal in the first stage, the first capacitive element is discharged; In response to the detection of the input switch signal in the second stage, the first capacitive element and the second capacitive element are connected in parallel; as well as The output switching signal is generated based on the voltage at the second capacitive element.

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