Phase-locked loop locking detection circuit and method, chip and electronic equipment

Abstract

The invention provides a phase-locked loop locking detection circuit, a phase-locked loop locking detection method, a chip and electronic equipment. The phase-locked loop locking detection circuit comprises a phase frequency detection circuit, a first OR gate, an anti-spike pulse circuit and a counting zero clearing circuit, the phase frequency detection circuit generates a first phase signal and a second phase signal according to the logic high level signal, the reference clock signal and the feedback clock signal; the first OR gate performs OR operation on the first phase signal and the second phase signal to obtain a first trigger signal; the anti-spike pulse circuit shortens the pulse width of the first trigger signal according to a preset threshold to obtain a second trigger signal; the counting zero clearing circuit performs resetting zero clearing when the second trigger signal has a pulse, the output locking indication signal is in a low level and represents that the phase-locked loop is in a lock losing state, and when the second trigger signal does not have a pulse, the counting zero clearing circuit performs delay according to the feedback clock signal and the control logic high level signal, and the output locking indication signal is in a high level and represents that the phase-locked loop is in a lock losing state. And representing that the phase-locked loop is in a locked state. Therefore, whether the phase-locked loop is in a locked state is detected.

Description

Technical Field

[0001] This application relates to the field of power management chip technology, and in particular to a phase-locked loop (PLL) locking detection circuit, method, chip, and electronic device. Background Technology

[0002] A phase-locked loop (PLL) is a control system used to achieve automatic phase synchronization. Based on feedback control circuitry, it adjusts the phase of the output signal to match the phase of the input signal. See also... Figure 1 , Figure 1 A schematic diagram of a phase-locked loop circuit structure is provided for related technologies, such as... Figure 1 As shown, a phase-locked loop (PLL) typically includes a PFD (Phase Frequency Detector), a CP (charge pump), an LPF (Low-Pass Filter), a VCO (Voltage-Controlled Oscillator), and a DIV (Divider). During PLL operation, the phase detector detects the phase difference (UP0 and DN0) between the input signal (CLK_REF) and the feedback signal (CLK_FB). The charge pump converts the phase difference (UP0 and DN0) output by the phase detector into a current signal (IS0). The low-pass filter filters the current signal (IS0), and the VCO adjusts the phase of the output signal (FREQ) based on the filtered current signal (IS1). The divider divides the output signal (FREQ) to obtain the feedback signal (CLK_FB), which is then input to the phase detector.

[0003] like Figure 1As shown, the phase-locked loop further comprises: an LDC (Lock Detect Circuit, lock detection circuit), as a key component in the phase-locked loop, the lock detection circuit is used to output a lock signal LOCK0 according to the phase difference (i.e. UP0 and DN0) output by the frequency discriminator and phase discriminator, to detect whether the phase-locked loop is in a locked state, the phase-locked loop in the locked state means that the phase of the output signal of the phase-locked loop is synchronized with the phase of the input signal. For example, when the phase-locked loop is applied in a chip, the lock signal output by the lock detection circuit can affect the working clock of the chip, and can reduce the timing confusion during power-on of the chip. For example, the lock detection circuit outputs a lock flag to the digital unit when the clock signal is locked or stable, and outputs an unlock flag to the digital unit when the clock signal is not locked or the system suddenly has a clock exception. Since the clock signal output by the phase-locked loop is generally used as the main clock of the digital unit, based on the lock flag and the unlock flag, the digital unit can start working under the condition that the clock is normal, so as to ensure the normal working state of the chip.

[0004] A phase-locked loop detection circuit provided by the prior art can stably output a lock flag when the phase-locked loop is in a locked state, but when the phase-locked loop is in an unlocked state, the lock flag is still mis-triggered to be output, which cannot meet the requirement of stably outputting an unlock flag when the phase-locked loop is in an unlocked state, and thus cannot accurately detect whether the phase-locked loop is in a locked state. SUMMARY

[0005] The present application provides a phase-locked loop lock detection circuit, method, chip and electronic equipment to detect whether the phase-locked loop is in a locked state.

[0006] In a first aspect, the present application provides a phase-locked loop lock detection circuit, which comprises: a frequency discriminator and phase discriminator, a first OR gate, an anti-peak pulse circuit and a counting and clearing circuit. The first data input end and the second data input end of the frequency discriminator and phase discriminator are connected to a logic high level signal, the first clock end of the frequency discriminator and phase discriminator is connected to a reference clock signal, the second clock end of the frequency discriminator and phase discriminator is connected to a feedback clock signal, and the first output end of the frequency discriminator and phase discriminator is electrically connected to the first input end of the first OR gate. The second output end of the frequency discriminator and phase discriminator is electrically connected to the second input end of the first OR gate, the output end of the first OR gate is electrically connected to the input end of the anti-peak pulse circuit, the output end of the anti-peak pulse circuit is electrically connected to the reset end of the counting and clearing circuit, the clock end of the counting and clearing circuit is connected to the feedback clock signal, and the input end of the counting and clearing circuit is connected to the logic high level signal. The frequency discriminator and phase discriminator are configured to generate a first phase signal and a second phase signal according to the logic high level signal, the reference clock signal and the feedback clock signal. the first or gate is configured to perform an or operation on the first phase signal and the second phase signal, and output a first trigger signal; the anti-peak pulse circuit is configured to shorten a pulse width of the first trigger signal according to a preset threshold, and obtain a second trigger signal; the counting and clearing circuit is configured to output a lock indication signal according to the second trigger signal, the feedback clock signal and the logic high level signal, wherein the lock indication signal is used to indicate whether the phase-locked loop is locked.

[0007] In a possible design, the anti-peak pulse circuit is specifically configured to obtain the second trigger signal when the pulse width of the first trigger signal is greater than the preset threshold, and the second trigger signal has a pulse. In a possible design, the anti-peak pulse circuit is specifically configured to obtain the second trigger signal when the pulse width of the first trigger signal is less than or equal to the preset threshold, and the second trigger signal has no pulse.

[0008] In a possible design, the counting and clearing circuit is specifically configured to control itself to reset when the second trigger signal has a pulse, and output the lock indication signal, wherein the lock indication signal is at a low level and is used to indicate that the phase-locked loop is in an unlocked state. In a possible design, the counting and clearing circuit is specifically configured to control the logic high level signal to delay when the second trigger signal has no pulse, and output the lock indication signal, wherein the lock indication signal is at a high level and is used to indicate that the phase-locked loop is in a locked state.

[0009] In a possible design, the frequency and phase detection circuit includes a first D flip-flop, a second D flip-flop, an and gate, a delay device and a second or gate. The data terminal of the first D flip-flop is electrically connected with a first data input terminal of the frequency and phase detection circuit, and is configured to access the logic high level signal; the clock terminal of the first D flip-flop is electrically connected with a first clock terminal of the frequency and phase detection circuit, and is configured to access the reference clock signal; and the output terminal of the first D flip-flop is electrically connected with a first input terminal of the and gate, and serves as a first output terminal of the frequency and phase detection circuit, and is configured to output the first phase signal. The data terminal of the second D flip-flop is electrically connected with a second data input terminal of the frequency and phase detection circuit, and is configured to access the logic high level signal; the clock terminal of the second D flip-flop is electrically connected with a second clock terminal of the frequency and phase detection circuit, and is configured to access the feedback clock signal; and the output terminal of the second D flip-flop is electrically connected with a second input terminal of the and gate, and serves as a second output terminal of the frequency and phase detection circuit, and is configured to output the second phase signal. The output of the AND gate is electrically connected to the input of the delay unit, the output of the delay unit is electrically connected to the first input of the second OR gate, and the second input of the second OR gate is connected to an enable signal. The output of the second OR gate is electrically connected to the reset terminal of the first D flip-flop and the reset terminal of the second D flip-flop, respectively.

[0010] In one possible design, the counter clearing circuit includes N flip-flops, where N is a positive integer greater than or equal to 1; The reset terminal of each of the flip-flops is electrically connected to the reset terminal of the count clearing circuit to receive the second trigger signal, and the clock terminal of each of the flip-flops is electrically connected to the clock terminal of the count clearing circuit to receive the feedback clock signal. The data terminals and output terminals of each flip-flop are connected in series sequentially. The data terminal of the first flip-flop among the N flip-flops serves as the input terminal of the count clearing circuit, used to connect to the logic high-level signal. The output terminal of the first flip-flop among the N flip-flops is electrically connected to the data terminal of the second flip-flop among the N flip-flops. The output terminal of the Nth flip-flop among the N flip-flops serves as the output terminal of the count clearing circuit, used to output the lock indication signal.

[0011] In one possible design, the count clearing circuit is specifically used to control the logic high-level signal to be delayed by N feedback clock cycles and output when there is no pulse in the second trigger signal, and to serve as the lock indication signal, wherein the lock indication signal is high level and is used to indicate that the phase-locked loop is in a locked state; the feedback clock cycle is the clock cycle corresponding to the feedback clock signal.

[0012] In one possible design, when the phase-locked loop is in a locked state, the clock period corresponding to the feedback clock signal is equal to the clock period corresponding to the reference clock signal.

[0013] Secondly, this application provides a phase-locked loop (PLL) lock-in detection method, applied to the PLL lock-in detection circuit described in the first aspect, the method comprising: Based on the logic high-level signal, the reference clock signal, and the feedback clock signal, generate the first phase signal and the second phase signal; Perform an OR operation on the first phase signal and the second phase signal, and output the first trigger signal; The pulse width of the first trigger signal is shortened according to a preset threshold to obtain the second trigger signal; Based on the second trigger signal, the feedback clock signal, and the logic high-level signal, a lock indication signal is output, wherein the lock indication signal is used to indicate whether the phase-locked loop is locked.

[0014] Thirdly, this application provides a chip including: a phase-locked loop (PLL) locking detection circuit as described in the first aspect.

[0015] Fourthly, this application provides an electronic device, including: a chip as described in the third aspect.

[0016] The beneficial effects of the embodiments of this application are as follows: The phase-locked loop (PLL) locking detection circuit provided in this application embodiment specifically includes: a frequency and phase discrimination circuit, a first OR gate, an anti-spiking pulse circuit, and a count clearing circuit. The frequency and phase discrimination circuit generates a first phase signal and a second phase signal based on a logic high-level signal, a reference clock signal, and a feedback clock signal. The first OR gate performs an OR operation on the first and second phase signals and outputs a first trigger signal. The anti-spiking pulse circuit shortens the pulse width of the first trigger signal according to a preset threshold to obtain a second trigger signal. The count clearing circuit then outputs a locking indication signal based on the second trigger signal, the feedback clock signal, and the logic high-level signal, used to indicate whether the PLL is locked. Compared with solutions provided by related technologies, the PLL locking detection circuit provided in this application embodiment has a different topology and can output a locking indication signal to detect whether the PLL is in a locked state. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0018] Figure 1 A schematic diagram of a phase-locked loop circuit structure provided for related technologies; Figure 2 A schematic diagram of the circuit structure of a phase-locked detection circuit provided for the prior art; Figure 3 A timing diagram of a phase-locked loop (PLL) detection circuit in the prior art when the PLL is in an unlocked state; Figure 4 A timing diagram of a phase-locked loop (PLL) detection circuit in the locked state, provided for the present technology; Figure 5 A schematic diagram of the circuit structure of a phase-locked loop locking detection circuit provided in an embodiment of this application; Figure 6 A schematic diagram of another phase-locked loop locking detection circuit provided in an embodiment of this application; Figure 7A timing diagram of a phase-locked loop (PLL) locking detection circuit provided for an embodiment of this application; Figure 8 This is a flowchart of a phase-locked loop locking detection method provided in an embodiment of this application. Detailed Implementation

[0019] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0022] See Figure 2 , Figure 2 A schematic diagram of the circuit structure of a phase-locked loop detection circuit provided for the prior art is shown below. Figure 2As shown, the phase-locked loop detection circuit includes: a first flip-flop DF1, a second flip-flop DF2, a third flip-flop DF3, a fourth flip-flop DF4, an AND gate A1, a delay circuit A2, an OR gate A3, and a NOR gate A4.

[0023] See Figure 2 The electrical connections of the components in this phase-locked loop (PLL) detection circuit are as follows: the data terminal (data1) of the first flip-flop DF1 is connected to a high level (High), and its clock terminal (CL1) is connected to a reference clock (CLK_REF). The data terminal (data2) of the second flip-flop DF2 is connected to a high level (High), and its clock terminal (CL2) is connected to a feedback clock (CLK_FB). The output terminal (Q1) of the first flip-flop DF1 is electrically connected to the first input terminal of AND gate A1 and the data terminal (data3) of the third flip-flop DF3. The output terminal (Q2) of the second flip-flop DF2 is electrically connected to the second input terminal of AND gate A1 and the data terminal (data4) of the fourth flip-flop DF4. The output terminal of AND gate A1 is electrically connected to the input terminal of delay circuit A2, and the output terminal of delay circuit A2 is electrically connected to the first input terminal of OR gate A3. One input terminal is electrically connected, and the second input terminal of the OR gate A3 is connected to the enable signal ENB. The output terminal of the OR gate A3 is electrically connected to the reset terminal RST1 of the first flip-flop DF1 and the reset terminal RST2 of the second flip-flop DF2. The clock terminal CL3 of the third flip-flop DF3 is connected to the reference clock CLK_REF. The output terminal Q3 of the third flip-flop DF3 is electrically connected to the first input terminal of the NOR gate A4. The reset terminal RST3 of the third flip-flop DF3 is connected to the enable signal ENB. The clock terminal CL4 of the fourth flip-flop DF4 is connected to the feedback clock CLK_FB. The output terminal Q4 of the fourth flip-flop DF4 is electrically connected to the second input terminal of the NOR gate A4. The reset terminal RST4 of the fourth flip-flop DF4 is connected to the enable signal ENB. The output terminal of the NOR gate A4 outputs the phase-locked signal flag LOCK1.

[0024] Normally, when the phase-locked loop (PLL) signal flag LOCK1 is 1 (i.e., the lock detection circuit outputs the lock flag), it indicates that the PLL is in a locked state; when the PLL signal flag LOCK1 is 0 (i.e., the lock detection circuit outputs the unlock flag), it indicates that the PLL is in an unlocked state.

[0025] See Figure 2The operation of the existing phase-locked loop detection circuit is as follows: the first flip-flop DF1 locks the high level High connected to the data terminal data1 of the first flip-flop DF1 at the rising edge of the reference clock CLK_REF, and obtains the first signal UP1. At the same time, the second flip-flop DF2 locks the high level High connected to the data terminal data2 of the second flip-flop DF2 at the rising edge of the feedback clock CLK_FB, and obtains the second signal DN1. The logic AND gate A1 performs an AND operation on the first signal UP1 and the second signal DN1, and delays the result through the delay circuit A2. The logic OR gate A3 performs an OR operation on the delay result of the delay circuit A2 and the enable signal ENB, and then uses the result of the OR operation as the reset signal for the first flip-flop DF1 and the second flip-flop DF2.

[0026] In addition, the third flip-flop DF3 locks the first signal UP1 connected to its data terminal DF3 at the rising edge of the reference clock CLK_REF and outputs the locking result. At the same time, the fourth flip-flop DF4 locks the second signal DN1 connected to its data terminal DF4 at the rising edge of the feedback clock CLK_FB and outputs the locking result. The logic NOR gate A4 performs a NOR operation on the locking results output by the third flip-flop DF3 and the fourth flip-flop DF4 to obtain the phase-locked loop (PLL) signal flag LOCK1. The PLL is determined to be in a locked state based on whether the PLL signal flag LOCK1 is 0 or 1. Specifically, when the PLL signal flag LOCK1 is 0, the PLL is determined to be in an unlocked state, and when the PLL signal flag LOCK1 is 1, the PLL is determined to be in a locked state.

[0027] See Figure 3 , Figure 3 A timing diagram of a phase-locked loop (PLL) detection circuit in the prior art when the PLL is in an unlocked state is provided, as follows: Figure 3As shown, when the phase-locked loop (PLL) is in an unlocked state, the phases of the reference clock CLK_REF and the feedback clock CLK_FB are out of phase. In the initial state, both the reference clock CLK_REF and the feedback clock CLK_FB are low. The first flip-flop DF1, the second flip-flop DF2, the third flip-flop DF3, and the fourth flip-flop DF4 are reset. The first signal UP1 output by the output terminal Q1 of the first flip-flop DF1 is low, and the second signal DN1 output by the output terminal Q2 of the second flip-flop DF2 is low. Since the signal output by the output terminal Q3 of the third flip-flop DF3 is low, the signal output by the output terminal Q4 of the fourth flip-flop DF4 is also low. Therefore, the low level output by the third flip-flop DF3 and the low level output by the fourth flip-flop DF4 are ORed by the logic gate A4. Finally, in the initial state, the PLL signal flag LOCK1 is high, indicating that the PLL is in a locked state.

[0028] Then, when the first rising edge of the reference clock CLK_REF arrives, the first flip-flop DF1 locks the high level High connected to the data terminal data1 of the first flip-flop DF1 to obtain the first signal UP1. The first signal UP1 switches from the low level in the initial state to the high level (i.e., node a). When the first rising edge of the feedback clock CLK_FB arrives, the second flip-flop DF2 locks the high level High connected to the data terminal data2 of the second flip-flop DF2 to obtain the second signal DN1. The second signal DN1 switches from the low level in the initial state to the high level (i.e., node b).

[0029] When both the first signal UP1 and the second signal DN1 are high, the AND gate A1 performs a bitwise AND operation on the first signal UP1 and the second signal DN1. The output of the AND gate A1 is high. After being delayed by the delay circuit A2, the high level is transmitted to the first input of the OR gate A3. The OR gate A3 performs a bitwise OR operation on the high level and the enable signal ENB, and the output is still high. Since the reset terminals RST1 of the first flip-flop DF1 and RST2 of the second flip-flop DF2 are reset when the input reset signal is high, the first flip-flop DF1... 1. When the first flip-flop DF1 and the second flip-flop DF2 are reset, the first signal UP1 output by the first flip-flop DF1 switches to a low level (i.e., node c), and at the same time, the second signal DN1 output by the second flip-flop DF2 also switches to a low level (i.e., node d). Since the operation process of the AND gate A1, the delay circuit A2, and the OR gate A3 will have a delay, the high level of the first signal UP1 will switch to a low level after a certain delay (i.e., the process from node a to node c). Similarly, the high level of the second signal DN1 will also switch to a low level after a certain delay (i.e., the process from node b to node d).

[0030] When both the first signal UP1 and the second signal DN1 are low, the AND gate A1 performs an AND operation on the first signal UP1 and the second signal DN1. The output of the AND gate A1 is low. After being delayed by the delay circuit A2, the low level is transmitted to the first input of the OR gate A3. The OR gate A3 performs an OR operation on the low level and the enable signal ENB (which is low). The output is still low. Since the reset terminals RST1 of the first flip-flop DF1 and RST2 of the second flip-flop DF2 are reset when the input reset signal is high, the first flip-flop DF1 and the second flip-flop DF2 are not reset at this time. At this time, the lock result output by the output Q3 of the third flip-flop DF3 is low, and the lock result output by the output Q4 of the fourth flip-flop DF4 is low. The NOR gate A4 performs a NOR operation on the lock result output by the third flip-flop DF3 and the lock result output by the fourth flip-flop DF4, resulting in the phase-locked loop (PLL) flag LOCK1 being high (i.e., node e), indicating that the PLL is in a locked state.

[0031] When the second rising edge of the reference clock CLK_REF arrives, the first flip-flop DF1 locks the high level High connected to its data terminal data1, resulting in the first signal UP1, which switches from low to high (i.e., node f). Since the third flip-flop DF3 locks the first signal UP1 connected to its data terminal data3 on the rising edge of the reference clock CLK_REF and outputs the locking result, simultaneously, the fourth flip-flop DF4 locks the second signal DN1 connected to its data terminal data4 on the rising edge of the feedback clock CLK_FB and outputs the locking result. When the third rising edge of the reference clock CLK_REF arrives, the third flip-flop DF3 locks the first signal UP1 connected to the data terminal data3 of the third flip-flop DF3. When the first signal UP1 is high, the lock result output by the output terminal Q3 of the third flip-flop DF3 is high. After the logic NOR gate A4 performs a NOR operation on the lock result output by the third flip-flop DF3 and the lock result output by the fourth flip-flop DF4, the phase-locked loop signal flag LOCK1 switches from high to low (i.e., node g), indicating that the phase-locked loop is in an unlocked state.

[0032] As can be seen from the above analysis, when the phase-locked loop is in an unlocked state, the phase-locked signal flag LOCK1 will be at a high level when both the first signal UP1 and the second signal DN1 are at a low level, thus determining that the phase-locked loop is in a locked state, which leads to an error in the determination of the phase-locked loop's state.

[0033] SeeFigure 4 , Figure 4 A timing diagram of a phase-locked loop (PLL) detection circuit in the prior art when the PLL is in a locked state is provided, as follows: Figure 4 As shown, when the phase-locked loop is in the locked state, the reference clock CLK_REF and the feedback clock CLK_FB are synchronized. When the rising edge of the reference clock CLK_REF arrives, the first flip-flop DF1 locks the high level High connected to the data terminal data1 of the first flip-flop DF1, obtaining the first signal UP1, which switches from the low level in the initial state to the high level. When the rising edge of the feedback clock CLK_FB arrives, the second flip-flop DF2 locks the high level High connected to the data terminal data2 of the second flip-flop DF2, obtaining the second signal DN1, which switches from the low level in the initial state to the high level.

[0034] Similarly, when both the first signal UP1 and the second signal DN1 are high, the AND gate A1 performs an AND operation on the first signal UP1 and the second signal DN1, resulting in a high output. After being delayed by the delay circuit A2, the high level is transmitted to the first input of the OR gate A3. The OR gate A3 performs an OR operation on the high level and the enable signal ENB, and the output is still high. Since the reset terminals RST1 of the first flip-flop DF1 and RST2 of the second flip-flop DF2 are reset when the input reset signal is high, the first flip-flop DF1 and the second flip-flop DF2 are reset. After the reset, the first signal UP1 output by the first flip-flop DF1 switches to a low level, and the second signal DN1 output by the second flip-flop DF2 also switches to a low level. Since the operation process of the AND gate A1, the delay circuit A2, and the OR gate A3 has a delay, the high level of the first signal UP1 will switch to a low level after a certain delay, and the high level of the second signal DN1 will also switch to a low level after a certain delay.

[0035] See Figure 4 Since the reference clock CLK_REF and the feedback clock CLK_FB are synchronized when the phase-locked loop (PLL) is in the locked state, the third flip-flop DF3 outputs a low-level lock result when it locks the first signal UP1 connected to its data terminal (data3) on the rising edge of the reference clock CLK_REF. Simultaneously, the fourth flip-flop DF4 also outputs a low-level lock result when it locks the second signal DN1 connected to its data terminal (data4) on the rising edge of the feedback clock CLK_FB. The NOR gate A4 performs a OR operation on the lock results output by the third flip-flop DF3 and the fourth flip-flop DF4, resulting in the PLL flag LOCK1 being high.

[0036] See Figure 3 and Figure 4 As can be seen from the above analysis, when the phase-locked loop (PLL) is in the locked state, the LOCK1 flag is high, indicating that the PLL is in the locked state, and the state determination of the PLL is correct. However, when the PLL is in the unlocked state, the LOCK1 flag will be high even when the first signal UP1 and the second signal DN1 are both low, indicating that the PLL is in the locked state. This leads to an incorrect determination of the PLL's state and makes it impossible to accurately detect whether the PLL is in the locked state.

[0037] To address the problem in related technologies where the LOCK1 flag is mistakenly set to high when the phase-locked loop (PLL) is in an unlocked state, leading to incorrect PLL state determination, this application provides a PLL locking detection circuit, see [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of the circuit structure of a phase-locked loop (PLL) locking detection circuit provided in an embodiment of this application, as shown below. Figure 5 As shown, the phase-locked loop locking detection circuit 1000 includes: a frequency and phase discrimination circuit 100, a first OR gate 200, an anti-spiking pulse circuit 300, and a count clearing circuit 400.

[0038] The first data input terminal P1 and the second data input terminal P2 of the frequency and phase detection circuit 100 are connected to a logic high-level signal H. The first clock terminal CK1 of the frequency and phase detection circuit 100 is connected to a reference clock signal Ref_Clk. The second clock terminal CK2 of the frequency and phase detection circuit 100 is connected to a feedback clock signal Fb_Clk. The first output terminal P3 of the frequency and phase detection circuit 100 is electrically connected to the first input terminal of the first OR gate 200. The second output terminal P4 of the frequency and phase detection circuit 100 is electrically connected to the second input terminal of the first OR gate 200. The output terminal of the first OR gate 200 is electrically connected to the input terminal of the anti-spiking circuit 300. The output terminal of the anti-spiking circuit 300 is electrically connected to the reset terminal RS of the count clearing circuit 400. The clock terminal CK3 of the count clearing circuit 400 is connected to the feedback clock signal Fb_Clk. The input terminal IN of the count clearing circuit 400 is connected to a logic high-level signal H.

[0039] The frequency and phase discrimination circuit 100 is used to generate a first phase signal UP and a second phase signal DN based on the logic high-level signal H, the reference clock signal Ref_Clk, and the feedback clock signal Fb_Clk.

[0040] The first OR gate 200 is used to perform an OR operation on the first phase signal UP and the second phase signal DN, and output the first trigger signal Es_pre.

[0041] The anti-spiking pulse circuit 300 is used to shorten the pulse width of the first trigger signal Es_pre according to a preset threshold to obtain the second trigger signal Es.

[0042] The counter reset circuit 400 is used to output a lock indication signal LOCK based on the second trigger signal Es, the feedback clock signal Fb_Clk and the logic high level signal H. The lock indication signal LOCK is used to indicate whether the phase-locked loop is locked.

[0043] A phase-locked loop (PLL) is a closed-loop control system based on phase synchronization. Through feedback control circuitry, it achieves frequency and phase locking between the output and input signals. The PLL lock detection circuit described in this application is typically a key component of the PLL, used to detect whether the PLL is in a locked state. The logic state of the lock indicator signal LOCK determines whether the PLL lock detection circuit outputs a locked flag or an unlocked flag. Generally, when the lock indicator signal LOCK is high (LOCK=1), the PLL is considered locked, and the PLL lock detection circuit outputs a locked flag; when the lock indicator signal LOCK is low (LOCK=0), the PLL is considered unlocked, and the PLL lock detection circuit outputs an unlocked flag.

[0044] In this application, the first data input terminal P1 and the second data input terminal P2 of the frequency and phase detector circuit 100 are connected to a logic high-level signal H, and the input terminal IN of the count clearing circuit 400 is also connected to a logic high-level signal H. Logic levels are typically represented using binary 0 and 1, with "0" representing a logic low level and "1" representing a logic high level. Here, the logic high-level signal H is equivalent to logic high level 1. In practical applications, a 3.3V or 5V power supply voltage signal is typically connected to the corresponding port to indicate a logic high level, and grounding the corresponding port indicates a logic low level. For example, in practical applications, the first data input terminal P1 and the second data input terminal P2 of the frequency and phase detector circuit 100, as well as the input terminal IN of the count clearing circuit 400, can all be connected to a 3.3V or 5V power supply voltage signal to achieve the function of connecting the first data input terminal P1 and the second data input terminal P2 of the frequency and phase detector circuit 100, as well as the input terminal IN of the count clearing circuit 400, to the logic high-level signal H.

[0045] The core functions of a phase-locked loop (PLL) include frequency synthesis, clock synchronization, and signal modulation and demodulation, and it has wide applications in communications, industrial control, and radar. When used for clock synchronization, a PLL can achieve frequency and phase locking between a reference clock signal Ref_Clk and a feedback clock signal Fb_Clk. The reference clock signal Ref_Clk is a pre-set reference clock signal within the PLL, while the feedback clock signal Fb_Clk is the clock signal obtained by dividing the output signal of the voltage-controlled oscillator (VCO) in the PLL by a frequency divider.

[0046] The frequency and phase discrimination circuit 100 generates a first phase signal UP and a second phase signal DN based on the logic high-level signal H, the reference clock signal Ref_Clk, and the feedback clock signal Fb_Clk. When the reference clock signal Ref_Clk and the feedback clock signal Fb_Clk are out of phase, the generated first phase signal UP and second phase signal DN are also out of phase, exhibiting a phase deviation. This phase deviation can be represented by angle or time. In one example, when represented by angle, the phase deviation could be 1° or 2°; when represented by time, it could be 1ns or 2ns. In practical applications, most projects use time to represent the phase deviation.

[0047] The first OR gate 200 performs an OR operation on the first phase signal UP and the second phase signal DN, and outputs a first trigger signal Es_pre. The first trigger signal Es_pre can characterize the phase relationship between the first phase signal UP and the second phase signal DN, and transmits the first trigger signal Es_pre to the anti-spiking pulse circuit.

[0048] Anti-spiking circuits can filter out glitches in the input signal, making the output signal more stable. In one example, by setting a preset threshold, the anti-spiking circuit can shorten the pulse width of the first trigger signal Es_pre by the preset threshold, thus filtering out glitches in the first trigger signal Es_pre and obtaining the second trigger signal Es. The preset threshold can be set according to the user's design needs; for example, it can be set to 2ns or 3ns. For instance, assuming the pulse width of the first trigger signal Es_pre is 5ns, if the preset threshold is set to 3ns, the pulse width of the second trigger signal Es obtained after passing through the anti-spiking circuit will be 2ns, meaning the second trigger signal Es is a pulsed signal. Conversely, assuming the pulse width of the first trigger signal Es_pre is 2ns, if the preset threshold is set to 3ns, the pulse width of the second trigger signal Es obtained after passing through the anti-spiking circuit will be 0ns, meaning the second trigger signal Es is a pulseless signal.

[0049] The second trigger signal Es is used as an input signal to the count clearing circuit 400, so that the count clearing circuit 400 can output a lock indicator signal LOCK according to the second trigger signal Es, the feedback clock signal Fb_Clk and the logic high level signal H, which is used to indicate whether the phase-locked loop is locked.

[0050] The phase-locked loop (PLL) locking detection circuit provided in this application embodiment specifically includes: a frequency and phase discrimination circuit, a first OR gate, an anti-spiking pulse circuit, and a count clearing circuit. The frequency and phase discrimination circuit generates a first phase signal and a second phase signal based on a logic high-level signal, a reference clock signal, and a feedback clock signal. The first OR gate performs an OR operation on the first and second phase signals and outputs a first trigger signal. The anti-spiking pulse circuit shortens the pulse width of the first trigger signal according to a preset threshold to obtain a second trigger signal. The count clearing circuit then outputs a locking indication signal based on the second trigger signal, the feedback clock signal, and the logic high-level signal, used to indicate whether the PLL is locked. Compared with solutions provided by related technologies, the PLL locking detection circuit provided in this application embodiment has a different topology and can output a locking indication signal to detect whether the PLL is in a locked state.

[0051] In one possible embodiment, the anti-spiking pulse circuit 300 is specifically used to obtain a second trigger signal Es when the pulse width of the first trigger signal Es_pre is greater than a preset threshold, and the second trigger signal Es has a pulse.

[0052] When the pulse width of the first trigger signal Es_pre is less than or equal to a preset threshold, a second trigger signal Es is obtained, and the second trigger signal Es has no pulse.

[0053] The input of the anti-spiking circuit is connected to the first trigger signal Es_pre, and the output of the anti-spiking circuit outputs the second trigger signal Es. The anti-spiking circuit is used to process the first trigger signal Es_pre output by the first OR gate 200 to improve the stability of the second trigger signal Es.

[0054] Specifically, the anti-spiking circuit shortens the pulse width of the first trigger signal Es_pre according to a preset threshold to obtain the second trigger signal Es. For example, assuming the pulse width of the first trigger signal Es_pre is 5ns, if the preset threshold is set to 3ns, the pulse width of the first trigger signal Es_pre is greater than the preset threshold. After shortening the pulse width of the first trigger signal Es_pre according to the preset threshold, there will be a remaining pulse width. Therefore, the pulse width of the second trigger signal Es obtained after the first trigger signal Es_pre passes through the anti-spiking circuit is 2ns, and the second trigger signal Es is a pulsed signal. Conversely, assuming the pulse width of the first trigger signal Es_pre is 2ns, if the preset threshold is set to 3ns, the pulse width of the first trigger signal Es_pre is less than the preset threshold. After shortening the pulse width of the first trigger signal Es_pre according to the preset threshold, there will be no remaining pulse width. Therefore, the pulse width of the second trigger signal Es obtained after the first trigger signal Es_pre passes through the anti-spiking circuit is 0ns, and the second trigger signal Es is a pulseless signal.

[0055] By setting a preset threshold, the pulse width of the first trigger signal Es_pre is compared with the preset threshold to obtain different second trigger signals Es. For the anti-spiking pulse circuit, the preset threshold determines the time required for the anti-spiking pulse circuit to process the pulse (also known as the deglitch time). The larger the preset threshold is set, the shorter the time required for the first trigger signal Es_pre to convert to the pulse-free second trigger signal Es; the smaller the preset threshold is set, the longer the time required for the first trigger signal Es_pre to convert to the pulse-free second trigger signal Es.

[0056] In this embodiment of the application, by reasonably setting a preset threshold, the anti-spiking pulse circuit performs anti-spiking pulse processing on the first trigger signal Es_pre, and the resulting second trigger signal Es can be a signal with pulse or a signal without pulse, and is used as the input signal of the counting reset circuit to control the working state of the counting reset circuit.

[0057] In one possible embodiment, the counter reset circuit 400 is specifically used to control itself to reset and output a lock indication signal LOCK when there is a pulse in the second trigger signal Es, wherein the lock indication signal LOCK is low level and is used to indicate that the phase-locked loop is in an unlocked state.

[0058] The counter clearing circuit 400 is specifically used to delay the high-level control logic signal according to the feedback clock signal Fb_Clk when there is no pulse in the second trigger signal Es, and output the lock indicator signal LOCK. The lock indicator signal LOCK is high level, which is used to indicate that the phase-locked loop is in the locked state.

[0059] The anti-spiking pulse circuit 300 transmits its own output second trigger signal Es to the counting clear circuit 400, and uses it as the reset signal for the counting clear circuit 400. When there is a pulse in the second trigger signal Es, it controls itself to reset and outputs a lock indication signal LOCK. After the counting clear circuit 400 is reset, the output lock indication signal LOCK is low, i.e., LOCK=0. This signal can be used as a lost-lock flag to indicate that the phase-locked loop is in a lost-lock state (or an unlocked state).

[0060] In addition, the count reset circuit 400 is also used when the second trigger signal Es has no pulse and cannot be used as a reset signal for itself, thus failing to control its own reset. In this case, the count reset circuit 400 controls its input terminal IN to receive a logic high-level signal H for a delay based on the feedback clock signal Fb_Clk, and outputs a lock indicator signal LOCK. The logic high-level signal H is delayed and then output as the lock indicator signal LOCK. In this situation, the lock indicator signal LOCK is high, i.e., LOCK=1. This signal can be used as a lock flag to indicate that the phase-locked loop is in a locked state.

[0061] Based on all the above embodiments, the working process of the phase-locked loop locking detection circuit 1000 provided in this application is as follows: First, the frequency and phase discrimination circuit 100 generates a first phase signal UP and a second phase signal DN according to the logic high-level signal H, the reference clock signal Ref_Clk, and the feedback clock signal Fb_Clk; then, the first phase signal UP and the second phase signal DN are ORed by the first OR gate 200, and a first trigger signal Es_pre is output; the first trigger signal Es_pre is shortened by the anti-spiking pulse circuit 300 according to a preset threshold to obtain the second phase signal DN. The second trigger signal Es is used as the trigger signal for the count reset circuit 400. If there is a pulse in the second trigger signal Es, the circuit resets itself and outputs a lock indicator signal LOCK. At this time, the lock indicator signal LOCK is low, indicating that the phase-locked loop (PLL) is unlocked. If there is no pulse in the second trigger signal Es, the high-level control logic signal H is delayed according to the feedback clock signal Fb_Clk, and the lock indicator signal LOCK is output. At this time, the lock indicator signal LOCK is high, indicating that the PLL is locked. This process is used to detect whether the PLL is locked.

[0062] In one possible embodiment, see Figure 6 , Figure 6 A schematic diagram of another phase-locked loop (PLL) locking detection circuit provided in an embodiment of this application is shown below. Figure 6As shown, the frequency and phase detection circuit 100 includes: a first D flip-flop DFF1, a second D flip-flop DFF2, an AND gate, a delay unit DE, and a second OR gate.

[0063] The data terminal D1 of the first D flip-flop DFF1 is electrically connected to the first data input terminal P1 of the frequency and phase detection circuit 100, and is used to receive the logic high-level signal H. The clock terminal CLK1 of the first D flip-flop DFF1 is electrically connected to the first clock terminal CK1 of the frequency and phase detection circuit 100, and is used to receive the reference clock signal Ref_Clk. The output terminal Q11 of the first D flip-flop DFF1 is electrically connected to the first input terminal of the AND gate, and serves as the first output terminal P3 of the frequency and phase detection circuit 100, used to output the first phase signal UP.

[0064] The data terminal D2 of the second D flip-flop DFF2 is electrically connected to the second data input terminal P2 of the frequency and phase detection circuit 100, and is used to receive the logic high-level signal H. The clock terminal CLK2 of the second D flip-flop DFF2 is electrically connected to the second clock terminal CK2 of the frequency and phase detection circuit 100, and is used to receive the feedback clock signal Fb_Clk. The output terminal Q22 of the second D flip-flop DFF2 is electrically connected to the second input terminal of the AND gate, and serves as the second output terminal P4 of the frequency and phase detection circuit 100, used to output the second phase signal DN.

[0065] The output of the AND gate is electrically connected to the input of the delay unit DE. The output of the delay unit DE is electrically connected to the first input of the second OR gate OR. The second input of the second OR gate OR is connected to the enable signal ENB1.

[0066] The output of the second OR gate is electrically connected to the reset terminal RST11 of the first D flip-flop DFF1 and the reset terminal RST22 of the second D flip-flop DFF2, respectively.

[0067] Generally, a D flip-flop typically includes: a data input, a clock input, a reset input, a first output, and a second output. The data input is used to receive a high or low level signal, the clock input is used to receive a clock signal, the reset input is used to receive a reset signal, the first output latches the data input at the data input on the rising edge of the clock signal, and the output signal of the second output is logically opposite to that of the first output.

[0068] The frequency and phase detection circuit 100 in this application may include a first D flip-flop DF1, a second D flip-flop DF2, an AND gate, a delay unit DE, and a second OR gate. An enable signal ENB1 is connected to the second input of the second OR gate, which is used to control the reset of the first D flip-flop DF1 and the second D flip-flop DF2. Normally, the enable signal ENB1 is active when it is low.

[0069] The frequency and phase discrimination circuit 100 is a key module in the phase-locked loop. It is used to implement the phase comparison function between the reference clock signal Ref_Clk and the feedback clock signal Fb_Clk. It can generate the first phase signal UP and the second phase signal DN based on the logic high-level signal H, the reference clock signal Ref_Clk, and the feedback clock signal Fb_Clk.

[0070] Specifically, the first D flip-flop DFF1 latches the logic high-level signal H connected to its data terminal D1 when the rising edge of the reference clock signal Ref_Clk arrives, obtaining the first phase signal UP. Similarly, the second D flip-flop DF2 latches the logic high-level signal H connected to its data terminal D2 when the rising edge of the feedback clock signal Fb_Clk arrives, obtaining the second phase signal DN. The first phase signal UP and the second phase signal DN are then used as input signals for the subsequent circuit.

[0071] The AND gate, the DE delay gate, and the OR gate are used to perform delay and logic operations on the first phase signal UP and the second phase signal DN to obtain the reset signals of the first D flip-flop DFF1 and the second D flip-flop DF2, thereby realizing the reset function of the first D flip-flop DFF1 and the second D flip-flop DF2.

[0072] When there is a phase deviation between the reference clock signal Ref_Clk and the feedback clock signal Fb_Clk, there will also be a phase deviation between the first phase signal UP and the second phase signal DN output by the frequency and phase discrimination circuit 100.

[0073] In one possible embodiment, see Figure 6 The counter clearing circuit 400 includes N flip-flops, where N is a positive integer greater than or equal to 1.

[0074] The reset terminal of each flip-flop is electrically connected to the reset terminal RS of the count clearing circuit 400 to receive the second trigger signal Es. The clock terminal of each flip-flop is electrically connected to the clock terminal CK3 of the count clearing circuit 400 to receive the feedback clock signal Fb_Clk.

[0075] The data terminals and output terminals of each flip-flop are connected in series sequentially. The data terminal DN1 of the first flip-flop DFN1 among the N flip-flops serves as the input terminal IN of the count clearing circuit 400, used to connect to the logic high-level signal H. The output terminal QN1 of the first flip-flop DFN1 among the N flip-flops is electrically connected to the data terminal DN2 of the second flip-flop DFN2 among the N flip-flops. The output terminal QNN of the Nth flip-flop DFNN among the N flip-flops serves as the output terminal of the count clearing circuit 400, used to output the lock indication signal LOCK.

[0076] The counter clearing circuit 400 in this application may include N flip-flops, and the specific value of N can be selected from positive integers greater than or equal to 1 according to the user's needs. See also Figure 6 The counter reset circuit 400 includes N flip-flops, namely the first flip-flop DFN1, the second flip-flop DFN2, ..., the Nth flip-flop DFNN. The flip-flops can be D flip-flops.

[0077] The electrical connections of the N flip-flops are as follows: the reset terminal of each flip-flop is electrically connected to the reset terminal RS of the counting and clearing circuit 400, which is used to receive the second trigger signal Es. For example, the reset terminal RSTN1 of the first flip-flop DFN1, the reset terminal RSTN2 of the second flip-flop DFN2, ..., the reset terminal RSTNN of the Nth flip-flop DFNN are all electrically connected to the reset terminal RS of the counting and clearing circuit 400, which is used to receive the second trigger signal Es. When there is a pulse in the second trigger signal Es, each flip-flop is reset, which causes the counting and clearing circuit to clear to zero. The output lock indication signal LOCK is low, i.e., LOCK=0. This signal can be used as a lockout flag to indicate that the phase-locked loop is in a lockout state (or an unlocked state).

[0078] In addition, the clock terminal of each flip-flop is electrically connected to the clock terminal CK3 of the count clearing circuit 400 to receive the feedback clock signal Fb_Clk. For example, the clock terminal CLKN1 of the first flip-flop DFN1, the clock terminal CLKN2 of the second flip-flop DFN2, ..., the clock terminal CLKNN of the Nth flip-flop DFNN are all electrically connected to the clock terminal CK3 of the count clearing circuit 400 to receive the feedback clock signal Fb_Clk.

[0079] The data terminals and output terminals of N flip-flops are connected in series sequentially. Specifically, the data terminal DN1 of the first flip-flop DFN1 is used as the input terminal IN of the count clearing circuit 400, which is used to connect to the logic high-level signal H. Based on the sequential serial connection relationship of the data terminals and output terminals of the N flip-flops, when there is no pulse of the second trigger signal Es, the flip-flops will not be reset. When the rising edge of the feedback clock signal Fb_Clk arrives, the N flip-flops will be triggered, and the data terminal DN1 of the first flip-flop DFN1 will be connected to the logic high-level signal H. After being locked by the N flip-flops in sequence, the output is used as the lock indicator signal LOCK. At this time, the lock indicator signal LOCK is high, which is used to indicate that the phase-locked loop is in a locked state.

[0080] In this embodiment, N flip-flops are configured in the count-clearing circuit, with the reset terminal of each flip-flop electrically connected to the reset terminal of the count-clearing circuit to receive the second trigger signal. The clock terminal of each flip-flop is also electrically connected to the clock terminal of the count-clearing circuit to receive the feedback clock signal. Simultaneously, the data terminals and output terminals of each flip-flop are connected serially. Thus, when the second trigger signal has a pulse, each flip-flop is reset, causing the count-clearing circuit to clear, and the output lock indicator signal is low. When the second trigger signal has no pulse, the flip-flops do not reset. When the rising edge of the feedback clock signal arrives, all N flip-flops are triggered, and a logic high-level signal is connected to the input terminal of the count-clearing circuit for delay. After being locked sequentially by the N flip-flops, the output signal serves as the lock indicator signal. At this time, the lock indicator signal is high, indicating that the phase-locked loop (PLL) is in a locked state. Based on the above process, the state of the PLL is detected.

[0081] In one possible embodiment, the count clearing circuit 400 is specifically used to output the control logic high-level signal H after a delay of N feedback clock cycles when the second trigger signal Es has no pulse, and to serve as the lock indication signal LOCK, wherein the lock indication signal LOCK is high level to indicate that the phase-locked loop is in a locked state; the feedback clock cycle is the clock cycle corresponding to the feedback clock signal Fb_Clk.

[0082] See Figure 6 When there is no pulse in the second trigger signal Es, the flip-flops will not be reset. When the first rising edge of the feedback clock signal Fb_Clk arrives, the first flip-flop DFN1 among the N flip-flops latches its data terminal DN1 with a logic high-level signal H, and outputs it based on the output terminal QN1 to the data terminal DN2 of the second flip-flop DFN2 among the N flip-flops. When the second rising edge of the feedback clock signal Fb_Clk arrives, the second flip-flop DFN2 among the N flip-flops latches its data terminal DN2 with a logic high-level signal H, and outputs it based on the output terminal QN2 to the data terminal DN3 of the third flip-flop DFN3 among the N flip-flops... until the Nth rising edge of the feedback clock signal Fb_Clk arrives, the Nth flip-flop DFNN among the N flip-flops latches its data terminal DNN with a logic high-level signal H, and outputs it based on the output terminal QNN as the lock indicator signal LOCK. At this time, the lock indicator signal LOCK is high, used to indicate that the phase-locked loop is in a locked state.

[0083] Since the count clearing circuit 400 includes N flip-flops, the logic high-level signal H input to the count clearing circuit 400 needs to be delayed by N flip-flops before outputting the lock indication signal LOCK. During this process, the delay time is N feedback clock cycles, which is the clock cycle corresponding to the feedback clock signal Fb_Clk. That is, the logic high-level signal H needs to stabilize for N feedback clock cycles before it can finally indicate that the phase-locked loop is in a locked state. During this period, if the second trigger signal Es has a pulse, each flip-flop will be reset, causing the count clearing circuit to clear, and the output lock indication signal will be low, indicating that the phase-locked loop is in an unlocked state (or a unlocked state).

[0084] In one possible embodiment, when the phase-locked loop is in a locked state, the clock period corresponding to the feedback clock signal Fb_Clk is equal to the clock period corresponding to the reference clock signal Ref_Clk.

[0085] When the phase-locked loop is in the locked state, that is, when the phase-locked loop achieves synchronization between the feedback clock signal Fb_Clk and the reference clock signal Ref_Clk, the clock period corresponding to the feedback clock signal Fb_Clk is equal to the clock period corresponding to the reference clock signal Ref_Clk.

[0086] In this case, for the above embodiment, the count clearing circuit 400 is specifically used to output the control logic high-level signal H after a delay of N feedback clock cycles when the second trigger signal Es has no pulse, and this output serves as the lock indication signal LOCK. The lock indication signal LOCK is high to indicate that the phase-locked loop is in a locked state; the feedback clock cycle is the clock cycle corresponding to the feedback clock signal Fb_Clk. Since the clock cycle corresponding to the feedback clock signal Fb_Clk is equal to the clock cycle corresponding to the reference clock signal Ref_Clk, the count clearing circuit 400 is also used to output the control logic high-level signal H after a delay of N reference clock cycles when the second trigger signal Es has no pulse, and this output serves as the lock indication signal LOCK. The lock indication signal LOCK is high to indicate that the phase-locked loop is in a locked state; the reference clock cycle is the clock cycle corresponding to the reference clock signal Ref_Clk.

[0087] See Figure 7 , Figure 7 A timing diagram of a phase-locked loop (PLL) locking detection circuit provided in an embodiment of this application is shown below. Figure 7As shown, the frequency and phase detector circuit generates a first phase signal UP and a second phase signal DN. When the phase-locked loop is unlocked, since the reference clock signal Ref_Clk and the feedback clock signal Fb_Clk are asynchronous, the first phase signal UP and the second phase signal DN are also asynchronous, resulting in a phase deviation. Because the reset signals obtained after passing through an AND gate, a delay unit DE, and a second OR gate, the first phase signal UP and the second phase signal DN, are simultaneously transmitted to the first D flip-flop DFF1 and the second D flip-flop DFF2, the first phase signal UP and the second phase signal DN will be reset simultaneously, transitioning from high to low levels.

[0088] See Figure 7 The first OR gate 200 performs an OR operation on the first phase signal UP and the second phase signal DN to obtain the first trigger signal Es_pre. The waveform of the first trigger signal Es_pre is consistent with the waveform of the wider pulse in the first phase signal UP and the second phase signal DN.

[0089] See Figure 7 The anti-spiking circuit 300 shortens the pulse width of the first trigger signal Es_pre according to a preset threshold. Since the preset threshold determines the time required for the anti-spiking circuit to process the spikes (also known as the deglitch time), the second trigger signal Es can be obtained after shortening the pulse width of the first trigger signal Es_pre by the preset threshold. During the operation of the phase-locked loop, since the phase deviation between the reference clock signal Ref_Clk and the feedback clock signal Fb_Clk gradually decreases, the pulse width of the second trigger signal Es also gradually decreases. When there is no pulse in the second trigger signal Es, the logic high-level signal H outputs the lock indicator signal LOCK after a delay of N feedback clock cycles. At this time, the lock indicator signal LOCK is high, which is used to indicate that the phase-locked loop is in a locked state.

[0090] Based on all the above embodiments, the phase-locked loop (PLL) locking detection circuit provided in this application resets each flip-flop when the second trigger signal has a pulse, causing the count clearing circuit to clear and the output locking indication signal to be low. When the second trigger signal has no pulse, the flip-flops do not reset. When the rising edge of the feedback clock signal arrives, N flip-flops are triggered, and the input terminal of the count clearing circuit is connected to a logic high-level signal for delay. After the N flip-flops lock sequentially, the output is used as the locking indication signal. At this time, the locking indication signal is high, used to indicate that the PLL is in a locked state. Based on the above process, the PLL is detected to be in a locked state. Compared with the solutions in related technologies, this method can avoid the error of determining the PLL to be locked when the PLL is in an unlocked state by obtaining a high level of the PLL flag bit. This allows for accurate detection of whether the PLL is in a locked state and has good robustness.

[0091] This application also provides a phase-locked loop (PLL) locking detection method, see [link to relevant documentation]. Figure 8 , Figure 8 A flowchart of a phase-locked loop locking detection method provided in this application embodiment is shown below. Figure 8 As shown, the method includes: S1 generates a first phase signal and a second phase signal based on the logic high-level signal, the reference clock signal, and the feedback clock signal.

[0092] S2 performs an OR operation on the first phase signal and the second phase signal, and outputs the first trigger signal.

[0093] S3, shorten the pulse width of the first trigger signal according to a preset threshold to obtain the second trigger signal.

[0094] S4 outputs a lock indication signal based on the second trigger signal, the feedback clock signal, and the logic high-level signal. The lock indication signal is used to indicate whether the phase-locked loop is locked.

[0095] This application also provides a phase-locked loop (PLL) lock detection method, applied to the aforementioned PLL lock detection circuit. The method generates a first phase signal and a second phase signal based on a logic high-level signal, a reference clock signal, and a feedback clock signal. Then, it performs an OR operation on the first and second phase signals and outputs a first trigger signal. The pulse width of the first trigger signal is shortened according to a preset threshold to obtain a second trigger signal. Based on the second trigger signal, the feedback clock signal, and the logic high-level signal, a lock indication signal is output, wherein the lock indication signal is used to indicate whether the PLL is locked. This method can output a lock indication signal to detect whether the PLL is in a locked state.

[0096] This application also provides a chip, including: the phase-locked loop locking detection circuit as described above.

[0097] This chip can be a chip that includes a phase-locked loop (PLL) system, which includes a PLL lock-in detection circuit. Examples include PLL chips, PLL frequency synthesis chips, and clock circuit chips.

[0098] This application also provides an electronic device, including: the chip as described above.

[0099] This electronic device includes, but is not limited to, wireless communication devices, satellite communication devices, industrial automation devices, and measuring devices.

[0100] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A phase-locked loop (PLL) locking detection circuit, characterized in that, The phase-locked loop locking detection circuit includes: a frequency and phase discrimination circuit, a first OR gate, an anti-spiking pulse circuit, and a count clearing circuit; The first and second data input terminals of the frequency and phase detection circuit are connected to a logic high-level signal. The first clock terminal of the frequency and phase detection circuit is connected to a reference clock signal, and the second clock terminal of the frequency and phase detection circuit is connected to a feedback clock signal. The first output terminal of the frequency and phase detection circuit is electrically connected to the first input terminal of the first OR gate. The second output terminal of the frequency and phase detection circuit is electrically connected to the second input terminal of the first OR gate. The output terminal of the first OR gate is electrically connected to the input terminal of the anti-spiking circuit. The output terminal of the anti-spiking circuit is electrically connected to the reset terminal of the count clearing circuit. The clock terminal of the count clearing circuit is connected to the feedback clock signal, and the input terminal of the count clearing circuit is connected to the logic high-level signal. The frequency and phase discrimination circuit is used to generate a first phase signal and a second phase signal based on the logic high-level signal, the reference clock signal, and the feedback clock signal. The first OR gate is used to perform an OR operation on the first phase signal and the second phase signal, and output a first trigger signal; The anti-spiking pulse circuit is used to shorten the pulse width of the first trigger signal according to a preset threshold to obtain a second trigger signal; The count reset circuit is used to output a lock indication signal based on the second trigger signal, the feedback clock signal, and the logic high-level signal, wherein the lock indication signal is used to indicate whether the phase-locked loop is locked.

2. The phase-locked loop locking detection circuit according to claim 1, characterized in that, The anti-spiking pulse circuit is specifically used to obtain the second trigger signal when the pulse width of the first trigger signal is greater than the preset threshold, and the second trigger signal has a pulse; When the pulse width of the first trigger signal is less than or equal to the preset threshold, the second trigger signal is obtained, and the second trigger signal has no pulse.

3. The phase-locked loop locking detection circuit according to claim 2, characterized in that, The counting reset circuit is specifically used to control itself to reset when there is a pulse in the second trigger signal, and output the lock indication signal, wherein the lock indication signal is low level, used to indicate that the phase-locked loop is in an unlocked state; The count clearing circuit is specifically used to control the logic high-level signal to delay according to the feedback clock signal when there is no pulse in the second trigger signal, and output the lock indication signal, wherein the lock indication signal is high level and is used to indicate that the phase-locked loop is in a locked state.

4. The phase-locked loop locking detection circuit according to claim 1, characterized in that, The frequency and phase detection circuit includes: a first D flip-flop, a second D flip-flop, an AND gate, a delay unit, and a second OR gate; The data terminal of the first D flip-flop is electrically connected to the first data input terminal of the frequency and phase detection circuit to receive the logic high-level signal; the clock terminal of the first D flip-flop is electrically connected to the first clock terminal of the frequency and phase detection circuit to receive the reference clock signal; the output terminal of the first D flip-flop is electrically connected to the first input terminal of the AND gate and serves as the first output terminal of the frequency and phase detection circuit to output the first phase signal. The data terminal of the second D flip-flop is electrically connected to the second data input terminal of the frequency and phase detection circuit to receive the logic high-level signal; the clock terminal of the second D flip-flop is electrically connected to the second clock terminal of the frequency and phase detection circuit to receive the feedback clock signal; the output terminal of the second D flip-flop is electrically connected to the second input terminal of the AND gate and serves as the second output terminal of the frequency and phase detection circuit to output the second phase signal. The output of the AND gate is electrically connected to the input of the delay unit, the output of the delay unit is electrically connected to the first input of the second OR gate, and the second input of the second OR gate is connected to an enable signal. The output of the second OR gate is electrically connected to the reset terminal of the first D flip-flop and the reset terminal of the second D flip-flop, respectively.

5. The phase-locked loop locking detection circuit according to claim 3, characterized in that, The count clearing circuit includes N flip-flops, where N is a positive integer greater than or equal to 1; The reset terminal of each of the flip-flops is electrically connected to the reset terminal of the count clearing circuit to receive the second trigger signal, and the clock terminal of each of the flip-flops is electrically connected to the clock terminal of the count clearing circuit to receive the feedback clock signal. The data terminals and output terminals of each flip-flop are connected in series sequentially. The data terminal of the first flip-flop among the N flip-flops serves as the input terminal of the count clearing circuit, used to connect to the logic high-level signal. The output terminal of the first flip-flop among the N flip-flops is electrically connected to the data terminal of the second flip-flop among the N flip-flops. The output terminal of the Nth flip-flop among the N flip-flops serves as the output terminal of the count clearing circuit, used to output the lock indication signal.

6. The phase-locked loop locking detection circuit according to claim 5, characterized in that, The count clearing circuit is specifically used to control the logic high-level signal to be delayed by N feedback clock cycles and output when there is no pulse in the second trigger signal, and to serve as the lock indication signal. The lock indication signal is high level and is used to indicate that the phase-locked loop is in a locked state. The feedback clock cycle is the clock cycle corresponding to the feedback clock signal.

7. The phase-locked loop locking detection circuit according to claim 6, characterized in that, When the phase-locked loop is in a locked state, the clock period corresponding to the feedback clock signal is equal to the clock period corresponding to the reference clock signal.

8. A method for detecting phase-locked loop (PLL) locking, characterized in that, The method, applied to the phase-locked loop locking detection circuit as described in any one of claims 1-7, comprises: Based on the logic high-level signal, the reference clock signal, and the feedback clock signal, generate the first phase signal and the second phase signal; Perform an OR operation on the first phase signal and the second phase signal, and output the first trigger signal; The pulse width of the first trigger signal is shortened according to a preset threshold to obtain the second trigger signal; Based on the second trigger signal, the feedback clock signal, and the logic high-level signal, a lock indication signal is output, wherein the lock indication signal is used to indicate whether the phase-locked loop is locked.

9. A chip, characterized in that, include: The phase-locked loop locking detection circuit as described in any one of claims 1-7.

10. An electronic device, characterized in that, include: The chip as described in claim 9.

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