Sampling switch circuit for high-precision SAR ADC
By combining an operational amplifier and an N-type MOS transistor in a feedback circuit, along with substrate switching technology, the gate voltage bootstrap function of a high-precision SAR ADC was realized. This solved the problems of charge injection and clock feedthrough effects in traditional switching circuits, and improved sampling accuracy and linearity.
Patent Information
- Application Number
- CN202511589190.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-03
- Publication Date
- 2026-02-10
AI Technical Summary
Traditional SAR ADCs suffer from channel charge injection, clock feedthrough effect, and bias effect in their gate voltage bootstrap switching circuits, which leads to decreased accuracy and limited application range.
A gate voltage boosting circuit is constructed using a first operational amplifier circuit and an N-type MOS transistor. Combined with a substrate switching circuit, the gate drive voltage is boosted through closed-loop feedback, reducing nonlinear distortion and stabilizing the gate-source voltage of the switching transistor.
The linearity and speed of the sampling switch circuit were improved, the on-resistance variation was reduced, the problem of charge leakage from the bootstrap capacitor was solved, and the sampling accuracy was improved.
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Figure CN121508536A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to analog integrated circuits, and more specifically to a sampling switch circuit for a high-precision SAR ADC. Background Technology
[0002] The sample-and-hold switch circuit module is one of the key modules of an ADC (Analog-to-Digital Converter). Converting a continuous-time analog signal into a discrete analog signal is the first step of an ADC; therefore, any high-speed, high-precision ADC cannot function without a high-performance sample-and-hold circuit. As an important component of the sample-and-hold circuit, the performance of the sampling switch determines the performance of the entire sample-and-hold circuit.
[0003] Referring to the background section of patent application CN119675646A, conventional gate voltage bootstrap switching circuits for SAR ADCs, such as Figure 1 As shown, when the clock signal Clk is low, the inverted clock signal Clkn is high. At this time, MOSFETs M1, M3, M4, M7, and M9 are turned on, and the voltage at node c is the power supply voltage AVDD. When the clock signal Clk is high, MOSFET M10 is turned on, and the voltage at node a is the input signal Vin. Since the bootstrap capacitor Cs has charge conservation, the voltage change at node c is AVDD + Vin. Furthermore, since MOSFET M5 is turned on, the voltage at node d is equal to the voltage at node c. Therefore, the gate voltage of MOSFET M11 is AVDD + Vin, thus realizing the gate voltage bootstrap function.
[0004] In existing technologies, charge injection occurs the instant the MOSFET M11, acting as the main switch, is turned off. When MOSFET M11 is in the on-state, charge accumulates in the inversion layer within its channel. When the switch is turned off, this accumulated charge flows out through the source and drain of MOSFET M11; this phenomenon is known as channel charge injection. Additionally, a clock feedthrough effect also occurs the instant MOSFET M11 is turned off. Furthermore, the change in Vbs caused by the change in Vin of MOSFET M11 leads to a bias effect that distorts the output. The bootstrap function also relies on clock signal control. If the clock is not operated for a long time, the charge in the bootstrap capacitor will dissipate, also reducing the accuracy of the sampling switch. Clock feedthrough and charge injection affect the sampling accuracy of the switch, thus limiting the application range of gate voltage bootstrap switch circuits.
[0005] Therefore, to address the aforementioned technical problems, it is necessary to provide a new circuit structure for implementing gate voltage bootstrapping functionality. Summary of the Invention
[0006] To improve the linearity and speed of switching, this invention proposes a sampling switch circuit for high-precision SAR ADCs. This circuit employs a first operational amplifier circuit and an N-type MOS transistor acting as a source follower to form a gate voltage boosting circuit, ensuring that the output voltage of the first operational amplifier circuit is always higher than the input signal by the gate-source voltage V of the source follower. GS The output voltage of the first operational amplifier circuit is used as the power supply for the pull-up-pull-down switch. During the sampling and conversion process, the working state of the pull-up-pull-down switch is controlled by the sampling clock signal. The output terminal of the pull-up-pull-down switch directly drives the gate of the sampling switch.
[0007] Furthermore, the control signal for accessing the sampling switch substrate is controlled by the substrate switching circuit.
[0008] Furthermore, the substrate switching circuit includes a second operational amplifier circuit and two N-type MOS transistors. The second operational amplifier circuit is used to increase the gain of the input signal. The increased input signal is connected to the drain of one of the N-type MOS transistors. The gate of the N-type MOS transistor is connected to the inverted signal of the sampling clock signal. The source of the N-type MOS transistor is connected to the drain of the other N-type MOS transistor and the substrate of the sampling switch. The gate of the other N-type MOS transistor is connected to the sampling clock signal, and the source of the other N-type MOS transistor is grounded.
[0009] Furthermore, the closed-loop feedback formed by the first operational amplifier circuit and the source follower specifically includes the source follower and the first to thirty-third MOSFETs. The gate of the first MOSFET serves as the inverting input terminal of the first operational amplifier circuit, and the gate of the second MOSFET serves as the inverting input terminal of the first operational amplifier circuit, wherein:
[0010] The gate of the first MOSFET is connected to the source of the source follower and the drain of the thirteenth MOSFET. The source of the first MOSFET is connected to the source of the second MOSFET and the drain of the twenty-ninth MOSFET. The drain of the first MOSFET is connected to the source of the nineteenth MOSFET and the drain of the twentieth MOSFET.
[0011] The gate of the second MOSFET is connected to the input signal of the sampling switch circuit, and its drain is connected to the source of the seventeenth MOSFET and the drain of the eighteenth MOSFET.
[0012] The gate and drain of the third MOSFET are connected to the gates of the fifth MOSFET, the seventh MOSFET, the thirteenth MOSFET, and the bias voltage terminal. The source is connected to the gate and source of the fourth MOSFET, the gate of the sixth MOSFET, and the gate of the eighth MOSFET.
[0013] The sources of the fourth, sixth, eighth, ninth, tenth, eleventh, twelfth, sixteenth, eighteenth, and twentieth MOSFETs are connected to the ground terminal.
[0014] The source of the fifth MOSFET is connected to the drain of the sixth MOSFET, and the drain is connected to the drain and gate of the twenty-first MOSFET, the gate of the twenty-second MOSFET, the gate of the twenty-seventh MOSFET, the gate of the twenty-eighth MOSFET, the gate of the twenty-ninth MOSFET, the gate of the thirty-first MOSFET, and the gate of the thirty-third MOSFET.
[0015] The source of the seventh MOSFET is connected to the drain of the eighth MOSFET, and the source is connected to the drain of the twenty-second MOSFET, the gate of the twenty-third MOSFET, the gate of the twenty-fourth MOSFET, the gate of the twenty-fifth MOSFET, and the gate of the twenty-sixth MOSFET.
[0016] The gate of the ninth MOSFET is connected to the gates of the tenth, eleventh, twelfth, sixteenth, eighteenth, and twentieth MOSFETs, the drain of the fifteenth MOSFET, and the drain of the twenty-eighth MOSFET. The drain of the ninth MOSFET is connected to the drains of the tenth, eleventh, and twelfth MOSFETs, the source of the thirteenth MOSFET, and the source of the fourteenth MOSFET.
[0017] The gate and drain of the fourteenth MOSFET are connected together with the gates of the fifteenth MOSFET, the seventeenth MOSFET, the nineteenth MOSFET, and the drain of the twenty-seventh MOSFET.
[0018] The source of the fifteenth MOSFET is connected to the drain of the sixteenth MOSFET;
[0019] The drain of the seventeenth MOSFET is connected to the drain of the thirty-first MOSFET, the gate of the thirtieth MOSFET, and the gate of the thirty-second MOSFET.
[0020] The drain of the nineteenth MOSFET is connected to the gate of the source follower and the drain of the thirty-third MOSFET, and serves as the output of the closed-loop feedback.
[0021] The sources of the twenty-first, twenty-third, twenty-fourth, twenty-fifth, twenty-sixth, thirtieth, and thirty-second MOSFETs are connected to the power supply terminal.
[0022] The source of the 22nd MOSFET is connected to the drain of the 23rd MOSFET;
[0023] The drain of the 24th MOSFET is connected to the source of the 27th MOSFET;
[0024] The drain of the 25th MOSFET is connected to the source of the 28th MOSFET;
[0025] The drain of the 26th MOSFET is connected to the source of the 29th MOSFET;
[0026] The drain of the 30th MOSFET is connected to the source of the 31st MOSFET;
[0027] The drain of the thirty-second MOSFET is connected to the source of the thirty-third MOSFET.
[0028] Furthermore, the first to twentieth MOSFETs are N-type MOSFETs, and the twenty-first to thirty-third MOSFETs are P-type MOSFETs.
[0029] Furthermore, the pull-up / pull-down switch includes a P-type MOS transistor and an N-type MOS transistor. The gates of the P-type MOS transistor and the N-type MOS transistor are connected together with the sampling clock signal. The source of the N-type MOS transistor is grounded. The source of the P-type MOS transistor is connected to the output terminal of the first operational amplifier circuit. The drains of the P-type MOS transistor and the N-type MOS transistor are connected to the gate of the sampling switch.
[0030] This invention uses a combination of operational amplifier and source follower feedback to boost the gate drive voltage. Combined with substrate switching technology, it can effectively reduce the nonlinear distortion of the switching MOSFET and improve the performance of the sampling switching circuit. Attached Figure Description
[0031] Figure 1 This is a structural diagram of a traditional gate voltage bootstrap circuit in the prior art;
[0032] Figure 2 This is a structural diagram of a sampling switch circuit for a high-precision SAR ADC proposed in this invention;
[0033] Figure 3 This is a circuit diagram illustrating the gate voltage boosting function in this invention.
[0034] Figure 4 The above is the FFT analysis result of the sampling switch circuit of the present invention applied to the actual SAR ADC circuit. Detailed Implementation
[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0036] This invention proposes a sampling switch circuit for high-precision SAR ADCs. This circuit employs a first operational amplifier circuit and an N-type MOS transistor acting as a source follower to form a closed-loop feedback, ensuring that the output voltage of the first operational amplifier circuit is always higher than the input signal by the gate-source voltage V of the source follower. GS The output voltage of the first operational amplifier circuit is used as the power supply for the pull-up-pull-down switch. During the sampling and conversion process, the working state of the pull-up-pull-down switch is controlled by the sampling clock signal. The output terminal of the pull-up-pull-down switch directly drives the gate of the sampling switch.
[0037] In successive approximation analog-to-digital converters (SAR ADCs), the performance of the sample-and-hold circuit directly determines the overall conversion accuracy and speed. To achieve high linearity and low distortion sampling, gate voltage bootstrapping technology is often used to boost the gate voltage to VDD+Vin during the conduction phase in order to reduce the change in conduction impedance.
[0038] The formula for the on-resistance Ron of a MOSFET is as follows:
[0039]
[0040] in These are process-related parameters. W / L is the width-to-length ratio of the MOSFET. Therefore, as long as Vgs-Vth is a fixed value, the on-resistance of the MOSFET will be constant.
[0041] Based on the above, this invention designs a novel switching circuit structure for SAR ADCs, which has a gate voltage bootstrapping function and can achieve stable high gate voltage drive without the need for a bootstrapping capacitor, thereby reducing on-resistance, reducing distortion and suppressing non-ideal effects.
[0042] To achieve the above objectives, this embodiment provides a sampling switch circuit for a SAR ADC, the specific circuit diagram of which is shown below. Figure 2 It includes a gate voltage boosting circuit 1, a pull-up / pull-down switch 2, a sampling switch 3, and a substrate switching circuit 4, wherein:
[0043] Sampling switch 3 is implemented using an N-type MOSFET M0_6;
[0044] The first operational amplifier circuit AMP_1 and an N-type MOS transistor M0_1, which acts as a source follower, constitute a gate voltage boosting circuit. The output of the gate voltage boosting circuit provides power to the pull-up / pull-down switch 2.
[0045] The pull-up / pull-down switch 2 provides gate drive as a MOS switching circuit and is controlled by the sampling clock signal sw. The sampling clock signal is low voltage (generally set to 0) during the sampling phase and high voltage during the holding phase.
[0046] The substrate switching circuit 4 is controlled by the sampling clock signal sw and its inverted signal swn. It includes a second operational amplifier circuit AMP_2 and two N-type MOS transistors. The second operational amplifier circuit is used to increase the gain of the input signal Vin. The increased input signal is connected to the drain of one of the N-type MOS transistors M0_5. The gate of the N-type MOS transistor M0_5 is connected to the inverted signal swn of the sampling clock signal. The source of the N-type MOS transistor M0_5 is connected to the drain of another N-type MOS transistor M0_4 and the substrate of the sampling switch M0_6. The gate of the other N-type MOS transistor M0_4 is connected to the sampling clock signal sw, and the source of the other N-type MOS transistor M0_4 is grounded.
[0047] This invention employs an operational amplifier and a source follower to form a closed-loop feedback, ensuring that the output voltage of the first operational amplifier circuit AMP_1 is always higher than the input signal by the gate-source voltage V of the N-type MOS transistor M0_1, which acts as the source follower. GS The output of the first operational amplifier circuit AMP_1 is used as the power supply for the pull-up-pull-down switch 2. During sampling and conversion, the working state of the pull-up-pull-down switch is controlled by the sampling clock signal sw. The output of the pull-up-pull-down switch 2 directly drives the gate of the sampling switch M0_6, that is, the output voltage of the first operational amplifier circuit AMP_1 drives the gate of the sampling switch M0_6. The high level generated by the active circuit replaces the boost voltage generated by the traditional bootstrap capacitor, and realizes the function of the traditional gate voltage bootstrap switch. It can also stabilize the gate-source voltage of the switch, that is, the on-resistance of the sampling switch is constant, and the problem of charge discharge of the bootstrap capacitor in the traditional gate voltage bootstrap circuit will not occur.
[0048] Furthermore, the substrate switching circuit in this invention employs a unity negative feedback operational amplifier to ensure that the amplifier output follows the input signal. During the sampling phase, under the control of the switch, the substrate voltage of the sampling switch is set to the same potential as the input signal; when in the hold phase, the substrate voltage is switched to ground potential, thus resolving the substrate bias effect of the sampling switch.
[0049] The first operational amplifier circuit employs a differential P-type MOS input folded common-source common-gate circuit to achieve high gain and meet stability requirements. The output is fed back to the negative input of the operational amplifier via a source follower circuit. When the operational amplifier gain is high, the output voltage is the power supply voltage Vin plus the gate-source voltage Vgs of the N-type MOS transistor acting as the source follower. That is, the output voltage of the first operational amplifier circuit is Vin + Vgs, thus boosting the output voltage. As an optional implementation, the first operational amplifier circuit includes a source follower and first to thirty-third MOS transistors. The gate of the first MOS transistor serves as the inverting input of the first operational amplifier circuit, and the gate of the second MOS transistor also serves as the inverting input. Figure 3 ,in:
[0050] The gate of the first MOSFET M1 is connected to the source of the N-type MOSFET M0_1 (which is a source follower) and the drain of the thirteenth MOSFET M13. The source is connected to the source of the second MOSFET M2 and the drain of the twenty-ninth MOSFET M29. The drain is connected to the source of the nineteenth MOSFET M19 and the drain of the twentieth MOSFET M20.
[0051] The gate of the second MOSFET M2 is connected to the input signal Vin of the sampling switch circuit, and its drain is connected to the source of the seventeenth MOSFET M17 and the drain of the eighteenth MOSFET M18.
[0052] The gate and drain of the third MOSFET M3 are connected to the gate of the fifth MOSFET M5, the gate of the seventh MOSFET M7, the gate of the thirteenth MOSFET M13, and the bias voltage terminal Vb. The source is connected to the gate and source of the fourth MOSFET M4, the gate of the sixth MOSFET M6, and the gate of the eighth MOSFET M8.
[0053] The sources of the fourth MOSFET M4, the sixth MOSFET M6, the eighth MOSFET M8, the ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, the sixteenth MOSFET M16, the eighteenth MOSFET M18, and the twentieth MOSFET M20 are connected to the ground terminal AGND.
[0054] The source of the fifth MOSFET M5 is connected to the drain of the sixth MOSFET M6, and the drain is connected to the drain and gate of the twenty-first MOSFET M21, the gate of the twenty-second MOSFET M22, the gate of the twenty-seventh MOSFET M27, the gate of the twenty-eighth MOSFET M28, the gate of the twenty-ninth MOSFET M29, the gate of the thirty-first MOSFET M31, and the gate of the thirty-third MOSFET M33.
[0055] The source of the seventh MOSFET M7 is connected to the drain of the eighth MOSFET M8, and the source is connected to the drain of the twenty-second MOSFET M22, the gate of the twenty-third MOSFET M23, the gate of the twenty-fourth MOSFET M24, the gate of the twenty-fifth MOSFET M25, and the gate of the twenty-sixth MOSFET M26.
[0056] The gate of the ninth MOSFET M9 is connected to the gates of the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, the sixteenth MOSFET M16, the eighteenth MOSFET M18, the twentieth MOSFET M20, the drain of the fifteenth MOSFET M15, and the drain of the twenty-eighth MOSFET M28. The drain of the ninth MOSFET M9 is connected to the drains of the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, the source of the thirteenth MOSFET M13, and the source of the fourteenth MOSFET M14.
[0057] The gate and drain of the fourteenth MOSFET M14 are connected to the gates of the fifteenth MOSFET M15, the seventeenth MOSFET M17, the nineteenth MOSFET M19, and the drain of the twenty-seventh MOSFET M27.
[0058] The source of the fifteenth MOSFET M15 is connected to the drain of the sixteenth MOSFET M16;
[0059] The drain of the seventeenth MOSFET M17 is connected to the drain of the thirty-first MOSFET M31, the gate of the thirtieth MOSFET M30, and the gate of the thirty-second MOSFET M32.
[0060] The drain of the nineteenth MOSFET M19 is connected to the gate of the N-type MOSFET M0_1 (which serves as a source follower) and the drain of the thirty-third MOSFET M33, and serves as the output of the closed-loop feedback.
[0061] The sources of the twenty-first MOSFET M21, the twenty-third MOSFET M23, the twenty-fourth MOSFET M24, the twenty-fifth MOSFET M25, the twenty-sixth MOSFET M26, the thirtieth MOSFET M30, and the thirty-second MOSFET M32 are connected to the power supply terminal VANA.
[0062] The source of the twenty-second MOSFET M22 is connected to the drain of the twenty-third MOSFET M23;
[0063] The drain of the 24th MOSFET M24 is connected to the source of the 27th MOSFET M27;
[0064] The drain of the 25th MOSFET M25 is connected to the source of the 28th MOSFET M28;
[0065] The drain of the 26th MOSFET M26 is connected to the source of the 29th MOSFET M29;
[0066] The drain of the 30th MOSFET M30 is connected to the source of the 31st MOSFET M31;
[0067] The drain of the thirty-second MOSFET M32 is connected to the source of the thirty-third MOSFET M33.
[0068] The output voltage of the first operational amplifier circuit serves as the gate drive voltage for the sampling switch, providing a stable Vgs for the switching transistor. Combined with substrate switching technology, this ensures a constant output resistance for the switching transistor and reduces non-ideal effects. It solves the problem of charge leakage from the bootstrap capacitor in traditional gate voltage bootstrap switches, significantly improving the linearity of the switch.
[0069] To further verify the above-mentioned advantages of the present invention, the present invention was applied to a SAR ADC circuit and simulated, as follows: Figure 4 An FFT analysis of the sampling switch revealed that it has an effective bit depth of 17.2 bits, a signal-to-noise ratio (SINAD) of 105.4 dB, and a signal-to-noise ratio (SNR) of 130.1 dB, indicating that the sampling switch circuit of this invention has good performance.
[0070] In the description of this invention, it should be understood that the terms "coaxial," "bottom," "one end," "top," "middle," "other end," "upper," "side," "top," "inner," "outer," "front," "center," "both ends," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0071] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," "fixing," "rotation," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Unless otherwise explicitly limited, those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0072] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A sampling switch circuit for a high-precision SAR ADC, characterized in that, This circuit uses a first operational amplifier circuit and an N-type MOS transistor as a source follower to form a gate voltage boosting circuit, so that the output voltage of the first operational amplifier circuit is always higher than the input signal by the gate-source voltage V of the source follower. GS The output voltage of the first operational amplifier circuit is used as the power supply for the pull-up-pull-down switch. During the sampling and conversion process, the working state of the pull-up-pull-down switch is controlled by the sampling clock signal. The output terminal of the pull-up-pull-down switch directly drives the gate of the sampling switch.
2. The sampling switch circuit for a high-precision SAR ADC according to claim 1, characterized in that, The control signal for accessing the sampling switch substrate is controlled by the substrate switching circuit.
3. A sampling switch circuit for a high-precision SAR ADC according to claim 1 or 2, characterized in that, The substrate switching circuit includes a second operational amplifier circuit and two N-type MOS transistors. The second operational amplifier circuit is used to increase the gain of the input signal. The increased input signal is connected to the drain of one of the N-type MOS transistors. The gate of the N-type MOS transistor is connected to the inverted signal of the sampling clock signal. The source of the N-type MOS transistor is connected to the drain of the other N-type MOS transistor and the substrate of the sampling switch. The gate of the other N-type MOS transistor is connected to the sampling clock signal, and the source of the other N-type MOS transistor is grounded.
4. A sampling switch circuit for a high-precision SAR ADC according to claim 1 or 2, characterized in that, The gate voltage boosting circuit, composed of the first operational amplifier circuit and the source follower, specifically includes the source follower and the first to thirty-third MOSFETs. The gate of the first MOSFET serves as the inverting input terminal of the first operational amplifier circuit, and the gate of the second MOSFET serves as the inverting input terminal of the first operational amplifier circuit. The gate of the first MOSFET is connected to the source of the source follower and the drain of the thirteenth MOSFET. The source of the first MOSFET is connected to the source of the second MOSFET and the drain of the twenty-ninth MOSFET. The drain of the first MOSFET is connected to the source of the nineteenth MOSFET and the drain of the twentieth MOSFET. The gate of the second MOSFET is connected to the input signal of the sampling switch circuit, and its drain is connected to the source of the seventeenth MOSFET and the drain of the eighteenth MOSFET. The gate and drain of the third MOSFET are connected to the gates of the fifth MOSFET, the seventh MOSFET, the thirteenth MOSFET, and the bias voltage terminal. The source is connected to the gate and source of the fourth MOSFET, the gate of the sixth MOSFET, and the gate of the eighth MOSFET. The sources of the fourth, sixth, eighth, ninth, tenth, eleventh, twelfth, sixteenth, eighteenth, and twentieth MOSFETs are connected to the ground terminal. The source of the fifth MOSFET is connected to the drain of the sixth MOSFET, and the drain is connected to the drain and gate of the twenty-first MOSFET, the gate of the twenty-second MOSFET, the gate of the twenty-seventh MOSFET, the gate of the twenty-eighth MOSFET, the gate of the twenty-ninth MOSFET, the gate of the thirty-first MOSFET, and the gate of the thirty-third MOSFET. The source of the seventh MOSFET is connected to the drain of the eighth MOSFET, and the source is connected to the drain of the twenty-second MOSFET, the gate of the twenty-third MOSFET, the gate of the twenty-fourth MOSFET, the gate of the twenty-fifth MOSFET, and the gate of the twenty-sixth MOSFET. The gate of the ninth MOSFET is connected to the gates of the tenth, eleventh, twelfth, sixteenth, eighteenth, and twentieth MOSFETs, the drain of the fifteenth MOSFET, and the drain of the twenty-eighth MOSFET. The drain of the ninth MOSFET is connected to the drains of the tenth, eleventh, and twelfth MOSFETs, the source of the thirteenth MOSFET, and the source of the fourteenth MOSFET. The gate and drain of the fourteenth MOSFET are connected together with the gates of the fifteenth MOSFET, the seventeenth MOSFET, the nineteenth MOSFET, and the drain of the twenty-seventh MOSFET. The source of the fifteenth MOSFET is connected to the drain of the sixteenth MOSFET; The drain of the seventeenth MOSFET is connected to the drain of the thirty-first MOSFET, the gate of the thirtieth MOSFET, and the gate of the thirty-second MOSFET. The drain of the nineteenth MOSFET is connected to the gate of the source follower and the drain of the thirty-third MOSFET, and serves as the output of the closed-loop feedback. The sources of the twenty-first, twenty-third, twenty-fourth, twenty-fifth, twenty-sixth, thirtieth, and thirty-second MOSFETs are connected to the power supply terminal. The source of the 22nd MOSFET is connected to the drain of the 23rd MOSFET; The drain of the 24th MOSFET is connected to the source of the 27th MOSFET; The drain of the 25th MOSFET is connected to the source of the 28th MOSFET; The drain of the 26th MOSFET is connected to the source of the 29th MOSFET; The drain of the 30th MOSFET is connected to the source of the 31st MOSFET; The drain of the thirty-second MOSFET is connected to the source of the thirty-third MOSFET.
5. A sampling switch circuit for a high-precision SAR ADC according to claim 4, characterized in that, The first to twentieth MOSFETs are N-type MOSFETs, and the twenty-first to thirty-third MOSFETs are P-type MOSFETs.
6. A sampling switch circuit for a high-precision SAR ADC according to claim 1, characterized in that, The pull-up / pull-down switch includes a P-type MOSFET and an N-type MOSFET. The gates of the P-type MOSFET and the N-type MOSFET are connected together with the sampling clock signal. The source of the N-type MOSFET is grounded. The source of the P-type MOSFET is connected to the output terminal of the first operational amplifier circuit. The drains of the P-type MOSFET and the N-type MOSFET are connected to the gate of the sampling switch.
Citation Information
Patent Citations
Gate voltage bootstrapped switch circuit for SAR ADC
CN119675646A