Two-path switching data weighted average circuit and analog-to-digital converter

Abstract

The invention discloses a two-path switching data weighted average circuit and an analog-to-digital converter, and belongs to the technical field of signal processing.The two-path switching data weighted average circuit comprises a first data selector, a second data selector, a first DWA sub-circuit and a second DWA sub-circuit, the input end of the first data selector is connected with a binary input signal, and the input end of the second data selector is connected with a binary output signal; the first output end and the second output end of the first data selector are respectively connected with the input end of the first DWA sub-circuit and the input end of the second DWA sub-circuit, and the output end of the first DWA sub-circuit and the output end of the second DWA sub-circuit are respectively connected with the first input end and the second input end of the second data selector. Based on the characteristic that an input signal has randomness, according to the fact that the lowest bit of the input signal is' 0 'or' 1 ', random switching is carried out in two paths of data weighted average circuits, and spurious generation is restrained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, in particular to a two-path switching data weighted averaging circuit and an analog-to-digital converter. BACKGROUND

[0002] Sigma Delta ADC is the abbreviation of Sigma-Delta Modulator Analog-to-Digital Converter, the internal quantization mode is divided into single-bit quantization and multi-bit quantization, the single-bit quantization circuit contains a 1-bit ADC and a 1-bit DAC (Digital-to-Analog Converter) inside, and the multi-bit quantization circuit contains an N-bit ADC and an N-bit DAC inside. Corresponding to the structure block diagram as shown in Figure 1 The main contents include: a sample and hold amplifier (not shown), a differential amplifier or subtractor, an integrator (or an analog low-pass filter), a 1-bit or multi-bit A / D converter (comparator), a 1-bit or multi-bit DAC, a digital filter and a decimator. The core of the Sigma Delta ADC is divided into two parts: Sigma-Delta modulator and digital filter.

[0003] In recent years, the multi-bit quantization mode has gradually become the mainstream design direction of Sigma Delta ADC. The advantages are that it can increase the SNR (Signal-to-Noise Ratio), make the system easy to stabilize, produce fewer harmonic components, and make the decimation filter relatively simple, and the disadvantage is that the linearity of the circuit depends on the linearity of the DAC. Using DWA (Data Weighted Averaging) switching technology (industry conventional practice) can improve the linearity of the DAC and improve the SNR of the system, but the periodic characteristics of DWA will produce in-band spurious tones, which limits the dynamic performance of the ADC.

[0004] It should be noted that the information disclosed in the background art part of the present application is only intended to deepen the understanding of the general background art of the present application, and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. SUMMARY

[0005] The purpose of the present application is to provide a two-path switching data weighted averaging circuit and an analog-to-digital converter to solve the problem of in-band spurious tones.

[0006] To solve the above technical problems, the present application provides a two-way switching data weighted average circuit, comprising a first data selector, a second data selector, a first DWA sub-circuit and a second DWA sub-circuit, the input end of the first data selector is connected with a binary input signal, the first output end and the second output end of the first data selector are respectively connected with the input end of the first DWA sub-circuit and the input end of the second DWA sub-circuit, the output end of the first DWA sub-circuit and the output end of the second DWA sub-circuit are respectively connected with the first input end and the second input end of the second data selector, wherein: The least significant data of the input signal is output to the control end of the first data selector and the control end of the second data selector, the first data selector is used for selecting the input signal to be output to the first DWA sub-circuit or the second DWA sub-circuit for processing according to the least significant data of the input signal, and a shift control signal is generated, and the second data selector outputs the generated shift control signal to a barrel shifter under the control of the least significant data of the input signal.

[0007] Preferably, the first data selector and the second data selector are both 2-to-1 data selectors.

[0008] Preferably, a thermometer decoder is further included, the input end of the thermometer decoder is connected with the input signal, and the output end of the thermometer decoder is connected with the barrel shifter, which is used for encoding the input signal into a corresponding thermometer code and outputting the thermometer code to the barrel shifter.

[0009] Preferably, the first DWA sub-circuit comprises a first full adder and a first D flip-flop, the first input end of the first full adder is connected with the first output end of the first data selector, the output end of the first full adder is connected with the input end of the first D flip-flop, the output end of the first D flip-flop is connected with the first input end of the second data selector and the second input end of the first full adder, and the carry output end of the first full adder is connected with the carry input end.

[0010] Preferably, the first DWA sub-circuit and the second DWA sub-circuit have the same circuit structure.

[0011] Preferably, the second DWA sub-circuit comprises a second full adder and a second D flip-flop, the first input end of the second full adder is connected with the second output end of the first data selector, the output end of the second full adder is connected with the input end of the second D flip-flop, the output end of the second D flip-flop is connected with the second input end of the second data selector and the second input end of the second full adder, and the carry output end of the second full adder is connected with the carry input end.

[0012] Preferably, the input signal is 3-bit data, 4-bit data, 5-bit data, or 6-bit data.

[0013] An analog-to-digital converter (ADC) includes a two-channel switching data weighted averaging circuit. The two-channel switching data weighted averaging circuit includes a first data selector, a second data selector, a first DWA sub-circuit, and a second DWA sub-circuit. The input terminal of the first data selector is connected to a binary input signal. The first and second output terminals of the first data selector are respectively connected to the input terminals of the first and second DWA sub-circuits. The output terminals of the first and second DWA sub-circuits are respectively connected to the first and second input terminals of the second data selector. Wherein: The least significant bit of the input signal is output to the control terminals of the first data selector and the second data selector. The first data selector is used to select the least significant bit of the input signal and output it to the first DWA sub-circuit or the second DWA sub-circuit for processing to generate a shift control signal. Under the control of the least significant bit of the input signal, the second data selector outputs the generated shift control signal to the barrel shifter.

[0014] Preferably, both the first data selector and the second data selector are 2-to-1 data selectors.

[0015] Preferably, the first DWA sub-circuit includes a first full adder and a first D flip-flop. The first input terminal of the first full adder is connected to the first output terminal of the first data selector. The output terminal of the first full adder is connected to the input terminal of the first D flip-flop. The output terminal of the first D flip-flop is connected to the first input terminal of the second data selector and the second input terminal of the first full adder. The carry output terminal of the first full adder is connected to the carry input terminal. The first DWA sub-circuit and the second DWA sub-circuit have the same circuit structure.

[0016] In the two-channel switching data weighted averaging circuit provided by the present invention, the randomness of the least significant bit "0" or "1" of the binary input signal is utilized to introduce a data selector. Under the control of the least significant bit of the input signal, the two-channel data weighted averaging circuit is randomly switched to suppress spurious generation.

[0017] The analog-to-digital converter provided by this invention and the two-channel switching data weighted averaging circuit provided by this invention belong to the same inventive concept. Therefore, the analog-to-digital converter provided by this invention has at least all the advantages of the two-channel switching data weighted averaging circuit provided by this invention, which will not be repeated here. Attached Figure Description

[0018] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein: Figure 1 This refers to the location of the DWA algorithm circuit in the Sigma Delta ADC in the existing technology; Figure 2 It is a Sigma Delta ADC architecture in the existing technology; Figure 3 This is a schematic diagram of an existing DWA circuit; Figure 4 It is the encoding table of existing technology DWA; Figure 5 This is a circuit architecture diagram of a two-channel switching data weighted average according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the input signal encoding according to an embodiment of the present invention; Figure 7 This is a barrel-shaped shifter according to an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0020] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] like Figure 2 As shown, the Σ∆ modulator architecture in Yi-Gyeong Kim's paper "105.5 dB, 0.49 mm² Σ∆ modulator with chopper stabilization and fully randomized DWA" is illustrated, along with existing DWA circuit diagrams and encoding tables, such as... Figure 3 and Figure 4 As shown, research has found that randomized DWA can suppress the generation of spurious signals.

[0022] Further research revealed that the input signal of the DWA circuit has a random characteristic, and this randomness has a certain regularity, which can be used to control the output or input of the DWA circuit.

[0023] Based on this, the core idea of ​​the present invention is to suppress spurious emissions by randomly switching between two data weighted averaging circuits based on the randomness of the input signal and the least significant bit of the input signal being either "0" or "1".

[0024] For details, please refer to Figures 5-7 This is a schematic diagram of an embodiment of the present invention. Figure 5 As shown, a two-way switching data weighted averaging circuit includes a first data selector MUX1, a second data selector MUX2, a first DWA sub-circuit DWA_1, and a second DWA sub-circuit DWA_2. The input terminal of the first data selector MUX1 is connected to a binary input signal. The first and second output terminals of the first data selector MUX1 are respectively connected to the input terminals of the first DWA sub-circuit DWA_1 and the second DWA sub-circuit DWA_2. The output terminals of the first DWA sub-circuit DWA_1 and the second DWA sub-circuit DWA_2 are respectively connected to the first and second input terminals of the second data selector MUX2. Wherein: The least significant bit of the input signal is output to the control terminals of the first data selector MUX1 and the second data selector MUX2. The first data selector MUX1 is used to select the least significant bit of the input signal and output it to the first DWA sub-circuit DWA_1 or the second DWA sub-circuit DWA_2 for processing to generate a shift control signal. Under the control of the least significant bit of the input signal, the second data selector MUX2 outputs the generated shift control signal to the barrel shifter.

[0025] In a DWA circuit, the input signal is generally binary data. The least significant bit or last bit of the binary data is either logic "0" or logic "1", and the occurrence of logic "0" or logic "1" is random. Based on this characteristic, a data selector is introduced. The least significant bit of the input signal is used to control the data selector. The first data selector MUX1 selectively transmits the input signal to the first DWA sub-circuit DWA_1 or the second DWA sub-circuit DWA_2 for processing. Similarly, under the control of the least significant bit of the input signal, the second data selector MUX2 outputs the processed signal to the barrel shifter at the output terminal, thereby realizing random switching between the two data weighted averaging circuits and suppressing spurious signal generation.

[0026] Specifically, both the first data selector MUX1 and the second data selector MUX2 are 2-to-1 data selectors.

[0027] In one embodiment, a thermometer decoder is further included. The input terminal of the thermometer decoder is connected to the input signal, and the output terminal is connected to the barrel shifter. The decoder is used to encode the input signal into a corresponding thermometer code and output it to the barrel shifter. Figure 7 As shown, the barrel shifter consists of 21 two-way selectors, or two-to-one data selectors (MUX).

[0028] Understandably, under the combined action of the first data selector MUX1 and the second data selector MUX2, the DWA sub-circuit for data processing is selected based on the least significant bit of the input signal, and the processed signal is output to the barrel shifter. If the first data selector MUX1 is not present at the input end, the input signal will enter both DWA sub-circuits. Regardless of which DWA sub-circuit output the second data selector MUX2 selects, its overall function is equivalent to a single DWA circuit. Therefore, the first data selector MUX1 and the second data selector MUX2 are respectively set at the input and output ends to select either the first DWA sub-circuit DWA_1 or the second DWA sub-circuit DWA_2 to process the input signal.

[0029] For example, the input signal can be 3-bit, 4-bit, 5-bit, or 6-bit data. Since the occurrence of the last two bits ("0" and "1") in any binary data is random, and the probability of "0" and "1" appearing is equal, the number of bits in the input signal is not limited to the data described above, and can also be other types of data.

[0030] Specifically, the first DWA sub-circuit DWA_1 includes a first full adder and a first D flip-flop DFF1. The first input terminal of the first full adder is connected to the first output terminal of the first data selector MUX1. The output terminal of the first full adder is connected to the input terminal of the first D flip-flop DFF1. The output terminal of the first D flip-flop DFF1 is connected to the first input terminal of the second data selector MUX2 and the second input terminal of the first full adder. The carry output terminal of the first full adder is connected to the carry input terminal.

[0031] The first DWA sub-circuit DWA_1 and the second DWA sub-circuit DWA_2 have the same circuit structure.

[0032] Similarly, the second DWA sub-circuit DWA_2 includes a second full adder and a second D flip-flop DFF2. The first input of the second full adder is connected to the second output of the first data selector MUX1. The output of the second full adder is connected to the input of the second D flip-flop DFF2. The output of the second D flip-flop DFF2 is connected to the second input of the second data selector MUX2 and the second input of the second full adder. The carry output of the second full adder is connected to the carry input.

[0033] This explanation will be based on an example where the input signal has 3 bits of data. Figure 5The input signal IN<2:0> will have its least significant bit IN... <0> The input is given to the control terminals of the first data selector MUX1 and the second data selector MUX2, selecting the output to either the first DWA sub-circuit DWA_1 or the second DWA sub-circuit DWA_2. The first DWA sub-circuit DWA_1 is connected to the first output terminal (port "0") of the first data selector MUX1, and the second DWA sub-circuit DWA_2 is connected to the second output terminal (port "1") of the first data selector MUX1. The first DWA sub-circuit DWA_1 is also connected to the first input terminal (port "0") of the second data selector MUX2, and the second DWA sub-circuit DWA_2 is connected to the second input terminal (port "1") of the second data selector MUX2. If IN... <0> If = 0, then the first DWA sub-circuit DWA_1 switches, and the second DWA sub-circuit DWA_2 remains unchanged; if IN <0> =1, then the first DWA sub-circuit DWA_1 remains unchanged, the second DWA sub-circuit DWA_2 switches, and finally the output code is obtained after passing through the barrel shifter. Figure 6 As shown.

[0034] The first data selector MUX1 uses the least significant bit IN of the input signal. <0> Under control, when the input signal is transmitted to the first DWA sub-circuit DWA_1, the input and output terminals of the first full adder and the first D flip-flop DFF1 are both set to receive three bits of data. The first input terminal A<2:0> of the first full adder is used to receive the data transmitted from the first data selector MUX1, and outputs the data D<2:0> to the input terminal D of the first D flip-flop DFF1 at the output terminal S<2:0>. The second input terminal B<2:0> of the first full adder is also connected to the output terminal Q of the first D flip-flop DFF1 and the first input terminal of the second data selector MUX2. The carry output terminal Co and the carry input terminal Ci of the first full adder are connected. The first D flip-flop DFF1 is also connected to the clock signal CLK. The output terminal Q of the first D flip-flop DFF1 outputs the shift control signal Q<2:0> to the second data selector MUX2. Under the same control signal, the second data selector MUX2 selects the output M<2:0> to output to the barrel shifter.

[0035] Similarly, the first data selector MUX1 uses the least significant bit IN of the input signal. <0> Under control, when the input signal is transmitted to the second DWA sub-circuit DWA_2, the same execution flow is followed, which will not be described in detail here.

[0036] Based on the same technical concept, the present invention also provides an analog-to-digital converter, including a two-channel switching data weighted averaging circuit. The two-channel switching data weighted averaging circuit includes a first data selector MUX1, a second data selector MUX2, a first DWA sub-circuit DWA_1, and a second DWA sub-circuit DWA_2. The input terminal of the first data selector MUX1 is connected to a binary input signal. The first and second output terminals of the first data selector MUX1 are respectively connected to the input terminals of the first DWA sub-circuit DWA_1 and the second DWA sub-circuit DWA_2. The output terminals of the first DWA sub-circuit DWA_1 and the second DWA sub-circuit DWA_2 are respectively connected to the first and second input terminals of the second data selector MUX2, wherein: The least significant bit of the input signal is output to the control terminals of the first data selector MUX1 and the second data selector MUX2. The first data selector MUX1 is used to select the least significant bit of the input signal and output it to the first DWA sub-circuit DWA_1 or the second DWA sub-circuit DWA_2 for processing to generate a shift control signal. Under the control of the least significant bit of the input signal, the second data selector MUX2 outputs the generated shift control signal to the barrel shifter.

[0037] The analog-to-digital converter is a Σ-Δ modulator analog-to-digital converter, and its internal quantization method is multi-bit quantization.

[0038] Under the combined action of the first data selector MUX1 and the second data selector MUX2, the DWA sub-circuit for data processing is selected based on the least significant bit of the input signal, and the processed signal is output to the barrel shifter. If the first data selector MUX1 is not present at the input end, the input signal will enter both DWA sub-circuits. Regardless of which DWA sub-circuit output the second data selector MUX2 selects, its overall function is equivalent to a single DWA circuit. Therefore, the first data selector MUX1 and the second data selector MUX2 are respectively set at the input and output ends to select either the first DWA sub-circuit DWA_1 or the second DWA sub-circuit DWA_2 to process the input signal.

[0039] More preferably, both the first data selector MUX1 and the second data selector MUX2 are 2-to-1 data selectors.

[0040] Specifically, the first DWA sub-circuit DWA_1 includes a first full adder and a first D flip-flop DFF1. The first input terminal of the first full adder is connected to the first output terminal of the first data selector MUX1, the output terminal of the first full adder is connected to the input terminal of the first D flip-flop DFF1, the output terminal of the first D flip-flop DFF1 is connected to the first input terminal of the second data selector MUX2 and the second input terminal of the first full adder, and the carry output terminal of the first full adder is connected to the carry input terminal. The first DWA sub-circuit DWA_1 and the second DWA sub-circuit DWA_2 have the same circuit structure.

[0041] In the two-channel switching data weighted averaging circuit and analog-to-digital converter provided by the present invention, based on the randomness of the input signal, the two-channel data weighted averaging circuit is randomly switched according to whether the least significant bit of the input signal is "0" or "1", thereby suppressing the generation of spurious signals.

[0042] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A two-channel switching data weighted averaging circuit, characterized in that, The system includes a first data selector, a second data selector, a first DWA subcircuit, and a second DWA subcircuit. The input of the first data selector is connected to a binary input signal. The first and second outputs of the first data selector are respectively connected to the inputs of the first and second DWA subcircuits. The outputs of the first and second DWA subcircuits are respectively connected to the first and second inputs of the second data selector. The least significant bit of the input signal is output to the control terminals of the first data selector and the second data selector. The first data selector is used to select the least significant bit of the input signal and output it to the first DWA sub-circuit or the second DWA sub-circuit for processing to generate a shift control signal. Under the control of the least significant bit of the input signal, the second data selector outputs the generated shift control signal to the barrel shifter.

2. The two-channel switching data weighted averaging circuit according to claim 1, characterized in that, Both the first data selector and the second data selector are 2-to-1 data selectors.

3. The two-channel switching data weighted averaging circuit according to claim 1, characterized in that, It also includes a thermometer decoder, the input terminal of which is connected to the input signal and the output terminal of which is connected to the barrel shifter, for encoding the input signal into the corresponding thermometer code and outputting it to the barrel shifter.

4. The two-channel switching data weighted averaging circuit according to claim 1, characterized in that, The first DWA sub-circuit includes a first full adder and a first D flip-flop. The first input terminal of the first full adder is connected to the first output terminal of the first data selector. The output terminal of the first full adder is connected to the input terminal of the first D flip-flop. The output terminal of the first D flip-flop is connected to the first input terminal of the second data selector and the second input terminal of the first full adder. The carry output terminal of the first full adder is connected to the carry input terminal.

5. The two-channel switching data weighted averaging circuit according to claim 1, characterized in that, The first DWA sub-circuit and the second DWA sub-circuit have the same circuit structure.

6. The two-channel switching data weighted averaging circuit according to claim 1, characterized in that, The second DWA sub-circuit includes a second full adder and a second D flip-flop. The first input terminal of the second full adder is connected to the second output terminal of the first data selector. The output terminal of the second full adder is connected to the input terminal of the second D flip-flop. The output terminal of the second D flip-flop is connected to the second input terminal of the second data selector and the second input terminal of the second full adder. The carry output terminal of the second full adder is connected to the carry input terminal.

7. The two-channel switching data weighted averaging circuit according to claim 1, characterized in that, The input signal is 3-bit data, 4-bit data, 5-bit data, or 6-bit data.

8. An analog-to-digital converter, characterized in that, The system includes a two-channel switching data weighted averaging circuit. This circuit comprises a first data selector, a second data selector, a first DWA sub-circuit, and a second DWA sub-circuit. The input of the first data selector is connected to a binary input signal. The first and second outputs of the first data selector are respectively connected to the inputs of the first and second DWA sub-circuits. The outputs of the first and second DWA sub-circuits are respectively connected to the first and second inputs of the second data selector. The least significant bit of the input signal is output to the control terminals of the first data selector and the second data selector. The first data selector is used to select the least significant bit of the input signal and output it to the first DWA sub-circuit or the second DWA sub-circuit for processing to generate a shift control signal. Under the control of the least significant bit of the input signal, the second data selector outputs the generated shift control signal to the barrel shifter.

9. The analog-to-digital converter according to claim 8, characterized in that, Both the first data selector and the second data selector are 2-to-1 data selectors.

10. The analog-to-digital converter according to claim 8, characterized in that, The first DWA sub-circuit includes a first full adder and a first D flip-flop. The first input terminal of the first full adder is connected to the first output terminal of the first data selector. The output terminal of the first full adder is connected to the input terminal of the first D flip-flop. The output terminal of the first D flip-flop is connected to the first input terminal of the second data selector and the second input terminal of the first full adder. The carry output terminal of the first full adder is connected to the carry input terminal. The first DWA sub-circuit and the second DWA sub-circuit have the same circuit structure.

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