Method and device for detecting power of repeater system, and storage medium

Abstract

The invention discloses a power detection method and device of a repeater system and a storage medium, an upper computer, a target bus and a controller are deployed in the repeater system, the controller sequentially executes a plurality of controller tasks in a preset polling period, and the plurality of controller tasks comprise a query task for querying the power of one or more power links, a query task for querying the power of the target bus, and a query task for querying the power of the target bus. The method is applied to the controller, and comprises the following steps: detecting a target query frequency of an upper computer for querying a target power link in one or more power links through a target bus; allocating task durations of the plurality of controller tasks according to the target query frequency to obtain allocated controller tasks and task durations with a corresponding relationship; and executing the plurality of controller tasks according to the allocated controller tasks and task durations with the corresponding relationship, and by adopting the technical scheme, the problems of low accuracy of power detection of the repeater system and the like are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a method and device for detecting power of a repeater system, and a storage medium. BACKGROUND

[0002] In the prior art, a controller of a repeater executes multiple controller tasks in a preset polling period according to a fixed time allocation scheme. In the scheme, the query tasks of multiple power links are allocated a fixed and short detection duration (such as 100 ms), and the algorithm tasks of running controller algorithms are allocated a fixed and long execution duration (such as 1.6 s).

[0003] The fixed and rigid time allocation scheme results in that when on-demand detection of a specific power link is required, the system cannot concentrate resources and must wait for a complete polling period to obtain data once, resulting in low detection efficiency. At the same time, since the sampling duration allocated to a single power link is fixed and short, in a scenario requiring long-time sampling to obtain high-precision data, the scheme cannot provide sufficient data quantity, resulting in low detection accuracy.

[0004] There is no effective solution to the problem of low accuracy of power detection of a repeater system in the related art. SUMMARY

[0005] Embodiments of the present application provide a method and device for detecting power of a repeater system, and a storage medium, to at least solve the problem of low accuracy of power detection of a repeater system in the related art.

[0006] According to one embodiment of an embodiment of the present application, a method for detecting power of a repeater system is provided. An upper computer, a target bus and a controller are deployed in the repeater system. The target bus is connected between the upper computer and the controller. The controller executes multiple controller tasks in a preset polling period. The multiple controller tasks include a query task of querying power of one or more power links and an algorithm task of running a controller algorithm. The method is applied to the controller and includes the following steps.

[0007] Detecting a target query frequency at which the upper computer queries a target power link in the one or more power links through the target bus;

[0008] Allocating task durations of the multiple controller tasks according to the target query frequency to obtain the controller tasks and the task durations after allocation, which have a corresponding relationship, wherein the higher the query frequency of the power link is, the higher the proportion of the duration of the task duration in the preset polling period is;

[0009] perform the plurality of controller tasks according to the assigned controller tasks and the task duration with the corresponding relationship.

[0010] Optionally, the detecting the target query frequency of the target power link queried by the host computer through the target bus includes:

[0011] collecting a query request sent by the host computer through the target bus in a first detection period, wherein the query request is used to request to query power of one or more power links;

[0012] detecting, from the query request, a number of times that the power of the target power link is requested to be queried to obtain a target number of times;

[0013] determining a ratio of the target number of times to the first detection period as the target query frequency.

[0014] Optionally, the assigning a task duration of a plurality of controller tasks according to the target query frequency includes:

[0015] detecting a target frequency range into which the target query frequency falls in a plurality of frequency ranges;

[0016] selecting, from frequency range and duration assignment information with a corresponding relationship, target duration assignment information corresponding to the target frequency range, wherein the target duration assignment information records a duration assignment operation for each of the controller tasks;

[0017] assigning, according to a duration assignment operation indicated by the target duration assignment information, a task duration occupied by a plurality of controller tasks in the preset polling period to obtain the assigned controller tasks and the task duration with the corresponding relationship.

[0018] Optionally, the selecting, from the frequency range and duration assignment information with the corresponding relationship, the target duration assignment information corresponding to the target frequency range includes:

[0019] in a case where the target frequency range is a frequency range greater than or equal to a first frequency threshold, selecting, from the frequency range and duration assignment information with the corresponding relationship, first duration assignment information, wherein a first duration assignment operation indicated by the first duration assignment information includes: increasing a first execution duration of a first query task for querying the target power link, decreasing a second execution duration of a second query task for querying the power link other than the target power link in the one or more power links, and maintaining a third execution duration of the algorithm task unchanged;

[0020] determining the first duration allocation information as the target duration allocation information.

[0021] Optionally, after determining the first duration allocation information as the target duration allocation information, the method further comprises:

[0022] detecting whether the host computer is still continuously querying the target power link;

[0023] in a case where it is detected that the host computer is still continuously querying the target power link, determining second duration allocation information as the target duration allocation information, wherein a second duration allocation operation indicated by the second duration allocation information comprises: after performing the first duration allocation operation indicated by the first duration allocation information, continuing to increase the first execution duration, maintaining the second execution duration unchanged, and decreasing the third execution duration.

[0024] Optionally, after the task durations of the plurality of controller tasks are allocated according to the target query frequency, to obtain the controller tasks and the task durations having a corresponding relationship after allocation, the method further comprises:

[0025] detecting whether one or more of the power links satisfy a reset triggering condition;

[0026] in a case where it is detected that one or more of the power links satisfy the reset triggering condition, restoring the task durations of the plurality of controller tasks to corresponding initial durations.

[0027] Optionally, the detecting whether one or more of the power links satisfy the reset triggering condition comprises:

[0028] detecting, in a second detection period, a first query frequency of the target power link, and detecting a second query frequency of the power link other than the target power link among the one or more of the power links;

[0029] in a case where it is detected that the first query frequency is less than or equal to a second frequency threshold, and / or, it is detected that the second query frequency of the reference power link other than the target power link among the one or more of the power links is greater than or equal to a third frequency threshold, it is determined that one or more of the power links satisfy the reset triggering condition.

[0030] According to another embodiment of the embodiment of the present application, a device for detecting power of a repeater system is further provided. The repeater system is deployed with a host computer, a target bus and a controller. The target bus is connected between the host computer and the controller. The controller executes a plurality of controller tasks in a preset polling period in sequence. The plurality of controller tasks include a query task for querying power of one or more power links and an algorithm task for running a controller algorithm. The device is applied to the controller and includes:

[0031] A first detecting module is configured to detect a target query frequency of the host computer querying a target power link in the one or more power links via the target bus.

[0032] A distributing module is configured to distribute task time lengths of the plurality of controller tasks according to the target query frequency, to obtain the controller tasks and the task time lengths having a corresponding relationship after distribution. The task time length of the power link with a higher query frequency is allocated with a higher proportion of time length in the preset polling period.

[0033] An executing module is configured to execute the plurality of controller tasks according to the controller tasks and the task time lengths having the corresponding relationship after distribution.

[0034] According to still another aspect of the embodiment of the present application, a computer readable storage medium is further provided. The computer readable storage medium stores a computer program. The computer program is set to execute the above-mentioned method for detecting power of a repeater system when running.

[0035] According to still another aspect of the embodiment of the present application, an electronic device is further provided. The electronic device includes a memory, a processor and a computer program stored in the memory and capable of running on the processor. The processor executes the above-mentioned method for detecting power of a repeater system through the computer program.

[0036] In the embodiment of the present application, the scheme provides a power detection method applied to a controller. The method first detects a target query frequency of a target power link in one or more power links queried by an upper computer through a target bus. Then, task durations of a plurality of controller tasks are allocated according to the target query frequency, to obtain the controller tasks and the task durations after allocation and having a corresponding relationship. The allocation ensures that the higher the query frequency of the power link is, the higher the proportion of the duration of the task duration in the preset polling period is, so that more time resources are dynamically concentrated on the link that needs high-frequency sampling. Finally, the controller executes the plurality of controller tasks according to the controller tasks and the task durations after allocation and having a corresponding relationship, thereby improving the detection efficiency and accuracy of the specific power link. By using the above technical scheme, the problems such as low accuracy of power detection of the repeater system in the related art are solved, and the technical effect of improving the accuracy of power detection of the repeater system is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0037] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0039] Figure 1 FIG. 1 is a hardware environment schematic diagram of a power detection method of a repeater system according to an embodiment of the present application;

[0040] Figure 2 FIG. 2 is a flowchart of a power detection method of a repeater system according to an embodiment of the present application;

[0041] Figure 3 FIG. 3 is a schematic diagram of a power detection flow of a repeater system according to an embodiment of the present application;

[0042] Figure 4 FIG. 4 is a structural block diagram of a power detection device of a repeater system according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the personnel in the technical field better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should fall within the scope of protection of the present application.

[0044] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0045] The method embodiments provided by the embodiments of the present application can be executed in a computer terminal, a device terminal or similar computing devices. Taking the running on a computer terminal as an example, Figure 1 is a hardware environment schematic diagram of a method for detecting the power of a repeater system according to the embodiments of the present application. As shown in Figure 1 , the computer terminal can include one or more (only one is shown in Figure 1 ) processor 102 (the processor 102 can include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, in an exemplary embodiment, the above-mentioned computer terminal can also include a transmission device 106 for communication function and an input and output device 108. Those of ordinary skill in the art can understand that Figure 1 The structure shown is only schematic, which does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal can also include more or fewer components than Figure 1 shown, or have a different configuration with the same function as Figure 1 shown or more functions than Figure 1 shown.

[0046] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the power detection method of the repeater system in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0047] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0048] This embodiment provides a method for detecting the power of a repeater system, applied to the aforementioned computer terminal. Figure 2 This is a flowchart of a power detection method for a repeater system according to an embodiment of this application, as shown below. Figure 2 As shown, the repeater system deploys a host computer, a target bus, and a controller. The target bus connects the host computer and the controller. Within a preset polling cycle, the controller sequentially executes multiple controller tasks. These tasks include: a query task to check the power of one or more power links, and an algorithm task to run a controller algorithm. The method is applied to the controller, and the process includes the following steps:

[0049] Step S1: Detect the host computer querying the target query frequency of one or more target power links in the power links through the target bus;

[0050] Step S2: Allocate the task duration of multiple controller tasks according to the target query frequency to obtain the allocated controller tasks and task durations with corresponding relationships. Among them, the power link with a higher query frequency has a higher proportion of the allocated task duration in the preset polling cycle.

[0051] Step S3: Execute the multiple controller tasks according to the assigned controller tasks with corresponding relationships and the task duration.

[0052] This solution provides a power detection method for a controller. The method first detects the target query frequency of one or more power links queried by the host computer via the target bus. Then, it allocates the task durations of multiple controller tasks according to the target query frequency, resulting in corresponding controller tasks and task durations. This allocation ensures that the power link with a higher query frequency receives a higher proportion of its task duration within the preset polling cycle, thus dynamically concentrating more time resources on links requiring high-frequency sampling. Finally, the controller executes the multiple controller tasks according to the corresponding controller tasks and task durations, thereby improving the detection efficiency and accuracy of specific power links. This technical solution solves the problem of low accuracy in power detection in repeater systems, achieving the technical effect of improving the accuracy of power detection in repeater systems.

[0053] Optionally, in this embodiment, the host computer may, but is not limited to, instruct: a supervisory system or main control unit whose function is to monitor the overall status of the repeater and initiate data query requests.

[0054] Optionally, in this embodiment, the target bus may, but is not limited to, indicate: a serial or parallel data bus for transmitting query commands and reporting data between the host computer and the controller.

[0055] Optionally, in this embodiment, the controller may, but is not limited to, instruct a hardware logic unit, such as a field-programmable gate array (FPGA), configured to perform logic for time-division multiplexing detection and dynamic time allocation.

[0056] Optionally, in this embodiment, the preset polling period can be, but is not limited to, an indication of a time base required to fully detect all tasks, such as 2000 milliseconds (2 seconds).

[0057] Optionally, in this embodiment, the controller task may, but is not limited to, indicating: a set of all events that need to be scheduled and executed by the controller (FPGA) within a preset polling period.

[0058] Optionally, in this embodiment, the query task may, but is not limited to, instructing: the controller (FPGA) to control the analog-to-digital converter (ADDA) chip to collect power data of a specific physical link (such as A-path reflection, B-path feedback, C-path reception, and D-path transmission) and perform statistical analysis.

[0059] Optionally, in this embodiment, the algorithm task may, but is not limited to, instructing the controller (FPGA) or ADDA chip to perform internal processing tasks (such as E-paths) required by its internal data processing, system calibration, status self-test, or filter calculation.

[0060] Optionally, in this embodiment, the target power link may, but is not limited to, indicate a specific power link that is currently frequently queried by the host computer, such as the A-path reflection signal.

[0061] Optionally, in this embodiment, the target query frequency may be, but is not limited to, an indicator: a numerical value used to quantify the urgency of queries by the host computer, such as the number of queries per unit time.

[0062] Optionally, in this embodiment, the task duration may be, but is not limited to, an execution time slice allocated to a specific controller task (such as A-way query or E-way algorithm) within a preset polling period (such as 2000ms).

[0063] Optionally, in this embodiment, the duration percentage can be, but is not limited to, indicating: the percentage of a task's duration to the total duration of a preset polling cycle, for example, 100ms / 2000ms = 5%.

[0064] Optionally, in this embodiment, the above scheme can be explained using, but is not limited to, the following scenario: The initial state of the system controller (FPGA) is to execute five controller tasks within a preset polling cycle of 2000ms, with a fixed initial time allocation: A-path (reflection) query task (100ms), B-path (feedback) query task (100ms), C-path (receive) query task (100ms), D-path (transmit) query task (100ms), and E-path (algorithm) task (1600ms). At a certain moment, the A-path (reflection) signal exhibits abnormal fluctuations. The host computer system detects this state and begins to initiate a high-frequency query for the A-path power to the controller (FPGA) via the target bus. The controller (FPGA) executes the first step: detecting a significant increase in the "target query frequency" of the A-path (target power link). The controller (FPGA) then executes the second step: dynamically allocating the duration of these five tasks according to this frequency. Since the A-path has the highest query frequency, its "duration percentage" is determined to need to be increased. For example, the system calculates a new allocation vector: the duration of task A becomes 500ms (its proportion increases from 5% to 25%), the duration of tasks B, C, and D is shortened to 50ms (each accounting for 2.5%), and the duration of algorithm task E is shortened to 1350ms (accounting for 67.5%). The controller (FPGA) then executes the third step: according to this new allocation vector {A=500, B=50, C=50, D=50, E=1350}, it executes these five controller tasks.

[0065] This embodiment achieves the following technical effects: it enables intelligent switching from a fixed time allocation vector to a dynamic time allocation vector. By using the query frequency of the host computer as the basis for dynamic adjustment, this solution breaks the rigid time allocation pattern, allowing system resources (detection duration) to be allocated as needed to the target links that require the most monitoring. This solves the technical problem that existing technologies cannot respond to sudden detection demands under a fixed allocation mode, resulting in poor real-time performance and low accuracy.

[0066] As an optional solution, detecting the host computer's query for the target query frequency of one or more power links in the power links via the target bus includes:

[0067] Step S21: Collect the query requests sent by the host computer through the target bus during the first detection period, wherein the query requests are used to request the power of one or more power links;

[0068] Step S22: Detect the number of times the power of the target power link is requested to be queried from the query requests, and obtain the target number;

[0069] Step S23: Determine the ratio of the target number of times to the first detection period as the target query frequency.

[0070] Optionally, in this embodiment, the first detection period may, but is not limited to, indicate: a time window used by the controller to count the number of queries, such as a sliding window or a fixed window of 3000 milliseconds (3 seconds).

[0071] Optionally, in this embodiment, the query request may be, but is not limited to, an instruction: a data frame sent by the host computer through the target bus, which contains the link identifier (such as link A) requested for query.

[0072] Optionally, in this embodiment, the target count may be, but is not limited to, indicating: the count value accumulated by one or more counters inside the controller (FPGA) for the target power link (such as the A-path) during the first detection cycle.

[0073] Optionally, in this embodiment, the target query frequency may be, but is not limited to, an indication: a standardized floating-point or fixed-point number used to describe the urgency of the query, in units such as Hertz (Hz).

[0074] Optionally, in this embodiment, the above scheme can be explained using, but is not limited to, the following scenario: This scheme details the specific implementation of the first step (detecting the target query frequency). The controller (FPGA) internally sets up a timer and a counter group. The timer defines a "first detection period" T_period = 3000ms. The counter group corresponds to four power links A, B, C, and D (N_A, N_B, N_C, N_D). The controller (FPGA) executes the first sub-step: collecting all "query requests" transmitted through the target bus within T_period = 3000ms. The controller (FPGA) executes the second sub-step: parsing each request. For example, within 3000ms, the following request sequence is collected: {T=100ms, Link=A}, {T=800ms, Link=B}, {T=1200ms, Link=A}, {T=2100ms, Link=A}, {T=2800ms, Link=A}. The controller (FPGA) iterates through this sequence and detects that path A (the target power link) has been requested 4 times and path B has been requested 1 time. It obtains the "target number of requests" N_A = 4 for path A and N_B = 1 for path B. The controller (FPGA) then performs a third sub-step: a division operation for normalization. It calculates the ratio of the "target number of requests" N_A = 4 for path A to the "first detection period" T_period = 3 (in seconds), obtaining the "target query frequency" Freq_A = 4 / 3 ≈ 1.33 Hz. Simultaneously, it calculates Freq_B = 1 / 3 ≈ 0.33 Hz. This 1.33 Hz "target query frequency" is then passed to the second step (the allocation module) as the basis for dynamic allocation. If path A has been requested 6 times, then Freq_A = 6 / 3 = 2 Hz. If path A is not requested even once, then Freq_A = 0 / 3 = 0 Hz.

[0075] This embodiment achieves the following technical effect: it provides a technical means to quantify the abstract query behavior (frequent requests) of the host computer into a specific mathematical indicator (target query frequency). This scheme provides a standardized and reliable input for subsequent logical judgment and threshold comparison through the method of "count value within a period / period duration," ensuring the accuracy and consistency of frequency detection.

[0076] As an optional approach, the step of allocating the task duration of multiple controller tasks according to the target query frequency to obtain the allocated controller tasks and task durations with corresponding relationships includes:

[0077] Step S31: Detect the target frequency range that the target query frequency falls into among multiple frequency ranges;

[0078] Step S32: Filter out the target duration allocation information corresponding to the target frequency range from the frequency range and duration allocation information with corresponding relationships, wherein the target duration allocation information records the duration allocation operation for each controller task;

[0079] Step S33: Allocate the task duration occupied by multiple controller tasks in the preset polling cycle according to the duration allocation operation indicated by the target duration allocation information, and obtain the allocated controller tasks and task durations with corresponding relationships.

[0080] Optionally, in this embodiment, the frequency range may, but is not limited to, indicate a query frequency interval defined by a lower threshold and an upper threshold.

[0081] Optionally, in this embodiment, the target frequency range may, but is not limited to, indicate the specific interval into which the currently calculated "target query frequency" falls.

[0082] Optionally, in this embodiment, the duration allocation information may include, but is not limited to, an indication of: a set of predefined time allocation vectors that define the duration of each of the five tasks A, B, C, D, and E within a specific frequency range.

[0083] Optionally, in this embodiment, the target duration allocation information may, but is not limited to, indicate: a specific set of time allocation vectors selected from a preset correspondence based on the "target frequency range".

[0084] Optionally, in this embodiment, the duration allocation operation may, but is not limited to, instructing the controller (FPGA) to actually update the parameters of its internal time-division multiplexing logic (such as timers, state machines) according to the "target duration allocation information" in order to apply the new time allocation.

[0085] Optionally, in this embodiment, the above scheme can be explained using, but is not limited to, the following scenarios: This scheme details the specific implementation of the second step (allocating duration according to frequency). The controller (FPGA) internally stores a lookup table or read-only memory (ROM) that stores "corresponding frequency ranges and duration allocation information". This table can be defined as follows: Range 0 (Idle): Freq < 0.5 Hz. Duration allocation information: {A=100ms, B=100ms, C=100ms, D=100ms, E=1600ms}. Range 1 (Frequent): 0.5 Hz ≤ Freq < 2.0 Hz. Duration allocation information: {A=340ms, B=20ms, C=20ms, D=20ms, E=1600ms}. Range 2 (Continuously Frequent): Freq ≥ 2.0 Hz. Duration allocation information: {A=1000ms, B=20ms, C=20ms, D=20ms, E=940ms}. The controller (FPGA) receives the "target query frequency" Freq_A = 1.33 Hz from the previous scheme. The controller (FPGA) executes the first sub-step: detecting which "frequency range" this 1.33 Hz falls into. By comparison, it is determined that Freq_A satisfies 0.5 ≤ 1.33 < 2.0, therefore the "target frequency range" is "range 1". The controller (FPGA) executes the second sub-step: using "range 1" as an index, it filters the corresponding "target duration allocation information" from the lookup table, i.e., {A=340ms, B=20ms, C=20ms, D=20ms, E=1600ms}. The controller (FPGA) executes the third sub-step: performing a "duration allocation operation," loading the new set of duration parameters {340, 20, 20, 20, 1600} into the timer register of the control time-division multiplexing state machine. Starting from the next 2000ms cycle, the system will execute tasks according to this new time allocation vector.

[0086] This embodiment achieves the following technical effects: it implements an efficient and configurable allocation mechanism. By using a lookup table with preset "frequency range" and "duration allocation information," the system avoids complex dynamic calculations during real-time operation and can instantly and deterministically switch to the corresponding allocation scheme based on the query frequency, ensuring the speed and reliability of allocation.

[0087] As an optional approach, the step of filtering the target duration allocation information corresponding to the target frequency range from the frequency range and duration allocation information with corresponding relationships includes:

[0088] Step S41: When the target frequency range is a frequency range greater than or equal to the first frequency threshold, filter out the first duration allocation information from the frequency range and duration allocation information with corresponding relationship. The first duration allocation operation indicated by the first duration allocation information includes: increasing the first execution duration of the first query task for querying the target power link, decreasing the second execution duration of the second query task for querying one or more power links other than the target power link, and keeping the third execution duration of the algorithm task unchanged.

[0089] Step S42: Determine the first duration allocation information as the target duration allocation information.

[0090] Optionally, in this embodiment, the first frequency threshold may, but is not limited to, indicate a frequency threshold used to distinguish between "idle" and "frequent" states, such as 0.5 Hz.

[0091] Optionally, in this embodiment, the first duration allocation information may, but is not limited to, indicate: a time allocation vector corresponding to the "frequent" state (i.e., the first stage).

[0092] Optionally, in this embodiment, the first duration allocation operation may, but is not limited to, indicating the specific action of changing the "idle" vector {100, 100, 100, 100, 1600} to the "frequent" vector {340, 20, 20, 20, 1600}.

[0093] Optionally, in this embodiment, the first query task may, but is not limited to, indicate a query task corresponding to a “target power link” (such as A-path).

[0094] Optionally, in this embodiment, the first execution duration may, but is not limited to, indicate the duration allocated to the "first query task" (A path).

[0095] Optionally, in this embodiment, the second query task may, but is not limited to, indicate a query task corresponding to "the power links other than the target power link" (such as B-path, C-path, D-path).

[0096] Optionally, in this embodiment, the second execution duration may, but is not limited to, indicate the duration allocated to the "second query task" (paths B, C, and D).

[0097] Optionally, in this embodiment, the algorithm task may, but is not limited to, indicating: E-path task.

[0098] Optionally, in this embodiment, the third execution duration may, but is not limited to, indicate the duration allocated to the "algorithm task" (E-path).

[0099] Optionally, in this embodiment, the above scheme can be explained using, but is not limited to, the following scenario: This scheme specifies the detailed allocation strategy for "Range 1" (first stage). The controller (FPGA) sets the "first frequency threshold" T_Freq1 = 0.5 Hz. The controller (FPGA) receives Freq_A = 1.33 Hz. The first sub-step is executed: a comparison is made, 1.33 Hz is greater than 0.5 Hz, and it is determined that the "target frequency range" satisfies "greater than or equal to the first frequency threshold". The controller (FPGA) filters out the "first duration allocation information" (i.e., the information corresponding to Range 1) from the lookup table. The "first duration allocation operation" indicated by this information is parsed as follows: 1. Increase the first execution duration: increase the duration (first execution duration) of path A (first query task) from the initial 100ms to 340ms. 2. Decrease the second execution duration: decrease the duration (second execution duration) of paths B, C, and D (second query tasks) from the initial 100ms to 20ms respectively. 3. Maintain... Third Execution Duration: Keep the duration of path E (algorithm task) (third execution duration) unchanged at 1600ms (1.6s). The controller (FPGA) executes the second sub-step: determine the "first duration allocation information" of the selected {A=340, B=20, C=20, D=20, E=1600} as the "target duration allocation information" and pass it to the third sub-step (allocation unit) in the previous scheme for execution.

[0100] This embodiment achieves the following technical effects: It realizes the first-stage intelligent allocation, namely the "protect E, suppress B, C, D" strategy. While ensuring the stability of the core system (the duration of algorithm task E remains unchanged at 1.6s), this scheme prioritizes improving the real-time performance and accuracy of the target link (A) detection (increasing from 100ms to 340ms) by sacrificing the detection time of non-target power links (B, C, D) (compressing it from 100ms to 20ms). This achieves performance improvement without sacrificing stability.

[0101] As an optional approach, after determining the first duration allocation information as the target duration allocation information, the method further includes:

[0102] Step S51: Detect whether the host computer is still continuously querying the target power link;

[0103] Step S52: When it is detected that the host computer is still continuously querying the target power link, the second duration allocation information is determined as the target duration allocation information. The second duration allocation operation indicated by the second duration allocation information includes: after executing the first duration allocation operation indicated by the first duration allocation information, continuing to increase the first execution duration, keeping the second execution duration unchanged, and decreasing the third execution duration.

[0104] Optionally, in this embodiment, continuous querying may, but is not limited to, indicating that the target query frequency is further increased, exceeding a second frequency threshold (e.g., 2.0 Hz).

[0105] Optionally, in this embodiment, the second duration allocation information may, but is not limited to, indicate a time allocation vector corresponding to the "continuously frequent" state (i.e., the second stage).

[0106] Optionally, in this embodiment, the second duration allocation operation may, but is not limited to, indicating the specific action of changing the "frequent" vector {340, 20, 20, 20, 1600} to the "continuously frequent" vector {1000, 20, 20, 20, 940}.

[0107] Optionally, in this embodiment, the above scheme can be explained using, but is not limited to, the following scenario: This scheme specifies in detail the strategy for transitioning from the first stage to the second stage. At this time, the system is running in the first stage state (A=340ms, BCD=20ms, E=1600ms). The controller (FPGA) executes the first sub-step: continuing to detect whether the host computer is "still continuously querying". For example, in the next 3-second detection cycle, the controller (FPGA) detects that path A has been queried 7 times, and calculates the new Freq_A = 7 / 3 ≈ 2.33 Hz. This frequency exceeds the threshold of "range 2" defined in the lookup table (i.e., the second frequency threshold, for example, 2.0 Hz). The controller (FPGA) executes the second sub-step: if "continuous querying" (Freq_A ≥ 2.0 Hz) is detected, the "second duration allocation information" (i.e., the information corresponding to range 2) is determined as the new "target duration allocation information". The "second duration allocation information" indicates the "second duration allocation operation," which is interpreted as follows: 1. After executing the first duration allocation operation, continue to increase the first execution duration: increase the duration (first execution duration) of path A (first query task) from 340ms to 1000ms (1 second). 2. Maintain the second execution duration unchanged: keep the duration (second execution duration) of paths B, C, and D (second query tasks) at 20ms. 3. Reduce the third execution duration: reduce the duration (third execution duration) of path E (algorithm task) from 1600ms (1.6s) to 940ms (0.94s). This new allocation vector {A=1000, B=20, C=20, D=20, E=940} is then executed by the system.

[0108] This embodiment achieves the following technical effects: it implements the second-stage extreme allocation strategy, namely the "protect A, suppress E" strategy. When the first-stage allocation (sacrificing only B, C, and D) still cannot meet the detection requirements of the host computer, the system activates this strategy. By sacrificing the execution time of some non-critical internal algorithm tasks (E), the system allocates detection resources (duration) to the target link (A) to the extreme, thereby providing the host computer with the highest detection accuracy and real-time performance in a short period of time.

[0109] As an optional approach, after allocating the task durations of multiple controller tasks according to the target query frequency to obtain the allocated controller tasks and task durations with corresponding relationships, the method further includes:

[0110] Step S61: Detect whether one or more of the power links meet the reset trigger condition;

[0111] Step S62: If one or more of the power links are detected to meet the reset trigger condition, the task duration of the multiple controller tasks is restored to the corresponding initial duration.

[0112] Optionally, in this embodiment, the reset trigger condition may be, but is not limited to, an indication: one or more logical conditions for determining that the detection requirement has been released, such as target link query timeout or query target switching.

[0113] Optionally, in this embodiment, the initial duration may, but is not limited to, indicate: the default time allocation vector of the system in the "idle" state, i.e., {A=100ms, B=100ms, C=100ms, D=100ms, E=1600ms}.

[0114] Optionally, in this embodiment, the above scheme can be explained using, but is not limited to, the following scenario: This scheme provides a recovery mechanism parallel to dynamic allocation. Assume the system is currently operating in the second-stage extreme allocation state (A=1000ms, BCD=20ms, E=940ms). The controller (FPGA) executes the first sub-step: while performing dynamic allocation, it continuously monitors the "reset trigger condition." For example, the fault in path A has been cleared, and the host computer has stopped querying path A. The controller (FPGA) executes the second sub-step: after detecting that the "reset trigger condition" is met (e.g., no query for path A is detected within 2 seconds as defined in the subsequent scheme), the controller (FPGA) performs a recovery action. It restores the "task duration" of all "multiple controller tasks" (A, B, C, D, E) to their "corresponding initial duration." That is, the controller (FPGA) reloads the time allocation vector from {1000, 20, 20, 20, 940} to the initial {100, 100, 100, 100, 1600}. Starting from the next 2000ms cycle, the system resumes the fixed polling mode in the "idle" state.

[0115] This embodiment achieves the following technical effects: it implements a closed-loop mechanism for intelligent dynamic allocation. Through automatic reset, the system ensures that high-intensity centralized detection (such as the states of the first and second stages) is only a temporary state. After the detection requirement ends, the system can automatically return to the highly stable initial polling mode (algorithm task E recovers in 1.6 seconds), thus achieving a balance between "real-time performance" and "long-term stability".

[0116] As an optional solution, detecting whether one or more of the power links meet the reset trigger condition includes:

[0117] Step S71: During the second detection period, detect the first query frequency of the target power link and detect the second query frequency of one or more power links other than the target power link.

[0118] Step S72: If the first query frequency is detected to be less than or equal to the second frequency threshold, and / or if the second query frequency of one or more reference power links other than the target power link is detected to be greater than or equal to the third frequency threshold, determine that one or more power links satisfy the reset trigger condition.

[0119] Optionally, in this embodiment, the second detection period may, but is not limited to, indicate a specific time window for the controller to detect reset conditions, such as 2000ms (2 seconds).

[0120] Optionally, in this embodiment, the first query frequency may, but is not limited to, indicate the query frequency of the "target power link" (such as path A) counted during the second detection period.

[0121] Optionally, in this embodiment, the second query frequency may, but is not limited to, indicate the query frequency of "the power links other than the target power link" (such as B-path, C-path, or D-path) counted during the second detection period.

[0122] Optionally, in this embodiment, the second frequency threshold may, but is not limited to, indicate: a lower frequency limit for determining "stop query", such as 0.5 Hz.

[0123] Optionally, in this embodiment, the reference power link may, but is not limited to, indicate the link with the highest query frequency among non-target links (such as link B).

[0124] Optionally, in this embodiment, the third frequency threshold may, but is not limited to, indicate the upper frequency limit used to determine the "direction query", for example, 1.0 Hz.

[0125] Optionally, in this embodiment, the above scheme can be explained using, but is not limited to, the following scenario: This scheme specifies two specific judgment logics for the "reset trigger condition," and these two logics are in an "OR" relationship (and / or). Assume the system is in the second stage state (A is the target). The controller (FPGA) initiates a "second detection cycle" T_reset = 2000ms. The controller (FPGA) executes the first sub-step: within this cycle, it detects the query frequency of all links. For example, it detects 0 queries for link A, 3 queries for link B, 0 queries for link C, and 0 queries for link D. It calculates Freq_A (first query frequency) = 0 / 2 = 0 Hz. It calculates Freq_B (second query frequency) = 3 / 2 = 1.5 Hz. The controller (FPGA) executes the second sub-step: performing logical judgments. It sets the "second frequency threshold" T_low = 0.5 Hz and sets the "third frequency threshold" T_high = 1.0 Hz. Decision 1 (Stop Query): Is Freq_A (0 Hz) less than or equal to T_low (0.5 Hz)? Yes. Decision 2 (Redirect Query): Is Freq_B (1.5 Hz) greater than or equal to T_high (1.0 Hz)? Yes. Since the AND / OR condition is met (both are met), the controller (FPGA) "determines that one or more of the power links meet the reset trigger condition" and performs a recovery action (returning to 100ms polling mode). In the next cycle, path B will be detected as the new "target power link" due to its high frequency of 1.5 Hz, thus initiating dynamic allocation to path B.

[0126] This embodiment achieves the following technical effects: it specifies two concrete triggering logics for the reset condition: one is "stop query" (target link frequency is below the lower threshold), and the other is "redirect query" (other link frequencies are above the upper threshold). This design ensures that the system can sensitively capture changes in detection requirements. Whether it is the end of a detection task (stop query) or the switching of a detection task (redirect query), a reset can be triggered in a timely manner, ensuring the system's response speed and flexibility.

[0127] To better understand the power detection process of the repeater system described above, the power detection process of the repeater system will be further explained below with reference to optional embodiments, but this is not intended to limit the technical solutions of the embodiments of this application.

[0128] This embodiment provides a method for detecting the power of a repeater system. Figure 3 This is a schematic diagram of the power detection process of a repeater system according to an embodiment of this application, as shown below. Figure 3As shown, the process starts with the judgment point of "power query bus idle". When the bus is idle, the system allocates and executes polling at a fixed initial time. When the bus is not idle and a query is initiated, the system further determines whether it is a "frequent application". If the determination is "yes" (i.e., a high query frequency is detected), the system will start the first-stage dynamic allocation, that is, "increase the weight of this power and re-allocate the polling time" (for example, increase the time of path A, reduce the time of paths B, C, and D, while keeping the algorithm task time of path E unchanged). Immediately afterwards, the process will check again whether "the power is still being queried". If "yes", the second-stage allocation will be started, that is, "reduce the allocation time of E" to further increase the duration of the target link. In each branch of the process, if the determination is "no" (for example, the query stops or switches to query other channels), the process will point to "restore to the 100ms polling mode", causing the system to automatically return from the dynamic allocation state to the initial stable polling state.

[0129] More specifically, for the current solution of fixed-time allocation (ABCD is 100ms each, and E is 1.6s) for multiple controller tasks (including query tasks for four power links A, B, C, D, and an algorithm task represented by E for running the controller algorithm) within a preset polling cycle (such as 2s), this embodiment has made corresponding improvements. The new solution mainly involves the host computer and the controller (such as FPGA) to perform linkage control through the target bus to achieve the effect of intelligent query.

[0130] The specific solution is that in the initial state of the system or after meeting the reset trigger condition (described later), the controller (FPGA) executes the multiple controller tasks according to the "initial duration" (that is, ABCD polls for 100ms and E occupies 1.6s).

[0131] When the host computer initiates a frequent application through the target bus, the controller (FPGA) will execute the step of [detecting the target query frequency of the target power link in one or more of the power links queried by the host computer through the target bus]. This step can be specifically implemented as follows: The controller collects the query requests sent by the host computer within the first detection period (such as 3s) and detects the number of times (target number of times, such as "several queries") that the power of the target power link (such as path A) is requested to be queried from the query requests. Then, the controller determines the ratio of the target number of times to the first detection period as the target query frequency.

[0132] After obtaining the target query frequency, the controller (FPGA) executes the step of [allocating the task duration of multiple controller tasks according to the target query frequency]. This step can be specifically implemented as follows: the controller detects the target frequency range that the calculated target query frequency (e.g., the frequency of channel A) falls into among multiple frequency ranges; then, the controller filters the target duration allocation information corresponding to the target frequency range from a preset "corresponding frequency range and duration allocation information"; finally, the controller allocates multiple controller tasks according to the duration allocation operation indicated by the target duration allocation information.

[0133] For example, this allocation process includes two phases:

[0134] Phase 1: When the controller detects that the target frequency range meets the condition of being "greater than or equal to the first frequency threshold" (e.g., querying path A more than twice within 3 seconds), the controller will filter out the first duration allocation information from the corresponding frequency range and duration allocation information. The "first duration allocation operation" indicated by this information includes: increasing the first execution duration of querying the target power link (path A) (e.g., from 100ms to 340ms), decreasing the second execution duration of querying the power links other than the target power link (paths B, C, and D) (e.g., from 100ms to 20ms), and keeping the third execution duration of the algorithm task (path E) unchanged (still 1.6s).

[0135] The second stage: After performing the first duration allocation operation described above, the controller will also detect whether the host computer is still continuously querying the target power link (for example, the query frequency of path A further increases, falling into a higher "target frequency range"). If continuous querying is detected, the controller will determine the second duration allocation information as the new "target duration allocation information". The "second duration allocation operation" indicated by this information includes: after performing the first duration allocation operation, continuing to increase the first execution duration (path A duration, for example, from 340ms to 1000ms or 1s), maintaining the second execution duration unchanged (paths B, C, and D remain at 20ms), and decreasing the third execution duration (the duration of the algorithm task for path E, for example, from 1.6s to the remaining 940ms). If the host computer continues to query, the first execution duration (percentage) of path A can be further increased.

[0136] In addition, this solution includes a reset step. The controller (FPGA) checks in parallel whether one or more of the power links meet the reset trigger condition. If the reset trigger condition is met, the controller restores the task duration of the multiple controller tasks (A, B, C, D, and E) to the corresponding initial duration (i.e., restores to a 100ms polling mode).

[0137] The specific detection of the "reset trigger condition" may include: within a second detection cycle (e.g., 2 seconds), the controller detects a first query frequency of the target power link (path A) and a second query frequency of other power links (e.g., path B) besides the target power link. When the controller detects that the first query frequency is less than or equal to a second frequency threshold (e.g., no query is performed within 2 seconds, i.e., "bus stops querying"), and / or detects that the second query frequency of one or more reference power links (e.g., path B) besides the target power link is greater than or equal to a third frequency threshold (i.e., "querying other channel power"), the controller determines that the reset trigger condition is met and performs a recovery action.

[0138] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0139] Figure 4 This is a structural block diagram of a power detection device for a repeater system according to an embodiment of this application; as shown... Figure 4 As shown, a power detection device for a repeater system is disclosed. The repeater system includes a host computer, a target bus, and a controller. The target bus connects the host computer and the controller. The controller executes multiple controller tasks sequentially within a preset polling period. These multiple controller tasks include: a query task to check the power of one or more power links, and an algorithm task to run a controller algorithm. The device is applied to the controller and includes:

[0140] The first detection module 402 is used to detect the target query frequency of the target power link in one or more power links queried by the host computer through the target bus.

[0141] The allocation module 404 is used to allocate the task duration of multiple controller tasks according to the target query frequency, so as to obtain the allocated controller tasks and task durations with corresponding relationships, wherein the task duration allocated to the power link with the higher query frequency accounts for a higher proportion of the duration in the preset polling cycle.

[0142] The execution module 406 is used to execute the plurality of controller tasks according to the allocated controller tasks with corresponding relationships and the task duration.

[0143] In an exemplary embodiment, the first detection module includes:

[0144] The acquisition unit is used to acquire query requests sent by the host computer through the target bus during the first detection period, wherein the query request is used to request the power of one or more power links;

[0145] The second detection unit is used to detect from the query request the number of times the power of the target power link has been requested to be queried, and to obtain the target number;

[0146] The first determining unit is used to determine the ratio of the target number to the first detection period as the target query frequency.

[0147] In one exemplary embodiment, the allocation module includes:

[0148] The third detection unit is used to detect the target frequency range that the target query frequency falls into among multiple frequency ranges;

[0149] A filtering unit is used to filter out target duration allocation information corresponding to the target frequency range from frequency ranges and duration allocation information that have a corresponding relationship, wherein the target duration allocation information records the duration allocation operation for each controller task;

[0150] The allocation unit is used to allocate the task duration occupied by multiple controller tasks in the preset polling cycle according to the duration allocation operation indicated by the target duration allocation information, so as to obtain the allocated controller tasks and the task duration with corresponding relationships.

[0151] In one exemplary embodiment, the filtering unit is further configured to:

[0152] When the target frequency range is a frequency range greater than or equal to the first frequency threshold, the first duration allocation information is filtered out from the frequency range and duration allocation information with corresponding relationships. The first duration allocation operation indicated by the first duration allocation information includes: increasing the first execution duration of the first query task that queries the target power link, decreasing the second execution duration of the second query task that queries one or more power links other than the target power link, and keeping the third execution duration of the algorithm task unchanged.

[0153] The first duration allocation information is determined as the target duration allocation information.

[0154] In one exemplary embodiment, the apparatus further includes:

[0155] The fourth detection module is used to detect whether the host computer is still continuously querying the target power link after the first duration allocation information is determined as the target duration allocation information;

[0156] The second determining module is configured to determine the second duration allocation information as the target duration allocation information after determining the first duration allocation information as the target duration allocation information, and when it is detected that the host computer is still continuously querying the target power link. The second duration allocation operation indicated by the second duration allocation information includes: after executing the first duration allocation operation indicated by the first duration allocation information, continuing to increase the first execution duration, maintaining the second execution duration unchanged, and decreasing the third execution duration.

[0157] In one exemplary embodiment, the apparatus further includes:

[0158] The reset detection module is used to detect whether one or more of the power links meet the reset triggering conditions after the task duration of multiple controller tasks is allocated according to the target query frequency to obtain the allocated controller tasks and task durations with corresponding relationships.

[0159] The recovery module is used to restore the task duration of the multiple controller tasks to the corresponding initial duration when one or more of the power links are detected to meet the reset trigger condition.

[0160] In one exemplary embodiment, the reset detection module includes:

[0161] The frequency detection unit is used to detect the first query frequency of the target power link and the second query frequency of one or more power links other than the target power link during the second detection period.

[0162] The reset determination unit is configured to determine that one or more power links satisfy the reset triggering condition when the first query frequency is less than or equal to a second frequency threshold, and / or the second query frequency of one or more reference power links other than the target power link is greater than or equal to a third frequency threshold.

[0163] Embodiments of this application also provide a storage medium including a stored program, wherein the program executes any of the methods described above when it is run.

[0164] Optionally, in this embodiment, the storage medium may be configured to store program code for performing the following steps:

[0165] S1, detect that the host computer queries the target query frequency of one or more target power links in the power links through the target bus;

[0166] S2, allocate the task duration of multiple controller tasks according to the target query frequency to obtain the allocated controller tasks and task durations with corresponding relationships, wherein the power link with the higher query frequency has a higher proportion of the allocated task duration in the preset polling cycle.

[0167] S3, execute the multiple controller tasks according to the allocated controller tasks with corresponding relationships and the task duration.

[0168] Embodiments of this application also provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0169] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0170] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0171] S1, detect that the host computer queries the target query frequency of one or more target power links in the power links through the target bus;

[0172] S2, allocate the task duration of multiple controller tasks according to the target query frequency to obtain the allocated controller tasks and task durations with corresponding relationships, wherein the power link with the higher query frequency has a higher proportion of the allocated task duration in the preset polling cycle.

[0173] S3, execute the multiple controller tasks according to the allocated controller tasks with corresponding relationships and the task duration.

[0174] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0175] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0176] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0177] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for detecting the power of a repeater system, characterized in that, The repeater system deploys a host computer, a target bus, and a controller. The target bus connects the host computer and the controller. Within a preset polling period, the controller sequentially executes multiple controller tasks. These tasks include: a query task to check the power of one or more power links, and an algorithm task to run a controller algorithm. The method is applied to the controller and includes: The host computer is detected querying the target query frequency of one or more target power links through the target bus; The task duration of multiple controller tasks is allocated according to the target query frequency to obtain the allocated controller tasks and task durations with corresponding relationships. Among them, the task duration allocated to the power link with the higher query frequency accounts for a higher proportion of the duration in the preset polling cycle. The multiple controller tasks are executed according to the assigned controller tasks with corresponding relationships and the task durations.

2. The method according to claim 1, characterized in that, The detection of the host computer querying the target query frequency of one or more power links in the power links through the target bus includes: Collect query requests sent by the host computer through the target bus during the first detection period, wherein the query request is used to request the power of one or more power links; The number of times the power of the target power link was requested to be queried is detected from the query requests, and the target number is obtained; The ratio of the target number of times to the first detection period is determined as the target query frequency.

3. The method according to claim 1, characterized in that, The step of allocating the task duration of multiple controller tasks according to the target query frequency to obtain the allocated controller tasks and task durations with corresponding relationships includes: Detecting the target frequency range that the target query frequency falls into among multiple frequency ranges; The target duration allocation information corresponding to the target frequency range is filtered out from the frequency range and duration allocation information with corresponding relationships, wherein the target duration allocation information records the duration allocation operation for each controller task; According to the duration allocation operation indicated by the target duration allocation information, the task duration occupied by multiple controller tasks in the preset polling cycle is allocated to obtain the allocated controller tasks and task durations with corresponding relationships.

4. The method according to claim 3, characterized in that, The step of filtering the target duration allocation information corresponding to the target frequency range from the frequency range and duration allocation information with corresponding relationships includes: When the target frequency range is a frequency range greater than or equal to the first frequency threshold, the first duration allocation information is filtered out from the frequency range and duration allocation information with corresponding relationships. The first duration allocation operation indicated by the first duration allocation information includes: increasing the first execution duration of the first query task that queries the target power link, decreasing the second execution duration of the second query task that queries one or more power links other than the target power link, and keeping the third execution duration of the algorithm task unchanged. The first duration allocation information is determined as the target duration allocation information.

5. The method according to claim 4, characterized in that, After determining the first duration allocation information as the target duration allocation information, the method further includes: Detect whether the host computer is still continuously querying the target power link; If the host computer is still continuously querying the target power link, the second duration allocation information is determined as the target duration allocation information. The second duration allocation operation indicated by the second duration allocation information includes: after executing the first duration allocation operation indicated by the first duration allocation information, continuing to increase the first execution duration, keeping the second execution duration unchanged, and decreasing the third execution duration.

6. The method according to claim 1, characterized in that, After allocating the task durations of multiple controller tasks according to the target query frequency to obtain the allocated controller tasks and task durations with corresponding relationships, the method further includes: Detect whether one or more of the power links meet the reset trigger condition; If one or more of the power links are detected to meet the reset trigger condition, the task duration of the multiple controller tasks is restored to the corresponding initial duration.

7. The method according to claim 6, characterized in that, The detection of whether one or more of the power links meet the reset trigger condition includes: During the second detection period, the first query frequency of the target power link is detected, and the second query frequency of one or more power links other than the target power link is detected. If the first query frequency is detected to be less than or equal to the second frequency threshold, and / or if the second query frequency of one or more reference power links other than the target power link is detected to be greater than or equal to the third frequency threshold, it is determined that one or more power links satisfy the reset trigger condition.

8. A power detection device for a repeater system, characterized in that, The repeater system deploys a host computer, a target bus, and a controller. The target bus connects the host computer and the controller. Within a preset polling period, the controller sequentially executes multiple controller tasks, including: a query task to query the power of one or more power links, and an algorithm task to run a controller algorithm. The device applied to the controller includes: The first detection module is used to detect the target query frequency of the target power link in one or more power links queried by the host computer through the target bus. The allocation module is used to allocate the task duration of multiple controller tasks according to the target query frequency, so as to obtain the allocated controller tasks and task durations with corresponding relationships, wherein the power link with the higher query frequency has a higher proportion of the allocated task duration in the preset polling period. An execution module is used to execute the multiple controller tasks according to the assigned controller tasks with corresponding relationships and the task durations.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein the program, when executed, performs the method of any one of claims 1 to 7.

10. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to execute the method of any one of claims 1 to 7 through the computer program.

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