Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes: a display portion including a base layer and a light emitting element on the base layer; a sensing portion on the display portion and including a sensing electrode; a multiplexer electrically connected to the sensing electrode through the sensing line, and including a multiplexer (MUX) transistor on a portion of the base layer; and a MUX gate line electrically connected to the MUX transistor.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0108051, filed on August 13, 2024, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Aspects of some embodiments of the present disclosure relate to a display device and an electronic device including the same. BACKGROUND

[0004] As interest in information display has recently increased, the demand for display devices configured to display images has increased in various forms. In addition, research and development of display devices having touch sensors are being implemented to enhance user convenience and expand the range of application fields.

[0005] The above information disclosed in this Background section is only for enhancing the understanding of the background of the present disclosure, and therefore, it can not necessarily constitute the prior art. SUMMARY

[0006] Aspects of some embodiments of the present disclosure include a display device that can be capable of relatively reducing the risk of distortion of a signal for sensing touch information and an electronic device including the same.

[0007] Aspects of some embodiments of the present disclosure include a display device that can be capable of relatively reducing the risk of damage to a wire and an electronic device including the same.

[0008] Aspects of some embodiments of the present disclosure include a display device that can be capable of relatively improving the reliability of touch performance and an electronic device including the same.

[0009] According to some embodiments of the disclosure, a display device includes a display portion including a base layer and a light emitting element on the base layer; a sensing portion on the display portion and including a sensing electrode; a multiplexer electrically connected to the sensing electrode by a sensing line and including a multiplexer (MUX) transistor on a portion of the base layer; and a MUX gate line electrically connected to the MUX transistor. According to some embodiments, the MUX transistor can include a first MUX transistor and a second MUX transistor. According to some embodiments, the MUX gate line can include a first MUX gate line electrically connected to a first gate electrode of the first MUX transistor and a second MUX gate line electrically connected to a second gate electrode of the second MUX transistor. According to some embodiments, each of the MUX gate lines can include a first MUX gate line portion extending in a first direction and a second MUX gate line portion extending in a second direction different from the first direction, and the second MUX gate line portion is electrically connected to the first MUX gate line portion at an end portion of the first MUX gate line portion. According to some embodiments, the first MUX gate line portion of the first MUX gate line and the second MUX gate line portion of the second MUX gate line can not overlap each other in a plan view.

[0010] According to some embodiments, the MUX gate line can include a plurality of first MUX gate line portions, and the plurality of first MUX gate line portions can not overlap each other in a plan view. According to some embodiments, the MUX gate line can include a plurality of second MUX gate line portions, and the plurality of second MUX gate line portions can not overlap each other in a plan view.

[0011] According to some embodiments, the second MUX gate line can be closer to the MUX transistor than the first MUX gate line.

[0012] According to some embodiments, the first MUX gate line portion of the second MUX gate line can extend farther in the first direction than the first MUX gate line portion of the first MUX gate line. According to some embodiments, the second MUX gate line portion of the second MUX gate line can extend farther in the second direction externally than the second MUX gate line portion of the first MUX gate line.

[0013] According to some embodiments, the second MUX gate line portion of the first MUX gate line and the second MUX gate line portion of the second MUX gate line can be spaced apart from each other by a first distance in the first direction. According to some embodiments, the first MUX gate line portion and the second MUX gate line portion of the first MUX gate line can be spaced apart from each other by a second distance in a thickness direction of the base layer. The first distance can be greater than the second distance.

[0014] According to some embodiments, the MUX gate lines can further include a third MUX gate line between the MUX transistors. According to some embodiments, the first MUX gate line portion and the second MUX gate line portion of the third MUX gate line can not overlap, in a plan view, the first MUX gate line portion and the second MUX gate line portion of each of the first MUX gate line and the second MUX gate line.

[0015] According to some embodiments, some of the MUX gate lines can be on a lower side of a multiplexer region in which the multiplexer is located, some of the MUX gate lines can be between the MUX transistors in the multiplexer region, and some of the MUX gate lines can be on an upper side of the multiplexer region.

[0016] According to some embodiments, the first MUX gate line portion and the second MUX gate line portion can be electrically connected to each other by a contact member. According to some embodiments, the MUX gate lines can include a plurality of contact members. According to some embodiments, the plurality of contact members can be sequentially arranged in an oblique direction extending in a direction between the first direction and the second direction.

[0017] According to some embodiments, in each of the MUX gate lines, the second MUX gate line portion can be provided as a plurality. According to some embodiments, one of the plurality of second MUX gate line portions can be electrically connected to the first MUX gate line portion at a first end portion of the first MUX gate line portion, and another of the plurality of second MUX gate line portions can be electrically connected to the first MUX gate line portion at a second end portion of the first MUX gate line portion.

[0018] According to some embodiments, the MUX gate lines can include a plurality of first MUX gate line portions, and the plurality of first MUX gate line portions can be arranged in the second direction. According to some embodiments, the MUX gate lines can include a plurality of second MUX gate line portions, and the plurality of second MUX gate line portions can be arranged in the first direction.

[0019] According to some embodiments, the MUX gate lines can further include a third MUX gate line between the MUX transistors. According to some embodiments, the first MUX gate line portion and the second MUX gate line portion of the third MUX gate line can not overlap, in a plan view, the first MUX gate line portion and the second MUX gate line portion of the first MUX gate line.

[0020] According to some embodiments, the second MUX gate line portion of the third MUX gate line can overlap, in a plan view, the first MUX gate line portion of the second MUX gate line.

[0021] According to some embodiments, the second MUX gate line portion of the third MUX gate line can be between the second MUX gate line portion of the first MUX gate line and the second MUX gate line portion of the second MUX gate line.

[0022] According to some embodiments, the gate control signals respectively supplied from the third MUX gate line and the second MUX gate line can have a potential difference of 1V or less.

[0023] According to some embodiments, the display device can further include a sensor driver electrically connected to the multiplexer through a signal line. According to some embodiments, the multiplexer can be on one side of a sensing area where the sensing electrode is located.

[0024] According to some embodiments, the multiplexer can select some of the signals supplied through the signal line and supply the selected signal to the sensing line.

[0025] According to some embodiments, the multiplexer can be provided as a plurality of multiplexers each including a multiplexer circuit, and some of the plurality of multiplexers can be arranged in a first direction, and some of the plurality of multiplexers can be arranged in a second direction.

[0026] According to some embodiments, the signal line can include a first signal line configured to supply a first signal, a second signal line configured to supply a second signal, and a third signal line configured to supply a third signal. According to some embodiments, the MUX transistor can further include a third MUX transistor and a fourth MUX transistor. According to some embodiments, the MUX gate line can further include a third MUX gate line and a fourth MUX gate line. According to some embodiments, a first electrode of the first MUX transistor can be electrically connected to the first signal line, and a second electrode of the first MUX transistor can be electrically connected to the first node. According to some embodiments, a first electrode of the second MUX transistor can be electrically connected to the second signal line, and a second electrode of the second MUX transistor can be electrically connected to the first node. According to some embodiments, a first electrode of the third MUX transistor can be electrically connected to the first node, a second electrode of the third MUX transistor can be electrically connected to a second node, and a third gate electrode of the third MUX transistor can be electrically connected to the third MUX gate line. According to some embodiments, a first electrode of the fourth MUX transistor can be electrically connected to the third signal line, a second electrode of the fourth MUX transistor can be electrically connected to the second node, and a fourth gate electrode of the fourth MUX transistor can be electrically connected to the fourth MUX gate line. According to some embodiments, the second node can be electrically connected to the sensing line.

[0027] According to some embodiments, the multiplexer can selectively supply any one of the first signal, the second signal, and the third signal to the sense line. According to some embodiments, the first MUX gate line can supply a first gate control signal. According to some embodiments, the second MUX gate line can supply a second gate control signal. According to some embodiments, the third MUX gate line can supply a third gate control signal. According to some embodiments, the fourth MUX gate line can supply a fourth gate control signal. According to some embodiments, the first gate control signal, the second gate control signal, the third gate control signal, and the fourth gate control signal can have different potentials.

[0028] According to some embodiments, the sensing electrode can acquire information about a user touch input using a self-capacitance method.

[0029] According to some embodiments, the display part can include a light emitting element layer including a light emitting element and an encapsulation layer on the light emitting element layer. According to some embodiments, the sensing part can be directly on the encapsulation layer.

[0030] According to some embodiments, the display part can include a circuit layer including a pixel transistor electrically connected to the light emitting element. According to some embodiments, the first MUX gate line part can include the same material as a material of a source electrode and / or a drain electrode of the pixel transistor. According to some embodiments, the second MUX gate line part can include the same material as a material of a conductive part in the circuit layer electrically connected to the light emitting element.

[0031] Aspects of some embodiments of the present disclosure can include an electronic device including a processor configured to provide input image data, a display device configured to display an image based on the input image data, and a power supply configured to supply power to the display device. According to some embodiments, the display device can include a display portion including a base layer and a light emitting element on the base layer, a sensing portion on the display portion and including a sensing electrode, a multiplexer electrically connected to the sensing electrode by a sensing line and including a multiplexer (MUX) transistor on a portion of the base layer, and a MUX gate line electrically connected to the MUX transistor. According to some embodiments, the MUX transistor can include a first MUX transistor and a second MUX transistor. According to some embodiments, the MUX gate line can include a first MUX gate line electrically connected to a first gate electrode of the first MUX transistor and a second MUX gate line electrically connected to a second gate electrode of the second MUX transistor. According to some embodiments, each of the MUX gate lines can include a first MUX gate line portion extending in a first direction and a second MUX gate line portion extending in a second direction different from the first direction, and the second MUX gate line portion can be electrically connected to the first MUX gate line portion at an end portion of the first MUX gate line portion. According to some embodiments, the first MUX gate line portion of the first MUX gate line and the second MUX gate line portion of the second MUX gate line can not overlap each other in a plan view. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 FIG. 1 is a schematic diagram to describe a display device according to some embodiments.

[0033] Figure 2 FIG. 2 is a schematic plan view illustrating a display portion according to some embodiments.

[0034] Figure 3 FIG. 3 is a schematic plan view illustrating a sensing portion according to some embodiments.

[0035] Figure 4 FIG. 4 is a schematic cross-sectional view illustrating a display device according to some embodiments.

[0036] Figure 5 FIG. 5 is a schematic cross-sectional view illustrating a circuit layer in a display area according to some embodiments.

[0037] Figure 6 FIG. 6 is a schematic plan view illustrating a sensing area and a multiplexer area according to some embodiments.

[0038] Figure 7 FIG. 7 is a schematic diagram to describe an operation of sensing a touch input by a sensing portion according to some embodiments.

[0039] Figure 8 and Figure 9 is a schematic plan view illustrating a multiplexer and lines electrically connected to the multiplexer according to some embodiments.

[0040] Figure 10 is a schematic plan view illustrating a multiplexer and a region surrounding the multiplexer according to some embodiments.

[0041] Figure 11 is a schematic cross-sectional view taken along line A-A' of Figure 10 .

[0042] Figure 12 is a schematic plan view illustrating a multiplexer and a region surrounding the multiplexer according to some embodiments.

[0043] Figure 13 is a schematic cross-sectional view taken along line B-B' of Figure 12 .

[0044] Figure 14 is a schematic block diagram illustrating an electronic device including a display device according to some embodiments.

[0045] Figure 15 is a schematic diagram illustrating an example in which the electronic device of Figure 14 is implemented as a smart phone.

[0046] Figure 16 is a schematic diagram illustrating an example in which the electronic device of Figure 14 is implemented as a tablet personal computer (PC). DETAILED DESCRIPTION

[0047] As the present disclosure allows various modifications and allows numerous embodiments, specific embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific mode of practice, and it should be appreciated that all changes, equivalents, and substitutes not departing from the spirit and technical scope of the present disclosure are encompassed in the present disclosure.

[0048] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element could be termed a first element. In the present disclosure, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0049] Some embodiments are described in the following description and attached drawings directed to specific embodiments of the application. Alternate embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. Aspects of the application can be modified or adapted under the teachings of the application to a wide variety of applications. Each embodiment of the present application is presented in terms of exemplary methods, systems, and devices. These methods, systems, and devices are not limited by the exemplary implementations described herein, but can be adapted under the teachings of the application for use in a variety of different types of systems and methods. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. It is to be understood that where the application is specifically declared to be an "application" or "comprise an application", the expression "application" is used in the sense of a claim to priority under 35 U.S.C. § 119(e) or 35 U.S.C. § 120, and / or as an application of a previously filed application, and the parties from which the application derives its title are intended to be set forth in the Specific Summary. As such, the following claims, as well as any equivalent claims which do not recite a specific member, element, feature, property, or characteristic, but include any and all equivalents thereof, are intended to cover and encompas any and all changes in or adaptations of the application with which the specific members, elements, features, properties, or characteristics can be practiced or associated, other than those which have already been specifically recited. It is intended that changes and modifications not recited in the specification can be resorted to by those skilled in the art, and that the application shall cover and encompas any such changes and modifications insofar as they come within the scope of the following claims and any equivalents thereto.

[0050] It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, it will be understood that when a first part is said to be "formed on" a second part, the first part can be directly formed on the second part, and a third part can be interposed therebetween. In addition, when it is indicated that a first part is formed on a second part, a surface of the second part on which the first part is formed is not limited to an upper surface of the second part, but can include other surfaces such as a side surface or a lower surface of the second part. Conversely, when a first part is said to be "under" a second part, the first part can be directly under the second part, and a third part can be interposed therebetween.

[0051] Various embodiments of the present disclosure relate to a display device and an electronic device including the same. Hereinafter, the display device and the electronic device including the same according to some embodiments will be described with reference to the accompanying drawings.

[0052] Hereinafter, the display device DD according to some embodiments will be described with reference to Figures 1 to 5

[0053] Figure 1 is a schematic view for describing the display device DD according to some embodiments. Figure 2 ​is a schematic plan view illustrating a display portion DP according to some embodiments. Figure 3 is a schematic plan view illustrating a sensing portion TSP according to some embodiments. Figure 4 is a schematic cross-sectional view illustrating a display device DD according to some embodiments. Figure 5 is a schematic cross-sectional view illustrating a circuit layer CIL in a display region DA according to some embodiments.

[0054] Reference Figure 1 and Figure 5 The display device DD is configured to provide (or emit) light. According to some embodiments, the display device DD can be applied to various devices, and applicable devices are not limited to specific examples.

[0055] The display device DD can include a panel PNL and a drive circuit component DV configured to drive the panel PNL.

[0056] The panel PNL can include a display portion DP configured to display an image and a sensing portion TSP configured to sense a user input (e.g., a touch input).

[0057] The display portion DP can include a pixel PXL. The sensing portion TSP can include a sensing electrode SP.

[0058] The drive circuit component DV can include a display driver (D-IC) DDV configured to drive the display portion DP and a sensor driver (T-IC) SDV configured to drive the sensing portion TSP.

[0059] According to some embodiments, the display portion DP can be referred to as a display layer or a display panel. The sensing portion TSP can be referred to as a sensing layer, a sensing panel, or a touch sensor.

[0060] The pixel PXL can display an image in units of each display frame period. The sensing electrode SP can sense an input (e.g., a touch input) from a user in units of each sensing frame period. According to some embodiments, the sensing frame period and the display frame period can be independent of each other, or can be different from each other. The sensing frame period and the display frame period can be synchronized with each other, or can be asynchronous.

[0061] The sensing portion TSP including the sensing electrode SP can obtain information about a user touch input UTI (refer to Figure 7 ). The information about the touch input (or touch event) can be information including a position of a touch provided from a user, and the like.

[0062] The first base layer BS1 can be a base substrate or a base member for supporting the display device DD. The first base layer BS1 can be a rigid substrate made of glass. Alternatively, the first base layer BS1 can be a flexible substrate. In this case, the base layer can include an insulating material such as a polymer resin (e.g., polyimide). However, embodiments according to the present disclosure are not particularly limited to the foregoing.

[0063] The display device DD (or the display portion DP) can include a display area DA and a non-display area NDA. The non-display area NDA can surround at least a portion of the display area DA. The non-display area NDA can be disposed around a periphery of the display area DA (e.g., outside of the footprint).

[0064] The pixels PXL and the scan lines and the data lines electrically connected to the pixels PXL can be located in the display area DA.

[0065] The pixels PXL can be supplied with data signals from the data lines based on the scan signals of the on level supplied from the scan lines, and can emit light having a luminance corresponding to the data signals. Accordingly, an image corresponding to the data signals can be displayed in the display area DA.

[0066] The pixels PXL can be arranged in the display area DA in accordance with an arrangement structure. For example, the pixels PXL can be arranged in accordance with a stripe or a mosaic arrangement or structure. However, embodiments according to the present disclosure are not limited to the foregoing examples. The pixels PXL can be arranged in accordance with an arrangement or structure of the formula. However, embodiments according to the present disclosure are not limited to the foregoing examples.

[0067] Each of the pixels PXL (or the sub-pixels SPX) can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The at least one first sub-pixel SPX1, the at least one second sub-pixel SPX2, and the at least one third sub-pixel SPX3 can form a pixel unit PXU, which can emit light of various colors.

[0068] For example, each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can emit light of a single color. For example, the first sub-pixel SPX1 can be a red pixel configured to emit light in red (e.g., a first color), the second sub-pixel SPX2 can be a green pixel configured to emit light in green (e.g., a second color), and the third sub-pixel SPX3 can be a blue pixel configured to emit light in blue (e.g., a third color).

[0069] Various wirings and / or internal circuits connected to the pixels PXL of the display area DA can be located in the non-display area NDA. For example, a plurality of wirings for supplying various power voltages and control signals to the display area DA can be located in the non-display area NDA.

[0070] The sensing portion TSP can obtain information related to an input provided from a user. The sensing portion TSP can be configured to recognize a touch input.

[0071] The display apparatus DD (or the sensing portion TSP) can include a sensing area SA and a non-sensing area NSA.

[0072] According to some embodiments, the sensing area SA can be arranged to overlap at least one area in the display area DA. For example, the sensing area SA can be set as an area corresponding to the display area DA (e.g., an area overlapping the display area DA). The non-sensing area NSA can be set as an area corresponding to the non-display area NDA (e.g., an area overlapping the non-display area NDA). In this case, when a touch input or the like is provided to the display area DA, the sensing portion TSP can detect the touch input.

[0073] The second base layer BS2 can include one or more insulating layers. For example, an insulating layer (e.g., an inorganic insulating layer) for forming the second base layer BS2 can be located (e.g., directly located) on the display portion DP (e.g., the encapsulation layer TFE), thereby forming a base for forming the sensing electrode SP. However, examples regarding the formation of the second base layer BS2 are not particularly limited.

[0074] The sensing area SA can be set as an area (e.g., an active area of a sensor) capable of responding to a touch input. To this end, the sensing electrode SP for sensing a touch input or the like can be located in the sensing area SA.

[0075] The sensing electrode SP can acquire information related to a user touch input UTI by using a self-capacitance method.

[0076] The sensing electrode SP can be arranged in the sensing area SA in various structures. For example, the sensing electrode SP can be arranged in the second direction DR2. The sensing electrode SP can be arranged in the first direction DR1. The sensing electrode SP can be arranged in a matrix pattern defined based on the second direction DR2 and the first direction DR1. However, the disclosure is not limited to the aforementioned examples. For example, the sensing electrode SP can be arranged in a circular shape or an elliptical shape, or can be obliquely arranged.

[0077] According to some embodiments, the first direction DR1 and the second direction DR2 can be different from each other. The first direction DR1 and the second direction DR2 can be perpendicular to each other. However, the disclosure is not limited to the aforementioned examples. For example, the first direction DR1 and the second direction DR2 can obliquely extend with respect to each other.

[0078] According to some embodiments, the sensing electrodes SP can have various shapes. For example, the sensing electrodes SP can have various shapes such as a rectangular shape, a triangular shape, a circular shape, an elliptical shape, or a mesh form.

[0079] According to some embodiments, the sensing electrodes SP can include an electrically conductive material. For example, the sensing electrodes SP can include at least one of a metal, a transparent conductive material, and other various electrically conductive materials, and thus have electrical conductivity. For example, the sensing electrodes SP can include at least one of various metals including gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or platinum (Pt), or an alloy thereof. The sensing electrodes SP can include at least one of various transparent conductive materials including silver nanowires (AgNW), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), tin oxide (SnO2), carbon nanotubes, or graphene. Each of the sensing electrodes SP can be formed of a single layer or multiple layers, and a cross-sectional structure thereof is not particularly limited.

[0080] The panel PNL can include a pad area PDA. The panel PNL can include display pads DPD and touch sensing pads TPD located in the pad area PDA.

[0081] The display pads DPD can be electrically connected to the pixels PXL in the display area DA through wiring. The display pads DPD can be electrically connected to a display driver DDV formed (e.g., included) in the driving circuit member DV. For example, an electrical signal provided from the display driver DDV can be applied to the pixels PXL through the display pads DPD.

[0082] The touch sensing pads TPD can be electrically connected to the sensing electrodes SP through wiring and a multiplexer MUX. The touch sensing pads TPD can be electrically connected to a sensor driver SDV formed (e.g., included) in the driving circuit member DV. For example, an electrical signal provided from the sensor driver SDV can be applied to the sensing electrodes SP through the touch sensing pads TPD.

[0083] The driving circuit member DV can include a flexible circuit substrate. The driving circuit member DV can be implemented as an integrated circuit (IC).

[0084] The driving circuit member DV can include a display driver DDV and a sensor driver SDV. The driving circuit member DV can be formed on a rear surface of the first base layer BS1.

[0085] The display driver DDV can be electrically connected to the display portion DP, and can be configured to drive the display portion DP. The display driver DDV can be formed on the rear surface of the first base layer BS1, and can be electrically connected to the pixels PXL through the display pads DPD. The display driver DDV can include a data driver, a timing controller, and a scan driver, etc.

[0086] The sensor driver SDV can be electrically connected to the sensing portion TSP, and can be configured to drive the sensing portion TSP. The sensor driver SDV can be formed on the rear surface of the first base layer BS1, and can be electrically connected to the sensing electrodes SP through the touch sensing pads TPD. The sensor driver SDV can include a sensing transmitter and a sensing receiver.

[0087] The panel PNL (e.g., the sensing portion TSP) can include a multiplexer area MUA. The panel PNL (e.g., the sensing portion TSP) can include a multiplexer MUX located in the multiplexer area MUA.

[0088] The multiplexer area MUA can be located between the sensing area SA and the pad area PDA. The multiplexer area MUA can be located on one side of the sensing area SA. An electrical signal supplied through the touch sensing pad TPD can be applied to the sensing electrode SP via the multiplexer MUX.

[0089] The electrical connection relationship between the multiplexer MUX and the sensing electrode SP, etc. will be described later with reference to Figure 6 and the subsequent drawings.

[0090] Referring to Figure 4 , according to some embodiments, the display portion DP can include a circuit layer CIL, a light emitting element layer LEL, and a package layer TFE located on the first base layer BS1.

[0091] The circuit layer CIL can be arranged across the display area DA and the non-display area NDA, and can be located on the first base layer BS1. The circuit layer CIL is configured to drive the sub-pixel SPX, and can include a pixel circuit electrically connected to the light emitting element. The circuit layer CIL can include a MUX transistor MT (refer to Figure 8 ) for forming each of the multiplexers MUX.

[0092] The light emitting element layer LEL can be located in the display area DA, on the circuit layer CIL. The light emitting element layer LEL can include a light emitting element configured to emit light. The light emitting element can be formed of an organic light emitting diode (LED) including an organic material, and can include an inorganic light emitting diode (e.g., a micro LED) including an inorganic material. However, the present disclosure is not limited to the aforementioned examples.

[0093] The encapsulation layer TFE can cover the light-emitting element layer LEL. At least a portion of the encapsulation layer TFE can be located in the display area DA. The encapsulation layer TFE can encapsulate the light-emitting element layer LEL.

[0094] The sensing portion TSP can be arranged across the sensing area SA and the non-sensing area NSA. The sensing portion TSP (e.g., at least a portion of the sensing portion TSP) can be located on (e.g., directly on) the encapsulation layer TFE.

[0095] According to some embodiments, the sensing portion TSP can be fabricated in such a way that the sensing portion TSP is formed on the encapsulation layer TFE, instead of being located on a separate substrate and coupled to the display portion DP. Therefore, the process of fabricating the display device DD can be simplified.

[0096] Figure 5 An example of a cross-section of the circuit layer CIL in the display area DA according to some embodiments is schematically illustrated. Referring to Figure 5 , the circuit layer CIL can include a plurality of insulating layers and a plurality of conductive layers located on the first base layer BS1.

[0097] For example, the circuit layer CIL can include a bottom conductive layer BML, a buffer layer BFL, an active layer ACT, a gate insulating layer GI, a gate conductive layer GAT, an interlayer insulating layer ILD, a first interlayer conductive layer ICL1, a first via layer VIA1, a second interlayer conductive layer ICL2, and a second via layer VIA2 arranged (e.g., sequentially arranged) in a thickness direction of the first base layer BS1 (e.g., in the third direction DR3). The circuit layer CIL can form the MUX transistor MT and a pixel circuit including the pixel transistor TR formed by patterning the respective layers.

[0098] The buffer layer BFL can be located on the first base layer BS1. The buffer layer BFL can prevent or reduce diffusion of contaminants or impurities into the active layer ACT or penetration of moisture into the active layer ACT.

[0099] The active layer ACT can be located on the buffer layer BFL. The active layer ACT can include a semiconductor. For example, the active layer ACT can include one or more of polysilicon (e.g., low-temperature polysilicon (LTPS)), amorphous silicon, and oxide semiconductor.

[0100] The bottom conductive layer BML, the gate conductive layer GAT, the first interlayer conductive layer ICL1, and the second interlayer conductive layer ICL2 can include a conductive material and can each have a single-layer or multi-layer structure. According to some embodiments, the gate conductive layer GAT can form a gate electrode of the pixel transistor TR. First and second portions of the first interlayer conductive layer ICL1 can form a source electrode and a drain electrode of the pixel transistor TR, respectively.

[0101] According to some embodiments, a portion of the first interlayer conductive layer ICL1 used to form the pixel transistor TR can be electrically connected to the light-emitting element (or the anode electrode of the light-emitting element) through at least a portion of the second interlayer conductive layer ICL2.

[0102] According to some embodiments, the first interlayer conductive layer ICL1 may be a first source / drain electrode layer, and the second interlayer conductive layer ICL2 may be a second source / drain electrode layer.

[0103] The buffer layer BFL, gate insulating layer GI, interlayer insulating layer ILD, first via layer VIA1, and second via layer VIA2 may be placed adjacent to the conductive layers included in the circuit layer CIL, and may comprise various insulating materials such as inorganic and / or organic materials. At least some of the conductive layers may be electrically connected to each other by contact members passing through at least one of the insulating layers.

[0104] Reference Figures 6 to 9 The sensing unit, including a multiplexer MUX, according to some embodiments will be described in more detail below. For ease of explanation, some descriptions that overlap with the content described above may be simplified or omitted.

[0105] Figure 6 This is a schematic plan view illustrating the sensing area SA and the multiplexer area MUA according to some embodiments. Figure 7 This is a schematic diagram illustrating the operation of sensing touch input by a sensing unit according to some embodiments. Figure 8 and Figure 9 This is a schematic plan view illustrating a multiplexer MUX according to some embodiments and the lines electrically connected to the multiplexer MUX.

[0106] According to the reference Figure 6 and Figure 7 In some embodiments, the display device DD (or panel PNL) may include sensing lines SL and signal lines SGL.

[0107] The sensing line SL can electrically connect the multiplexer MUX located in the multiplexer region MUA to the sensing electrode SP in the sensing region SA. According to some embodiments, the signal line SGL can electrically connect the multiplexer MUX to the sensor driver SDV. Accordingly, the sensing signal provided from the sensor driver SDV can be applied to the sensing electrode SP through the signal line SGL, the multiplexer MUX, and the sensing line SL.

[0108] At least a portion of the sensing line SL can extend in the second direction DR2. Accordingly, the sensing electrodes SP and the multiplexer MUX, which are spaced apart from each other in the second direction DR2, can be electrically connected to each other.

[0109] A multiplexer MUX can be electrically connected to one or more sensing electrodes SP. For example, a multiplexer MUX may include multiple multiplexer MUXs, each including multiplexer circuitry. Each of the multiple multiplexer MUXs can be electrically connected to one or more sensing electrodes SP. The multiplexer MUX can apply an electrical signal supplied through any one of the signal lines SGL via the sensing line SL to the sensing electrode SP.

[0110] Some of the multiple multiplexers (MUXs) can be arranged on the first direction DR1 (e.g., sequentially). Some of the multiple multiplexers (MUXs) can be arranged on the second direction DR2 (e.g., sequentially). In this way, multiple multiplexers (MUXs) can be arranged in a multiplexer region (MUA).

[0111] According to some embodiments, the sensor driver SDV can acquire information related to user touch input (UTI) by using a self-capacitance method. According to some embodiments, the display device DD (or panel PNL) may include a capacitive electrode CE. According to some embodiments, the capacitive electrode CE may be at least any one of the electrodes of the display unit DP. For example, the capacitive electrode CE may be the cathode electrode of a light-emitting element. However, this disclosure is not limited to the foregoing examples.

[0112] According to some embodiments, the sensor driver SDV can charge or discharge the sensing electrode SP via the signal line SGL, the multiplexer MUX, and the sensing line SL, and can obtain information related to the user touch input UTI by detecting changes in the capacitance of the sensing electrode SP. The information related to the user touch input UTI may include the location of the user touch input UTI and whether the user touch input UTI is present.

[0113] For example, a reference voltage provided by the sensor driver SDV can be applied to the sensing electrode SP. When a user touch input UTI is applied, a self-capacitance Csf can be formed between the sensing electrode SP and the capacitive electrode CE. The reference voltage can be changed to a voltage information with a waveform altered by the self-capacitance. The sensor driver SDV can receive the changed voltage information, analyze it, and determine the location of the user touch input UTI and whether the user touch input UTI is present, etc.

[0114] According to some embodiments, the multiplexer MUX can receive electrical signals via signal lines SGL and output electrical signals via sensing lines SL. According to some embodiments, the number of signal lines SGL can be greater than the number of sensing lines SL.

[0115] According to some embodiments, the multiplexer MUX can select some of the electrical signals supplied through the signal line SGL and supply the selected electrical signals to the corresponding sensing line SL.

[0116] For example, a display device DD (or panel PNL) may include a MUX gate line MGL. A multiplexer MUX may include two or more MUX transistors MT. The number of MUX transistors MT according to some embodiments is not limited to specific examples.

[0117] Multiple MUX gate lines MGL can exist that can be connected to the corresponding MUX transistor MT. Each of the multiple MUX gate lines MGL can be electrically connected to the gate electrode of the corresponding MUX transistor MT. The MUX gate line MGL can turn on the corresponding MUX transistor MT.

[0118] Accordingly, the operation of the MUX transistor MT can be controlled by using the MUX gate line MGL, thereby allowing some of the electrical signals supplied through the signal line SGL to be selected and applied to the corresponding sensing line SL.

[0119] Figure 9 The figure illustrates the circuit structure of a multiplexer MUX according to some embodiments. The structure of the multiplexer MUX is not limited to this. Figure 9 The circuit structure. Although Figure 9 The figures illustrate various components in a multiplexer MUX according to some embodiments, but according to various embodiments, the multiplexer MUX may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0120] refer to Figure 9 The multiplexer MUX can select any one of the applied signals S and apply the selected signal S to the corresponding sensing line SL. For example, the signal S may include a first signal S1, a second signal S2, and a third signal S3.

[0121] A multiplexer MUX may include multiple MUX transistors MT. For example, multiple MUX transistors MT may include a first MUX transistor MT1, a second MUX transistor MT2, a third MUX transistor MT3, and a fourth MUX transistor MT4.

[0122] A signal line SGL may include multiple signal lines SGL. For example, multiple signal lines SGL may include a first signal line SGL1, a second signal line SGL2, and a third signal line SGL3.

[0123] MUX gate lines MGL can include multiple MUX gate lines MGL and can provide multiple gate control signals GS. For example, multiple MUX gate lines MGL can include a first MUX gate line MGL1, a second MUX gate line MGL2, a third MUX gate line MGL3, and a fourth MUX gate line MGL4. For example, multiple gate control signals GS can include a first gate control signal GS1, a second gate control signal GS2, a third gate control signal GS3, and a fourth gate control signal GS4.

[0124] According to some embodiments, the first electrode of the first MUX transistor MT1 may be electrically connected to the first signal line SGL1. The second electrode of the first MUX transistor MT1 may be electrically connected to the first node N1. The first gate electrode GE1 of the first MUX transistor MT1 may be electrically connected to the first MUX gate line MGL1. The first MUX transistor MT1 may be turned on when a first gate control signal GS1 is applied to it from the first MUX gate line MGL1, thereby electrically connecting the first signal line SGL1 to the first node N1.

[0125] According to some embodiments, the first electrode of the second MUX transistor MT2 can be electrically connected to the second signal line SGL2. The second electrode of the second MUX transistor MT2 can be electrically connected to the first node N1. The second gate electrode GE2 of the second MUX transistor MT2 can be electrically connected to the second MUX gate line MGL2. The second MUX transistor MT2 can be turned on when a second gate control signal GS2 is applied to it from the second MUX gate line MGL2, thereby electrically connecting the second signal line SGL2 to the first node N1.

[0126] According to some embodiments, the first electrode of the third MUX transistor MT3 may be electrically connected to the first node N1. The second electrode of the third MUX transistor MT3 may be electrically connected to the second node N2. The third gate electrode GE3 of the third MUX transistor MT3 may be electrically connected to the third MUX gate line MGL3. The third MUX transistor MT3 may be turned on when a third gate control signal GS3 is applied to it from the third MUX gate line MGL3, thereby electrically connecting the first node N1 to the second node N2.

[0127] According to some embodiments, the first electrode of the fourth MUX transistor MT4 can be electrically connected to the third signal line SGL3. The second electrode of the fourth MUX transistor MT4 can be electrically connected to the second node N2. The fourth gate electrode GE4 of the fourth MUX transistor MT4 can be electrically connected to the fourth MUX gate line MGL4. The fourth MUX transistor MT4 can be turned on when a fourth gate control signal GS4 is applied to it from the fourth MUX gate line MGL4, thereby electrically connecting the third signal line SGL3 to the second node N2.

[0128] The operation of the first to fourth MUX transistors MT1 to MT4 can be controlled by the first to fourth MUX gate lines MGL1 to MGL4. Any one of the first to third signals S1 to S3 can be applied to the sensing line SL.

[0129] When the first MUX transistor MT1 and the third MUX transistor MT3 are turned on and the second MUX transistor MT2 and the fourth MUX transistor MT4 are not turned on, the first signal S1 can be applied from the first signal line SGL1 to the sensing line SL and the sensing electrode SP. The first signal S1 can be a sensing drive signal used to sense user touch input UTI at the location of the sensing electrode SP electrically connected to the sensing line SL.

[0130] When the second MUX transistor MT2 and the third MUX transistor MT3 are turned on and the first MUX transistor MT1 and the fourth MUX transistor MT4 are not turned on, the second signal S2 can be applied from the second signal line SGL2 to the sensing line SL and the sensing electrode SP. The second signal S2 can be a first auxiliary sensing signal, which is used to determine information related to the user touch input UTI when another sensing electrode SP senses a user touch input UTI in a region adjacent to the location of the sensing electrode SP electrically connected to the sensing line SL.

[0131] When the fourth MUX transistor MT4 is turned on and the first to third MUX transistors MT1 to MT3 are not turned on, the third signal S3 can be applied from the third signal line SGL3 to the sensing line SL and the sensing electrode SP. The third signal S3 can be a second auxiliary sensing signal, which is applied to the corresponding sensing electrode SP when no user touch input UTI is detected at the location of the sensing electrode SP electrically connected to the sensing line SL and in the area around that location.

[0132] According to some embodiments, the multiplexer MUX can apply any one of the first to third signals S1 to S3 to the sensing electrode SP via the sensing line SL. As a result, wiring complexity can be relatively reduced, and while the size of the non-display area NDA (or non-sensing area NSA) can be relatively reduced, the sensing electrode SP can acquire information related to the user touch input UTI with improved reliability by using the first to third signals S1 to S3.

[0133] According to some embodiments, the first to third signals S1 to S3 may have different electrical information. For example, the first to third signals S1 to S3 may have different waveforms, different potentials, and / or different phases.

[0134] According to some embodiments, the first to fourth gate control signals GS1 to GS4 supplied to the first to fourth MUX gate lines MGL1 to MGL4 can have different electrical information. For example, the first to fourth gate control signals GS1 to GS4 can have different potentials.

[0135] In this case, when the gate control signal GS is applied to the multiplexer MUX to operate the multiplexer MUX, voltages with different potentials can be applied to the corresponding MUX gate lines MGL.

[0136] In experiments, when wiring is too close to each other, there is a risk that electrical signals may be distorted when voltages with different potentials are applied to the wiring. Furthermore, there are concerns about the risk of corrosion in the wiring under harsh environments (e.g., high temperature and / or high humidity conditions).

[0137] Some aspects of embodiments of this disclosure may include MUX gate lines MGL and multiplexers MUX capable of relatively reducing (e.g., significantly reducing) the risks mentioned above. In this regard, reference will be made to... Figure 10 And the accompanying diagrams will explain more details.

[0138] Reference Figures 10 to 13 This section describes the structure of a multiplexer MUX according to some embodiments, as well as the components arranged around the multiplexer MUX. For ease of explanation, descriptions of content overlapping with the above description will be simplified or omitted.

[0139] Figure 10 This is a schematic plan view illustrating a multiplexer MUX and the area surrounding the multiplexer MUX according to some embodiments. Figure 11 It is along Figure 10 A schematic cross-sectional view of the line A-A'. Figure 12This is a schematic plan view illustrating a multiplexer MUX and the area surrounding the multiplexer MUX according to some embodiments. Figure 13 It is along Figure 12 A schematic cross-sectional view of line B-B'.

[0140] Figure 10 and Figure 12 A schematic diagram illustrates a structure in which various MUX transistors MT are arranged. According to some embodiments, Figure 10 and Figure 12 Some of the MUX transistors MT shown in the diagram can form a single multiplexer circuit, and some of the MUX transistors MT can form another multiplexer circuit. For example, in Figure 10 and Figure 12 In this context, each of the MUX transistors MT can form any one of the multiplexers MUX, and can be any one of the first to fourth MUX transistors MT1 to MT4. For ease of explanation, Figure 10 and Figure 11 The diagram only shows the third MUX gate portion MGL_P3 for some of the MUX gates MGL, but the embodiments are not limited thereto.

[0141] First, refer to Figure 10 and Figure 11 This describes a display device DD according to some embodiments. References Figure 5 and Figure 12 The MUX gate line MGL can be located in the peripheral portion of the MUX transistor MT.

[0142] MUX gate lines MGL can be arranged around MUX transistor MT, and can include multiple MUX gate lines MGL arranged sequentially in one direction.

[0143] For example, some of the multiple MUX gate lines MGL can be located on the lower side of the multiplexer region MUA. Some of the multiple MUX gate lines MGL can be located in the multiplexer region MUA, between the MUX transistors MT. Some of the multiple MUX gate lines MGL can be located on the upper side of the multiplexer region MUA.

[0144] The MUX gate line MGL can extend in two or more directions. For example, a portion of the MUX gate line MGL can extend in a first direction DR1, and another portion of the MUX gate line MGL can extend in a second direction DR2.

[0145] For example, the MUX gate line MGL may include a first MUX gate line portion MGL_P1 extending in a first direction DR1 and a second MUX gate line portion MGL_P2 extending in a second direction DR2. The first MUX gate line portion MGL_P1 and the second MUX gate line portion MGL_P2 may be electrically connected to each other via a contact member CNP. According to some embodiments, the MUX gate line MGL may include a third MUX gate line portion MGL_P3 extending in the second direction DR2 and electrically connecting the first MUX gate line portion MGL_P1 to the MUX transistor MT. The third MUX gate line portion MGL_P3 may be electrically connected to the first MUX gate line portion MGL_P1 via a contact member CNP.

[0146] According to some embodiments, the gate control signal GS provided from the sensor driver SDV can be applied to the gate electrode of the MUX transistor MT through the second MUX gate line portion MGL_P2, the first MUX gate line portion MGL_P1, and the third MUX gate line portion MGL_P3.

[0147] According to some embodiments, each MUX gate line MGL may include a plurality of second MUX gate line portions MGL_P2. One of the second MUX gate line portions MGL_P2 may be electrically connected to the first MUX gate line portion MGL_P1 at a first end EP1. Another of the second MUX gate line portions MGL_P2 may be electrically connected to the first MUX gate line portion MGL_P1 at a second end EP2.

[0148] According to some embodiments, the gate control signal GS can be applied to the first MUX gate line portion MGL_P1 through either the first end EP1 or the second end EP2. In this case, the gate control signal GS can be transmitted to the gate electrode of the MUX transistor MT through the second MUX gate line portion MGL_P2, the first MUX gate line portion MGL_P1, and the third MUX gate line portion MGL_P3, which are adjacent to the first end EP1 or the second end EP2. In this case, multiple paths can be formed that can supply the gate control signal GS from the sensor driver SDV along them, thereby enabling efficient control of the conduction operation of the MUX transistor MT.

[0149] The MUX gate lines MGL can be arranged sequentially in one direction. For example, the respective first MUX gate line portions MGL_P1 of the MUX gate line MGL can be arranged in the second direction DR2 (e.g., sequentially). The respective second MUX gate line portions MGL_P2 of the MUX gate line MGL can be arranged in the first direction DR1 (e.g., sequentially). The respective third MUX gate line portions MGL_P3 of the MUX gate line MGL can be arranged in the first direction DR1 (e.g., sequentially).

[0150] According to some embodiments, the MUX gate line MGL can be related to the above reference. Figure 13 At least some of the described layers are formed using the same process. The layer used to form the MUX gate line MGL may be formed using the same process as at least some of the layers included in the circuit layer CIL in the display area DA, and may include the same materials.

[0151] According to some embodiments, the first MUX gate line portion MGL_P1 can be patterned using the same process as the first interlayer conductive layer ICL1 and can include the same conductive material. For example, the first MUX gate line portion MGL_P1 can be patterned using the same process as the source electrode and / or drain electrode of the transistor used to form the pixel circuit and can include the same conductive material.

[0152] According to some embodiments, the second MUX gate line portion MGL_P2 can be patterned using the same process as the second interlayer conductive layer ICL2, and can include the same conductive material. For example, the second MUX gate line portion MGL_P2 can be patterned using the same process as the conductive portion in the circuit layer CIL that is electrically connected to the light-emitting element (or the anode electrode of the light-emitting element) in the display area DA, and can include the same conductive material.

[0153] According to some embodiments, the third MUX gate line portion MGL_P3 can be patterned using the same process as the gate conductive layer GAT and can include the same conductive material. For example, the third MUX gate line portion MGL_P3 can be patterned using the same process as the gate electrode of the transistor used to form the pixel circuit.

[0154] Here, the layer in which the first MUX gate line portion MGL_P1, the second MUX gate line portion MGL_P2, and the third MUX gate line portion MGL_P3 are formed is not limited to the example mentioned above.

[0155] According to some embodiments, when viewed in a plan view, the MUX gate lines MGL, to which different gate control signals GS are supplied respectively, may not overlap with each other in at least some regions. The overlap range between the MUX gate lines MGL to which different gate control signals GS are supplied can be relatively reduced (e.g., significantly reduced).

[0156] As a result, the overlap between the MUX gate lines MGL, which supply different gate control signals GS, can be relatively reduced, thereby reducing the risk of distortion in the electrical signals and reducing concerns about the risk of corrosion in the MUX gate lines MGL under harsh environments (e.g., high temperature and / or high humidity conditions).

[0157] According to some embodiments, the respective first MUX gate portions MGL_P1 of the MUX gate MGL may not overlap with each other in the planar view.

[0158] According to some embodiments, the respective second MUX gate portions MGL_P2 of the MUX gate MGL may not overlap with each other in the planar view.

[0159] According to some embodiments, the first MUX gate line portion MGL_P1 of one MUX gate line MGL and the second MUX gate line portion MGL_P2 of another MUX gate line MGL may not overlap with each other in the planar view.

[0160] For example, the first MUX gate line portion MGL_P1 of the first MUX gate line MGL1 may not overlap with the corresponding second MUX gate line portions MGL_P2 of the second MUX gate line MGL2 and the third MUX gate line MGL3 in the planar view. Similarly, the first MUX gate line portion MGL_P1 of the second MUX gate line MGL2 may not overlap with the corresponding second MUX gate line portions MGL_P2 of the first MUX gate line MGL1 and the third MUX gate line MGL3 in the planar view. Likewise, the first MUX gate line portion MGL_P1 of the third MUX gate line MGL3 may not overlap with the corresponding second MUX gate line portions MGL_P2 of the first MUX gate line MGL1 and the second MUX gate line MGL2 in the planar view.

[0161] According to some embodiments, the second MUX gate line MGL2 may be closer to the multiplexer region MUA (or MUX transistor MT) than the first MUX gate line MGL1. According to some embodiments, the first MUX gate portion MGL_P1 of the second MUX gate line MGL2 may extend further in the first direction DR1 than the first MUX gate portion MGL_P1 of the first MUX gate line MGL1. The second MUX gate portion MGL_P2 of the second MUX gate line MGL2 may extend further externally in the second direction DR2 than the second MUX gate portion MGL_P2 of the first MUX gate line MGL1. The second MUX gate portion MGL_P2 of the second MUX gate line MGL2 and the second MUX gate portion MGL_P2 of the first MUX gate line MGL1 may not overlap each other.

[0162] According to some embodiments, unlike the second MUX gate line MGL2, the third MUX gate line MGL3 can pass through the multiplexer region MUA. According to some embodiments, the first MUX gate line portion MGL_P1 of the third MUX gate line MGL3 can extend further in the first direction DR1 than the first MUX gate line portion MGL_P1 of the second MUX gate line MGL2. Therefore, the second MUX gate line portion MGL_P2 of the third MUX gate line MGL3 can extend further externally in the second direction DR2 than the second MUX gate line portion MGL_P2 of the second MUX gate line MGL2. The second MUX gate line portions MGL_P2 of the third MUX gate line MGL3 and the second MUX gate line MGL2 can not overlap each other.

[0163] According to some embodiments, the MUX gate lines MGL can be arranged sequentially. Each of the MUX gate lines MGL can include a contact member CNP. According to some embodiments, the contact members CNP can be arranged sequentially in an inclined direction. This inclined direction can be parallel to the direction between the first direction DR1 and the second direction DR2.

[0164] According to some embodiments, the respective second MUX gate portions MGL_P2 of the MUX gate line MGL can be spaced apart from each other by a first distance L1 and L1' in the first direction DR1. For example, the corresponding second MUX gate portions MGL_P2 of the first MUX gate line MGL1 and the second MUX gate line MGL2 can be spaced apart from each other by a first distance L1. The corresponding second MUX gate portions MGL_P2 of the second MUX gate line MGL2 and the third MUX gate line MGL3 can be spaced apart from each other by a first distance L1'.

[0165] According to some embodiments, the first interlayer conductive layer ICL1 and the second interlayer conductive layer ICL2 may be spaced apart from each other by a second distance L2 on the third-direction DR3. For example, the first MUX gate line portion MGL_P1 and the second MUX gate line portion MGL_P2 may be spaced apart from each other by a second distance L2 on the third-direction DR3. According to some embodiments, the first via layer VIA1 and the second via layer VIA2 may include organic materials. Accordingly, the portions used to form the MUX gate line MGL may be adjacent to each other through a structure containing organic materials.

[0166] According to some embodiments, each of the first distances L1 and L1' can be greater than the second distance L2. Accordingly, the MUX gate lines MGL to which gate control signals GS with different potentials are applied can be spaced apart from each other in the planar direction. In other words, since the MUX gate lines MGL to which gate control signals GS with different potentials are applied do not overlap and are patterned to be spaced apart from each other by a relatively long distance, the risk that may arise due to excessive proximity of the gate control signals GS with different potentials can be relatively reduced.

[0167] Next, we will refer to Figure 12 and Figure 13 This describes a display device DD according to some embodiments. For ease of explanation, descriptions overlapping with the embodiments described above will be simplified or omitted.

[0168] According to the reference Figure 10 and Figure 11 Some embodiments of the display device DD and according to the above reference Figure 12 and Figure 13 The difference between the display device DD of some of the described embodiments is that at least some of the MUX gate lines MGL overlap each other in the planar view.

[0169] refer to Figure 14 and Figure 15 According to some embodiments, some of the first MUX gate line portions MGL_P1 and the second MUX gate line portions MGL_P2 in the MUX gate line MGL can overlap each other in the planar view.

[0170] According to some embodiments, some MUX gate lines MGL to which gate control signals GS with similar potentials are applied may overlap each other in a planar view.

[0171] For example, according to some embodiments, the second gate control signal GS2 applied to the second MUX gate line MGL2 and the third gate control signal GS3 applied to the third MUX gate line MGL3 may have similar potentials. For example, the second gate control signal GS2 and the third gate control signal GS3 may have a potential difference of 1V or less. Alternatively, the second gate control signal GS2 and the third gate control signal GS3 may have voltages having the same potential (or substantially the same potential).

[0172] According to some embodiments, the first MUX gate line portion MGL_P1 and the second MUX gate line portion MGL_P2 of the first MUX gate line MGL1 may not overlap with the first MUX gate line portion MGL_P1 and the second MUX gate line portion MGL_P2 of each of the second MUX gate line MGL2 and the third MUX gate line MGL3 in the plan view.

[0173] According to some embodiments, the first MUX gate portion MGL_P1 of the second MUX gate line MGL2 and the first MUX gate portion MGL_P1 of the third MUX gate line MGL3 may not overlap with each other in the planar view. Similarly, the second MUX gate portion MGL_P2 of the second MUX gate line MGL2 and the second MUX gate portion MGL_P2 of the third MUX gate line MGL3 may not overlap with each other in the planar view.

[0174] According to some embodiments, the second MUX gate line portion MGL_P2 of the third MUX gate line MGL3 may be located between the corresponding second MUX gate line portions MGL_P2 of the first MUX gate line MGL1 and the second MUX gate line MGL2.

[0175] According to some embodiments, the first MUX gate line portion MGL_P1 of the second MUX gate line MGL2 and the second MUX gate line portion MGL_P2 of the third MUX gate line MGL3 may overlap each other in a planar view. For example, the first MUX gate line portion MGL_P1 of the second MUX gate line MGL2 and the second MUX gate line portion MGL_P2 of the third MUX gate line MGL3 may intersect each other in the overlapping region OVA.

[0176] According to some embodiments, the MUX gate lines MGLs typically do not overlap, but some MUX gate lines MGLs supplied with a gate control signal GS having a similar potential difference may partially overlap. Accordingly, the risk of distortion of the gate control signal GS can be relatively reduced, and the risk of damage to the MUX gate lines MGLs due to corrosion, etc., can also be relatively reduced.

[0177] As a result, some aspects of embodiments of this disclosure may include a display device DD that can relatively improve the reliability of touch performance.

[0178] Figure 14 This is a schematic block diagram illustrating an electronic device 1000 including a display device according to some embodiments. Figure 16 It is shown in the figure. Figure 14 A schematic diagram illustrating an example of an electronic device 1000 implemented as a smartphone. Figures 14 to 16 It is shown in the figure. Figure 15 A schematic diagram illustrating an example of an electronic device 1000 implemented as a tablet PC.

[0179] refer to Figure 16 Electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be the display device DD described above. Electronic device 1000 may further include various ports for communicating with a graphics card, sound card, memory card, USB device, or other systems. According to some embodiments, such as ​ As illustrated, the electronic device 1000 can be implemented as a smartphone. According to some embodiments, such as... ​ As illustrated, the electronic device 1000 can be implemented as a tablet PC. However, the examples mentioned above are exemplary, and the electronic device 1000 is not limited to the examples mentioned above. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smartboard, smartwatch, navigation device for vehicle, computer monitor, laptop computer, or head-mounted display device, etc.

[0180] Processor 1010 can perform specific calculations or tasks. According to some embodiments, processor 1010 may be a microprocessor, a central processing unit, or an application processor, etc. Processor 1010 can be connected to other components via address buses, control buses, and data buses, etc. According to some embodiments, processor 1010 can be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus. According to some embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data provided from processor 1010.

[0181] The memory device 1020 can store data required to perform the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices and / or volatile memory devices. The non-volatile memory devices are, for example, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nanofloating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, and ferroelectric random access memory (FRAM) devices. The volatile memory devices are, for example, dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0182] Storage device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), or CD-ROMs, etc.

[0183] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. According to some embodiments, display device 1060 may be included in I / O device 1040.

[0184] The power supply 1050 can supply the power required to operate the electronic device 1000. For example, the power supply 1050 can be a power management integrated circuit (PMIC). According to some embodiments, the power supply 1050 can supply power to the display device 1060.

[0185] The display device 1060 can display images corresponding to the visual information of the electronic device 1000. The display device 1060 can be connected to other components via a bus or other communication link.

[0186] Some aspects of embodiments of this disclosure may include a display device capable of relatively reducing the risk of distortion of signals used for sensing touch information, and an electronic device including the display device.

[0187] Some aspects of embodiments of this disclosure may include a display device capable of relatively reducing the risk of damage to wiring and an electronic device including the display device.

[0188] Some aspects of embodiments of this disclosure may include a display device that can relatively improve the reliability of touch performance and an electronic device including the display device.

[0189] While some aspects of the embodiments have been described above, those skilled in the art will appreciate that various modifications, additions, and substitutions can be made without departing from the scope and spirit of the embodiments according to this disclosure.

[0190] Therefore, the embodiments disclosed in this specification are for illustrative purposes only and are not intended to limit the technical spirit of the embodiments according to this disclosure. The scope of the embodiments according to this disclosure must be defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: The display unit includes a substrate layer and light-emitting elements on the substrate layer; A sensing unit is located on the display unit and includes sensing electrodes; A multiplexer is electrically connected to the sensing electrode via a sensing line and includes a multiplexer MUX transistor on a portion of the substrate layer; as well as The MUX gate line is electrically connected to the MUX transistor. The MUX transistor includes a first MUX transistor and a second MUX transistor. The MUX gate line includes a first MUX gate line electrically connected to the first gate electrode of the first MUX transistor and a second MUX gate line electrically connected to the second gate electrode of the second MUX transistor. Each of the MUX gate lines includes a first MUX gate line portion extending in a first direction and a second MUX gate line portion extending in a second direction different from the first direction, and the second MUX gate line portion is electrically connected to the first MUX gate line portion at its end. The first MUX gate portion of the first MUX gate and the second MUX gate portion of the second MUX gate do not overlap in the plan view.

2. The display device according to claim 1, wherein, The MUX gate line includes a plurality of first MUX gate line portions and a plurality of second MUX gate line portions, wherein the plurality of first MUX gate line portions do not overlap with each other in the planar view, and the plurality of second MUX gate line portions do not overlap with each other in the planar view. The second MUX gate line is closer to the MUX transistor than the first MUX gate line. The first MUX gate line portion of the second MUX gate line extends further in the first direction than the first MUX gate line portion of the first MUX gate line, and The second MUX gate line portion of the second MUX gate line extends further outward in the second direction than the second MUX gate line portion of the first MUX gate line.

3. The display device according to claim 1, wherein, The second MUX gate line portion of the first MUX gate line and the second MUX gate line portion of the second MUX gate line are spaced apart from each other by a first distance in the first direction. The first MUX gate portion and the second MUX gate portion of the first MUX gate are spaced apart from each other by a second distance in the thickness direction of the substrate layer, and The first distance is greater than the second distance.

4. The display device according to claim 1, wherein, The MUX gate line further includes a third MUX gate line between the MUX transistors, and The first and second MUX gate portions of the third MUX gate line do not overlap with the first and second MUX gate portions of each of the first and second MUX gate lines in the plan view.

5. The display device according to claim 1, wherein, Some of the MUX gate lines are located below the multiplexer region where the multiplexer is located, some of the MUX gate lines are located within the multiplexer region and between the MUX transistors, and some of the MUX gate lines are located above the multiplexer region.

6. The display device according to claim 1, wherein, The first MUX gate line portion and the second MUX gate line portion are electrically connected to each other via contact members. The MUX gate line includes multiple contact members, and The plurality of contact members are arranged sequentially in an inclined direction, which extends in a direction between the first direction and the second direction.

7. The display device according to claim 1, wherein, In each of the MUX gate lines, the second MUX gate line portion is provided as a plurality of portions. One of the plurality of second MUX gate line portions is electrically connected to the first MUX gate line portion at a first end, and another of the plurality of second MUX gate line portions is electrically connected to the first MUX gate line portion at a second end. The MUX gate line includes a plurality of first MUX gate line portions and a plurality of second MUX gate line portions, wherein the plurality of first MUX gate line portions are arranged in the second direction and the plurality of second MUX gate line portions are arranged in the first direction.

8. The display device according to claim 1, wherein, The MUX gate line further includes a third MUX gate line between the MUX transistors. Wherein, the first MUX gate line portion and the second MUX gate line portion of the third MUX gate line do not overlap with the first MUX gate line portion and the second MUX gate line portion of the first MUX gate line in the plan view, and The second MUX gate line portion of the third MUX gate line overlaps with the first MUX gate line portion of the second MUX gate line in the plan view.

9. The display device according to claim 8, wherein, The second MUX gate portion of the third MUX gate is located between the second MUX gate portion of the first MUX gate and the second MUX gate portion of the second MUX gate.

10. The display device according to claim 8, wherein, The gate control signals supplied from the third MUX gate line and the second MUX gate line have a potential difference of 1V or less.

11. The display device according to claim 1, further comprising: The sensor driver is electrically connected to the multiplexer via signal lines. The multiplexer is located on one side of the sensing area where the sensing electrode is located. The multiplexer is configured to select some of the signals supplied through the signal lines and supply the selected signals to the sensing lines. The multiplexer is provided as a plurality of multiplexers, each of the plurality of multiplexers including multiplexer circuitry, and some of the plurality of multiplexers are arranged in the first direction and some of the plurality of multiplexers are arranged in the second direction.

12. The display device according to claim 11, wherein, The signal lines include a first signal line configured to supply a first signal, a second signal line configured to supply a second signal, and a third signal line configured to supply a third signal. The MUX transistor further includes a third MUX transistor and a fourth MUX transistor. The MUX gate line further includes a third MUX gate line and a fourth MUX gate line. The first electrode of the first MUX transistor is electrically connected to the first signal line, and the second electrode of the first MUX transistor is electrically connected to the first node. The first electrode of the second MUX transistor is electrically connected to the second signal line, and the second electrode of the second MUX transistor is electrically connected to the first node. The first electrode of the third MUX transistor is electrically connected to the first node, the second electrode of the third MUX transistor is electrically connected to the second node, and the third gate electrode of the third MUX transistor is electrically connected to the third MUX gate line. The first electrode of the fourth MUX transistor is electrically connected to the third signal line, the second electrode of the fourth MUX transistor is electrically connected to the second node, and the fourth gate electrode of the fourth MUX transistor is electrically connected to the fourth MUX gate line. The second node is electrically connected to the sensing line. The multiplexer is configured to selectively supply any one of the first signal, the second signal, and the third signal to the sensing line. The first MUX gate line is configured to supply the first gate control signal. The second MUX gate line is configured to supply the second gate control signal. The third MUX gate line is configured to supply a third gate control signal. The fourth MUX gate line is configured to supply a fourth gate control signal, and The first gate control signal, the second gate control signal, the third gate control signal, and the fourth gate control signal have different potentials.

13. The display device according to claim 1, wherein, The sensing electrodes are configured to use a self-capacitance method to acquire information related to user touch input. The display unit includes a light-emitting element layer containing the light-emitting element and an encapsulation layer on the light-emitting element layer, and The sensing element is located directly on the encapsulation layer.

14. The display device according to claim 1, wherein, The display unit includes a circuit layer containing pixel transistors electrically connected to the light-emitting element. The first MUX gate line portion comprises the same material as the source electrode and / or drain electrode of the pixel transistor, and The second MUX gate line portion comprises the same material as the conductive portion in the circuit layer that is electrically connected to the light-emitting element.

15. An electronic device comprising: The processor is configured to provide input image data; The display device according to any one of claims 1 to 14 is configured to display an image based on the input image data; and A power supply is configured to supply power to the display device.

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