Implementation method and device of SRT divider

Abstract

The invention relates to the technical field of computers, in particular to an implementation method and device of an SRT divider. The method comprises the following steps: converting an original dividend mantissa and an original divisor mantissa by adopting the same conversion rule to obtain a second dividend mantissa, a second divisor mantissa and a second divisor cutoff value of the second divisor mantissa; wherein the representation form of the second divisor cut-off value is less than the representation form of the first divisor cut-off value corresponding to the first divisor mantissa; and according to the mantissa of the second dividend, the mantissa of the second dividend, the truncation value of the second dividend and a lookup table, executing SRT division iterative operation to obtain a final quotient value of the original dividend and the original dividend. According to the method provided by the embodiment of the invention, the dividend and the divisor are converted to improve the efficiency of matching the lookup table according to the cut-off value of the divisor, so that the efficiency of SRT division operation is improved.

Description

TECHNICAL FIELD

[0001] The present specification relates to the technical field of computer, and particularly relates to an implementation method and device of SRT divider. BACKGROUND

[0002] SRT (Sweeney-Robertson-Tocher) divider is a kind of calculator realized by using high-performance linear convergence division algorithm, and a certain number of fixed bit values of quotient can be calculated each time until the iteration operation is completed, and the final correct quotient and remainder are calculated, the core of SRT algorithm is the operation unit of multiple iterations, which is a kind of digital loop algorithm, and the key of SRT algorithm is the size of base, which determines the number of quotient bits that can be output each time, the more the bits, the less the iteration times, the smaller the operation period, and the higher the algorithm performance, but the corresponding hardware design will be more complex.

[0003] How to improve the operation efficiency of SRT divider at low cost is a problem to be solved. SUMMARY

[0004] In order to solve the problems in the prior art, the embodiments of the present specification provide an implementation method and device of SRT divider, which solves the problem of poor performance of SRT algorithm (such as srt4) with small base in division calculation.

[0005] The embodiments of the present specification provide an implementation method of SRT divider, comprising, The original dividend mantissa and the original divisor mantissa are converted by using the same conversion rule to obtain a second dividend mantissa and a second divisor mantissa, and the second divisor mantissa has a second divisor truncation value; wherein the second divisor truncation value has a form less than that of the first divisor truncation value corresponding to the first divisor mantissa; According to the second dividend mantissa, the second divisor mantissa, the second divisor truncation value and the lookup table, SRT division iteration operation is performed to obtain the final quotient of the original dividend and the original divisor.

[0006] As a further aspect of the present specification, the conversion of the original dividend mantissa and the original divisor mantissa by using the same conversion rule further comprises, The original dividend mantissa and the original divisor mantissa are amplified to obtain the first dividend mantissa and the first divisor mantissa.

[0007] As a further aspect of the present specification, the amplification of the original dividend mantissa and the original divisor mantissa further comprises, A bit is added in front of the highest bit of the original dividend mantissa and the original divisor mantissa, at least three bits are added in the tail of the original dividend mantissa and the original divisor mantissa, to obtain the first dividend mantissa and the first divisor mantissa.

[0008] As a further aspect of the present specification, the conversion of the original dividend mantissa and the original divisor mantissa to obtain the second dividend mantissa and the second divisor mantissa further comprises, According to the first divisor truncation value corresponding to the first divisor mantissa, the first dividend mantissa is converted based on the conversion rule to obtain the second dividend mantissa; wherein the second dividend mantissa comprises a second dividend truncation value. According to the first divisor truncation value corresponding to the first divisor mantissa, the first dividend mantissa is converted based on the conversion rule to obtain the second dividend mantissa; wherein the second dividend mantissa comprises a second dividend truncation value.

[0009] As a further aspect of the present specification, the conversion of the original dividend mantissa and the original divisor mantissa to obtain the second dividend mantissa and the second divisor mantissa further comprises, The same conversion rule is used for the first dividend mantissa and the first divisor mantissa with the same first dividend truncation value and the first divisor truncation value.

[0010] As a further aspect of the present specification, the conversion rule comprises: The first dividend mantissa and the first divisor mantissa with the same first dividend truncation value and the first divisor truncation value are multiplied by the same multiple.

[0011] As a further aspect of the present specification, the second divisor truncation value has a form less than the first divisor truncation value corresponding to the first divisor mantissa further comprises, The form of the second divisor truncation value has a corresponding column number in the lookup table less than the form of the first divisor truncation value.

[0012] As a further aspect of the present specification, the conversion rule comprises:

[0013] If the first dividend truncation value and the first divisor truncation value are in a first form, the second divisor truncation value is in the first form. If the first dividend truncation value and the first divisor truncation value are in a second form, the second divisor truncation value is in the second form. if the first dividend truncated value and the first divisor truncated value are in a third representation, then the second divisor truncated value is in a first representation; if the first dividend truncated value and the first divisor truncated value are in a fourth representation, then the second divisor truncated value is in a first representation; if the first dividend truncated value and the first divisor truncated value are in a fifth representation, then the second divisor truncated value is in a first representation; if the first dividend truncated value and the first divisor truncated value are in a sixth representation, then the second divisor truncated value is in a first representation; if the first dividend truncated value and the first divisor truncated value are in a seventh representation, then the second divisor truncated value is in a second representation; if the first dividend truncated value and the first divisor truncated value are in an eighth representation, then the second divisor truncated value is in a second representation.

[0014] As yet a further aspect of the present specification, the conversion rules include:

[0015] if the first dividend truncated value and the first divisor truncated value are in 000, then the second divisor truncated value is in 100; if the first dividend truncated value and the first divisor truncated value are in 001, then the second divisor truncated value is in 011; if the first dividend truncated value and the first divisor truncated value are in 010, then the second divisor truncated value is in 100; if the first dividend truncated value and the first divisor truncated value are in 011, then the second divisor truncated value is in 100; if the first dividend truncated value and the first divisor truncated value are in 100, then the second divisor truncated value is in 100; if the first dividend truncated value and the first divisor truncated value are in 101, then the second divisor truncated value is in 100; if the first dividend truncated value and the first divisor truncated value are in 110, then the second divisor truncated value is in 011; if the first dividend truncated value and the first divisor truncated value are in 111, then the second divisor truncated value is in 011.

[0016] As yet a further aspect of the present specification, the conversion rules include: if the first dividend truncated value and the first divisor truncated value are 000, then the first dividend tail + the first dividend tail right shifted by 1 bit + the first dividend tail right shifted by 2 bits results in the second dividend tail, the first divisor tail + the first divisor tail right shifted by 1 bit + the first divisor tail right shifted by 2 bits results in the second divisor tail, and the second divisor truncated value is 100; if the first dividend truncated value and the first divisor truncated value are 001, then the first dividend tail + the first dividend tail right shifted by 1 bit + the first dividend tail right shifted by 2 bits results in the second dividend tail, the first divisor tail + the first divisor tail right shifted by 1 bit + the first divisor tail right shifted by 2 bits results in the second divisor tail, and the second divisor truncated value is 011; if the first dividend truncated value and the first divisor truncated value are 010, then the first dividend tail + the first dividend tail right shifted by 1 bit + the first dividend tail right shifted by 3 bits results in the second dividend tail, the first divisor tail + the first divisor tail right shifted by 1 bit + the first divisor tail right shifted by 3 bits results in the second divisor tail, and the second divisor truncated value is 100; if the first dividend truncated value and the first divisor truncated value are 011, then the first dividend tail + the first dividend tail right shifted by 1 bit results in the second dividend tail, the first divisor tail + the first divisor tail right shifted by 1 bit results in the second divisor tail, and the second divisor truncated value is 100; if the first dividend truncated value and the first divisor truncated value are 100, then the first dividend tail + the first dividend tail right shifted by 2 bits + the first dividend tail right shifted by 3 bits results in the second dividend tail, the first divisor tail + the first divisor tail right shifted by 2 bits + the first divisor tail right shifted by 3 bits results in the second divisor tail, and the second divisor truncated value is 100; if the first dividend truncated value and the first divisor truncated value are 101, then the first dividend tail + the first dividend tail right shifted by 2 bits results in the second dividend tail, the first divisor tail + the first divisor tail right shifted by 2 bits results in the second divisor tail, and the second divisor truncated value is 100; if the first dividend truncated value and the first divisor truncated value are 110, then the first dividend tail + the first dividend tail right shifted by 3 bits results in the second dividend tail, the first divisor tail + the first divisor tail right shifted by 3 bits results in the second divisor tail, and the second divisor truncated value is 011; if the first dividend mantissa and the first divisor mantissa are 111, then the second dividend mantissa is obtained by right shifting the first dividend mantissa by 3 bits, and the second divisor mantissa is obtained by right shifting the first divisor mantissa by 3 bits, and the second divisor mantissa is 011.

[0017] As a further aspect of the present specification, the SRT division iterative operation is performed according to the second dividend mantissa, the second divisor mantissa, the second divisor mantissa and the lookup table, and the final quotient value of the original dividend and original divisor further comprises, when the original dividend mantissa is greater than or equal to the original divisor mantissa, two bits are added to the most significant bit of the second dividend mantissa; when the original dividend mantissa is less than the original divisor mantissa, one bit is added to the most significant bit of the second dividend mantissa, and one bit is added to the tail.

[0018] As a further aspect of the present specification, when determining the first quotient value according to the second dividend mantissa of the second dividend mantissa and the second divisor mantissa and the lookup table, when the first quotient value is 1, two bits are added to the most significant bit of the second divisor mantissa; when the first quotient value is not 1, one bit is added to the most significant bit of the second divisor mantissa, and one bit is added to the tail.

[0019] As a further aspect of the present specification, after determining the first quotient value, further comprising, according to the second divisor mantissa, the lookup table, and the truncated value of the partial remainder continuously updated in the SRT division iterative operation according to the second dividend mantissa and the second divisor mantissa, the partial remainder corresponding to all possible quotient values in each SRT division iterative operation is calculated by the 32 compressor at the same time when the quotient value of each SRT division iterative operation is obtained; according to the quotient value obtained in each SRT division iterative operation, the corresponding partial remainder is selected from all possible partial remainders corresponding to the quotient value as the partial remainder in the next SRT division iterative operation.

[0020] The embodiment of the present specification also provides an implementation device of an SRT divider, and the device comprises, a conversion unit configured to convert an original dividend mantissa and an original divisor mantissa to obtain a second dividend mantissa and a second divisor mantissa, and a second divisor mantissa of the second divisor mantissa; wherein the second divisor mantissa has a form less than a first divisor mantissa corresponding to a first divisor mantissa. The SRT division iteration unit is configured to perform an SRT division iteration operation according to the second dividend mantissa, the second divisor mantissa, the second divisor truncation value, and the lookup table to obtain a final quotient value of the original dividend and the original divisor.

[0021] The embodiments of the present specification further provide an arithmetic logic unit (ALU), which comprises the method described above.

[0022] The embodiments of the present specification further provide a computer device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method described above when executing the computer program.

[0023] The embodiments of the present specification further provide a computer readable storage medium, which stores computer instructions, and the computer instructions are executed by a processor to implement the method described above.

[0024] The embodiments of the present specification further provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the method described above.

[0025] By using the embodiments of the present specification, the efficiency of matching the lookup table according to the truncation value of the divisor is improved by converting the dividend and the divisor, so as to improve the efficiency of the SRT division operation. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present specification or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present specification, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0027] Figure 1 Robertson diagram corresponding to all parameters of the embodiments of the present specification is shown; Figure 2 The flowchart of the implementation method of the SRT divider in the embodiments of the present specification is shown; Figure 3 The schematic diagram of converting the original divisor mantissa into the second divisor mantissa according to the conversion rule in the embodiments of the present specification is shown; Figure 4 The flowchart of converting the first divisor into the second divisor according to different conversion rules in the embodiments of the present specification is shown; Figure 5 The flowchart of calculating the first quotient value to obtain the partial remainder in the embodiments of the present specification is shown; Figure 6 Fig. 1 shows a schematic diagram of an SRT division iterative operation structure according to an embodiment of the present specification; Figure 7 Fig. 2 shows a logic block diagram of an SRT divider according to an embodiment of the present specification; Figure 8 Fig. 3 shows a schematic diagram of an SRT divider device according to an embodiment of the present specification; Figure 9 Fig. 4 shows a computer device according to an embodiment of the present specification.

[0028]

BRIEF DESCRIPTION OF DRAWINGS

[0029] 801, conversion unit; 802, execution unit; 902, computer device; 904, processor; 906, memory; 908, drive mechanism; 910, input / output module; 912, input device; 914, output device; 916, presentation device; 918, graphical user interface; 920, network interface; 922, communication link; 924, communication bus. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present specification will be described clearly and completely below in conjunction with the drawings in the embodiments of the present specification. Obviously, the described embodiments are only part of the embodiments of the present specification, not all the embodiments. Based on the embodiments in the present specification, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present specification.

[0031] The definition of SRT division is basically as follows: X=q×d+rem (1) Where x is the dividend, d is the divisor, q is the quotient, rem is the remainder, sign represents the sign of the number, and ULP (unit of last position) represents the precision of the number.

[0032] If ULP=1, the quotient q is an integer; if ULP=r -n , n is the number of bits of the quotient, and r is the base of all input operands, and the quotient q is a decimal number.

[0033] Assume that the desired result value is obtained after k iterations, and the quotient obtained after the jth iteration is q[j] (the result after superimposing the quotient values generated by the jth and previous iterations) (2) where q[j] is a j-digit number in base r, q i is a 1-digit number determined by the quotient selection for each iteration, q i is generated from high to low, and thus the exponent part of r -i here is negative.

[0034] Since the SRT division is similar to the manual division, the quotient is selected by the partial dividend and the divisor, then the partial dividend is subtracted by the product of the quotient and the divisor, and finally the current base is left-shifted by j bits. r is the base of this algorithm, and thus the remainder w is defined as: w[j] = r j (x - d x q[j]) (3) then w[j+1] = r j+1 (x - d x q[j+1]) = r j+1 (x - d x q[j] - d x q j+1 r -(j+1) ) = r x r j (x - d x q[j]) - d x q j+1 = r w[j] - d x q j+1 That is, the iteration equation is w[j+1] = r w[j] - d x q j+1 (4) where the initial value w[0] = x (i.e., the dividend), and w[j] must satisfy - d < w[j] < d (5) In the SRT algorithm, the selection of the quotient bit q j+1 in each iteration is determined by a function containing the shifted remainder r w[j] and the divisor d, which is called the quotient selection function: (6) As can be seen from the above equation, in each iteration, as long as the corresponding quotient bit q j+1 is selected according to the current shifted remainder r w[j] and the divisor d value through equation (6), the next iteration partial remainder w[j+1] can be obtained according to the iteration equation (4). After all iterations, all partial remainders w[j] are obtained, and all quotient bits q j are also obtained.

[0035] For SRT algorithm with radix r, the quotient number set used is called redundant number set, and let a be the largest integer in the number set, then the number set can be expressed as: (7) where a satisfies r / 2≤a

[0036] For a redundant number set, its redundancy is defined as: 1 / 2<ρ=a / (r-1) (8) When a=r / 2, ρ takes the minimum value, which is called minimum redundancy; when a=r-1, ρ takes 1, which is called maximum redundancy.

[0037] The radix r used in SRT4 algorithm is 4, and for radix-4, there are two typical quotient number sets, which are {-2, -1, 0, 1, 2} and {-3, -2, -1, 0, 1, 2, 3}, and the largest numbers in the number sets are a=2 and a=3, respectively. Using a larger a can reduce the delay and complexity of the quotient selection function (i.e. lookup table), but selecting a smaller a can simplify the generation of the multiples of the divisor, i.e. there is no need to generate 3d and -3d operations. After comprehensive consideration, the quotient number set of SRT4 algorithm for floating-point division is selected as {-2, -1, 0, 1, 2}, and the redundancy ρ is 2 / 3, where the redundancy ρ=a / (r-1)=2 / 3 (a represents the largest integer in the quotient number set, and r represents the radix of SRT algorithm).

[0038] Using SRT4 division algorithm, the tail number part of two floating-point numbers is divided, and taking dp (double-precision floating-point number) as an example, the tail number of the dividend, divisor and quotient is 52 bits, plus the implicit bit, which is 53 bits. The specific process is as follows: (1) Set the iteration number to 29, and shift the remainder w[j] obtained by calculation to obtain the shifted remainder rw[j].

[0039] (2) Then, according to the partial remainder rw[j] and the divisor d, the quotient bit q j+1 of this time is selected through the quotient selection function (i.e. lookup table).

[0040] (3) At the same time, the partial remainder w[j+1]=rw[j]-d×q j+1 of the next loop is calculated.

[0041] (4) The operations of (2)-(3) are repeatedly performed until all quotient bits q i are obtained.

[0042] (5) The quotient after k iterations is .

[0043] (6) Finally, based on the weighting relationship of radix-4, convert it into a binary value.

[0044] Finally, the quotient in floating-point format can be obtained by combining the mantissa and exponent parts of the calculated quotient.

[0045] The partial remainder obtained in each iteration must be bounded; this is called the restraint condition. Let the upper and lower boundaries of the partial remainder w[j+1] obtained after the (j+1)th iteration be respectively... and ,Right now (9) For all shifted partial remainders, the following must be satisfied: (10) Meanwhile, substituting equation (4) into equation (10) yields: (11) That is, after j iterations, the remainder rw[j] after shifting must satisfy... (12) Let the selection interval of the shifted remainder rw[j] after the j-th iteration be [L]. q (j),U q (j)], then (13) when Sometimes, (14) like Figure 1 The image shown is a Robertson plot corresponding to all parameters in the embodiments of this specification. It can be seen that: Simplifying, we get: (15) At the same time, equation (14) can be simplified to (16) in, and It is the boundary for all partial remainders.

[0046] For a double-precision floating-point number (dp), the mantissa plus the hidden bits is 53 bits. If the accuracy of the result is not considered, at least 27 iterations are required. Therefore, increasing the number of iterations for looking up the quotient per clock cycle can speed up the division calculation, meaning that multiple 2-bit quotient values ​​can be obtained per clock cycle.

[0047] Generally, the truncation value rw[c] of the remainder is 7 bits, and the truncation value d[c] of the divisor is 3 bits; therefore, the 3 bits of the divisor truncation value d[c] correspond to 8 cases, and the conventional lookup table is shown in Table 1: Table 1. Lookup table corresponding to the SRT4 algorithm.

[0048] Where p2 represents a quotient of +2, p1 represents a quotient of +1, z represents a quotient of 0, n1 represents a quotient of -1, and n2 represents a quotient of -2. The table lookup process is as follows: 1) Determine the column to be searched based on the value of d[c]; 2) Assuming d[c] = 000, then if rw[c] ≥ a1, the quotient is +2; if a2 ≤ rw[c] < a1, the quotient is +1; if a3 ≤ rw[c] < a2, the quotient is 0; if a4 ≤ rw[c] < a3, the quotient is -1; if rw[c] < a4, the quotient is -2.

[0049] like Figure 2 The diagram shows a flowchart of an implementation method for an SRT divider according to an embodiment of this specification. The diagram illustrates how reducing the representation of the divisor truncation value improves the efficiency of matching in the lookup table, thereby accelerating the divider's operation and avoiding the problem of reducing the number of iterations by increasing the base. However, this approach faces the problem of complex divider circuitry and the generation of a large number of redundant number sets, such as [-7,7] with a base of 8. This leads to more comparisons in selecting the quotient digits and requires generating other difficult divisor multiples (e.g., ±5 and ±7), resulting in a more complex product of the divisor and each quotient, and thus higher latency. The specific method includes: Step 201: Using the same conversion rules, convert the original dividend mantissa and the original divisor mantissa to obtain the second dividend mantissa and the second divisor mantissa, and the second divisor truncation value of the second divisor mantissa; wherein, the representation of the second divisor truncation value is less than the representation of the first divisor truncation value corresponding to the first divisor mantissa.

[0050] Step 202: Based on the mantissa of the second dividend, the mantissa of the second divisor, the truncation value of the second divisor, and the lookup table, perform the SRT division iterative operation to obtain the final quotient of the original dividend and the original divisor.

[0051] The method described in this specification can improve the efficiency of SRT division in matching the lookup table, thereby improving the algorithm efficiency. Furthermore, the circuit composition of the divider is relatively simple, and the redundant number set is small.

[0052] In the embodiments of this specification, the same conversion rules are used to further convert the mantissa of the original dividend and the mantissa of the original divisor, including: The original dividend mantissa and the original divisor mantissa are amplified to obtain the first dividend mantissa and the first divisor mantissa.

[0053] In this embodiment, the division of the double-precision floating-point number is taken as an example. Only the mantissa actually participates in the algorithm calculation, and the exponent part only needs to use subtraction, which is similar to 1.1x2 5 / 1.1x2 2 = 2 3 . Wherein, opa[52:0] represents the original dividend mantissa (including a total of 53 bit hidden bits), and opb[52:0] represents the original divisor mantissa (including a total of 53 bit hidden bits). The dividend and the divisor are amplified for subsequent right shift when the original dividend mantissa and the original divisor mantissa are converted.

[0054] For example, in this embodiment, one 0 is added before the highest bit of opa[52:0], and three 0s are added at the tail to obtain the first dividend mantissa opa_new[56:0] with 57 bit after expansion. One 0 is added before the highest bit of opb[52:0], and three 0s are added at the tail to obtain the first divisor mantissa opb_new[56:0] with 57 bit after expansion.

[0055] In the embodiments of the present application, the same conversion rule is adopted to convert the original dividend mantissa and the original divisor mantissa to obtain the second dividend mantissa and the second divisor mantissa, which further comprises, According to the first divisor truncation value corresponding to the first divisor mantissa, the first dividend mantissa is converted based on the conversion rule to obtain the second dividend mantissa; wherein the second dividend mantissa comprises a second dividend truncation value; According to the first divisor truncation value corresponding to the first divisor mantissa, the first divisor mantissa is converted based on the conversion rule to obtain the second divisor mantissa; wherein the second divisor mantissa comprises a second divisor truncation value.

[0056] In this embodiment, the same conversion rule refers to determining the second dividend mantissa corresponding to the first dividend mantissa according to the first divisor truncation value corresponding to the first divisor mantissa; and determining the second divisor mantissa corresponding to the first divisor mantissa according to the first divisor truncation value corresponding to the first divisor mantissa. Only through the same conversion rule can the conversion results of the first dividend and the first divisor still conform to the division relationship of the original dividend and the original divisor.

[0057] In the embodiments of the present application, the same conversion rule is adopted to convert the original dividend mantissa and the original divisor mantissa to obtain the second dividend mantissa and the second divisor mantissa, which further comprises, The first dividend tail number and the first divisor tail number with the same first dividend truncated value and the first divisor truncated value adopt the same conversion rule.

[0058] In the embodiment, by adopting the same conversion rule for the first dividend tail number and the first divisor tail number with the same first dividend truncated value and the first divisor truncated value, the conversion result of the first dividend and the first divisor is still consistent with the division relationship of the original dividend and the original divisor.

[0059] For example, for the case that the first dividend truncated value and the first divisor truncated value are both 001, taking the first divisor truncated value as an example, the original divisor tail number is opb[52:0]=1001…, the first 4 bits of the original divisor are 1001, including 1 bit of the integer part as "1" and 3 bits of the decimal part as "001", and the truncated value is the high 3 bits of the decimal part "001"; the first divisor tail number opb_new[56:0] obtained by amplifying the original divisor tail number is 01001…000, in which 3 bits of "0" are added to the tail of the original divisor tail number and 1 bit of "0" is added to the front, the first divisor truncated value is 001, and the conversion rule corresponding to the first divisor truncated value is opb_new+opb_new / 2+opb_new / 4, in which opb_new / 2 is equivalent to shifting the first divisor tail number opb_new[56:0] to the right by 1 bit, opb_new / 4 is equivalent to shifting the first divisor tail number opb_new[56:0] to the right by 2 bits, and opb_new / 8 is equivalent to shifting the first divisor tail number opb_new[56:0] to the right by 3 bits. The conversion rule opb+opb / 2+opb / 4 for the first divisor truncated value 001 is as follows: 01001…000+001001…00+0001001…0=01111111…0; At this point, the first divisor tail number 01001…000 is converted into the second divisor tail number 011…, and the first divisor truncated value 001 is converted into the second divisor truncated value 011.

[0060] The same operation is performed on the first dividend tail number with the first dividend truncated value 001 to obtain the second dividend tail number and the second dividend truncated value.

[0061] For different divisor truncated values, there are corresponding conversion rules, and the same conversion rule is performed on the dividend and the divisor with the same truncated value to obtain the converted dividend and divisor, and the corresponding dividend truncated value and divisor truncated value.

[0062] The first and second divisor truncated values refer to the truncation of the integer part of the divisor, which in some embodiments can be truncated by 3 bits, such as [56:54] of opb_new in the second divisor mantissa. The 4 / 3 obtained above indicates that the integer bit only needs 1 bit, because 4 / 3 is the maximum value of the partial remainder. According to the iterative equation: w[j+1]=rw[j]-d×q j+1 ; where r represents the base, d represents the divisor, q represents the quotient, w[j] represents the remainder of the last iteration, rw[j] is referred to as the partial remainder, and w[j+1] represents the remainder of the current iteration. In the SRT division operation, the first quotient value is first obtained, the first quotient value is multiplied by the divisor, and then the first remainder is obtained; then the remainder is divided by the divisor to obtain the second quotient, the second quotient value is multiplied by the divisor, and then the second remainder is obtained, and so on.

[0063] In the embodiments of the present specification, the conversion rule comprises: The first dividend mantissa and the first divisor mantissa with the same first divisor truncated value are multiplied by the same multiple.

[0064] In the present embodiment, according to the conversion rule described above, opb_new+opb_new / 2+opb_new / 4 is equivalent to multiplying the first divisor mantissa by 1.75, and at the same time, the same operation is performed on the first dividend mantissa with the same first divisor truncated value as the first divisor mantissa, that is, multiplying by 1.75, which can ensure that the dividend and the divisor are enlarged by the same multiple, and the conversion rule corresponding to other forms of the first divisor truncated value also has a similar operation, that is, multiplying by the corresponding multiple, and the form of the second divisor truncated value obtained after the operation is less than the form of the first divisor truncated value. Of course, the form of the first dividend truncated value is also less than the form of the first dividend truncated value.

[0065] In the embodiments of the present specification, the form of the second divisor truncated value is less than the form of the first divisor truncated value corresponding to the first divisor mantissa further comprises, The number of columns corresponding to the form of the second divisor truncated value in the lookup table is less than the number of columns corresponding to the form of the first divisor truncated value in the lookup table.

[0066] As Figure 3The figure shows the conversion of the original divisor mantissa to the second divisor mantissa according to the conversion rule in the embodiment of the present specification. In the description of the figure, the conversion of the first divisor mantissa and the first divisor mantissa obtained by putting the original dividend mantissa and the original divisor mantissa behind is applicable. In this example, only the conversion of the divisor mantissa is used as an illustration. Through the conversion rule in the embodiment, the first divisor mantissa can be converted to obtain the second divisor mantissa, which has fewer forms than the first divisor mantissa. For simplicity, only the first four bits of the original divisor mantissa are displayed, and the first three bits of the second divisor mantissa are displayed. For the sake of simplicity, the other bits can all be 0. As shown in the figure, opb / 2, opb / 4, and opb / 8 can be obtained by right shifting opb by 1 bit, 2 bits, and 3 bits, respectively, and the formula (16) The selection range of the partial remainder rw[j] after the shift is [L q (j), U q (j)], so the maximum value of the partial remainder rw is equal to d× (q+ρ). After substituting the related parameters, the maximum value of the divisor d is equal to 1 / 2, the maximum value of the quotient q is equal to 2, and the redundancy p is equal to 2 / 3. It can be known that rw≤d× (q+ρ)=(1 / 2)× (2+2 / 3)=4 / 3, so the second divisor truncated value d[c] has only two forms of 100 or 011. When matching in the lookup table, the matching efficiency can be obviously improved. In other embodiments, the second divisor mantissa may cause a carry during the conversion process, so that the forms of the first few bits of the truncated value are different from those in the embodiment, but it does not affect the number of forms of all the second divisor mantissa truncated values.

[0067] For example, the original divisor mantissa opb[52:0] is enlarged to the first divisor mantissa opb_new[56:0] 01000…000 according to the truncated value 000 of the original divisor opb[51:49] of the original divisor mantissa opb[52:0] 1000…, and the first divisor mantissa opb_new[56:0] is converted to the second divisor mantissa 100… according to the conversion rule opb_new+opb_new / 2+opb_new / 4. Figure 3

[0068] For example, the original divisor mantissa opb[52:0] is enlarged to the first divisor mantissa opb_new[56:0] 01000…000 according to the truncated value 000 of the original divisor opb[51:49] of the original divisor mantissa opb[52:0] 1000…, and the first divisor mantissa opb_new[56:0] is converted to the second divisor mantissa 100… according to the conversion rule opb_new+opb_new / 2+opb_new / 4. Figure 4 For example, the original divisor mantissa opb[52:0] is enlarged to the first divisor mantissa opb_new[56:0] 01000…000 according to the truncated value 000 of the original divisor opb[51:49] of the original divisor mantissa opb[52:0] 1000…, and the first divisor mantissa opb_new[56:0] is converted to the second divisor mantissa 100… according to the conversion rule opb_new+opb_new / 2+opb_new / 4. ​When the original divisor truncated value is 010, according to the corresponding conversion rule opb_new+opb_new / 2+opb_new / 8, the converted second divisor truncated value is 100; When the original divisor truncated value is 011, according to the corresponding conversion rule opb_new+opb_new / 2, the converted second divisor truncated value is 100; When the original divisor truncated value is 100, according to the corresponding conversion rule opb_new+opb_new / 4+opb_new / 8, the converted second divisor truncated value is 100; When the original divisor truncated value is 101, according to the corresponding conversion rule opb_new+opb_new / 4, the converted second divisor truncated value is 100; When the original divisor truncated value is 110, according to the corresponding conversion rule opb_new+opb_new / 8, the converted second divisor truncated value is 011; When the original divisor truncated value is 111, according to the corresponding conversion rule opb_new+opb_new / 8, the converted second divisor truncated value is 011; Therefore, the second divisor truncated value has only two forms 100 and 011, and in the case of quotient, the original dividend mantissa and the original divisor mantissa are enlarged and converted, and the truncated value of the original divisor mantissa has eight forms 000 to 111 (as shown in Table 1) before conversion, and after conversion according to the conversion rule of the above embodiment of the present specification, the second divisor truncated value has only two forms 011 and 100 (as shown in Table 2).

[0069] Table 2

[0070] In other embodiments, other similar conversion rules can also be generated according to the idea of the embodiments of the present specification, and the ultimate goal is to reduce the forms of the first divisor truncated value to form the second divisor truncated value, and to reduce the matching in the lookup table by using the characteristic of fewer forms of the second divisor truncated value, thereby improving the efficiency of the SRT division operation. For example, a new lookup table can also be generated according to the second divisor truncated value in the embodiments of the present specification, or a direct mapping method can be used to map the original divisor truncated value or the first divisor truncated value to the corresponding second divisor truncated value, thereby reducing the forms of the divisor truncated value.

[0071] Due to the reduction of the forms of the second divisor truncated value, the efficiency of matching in the lookup table to obtain the quotient will be improved. For example, in the above embodiment, the matching efficiency in the lookup table can be improved by 4 times.

[0072] In the embodiments of the present application, the SRT division iteration operation is performed according to the second dividend mantissa, the second divisor mantissa, the second divisor truncation value and the lookup table to obtain the final quotient value of the original dividend and original divisor further comprises, When the original dividend mantissa is greater than or equal to the original divisor mantissa, two bits are added in the highest bit of the second dividend mantissa; When the original dividend mantissa is less than the original divisor mantissa, one bit is added in the highest bit of the second dividend mantissa and one bit is added in the tail.

[0073] In the embodiments of the present application, as shown in Figure 5 The flowchart of calculating the first quotient value to obtain the partial remainder in the embodiments of the present application is shown in the figure. After the original dividend mantissa and the original divisor mantissa are amplified and converted according to the conversion rule, the second dividend mantissa and the second divisor mantissa are further amplified according to the comparison result of the original dividend mantissa and the original divisor mantissa, and the partial remainder is expressed in the form of initial carry (carry_init) and initial sum (sum_init).

[0074] When the original dividend mantissa (opa) is greater than or equal to the original divisor mantissa (opb), two "0"s are added in front of the second dividend mantissa (opa_new[56:0]) to fill 59 bits.

[0075] When the original dividend mantissa (opa) is less than the original divisor mantissa (opb), the second dividend mantissa (opa_new[56:0]) needs to be left shifted by one bit, which is expressed as one "0" added in front and one "0" added in the tail to fill 59 bits.

[0076] The "0"s are added in front of opa_new, and the corresponding iteration equation at this time is w[1]=w[0]-d×q(1), wherein w[0] is carry_init and d×q(1) is sum_init.

[0077] The second divisor truncated value converted according to the conversion rule is also required to be matched in the lookup table to obtain a first quotient value, wherein if the original dividend mantissa (opa) is less than the original divisor mantissa (opb), the second dividend mantissa is left shifted by 1 bit, and then it is judged whether the first quotient value is 1, and if the original dividend mantissa (opa) is greater than or equal to the original divisor mantissa (opb), it is directly judged whether the first quotient value is 1. If the first quotient value is 1 (i.e. first_quot = 1 in the figure), 2 '0's are added in front of the second divisor mantissa opb_new[56:0] to make up 59 bits, which means w[1] = w[0] - d at this time, and d at this time is the initial significant sum (sum_init); if the first quotient value is not 1 (i.e. first_quot ≠ 1 in the figure), 1 '0' is added in front of and behind the second divisor mantissa opb_new[56:0], and if the first quotient value is not 1, it means that the first quotient value is 2, and at this time, opb_new[56:0] needs to be left shifted by 1 bit, i.e. w[1] = w[0] - 2xd, and 2xd at this time is the initial significant sum sum_init.

[0078] At this time, the first quotient value can be used to calculate the initial carry (carry_init) and the initial significant sum sum_init, which are used to represent the first part of the remainder w[1] = carry_init - sum_init in the subsequent SRT division iteration operation. Of course, the partial remainder in the SRT division iteration operation can be represented by the carry (carry) and the significant sum (sum).

[0079] In the embodiment of the present specification, after determining the first quotient value, further comprising, According to the second divisor truncated value, the lookup table, and the truncated value of the partial remainder which is constantly updated according to the second dividend mantissa and the second divisor mantissa in the SRT division iteration operation, the 32 compressor is used to simultaneously calculate the partial remainder corresponding to all possible quotient values in each SRT division iteration operation; According to the quotient value obtained in each SRT division iteration operation, the corresponding partial remainder is selected from all possible partial remainders corresponding to the quotient value as the partial remainder in the next SRT division iteration operation.

[0080] In the embodiment, after the first quotient value is calculated, the first quotient value can be calculated by using the method as shown in the following figure: Figure 6The SRT division iterative operation structure shown in the embodiment of the present specification is used to calculate the quotient value generated in each iteration, and obtain the final quotient value after the iteration. By distinguishing the calculation method of the first quotient value from the calculation method of the subsequent iterations, and using different calculation methods, the steps of matching to obtain the quotient value (q j+1 ) in the lookup table in the subsequent iteration process except for the first quotient value, and the steps of pre-calculating the carry and sum expression forms of all possible partial remainders (w[j+1]) in the current iteration process through the 32 compressor, the quotient value determined in the current iteration process through the lookup table is selected from the carry and sum expression forms of all possible partial remainders obtained through the 32 compressor, that is, by separating the calculation of the first quotient value from the subsequent SRT division iterative operation, the partial remainder of the current iteration can be obtained at one time in each iteration, which conforms to the iteration equation w[j+1]= rw[j]-d×q j+1 , where r represents the base, d represents the divisor, q j+1 represents the quotient value of the current iteration, and w[j] represents the partial remainder of the last iteration.

[0081] As Figure 6 shown, after scaling and converting the original dividend mantissa and the original divisor mantissa, and after the calculation of the first quotient value, the first partial remainder in the form of carry_init[58:0] and sum_init[58:0] is obtained, and the second divisor mantissa opb_new[56:0] of 57 bits is obtained, where the first partial remainder w[1]=carry_init-sum_init; according to the representation of the first partial remainder carry_init-sum_init obtained after the calculation of the first quotient value, and the representation of the second partial remainder w[2]=4w[1]-d×q(2) in the iteration equation, the truncated value of the first partial remainder w[1] and the truncated value of the second divisor mantissa d (after the conversion in the foregoing embodiment, there are only two forms of the truncated value of the second divisor mantissa) can be matched in the lookup table on the left side as Figure 6 shown, and the second quotient value can be obtained with higher efficiency. In other embodiments, according to different conversion rules (for example, other mapping conversion rules), the number of forms of the truncated value of the second divisor mantissa can have other possibilities, and is not limited to two forms. While obtaining the second quotient value by matching the truncated value of the first partial remainder w[1] and the truncated value of the second divisor mantissa through the lookup table, the second quotient value can be obtained according to the second quotient value q[2]=4w[1]-d×q(2) as Figure 6The right 32 compressors shown according to the first part of the remainder in the form of carry_init and sum_init and the second remainder truncation value, can obtain the expression form of the carry and sum of the second part of the remainder w[2]d of the second possible 5 different second quotient values, corresponding to w[2]=4w[1]-d×q(2), so that the quotient value in this iteration can be obtained in the lookup table matching, and the calculation of the partial remainder in the form of 5 expressions corresponding to the quotient value can be carried out, thereby improving the efficiency of the SRT division iteration operation. In the subsequent SRT division iteration process, the above iteration logic is continuously adopted, and the quotient value and the partial remainder in the form of multiple expressions (the partial remainder expressed by carry and sum) in this iteration can be obtained at one time. According to the quotient value obtained from the lookup table, the partial remainder expression form corresponding to the quotient value (i.e. the correct carry and sum in this iteration) is selected from the partial remainder in multiple expression forms, and the carry and sum expression form of the corresponding truncated value (i.e. rem_c_p2[6:0] and the like) is obtained according to the selected partial remainder, which is brought into the next SRT division iteration operation to obtain the quotient value in the next iteration process, until the iteration ends, and the quotient values q(2)…q(n) output in the iteration are obtained, and then q(1) obtained in the calculation process of the first quotient value is combined to obtain the final 2-bit quotient value, and then according to the weight relationship of the radix 4, the final quotient value q is obtained based on the weight accumulation calculation, q=q(1)×4 0 +q(2)×4 (-1) +q(3)×4 (-2) +…+q(n)×4 (-n+1) .

[0082] As Figure 7 shown in the logic block diagram of the SRT divider of the embodiment of the present specification, the first quotient value calculation and the subsequent iteration process are separated in the diagram, the parallel processing capability of the SRT divider is increased, and the processing efficiency of the SRT divider is improved. After the original dividend mantissa and the original divisor mantissa are converted, the first quotient value of the second dividend and the second divisor is obtained through the lookup table, and the first partial remainder is obtained through calculation.

[0083] The first partial remainder and the second divisor mantissa are input to the 32 compressor, and a series of quotient values are obtained after multiple iterations of the multiplexer. When matching in the lookup table, the truncated values of carry and sum, and the truncated value of the second divisor opb_new are needed. When looking up the quotient values according to the lookup table, the partial remainders and the truncated values of the partial remainders (for example, five kinds of {-2, -1, 0, 1, 2}) corresponding to different quotient values in the current iteration process are calculated synchronously by the 32 compressor, and then the corresponding partial remainder and the truncated value of the partial remainder are selected according to the real quotient value looked up, and the whole sequence of quotient values is obtained in this way. Finally, the final quotient value is obtained after the iteration ends.

[0084] As shown in Figure 8 The structure of the SRT divider device is shown in the figure, and the structure of the device for implementing the above method is described. The functions of the units and modules in the device can be realized by basic gate circuits or other digital circuits, or can also be realized by logic circuits in the compiler, thereby improving the code parallel efficiency. The device specifically includes: The conversion unit 801 is configured to convert the original dividend mantissa and the original divisor mantissa to obtain the second dividend mantissa and the second divisor mantissa by using the same conversion rule, and the second divisor mantissa has a second divisor truncated value; wherein the second divisor truncated value has a form less than that of the first divisor truncated value corresponding to the first divisor mantissa. The execution unit 802 is configured to perform SRT division iteration operation according to the second dividend mantissa, the second divisor mantissa, the second divisor truncated value, and the lookup table, to obtain the final quotient value of the original dividend and the original divisor.

[0085] Through the device of the above embodiment of the present specification, the efficiency of the SRT division operation in the lookup table matching can be improved, thereby improving the algorithm efficiency, and the circuit composition of the divider is relatively simple, and the redundant digital set is small.

[0086] The embodiment of the present specification also provides an arithmetic logic unit (ALU) which adopts the above-mentioned logical structure and performs the above-mentioned method.

[0087] As shown in Figure 9A computer device is shown that can host an SRT divider of embodiments of the present specification. The above-described methods can also be run on a computer device of embodiments of the present specification to perform the above-described methods of the present specification. The computer device 902 can include one or more processors 904, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. The computer device 902 can also include any memory 906 for storing any kind of information, such as code, settings, data, etc. Without limitation, for example, the memory 906 can include any one or combination of the following: any type of RAM, any type of ROM, a flash memory device, a hard disk, an optical disk, etc. More generally, any memory can use any technology for storing information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory can represent a fixed or removable component of the computer device 902. In one case, the computer device 902 can perform any operation of the associated instructions when executed by the processor 904, which are stored in any memory or combination of memories. The computer device 902 also includes one or more drive mechanisms 908, such as a hard disk drive mechanism, an optical disk drive mechanism, etc., for interacting with any memory.

[0088] The computer device 902 can also include an input / output module 910 (I / O) for receiving various inputs (via input devices 912) and for providing various outputs (via output devices 914). One particular output mechanism can include a presentation device 916 and an associated graphical user interface (GUI) 918. In other embodiments, the input / output module 910 (I / O), input devices 912, and output devices 914 can not be included, and the computer device 902 can simply be a computer device in a network. The computer device 902 can also include one or more network interfaces 920 for exchanging data with other devices via one or more communication links 922. One or more communication buses 924 couple the above-described components together.

[0089] The communication links 922 can be implemented in any manner, such as through a local area network, a wide area network (e.g., the Internet), a point-to-point connection, etc., or any combination thereof. The communication links 922 can include any combination of hardwired links, wireless links, routers, gateway functionality, name servers, etc., governed by any protocol or combination of protocols.

[0090] Embodiments of the present specification also provide a computer readable medium having stored thereon computer readable instructions, wherein the program of instructions, when executed by a processor, causes the processor to perform the above-described methods.

[0091] It should be understood that the size of the sequence number of each process described above in various embodiments of the present specification does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present specification.

[0092] It should also be understood that in the embodiments of the present specification, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships. For example, A and / or B can represent three cases of A alone, A and B together, and B alone. In addition, the character " / " in the present specification generally represents that the front and rear associated objects are in an "or" relationship.

[0093] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present specification can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present specification.

[0094] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0095] In several embodiments provided in the present specification, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division, and actual implementation can have another division manner. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displays or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can also be electrical, mechanical or other forms of connection.

[0096] The units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiments of the present specification.

[0097] In addition, each function unit in each embodiment of the present specification can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function unit.

[0098] When the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present specification or the entire or part of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present specification. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0099] The principles and implementation manners of the present specification are described by using specific embodiments in the present specification. The above embodiment description is only used to help understand the method of the present specification and its core idea; meanwhile, for those skilled in the art, according to the idea of the present specification, the specific implementation manner and application range will have changes; in summary, the content of the present specification should not be understood as a limitation of the present specification.

Claims

1. A method for implementing an SRT divider, characterized in that... include, Using the same conversion rules, the original dividend mantissa and the original divisor mantissa are converted to obtain the second dividend mantissa and the second divisor mantissa, and the second divisor truncation value of the second divisor mantissa; wherein, the representation of the second divisor truncation value is less than the representation of the original divisor truncation value corresponding to the original divisor mantissa. Based on the mantissa of the second dividend, the mantissa of the second divisor, the truncation value of the second divisor, and the lookup table, perform the SRT division iterative operation to obtain the final quotient of the original dividend and the original divisor.

2. The method according to claim 1, characterized in that, Using the same conversion rules, the conversion of the mantissa of the original dividend and the mantissa of the original divisor further includes: The mantissas of the original dividend and the original divisor are amplified to obtain the mantissas of the first dividend and the first divisor.

3. The method according to claim 2, characterized in that, Further amplification of the mantissas of the original dividend and divisor includes, Add one bit before the most significant bit of the original dividend mantissa and the original divisor mantissa, and add at least three bits to the end of the original dividend mantissa and the original divisor mantissa to obtain the first dividend mantissa and the first divisor mantissa.

4. The method according to claim 2, characterized in that, Using the same conversion rules, the mantissas of the original dividend and the original divisor are converted to obtain the mantissa of the second dividend. The mantissa of the second divisor further includes... Based on the first truncation value corresponding to the first divisor mantissa, the first dividend mantissa is converted according to the conversion rule to obtain the second dividend mantissa; wherein, the second dividend mantissa includes the second dividend truncation value; Based on the first divisor truncation value corresponding to the first divisor mantissa, the first divisor mantissa is converted according to the conversion rule to obtain the second divisor mantissa; wherein, the second divisor mantissa includes the second divisor truncation value.

5. The method according to claim 4, characterized in that, Using the same conversion rules, the mantissas of the original dividend and the original divisor are converted to obtain the mantissa of the second dividend. The mantissa of the second divisor further includes... The same conversion rule is applied to the mantissa of the first dividend and the mantissa of the first divisor, which are the same as the truncation value of the first dividend.

6. The method according to claim 5, characterized in that, The conversion rules include: The first dividend truncation value is the same as the first divisor truncation value. The first dividend truncation value and the first divisor truncation value are multiplied by the same multiple.

7. The method according to claim 5, characterized in that, The representation of the second divisor truncation value is less than the representation of the first divisor truncation value corresponding to the mantissa of the first divisor, further including: The number of columns corresponding to the representation of the second divisor truncation value in the lookup table is less than the number of columns corresponding to the representation of the first divisor truncation value in the lookup table.

8. The method according to claim 6, characterized in that, The conversion rules include: If the first truncated value of the dividend and the first truncated value of the divisor are in the first representation, then the second truncated value of the divisor is in the first representation. If the first truncated value of the dividend and the first truncated value of the divisor are in the second representation, then the second truncated value of the divisor is in the second representation. If the first truncated value of the dividend and the first truncated value of the divisor are in a third representation, then the second truncated value of the divisor is in a first representation. If the first truncated value of the dividend and the first truncated value of the divisor are in the fourth representation, then the second truncated value of the divisor is in the first representation. If the first truncated value of the dividend and the first truncated value of the divisor are in the fifth representation, then the second truncated value of the divisor is in the first representation. If the first truncated value of the dividend and the first truncated value of the divisor are in the sixth representation, then the second truncated value of the divisor is in the first representation. If the first truncated value of the dividend and the first truncated value of the divisor are in the seventh representation, then the second truncated value of the divisor is in the second representation. If the first truncated value of the dividend and the first truncated value of the divisor are in the eighth representation, then the second truncated value of the divisor is in the second representation.

9. The method according to claim 8, characterized in that, The conversion rules include: If the first dividend truncation value and the first divisor truncation value are both 000, then the second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are both 001, then the second divisor truncation value is 011. If the first dividend truncation value and the first divisor truncation value are both 010, then the second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are both 011, then the second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are both 100, then the second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are both 101, then the second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are both 110, then the second divisor truncation value is 011. If the first dividend truncation value and the first divisor truncation value are both 111, then the second divisor truncation value is 011.

10. The method according to claim 8, characterized in that, The conversion rules include: If the first dividend truncation value and the first divisor truncation value are both 000, then the second dividend truncation value is obtained by adding the first dividend truncation value to the first dividend truncation value, and the second divisor truncation value is obtained by adding the first divisor truncation value to the first divisor truncation value. The second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are both 001, then the second dividend truncation value is obtained by right-shifting the first dividend truncation value by 1 bit and right-shifting the first dividend truncation value by 2 bits, and the second divisor truncation value is obtained by right-shifting the first divisor truncation value by 1 bit and right-shifting the first divisor truncation value by 2 bits. The second divisor truncation value is 011. If the first dividend truncation value and the first divisor truncation value are 010, then the second dividend truncation value is obtained by right-shifting the first dividend truncation value by 1 bit and right-shifting the first dividend truncation value by 3 bits, and the second divisor truncation value is obtained by right-shifting the first divisor truncation value by 1 bit and right-shifting the first divisor truncation value by 3 bits. The second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are 011, then the first dividend mantissa plus the first dividend mantissa is shifted right by 1 bit to obtain the second dividend mantissa, and the first divisor mantissa plus the first divisor mantissa is shifted right by 1 bit to obtain the second divisor mantissa, and the second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are both 100, then the second dividend truncation value is obtained by right-shifting the first dividend truncation value by 2 bits and the first dividend truncation value by 3 bits. The second divisor truncation value is obtained by right-shifting the first divisor truncation value by 2 bits and the first divisor truncation value by 3 bits. The second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are both 101, then the first dividend mantissa plus the first dividend mantissa is right-shifted by 2 bits to obtain the second dividend mantissa, and the first divisor mantissa plus the first divisor mantissa is right-shifted by 2 bits to obtain the second divisor mantissa. The second divisor truncation value is 100. If the first dividend truncation value and the first divisor truncation value are 110, then the first dividend mantissa plus the first dividend mantissa is right-shifted by 3 bits to obtain the second dividend mantissa, and the first divisor mantissa plus the first divisor mantissa is right-shifted by 3 bits to obtain the second divisor mantissa. The second divisor truncation value is 011. If the first dividend truncation value and the first divisor truncation value are 111, then the first dividend mantissa plus the first dividend mantissa is right-shifted by 3 bits to obtain the second dividend mantissa, and the first divisor mantissa plus the first divisor mantissa is right-shifted by 3 bits to obtain the second divisor mantissa. The second divisor truncation value is 011.

11. The method according to claim 1, characterized in that, Based on the mantissa of the second dividend, the mantissa of the second divisor, the truncation value of the second divisor, and the lookup table, an SRT division iterative operation is performed to obtain the final quotient of the original dividend and the original divisor, which further includes... If the mantissa of the original dividend is greater than or equal to the mantissa of the original divisor, then two bits are added to the highest bit of the mantissa of the second dividend. If the mantissa of the original dividend is less than the mantissa of the original divisor, then add a bit to the highest bit of the mantissa of the second dividend and add a bit to the end.

12. The method according to claim 11, characterized in that, When determining the first quotient based on the second dividend truncation value, the second divisor truncation value, and the lookup table, When the first quotient is 1, two bits are added before the highest bit of the second divisor. If the first quotient is not 1, then add a bit before the highest bit of the second divisor and add a bit at the end.

13. The method according to claim 12, characterized in that, After determining the first quotient, further steps are included, Based on the second divisor truncation value, the lookup table, and the truncation value of the partial remainders that are continuously updated in the SRT division iteration operation based on the second dividend mantissa and the second divisor mantissa, when obtaining the quotient value of each SRT division iteration operation, the 32 compressor simultaneously calculates the partial remainders corresponding to all possible quotient values ​​in each SRT division iteration operation. Based on the quotient value obtained in each SRT division iteration, select the corresponding partial remainder from all possible partial remainders corresponding to the quotient value, and use it as the partial remainder in the next SRT division iteration.

14. An apparatus for implementing an SRT divider, characterized in that, The device includes, The conversion unit is configured to convert the original dividend mantissa and the original divisor mantissa to obtain a second dividend mantissa and a second divisor mantissa, and a second divisor truncation value of the second divisor mantissa; wherein the representation of the second divisor truncation value is less than the representation of the original divisor truncation value corresponding to the original divisor mantissa. The SRT division iteration unit is configured to perform SRT division iteration operations based on the mantissa of the second dividend, the mantissa of the second divisor, the truncation value of the second divisor, and a lookup table to obtain the final quotient of the original dividend and the original divisor.

15. An arithmetic logic unit, characterized in that... The arithmetic logic unit performs the method as described in any one of claims 1-13.

16. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1-13.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the method of any one of claims 1-13.

18. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-13.

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