Two-stage cache algorithm based on dynamic memory management and application thereof
By using a two-level caching algorithm with dynamic memory management, the problems of algorithm complexity and memory limitations in embedded systems are solved, enabling complex algorithms to run in real time and execute efficiently in resource-constrained environments.
Patent Information
- Application Number
- CN202511717101.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-21
- Publication Date
- 2026-02-13
AI Technical Summary
Hardware resource limitations in embedded systems prevent complex algorithms from running. Traditional methods, such as increasing algorithm complexity or pre-compiling tables, cannot simultaneously solve the dual constraints of computation time and storage space.
A two-level caching algorithm based on dynamic memory management is adopted. Through a priority-driven task scheduling mechanism and circular buffer management, the order of data loading and release is dynamically adjusted. The high-complexity signal processing algorithm and pre-computation table are split into two levels to handle coarse-grained and local fine-grained features respectively. The LRU algorithm and hardware acceleration unit DMA manage memory blocks to ensure the real-time performance and efficiency of critical tasks.
It significantly reduces algorithm time complexity and memory usage, improves system real-time performance and stability, enables complex algorithms to run in real time in embedded systems, and meets the resource utilization requirements under multi-task parallelism.
Smart Images
Figure CN121523908A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a two-level cache algorithm based on dynamic memory management and application thereof. BACKGROUND
[0002] In embedded systems, the limitation of hardware resources (such as MCU computing power, memory capacity) often leads to the inability of complex algorithms to run. Traditional solutions reduce memory usage by increasing algorithm complexity, trading time for space; or reduce runtime algorithm complexity by increasing pre-computed number tables (hash tables, arrays, etc.), trading space for time, but face the following problems:
[0003] 1. Computing power bottleneck: the time complexity of complex algorithms is high (such as O(n²)), and the operation cannot be completed within a limited processing period;
[0004] 2. Memory bottleneck: the storage requirement of pre-computed number tables far exceeds the memory capacity of embedded systems (such as tens of KB).
[0005] For example, in underwater acoustic detection, when generating a pulse compression waveform signal with a frequency of 40 kHz and a sampling rate of 1 MHz, the traditional method of generating a matched filter operation usually involves N x N convolution operation, with a time complexity of O(N 2 ). If N = 1024, 10 6 operations are required. Generally, a single operation takes 10 —7 seconds, so the total time is 100 ms, which is far beyond the real-time requirement of the system (generally 5 ms to 10 ms); if a pre-computed number table is used to implement the matched filter, taking a complex sequence of 8192 points for the transmitted waveform (each complex number occupies 8 bytes), a single number table needs to store 8192 x 8 = 64 KB bytes. It is close to the upper limit of the SRAM of the embedded MCU. And the parallel processing of multiple signals in actual working conditions generally needs to be expanded to 16 groups of parameters, which requires 16 x 64 KB = 1024 KB = 1 MB, far exceeding the memory capacity of embedded systems, resulting in the inability of the algorithm to run. Therefore, the existing technology still does not solve the problem of dual constraints of operation time and storage space. SUMMARY
[0006] To solve the above technical problems, the present application provides a two-level cache algorithm based on dynamic memory management and application thereof.
[0007] The technical solution of the present application to solve the above technical problems is: a two-level cache algorithm based on dynamic memory management, comprising the following steps:
[0008] S1: Establish a dynamic memory management architecture based on a ring buffer, dynamically adjust the data loading and release sequence of the two-level buffer area through a priority-driven task scheduling mechanism;
[0009] S2: Split the high-complexity signal processing algorithm into two levels, the first-level algorithm is used to process the coarse-grained features of the input signal, and the time complexity is O(N1 2 ); the second-level algorithm performs local fine calculation based on the processing result of the first-level algorithm, and the time complexity is O(N2 2 ); the total time complexity is O(N1 2 )+O(N2 2 ), wherein ;
[0010] S3: Split the pre-computed number table into two levels, the first-level number table is used to store low-resolution parameters corresponding to coarse-grained features, and the space complexity is O(N1); the second-level number table is used to store high-precision parameters corresponding to local fine features, and the space complexity is O(N2); the total storage requirement is O(N1+N2), and .
[0011] The above two-level cache algorithm based on dynamic memory management, in step S1, the real-time data stream is managed by a ring queue, and the LRU algorithm is used to realize the dynamic allocation and recovery of memory blocks of the two-level cache, to ensure that high-priority tasks obtain continuous memory space, and a hardware acceleration unit DMA is used to manage the data transfer of the ring buffer area to ensure real-time performance; the memory block size is dynamically adjusted based on the task priority, and the pre-allocation strategy is used to avoid memory fragmentation to ensure efficiency.
[0012] The above two-level cache algorithm based on dynamic memory management, the specific process of step S1 is:
[0013] (1-1) For real-time data stream, determine the state of the ring buffer area, if the memory space is insufficient, trigger the LRU eviction mechanism to release the ring buffer area space, if the memory space is sufficient, go to the next step;
[0014] (1-2) DMA direct write, for task request data, determine whether it is a high-priority task or a normal task, if it is a high-priority task, directly allocate continuous memory, if it is a normal task, go to the next step;
[0015] (1-3) Check the LRU memory pool, if the cache hits, increase the data popularity, and return the dynamic classification memory block; if the cache misses, execute the pre-allocation strategy, and then return the dynamic classification memory block.
[0016] The two-level cache algorithm based on dynamic memory management, in the step S2, the first level algorithm adopts low-order filtering, sliding window average or principal component analysis method to perform global feature extraction on the input signal, and generates an intermediate result set to provide a decision basis for subsequent local optimization.
[0017] The two-level cache algorithm based on dynamic memory management, in the step S2, based on the candidate region output by the first level algorithm, the second level algorithm adopts local convolution, interpolation or polynomial fitting to complete fine feature recognition.
[0018] The two-level cache algorithm based on dynamic memory management, in the step S2, further comprises a dynamic scheduling and fault tolerance mechanism: when memory shortage or cache loading failure is detected, automatically fallback to the first level algorithm output base signal; in a multi-task environment, the execution path and memory access permission of high priority tasks are preferentially guaranteed.
[0019] The two-level cache algorithm based on dynamic memory management, in the step S3, the first level number table adopts dimension reduction mapping strategy to extract signal main features and construct a low resolution coefficient table.
[0020] The two-level cache algorithm based on dynamic memory management, in the step S3, the second level number table only models high-precision parameters for key regions based on the upper level number table to generate fine-grained compensation table items.
[0021] The two-level cache algorithm based on dynamic memory management, in the step S3, through the cooperative calling of the two-level number tables, the memory occupation is reduced while the algorithm accuracy is guaranteed, and a resource scheduling closed loop is formed with the dynamic memory mechanism in step S1 and the algorithm splitting strategy in step S2, so that the deployment of complex algorithms in embedded systems is realized.
[0022] An application of a two-level cache algorithm based on dynamic memory management is applied to underwater acoustic detection, industrial control, communication equipment or audio processing in an embedded system.
[0023] The beneficial effects of the present application are as follows:
[0024] 1. The real-time performance and stability of the system are improved: the cache scheduling mechanism based on dynamic memory management architecture and priority driving ensures that critical tasks have priority execution right and memory resource guarantee, and enhances the system response speed and stability under multi-task parallelism.
[0025] 2. The time complexity of the algorithm is significantly reduced: by splitting the original O(N²) complex signal processing algorithm into two low complexity sub-tasks (O(N1 2 )+O(N2 2 )), the execution time is greatly shortened, so that the complex algorithm originally limited by the power bottleneck can run in real time in the embedded system.
[0026] 3. The memory pressure is effectively relieved: the two-stage splitting strategy of the list structure is adopted to divide the original large-capacity pre-computed list table into coarse-grained and fine-grained two parts, and the total storage demand is reduced from O(N) to O(N1+ N2), meeting the memory limit of the embedded system in the resource-limited environment.
[0027] 4. It is suitable for various embedded scenarios: the application is not only suitable for pulse compression waveform generation in underwater acoustic detection, but also can be popularized to the fields such as industrial control, communication equipment, audio processing and the like which have high requirements on real-time performance and resource utilization. BRIEF DESCRIPTION OF DRAWINGS
[0028] Figure 1 is the overall flowchart of the application.
[0029] Figure 2 is the processing flowchart of the annular cache data area.
[0030] Figure 3 is the two-stage list table cooperative processing flowchart. DETAILED DESCRIPTION
[0031] The application will be further described below in combination with the drawings and embodiments.
[0032] As shown in the figure, a two-stage cache algorithm based on dynamic memory management comprises the following steps: Figure 1
[0033] S1: Establish a dynamic memory management architecture based on annular cache, and dynamically adjust the data loading and release sequence of the two-stage cache area through a priority-driven task scheduling mechanism.
[0034] In the step S1, the real-time data stream is managed through the annular queue, the dynamic allocation and recovery of the memory blocks of the two-stage cache are realized in combination with the LRU algorithm, the continuous memory space is ensured to be acquired by the high-priority task, the annular cache area data handling is managed by the hardware acceleration unit DMA to ensure real-time performance, the memory block size is dynamically adjusted based on the task priority, and the memory fragmentation is avoided through the pre-allocation strategy to ensure high efficiency.
[0035] The specific process of the step S1 is as follows:
[0036] (1-1) For the real-time data stream, the annular cache area state is determined, if the memory space is insufficient, the LRU elimination mechanism is triggered to release the annular cache area space, and if the memory space is sufficient, the next step is entered;
[0037] (1-2) DMA direct writing: for the task request data, it is determined whether it is a high-priority task or a normal task, if it is a high-priority task, the continuous memory is directly allocated, and if it is a normal task, the next step is entered;
[0038] (1-3) Check the LRU memory pool, if the cache hits, promote the data hotness, return the dynamic classification memory block, if the cache misses, execute the pre-allocation strategy, and then return the dynamic classification memory block.
[0039] S2: split the high complexity signal processing algorithm into two levels, the first level algorithm is used for processing the coarse-grained features of the input signal, and the time complexity is O(N1 2 ); the second level algorithm performs local fine calculation based on the processing result of the first level algorithm, and the time complexity is O(N2 2 ); the total time complexity is O(N1 2 )+O(N2 2 ), wherein .
[0040] The first level algorithm uses low-order filtering, sliding window averaging or principal component analysis method to extract global features of the input signal, and generates an intermediate result set to provide a decision basis for subsequent local optimization.
[0041] Based on the candidate region output by the first level algorithm, the second level algorithm uses local convolution, interpolation or polynomial fitting to complete fine feature recognition.
[0042] In step S2, dynamic scheduling and fault tolerance mechanism are further included: when memory shortage or cache loading failure is detected, the first level algorithm output is automatically rolled back to the basic signal; in a multi-task environment, the execution path and memory access permission of high priority tasks are preferentially guaranteed.
[0043] S3: split the pre-computed table into two levels, the first level table is used to store low-resolution parameters corresponding to coarse-grained features, and the space complexity is O(N1); the second level table is used to store high-precision parameters corresponding to local fine features, and the space complexity is O(N2); the total storage requirement is O(N1+N2), and .
[0044] The first level table uses dimension reduction mapping strategy to extract signal main features and construct low-resolution coefficient table. The second level table only models high-precision parameters for key regions based on the upper table, and generates fine-grained compensation table items. Through the cooperative call of the two level tables, the memory occupation is reduced while the algorithm accuracy is guaranteed, and a resource scheduling closed loop is formed with the dynamic memory mechanism in step S1 and the algorithm splitting strategy in step S2, realizing the deployment of complex algorithms in embedded systems.
[0045] The application also provides an application example of the algorithm in water acoustic signal processing.
[0046] Taking the realization of pulse compression waveform signal generation in a water acoustic detection system based on an STM32H743 embedded platform as an example, the specific implementation process is described as follows in combination with the two-level cache mechanism and the algorithm / table dual splitting strategy based on dynamic memory management proposed in the application:
[0047] Step S1: Establish a circular cache dynamic memory management architecture.
[0048] In the STM32H743 single-chip microcomputer, a fixed-size circular buffer (8 KB) is initialized to build a dynamic memory for two-level cache data storage and scheduling. The memory is divided into two levels:
[0049] The first-level cache area is used to store coarse-grained waveform templates and first-level algorithm intermediate results.
[0050] The second-level cache area loads local fine parameters on demand according to the first-level processing results.
[0051] The system adopts a priority-driven scheduling strategy, marks the waveform generation task as high priority, and ensures that the table call and algorithm execution on the critical path are not disturbed by other communication or control tasks. When the memory space is insufficient, an improved LRU algorithm is used to automatically release the cache blocks with low frequency, to ensure the priority scheduling of high-frequency data.
[0052] Step S2: Split the algorithm - two-level signal processing strategy.
[0053] For the matching filter algorithm commonly used in water acoustic detection, the original time complexity is O(N 2 ), N=1024 points, and the operation amount is up to one million times. The algorithm is split into two stages:
[0054] The first-level algorithm performs coarse-grained processing, performs low-order filtering and sliding window averaging on the first 256 sampling points, extracts signal envelope features, and the time complexity is O(256 2 )=65536 operations;
[0055] The second-level algorithm performs local fine calculation, based on the candidate region output by the first level, performs high-precision convolution operation within a limited range, completes local waveform synthesis, and the time complexity is O(512 2 )=262144 operations. The total operation amount is 327680 times, which is about 50% less than the original algorithm, and the actual measurement time on the STM32H743 platform is only about 1.8 ms, which is much lower than the required 5 ms real-time response period.
[0056] It should be noted that although N1=256 and N2=512 here are not strictly O(N But due to the data dependency and functional division difference between the two stages, the overall performance is close to the sub-linear growth trend, so as to realize the effective improvement of computing efficiency.
[0057] Step S3: splitting and calculating the number table - two-stage pre-computation cache mechanism.
[0058] In order to reduce the memory occupation and improve the system resource utilization efficiency, the pre-computation number table structure is optimized in the application. In the traditional method, the matching filter needs to load 1024 complex number points of complete filter coefficients, each complex number point has a real part and an imaginary part, each of which is 4 bytes (total 8 bytes), and a total of 8KB memory space is occupied. The first stage number table (used in the coarse-grained screening stage) stores 512 low-resolution coefficients, which are represented in fixed-point number format (each data occupies 4 bytes), and is used to support fast screening and candidate region positioning in the first stage. The size of the number table is 2KB, which meets the low-power and lightweight operation requirements. The second stage number table (used in the local fine matching stage) loads 512 high-precision compensation coefficients on demand in the effective candidate region output by the first stage, and is also stored in 4-byte fixed-point number format, which is used to perform local waveform synthesis and detail feature extraction. The size of the number table is also 2KB, which is dynamically loaded only when needed, avoiding long-term occupation of memory resources.
[0059] Through the above structured splitting strategy, the total memory occupation of the filter coefficients is reduced from 8KB to 4KB, and the phased control of memory usage is realized, further improving the running efficiency of the embedded system under limited resources, and working with the dynamic memory management mechanism in S1 to realize efficient loading and recycling of cache blocks.
[0060] Step 4: hardware implementation and performance verification.
[0061] Hardware platform: STM32H743VI (clock frequency 480MHz, SRAM capacity 64KB), which integrates multiple SRAM blocks (such as DTCM-RAM, SRAM1 / 2 / 3 / 4) and high-speed AXI SRAM interface, providing flexible storage space division for number table data in different stages. The first stage number table is loaded into DTCM-RAM, which has zero-wait access characteristics and is suitable for low-resolution coefficient data that is frequently read, thereby ensuring the real-time performance and efficient execution of the first stage coarse-grained screening task. The second stage number table uses an on-demand loading strategy, which is loaded from Flash to SRAM2 through the DMA controller only after the candidate region is output in the first stage. This way avoids long-term occupation of limited on-chip resources while ensuring the fast access performance required for high-precision compensation calculation.
[0062] Task scheduling: multi-task parallelism is realized using the FreeRTOS operating system; the first-level algorithm is executed preferentially, occupying 1.0 ms; the second-level algorithm is executed subsequently, occupying 0.8 ms; the total time consumption is ≤2 ms, meeting the real-time waveform updating requirement under a high sampling rate;
[0063] In addition, the present example realizes asynchronous transfer of the meter data using the built-in DMA controller of the STM32H743, so that the CPU can continue to execute other control logic or preprocessing tasks during the waiting period of data loading, thereby significantly improving the system concurrency and overall throughput. In the actual test environment, the loading time of the second-level meter is controlled within 0.2 ms, meeting the real-time requirement of the underwater acoustic detection system.
[0064] Fault-tolerant mechanism: if the second-level cache loading fails, the system falls back to the first-level coarse-grained output, ensuring the minimum functional availability of the system.
[0065] The present example fully embodies the three core ideas of dynamic memory management, algorithm splitting and meter splitting proposed by the present application, and forms a one-to-one correspondence with each technical solution (steps S1-S3). Through the soft and hard collaborative design, the complex signal processing algorithm originally limited by the power and memory bottleneck is realized to be efficiently run on the resource-limited embedded platform (such as the STM32 series MCU), which has good engineering application value and promotion prospect.
Claims
1. A two-level cache algorithm based on dynamic memory management, characterized in that, Comprise the following steps: S1: Establish a dynamic memory management architecture based on a ring buffer, dynamically adjust the data loading and release sequence of the two-level cache area through a priority-driven task scheduling mechanism; S2: split the high complexity signal processing algorithm into two stages, the first stage algorithm is used to process the coarse-grained features of the input signal, the time complexity is O(N1 2 ); the second stage algorithm performs local fine calculation based on the processing result of the first stage algorithm, the time complexity is O(N2 2 ); the total time complexity is O(N1 2 )+O(N2 2 ), wherein ; S3: split the pre-computed table into two levels, the first level table is used to store the low resolution parameters corresponding to the coarse features, with a space complexity of O(N1); the second level table is used to store the high resolution parameters corresponding to the local fine features, with a space complexity of O(N2); the total storage requirement is O(N1+N2), and .
2. The two-level cache algorithm based on dynamic memory management according to claim 1, characterized in that, In the step S1, the real-time data stream is managed through a ring queue, the LRU algorithm is combined to realize the dynamic allocation and recovery of the memory blocks of the two-level cache, the continuous memory space is ensured to be obtained by the high-priority task, the hardware acceleration unit DMA is used to manage the data transfer of the ring buffer area to ensure real-time performance; the memory block size is dynamically adjusted based on the task priority, and the pre-allocation strategy is used to avoid memory fragmentation to ensure efficiency.
3. The two-level cache algorithm based on dynamic memory management according to claim 2, characterized in that, The specific process of the step S1 is: (1-1) For real-time data stream, determine the state of the ring buffer area, if the memory space is insufficient, trigger the LRU eviction mechanism to release the ring buffer area space, if the memory space is sufficient, go to the next step; (1-2) DMA direct write, for task request data, determine whether it is a high-priority task or a normal task, if it is a high-priority task, directly allocate continuous memory, if it is a normal task, go to the next step; (1-3) Check the LRU memory pool, if the cache hits, increase the data heat, and return the dynamic classification memory block; If the cache does not hit, execute the pre-allocation strategy, and return the dynamic classification memory block again.
4. The two-level cache algorithm based on dynamic memory management according to claim 1, wherein, In the step S2, the first-level algorithm uses low-order filtering, sliding window averaging or principal component analysis method to perform global feature extraction on the input signal to generate an intermediate result set to provide decision basis for subsequent local optimization.
5. The two-level cache algorithm based on dynamic memory management according to claim 4, characterized in that, In the step S2, based on the candidate region output by the first-level algorithm, the second-level algorithm uses local convolution, interpolation or polynomial fitting to complete fine feature recognition.
6. The two-level cache algorithm based on dynamic memory management according to claim 5, characterized in that, In the step S2, it also includes dynamic scheduling and fault tolerance mechanism: when detecting insufficient memory or cache loading failure, automatically fallback to the first-level algorithm output basis signal; in a multi-task environment, the execution path and memory access permission of high-priority task are preferentially guaranteed.
7. The dynamic memory management based two level cache algorithm of claim 1, wherein, In the step S3, the first-level number table uses dimension reduction mapping strategy to extract signal main features and construct low-resolution coefficient table.
8. The two-level cache algorithm based on dynamic memory management according to claim 7, characterized in that, In the step S3, the second-level number table only models high-precision parameters for key regions based on the upper-level number table to generate fine-grained compensation table items.
9. The two-level cache algorithm based on dynamic memory management according to claim 8, characterized in that, In the step S3, through the cooperative calling of the two-level number tables, the memory occupation is reduced while ensuring the accuracy of the algorithm, and a resource scheduling closed loop is formed with the dynamic memory mechanism in step S1 and the algorithm splitting strategy in step S2 to realize the deployment of complex algorithms in embedded systems.
10. Use of a two-level cache algorithm based on dynamic memory management according to any one of claims 1 to 9, characterized in that, Applied to embedded systems such as underwater acoustic detection, industrial control, communication equipment or audio processing.