Electronic device and method for timing the running time of an electronic device

Abstract

The invention provides electronic equipment and a method for timing the running time of the electronic equipment. According to one embodiment, an electronic device includes a processor in which a flash memory is built. The flash memory includes a first flash memory space for timing a runtime of the processor, and a second flash memory space for storing a first count value representing the runtime timed by the first flash memory space. The capacity of the first flash memory space is N bits, and N is an integer greater than 1. The processor is configured to cyclically execute the following operations: erasing the first flash memory space to enable N bits to be 1; one bit in the N bits is rewritten from 1 to 0 every M seconds, and M is an integer greater than or equal to 1; and when the N bits are rewritten from 1 to 0, adding 1 to the first count value stored in the second flash memory space.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of electronics, and more particularly to an electronic device and a method for timing the running time of the electronic device. BACKGROUND

[0002] In some electronic devices, it is necessary to record the cumulative running time of the electronic device. In particular, in some application scenarios with high reliability requirements, it is necessary to remind the user to perform preventive maintenance on the device after the power-on running time of the electronic device reaches a certain limit value, so as to avoid irreparable loss caused by sudden failure of the device. This can be simply obtained by counting clock pulses by the processor to obtain the cumulative running time. However, if the count value of the running time is stored in a volatile memory, the count value will be lost after power-off. Therefore, it is necessary to perform counting operation in a non-volatile memory. SUMMARY

[0003] This section is provided to summarize selected concepts disclosed in this document in a simplified form. This section is not intended to identify essential features of the claimed subject matter, nor is it meant to limit the scope of the claimed subject matter.

[0004] One of the purposes of the present disclosure is to provide an improved electronic device and a method for timing the running time of the electronic device. In particular, one of the technical problems to be solved by the present disclosure is that in the existing method of timing the running time by using the non-volatile memory built-in in the processor, the non-volatile memory is erased and written once per unit time interval, and the erase and write life of the non-volatile memory is limited, resulting in very limited recorded running time.

[0005] According to a first aspect of the present disclosure, an electronic device is provided. The electronic device comprises a processor, in which a flash memory is built-in. The flash memory comprises a first flash space for timing the running time of the processor, and a second flash space for storing a first count value representing the running time timed by the first flash space. The capacity of the first flash space is N bits, N being an integer greater than 1. The processor is configured to cyclically perform the following operations: erasing the first flash space so that the N bits are all 1; changing one bit of the N bits from 1 to 0 every M seconds, M being an integer greater than or equal to 1; when the N bits are changed from 1 to 0, increasing the first count value stored in the second flash space by 1.

[0006] According to the above first aspect, since the flash memory is erased and written every N*M seconds, the recorded running time can be made N times as long as that of the conventional scheme in which the flash memory is erased and written every M seconds, using the same built-in flash memory. Moreover, the above first aspect can be applied as long as the processor is built with the flash memory, and thus the running time can be counted without adding other memories.

[0007] In one embodiment of the present disclosure, the processor is configured to determine the running time of the processor as a product of the first count value, M, and N.

[0008] In one embodiment of the present disclosure, N is a quotient of the number of seconds included in a day divided by M. According to this embodiment, the product of N and M is the number of seconds included in a day, and thus the flash memory is erased and written every day. In the case where the life of the built-in flash memory is, for example, 100,000 times of erasing and writing, the running time that can be continuously recorded is 274 years, and thus the recordable running time is significantly extended.

[0009] In one embodiment of the present disclosure, M is 60, and N is a quotient of the number of seconds included in a day divided by M (i.e., 1440). According to this embodiment, the flash memory is erased and written every day, and the running time counting can be performed with an accuracy of 1 minute.

[0010] In one embodiment of the present disclosure, M is 1, and N is a quotient of the number of seconds included in a day divided by M (i.e., 86400). That is, the capacity of the first flash memory space is 86400 bits, i.e., 10800 bytes. According to this embodiment, the flash memory is erased and written every day, and the running time counting can be performed with an accuracy of 1 second.

[0011] In one embodiment of this disclosure, the flash memory further includes a third flash space for timing the runtime of the processor, and a fourth flash space for storing a second count value representing the runtime time timed through the third flash space. The third flash space has a capacity of N bits. The processor is further configured to cyclically perform the following operations: erasing the third flash space so that all N bits are 1; rewriting one of the N bits from 1 to 0 every M seconds; and incrementing the second count value stored in the fourth flash space by 1 when the N bits are rewritten from 1 to 0. The first time period for operating on the second flash space and the second time period for operating on the fourth flash space are spaced apart on a time axis. According to this embodiment, even if a power outage occurs during the storage of the first or second count value, since the power outage only affects the storage of one of the two count values, accurate recording of the runtime can be ensured, reliability can be improved, and data loss due to power outage during the storage of the first or second count value can be avoided.

[0012] In one embodiment of this disclosure, the processor is configured to determine the processor's runtime as the product of the following three factors: the larger of the first count value and the second count value; M; and N.

[0013] In one embodiment of this disclosure, N is the quotient obtained by dividing the number of seconds in a day by M.

[0014] According to a second aspect of this disclosure, a method for timing the operating time of an electronic device is provided. A flash memory is built into the processor of the electronic device. The flash memory includes a first flash space for timing the operating time of the processor, and a second flash space for storing a first count value representing the operating time timed through the first flash space. The capacity of the first flash space is N bits, where N is an integer greater than 1. The method includes: the processor cyclically performing the following operations: erasing the first flash space so that all N bits are 1; changing one bit from 1 to 0 every M seconds, where M is an integer greater than or equal to 1; and incrementing the first count value stored in the second flash space by 1 when the N bits are changed from 1 to 0.

[0015] According to the second aspect above, since the flash memory is erased and written only once every N*M seconds, the recorded runtime can be N times longer than the existing scheme, which erases and writes only once every M seconds, when using built-in flash memory with the same lifespan. Furthermore, the first aspect above applies as long as the processor has built-in flash memory, thus runtime timing can be achieved without adding other memory.

[0016] In one embodiment of this disclosure, the method further includes determining the processor's runtime as the product of three factors: the first count value; M; and N.

[0017] In one embodiment of this disclosure, N is the quotient obtained by dividing the number of seconds in a day by M.

[0018] In one embodiment of this disclosure, M is 60, and N is the quotient of the number of seconds in a day divided by M (i.e., 1440).

[0019] In one embodiment of this disclosure, M is 1, and N is the quotient of the number of seconds in a day divided by M (i.e., 86400).

[0020] In one embodiment of this disclosure, the flash memory further includes a third flash space for timing the runtime of the processor, and a fourth flash space for storing a second count value representing the runtime time timed through the third flash space. The third flash space has a capacity of N bits. The method further includes the processor cyclically performing the following operations: erasing the third flash space so that all N bits are 1; changing one of the N bits from 1 to 0 every M seconds; and incrementing the second count value stored in the fourth flash space by 1 when the N bits are changed from 1 to 0. A first time period for operating on the second flash space and a second time period for operating on the fourth flash space are spaced apart on a time axis.

[0021] In one embodiment of this disclosure, the method further includes determining the processor's runtime as the product of three factors: the larger of the first count value and the second count value; M; and N.

[0022] In one embodiment of this disclosure, N is the quotient obtained by dividing the number of seconds in a day by M.

[0023] According to a third aspect of this disclosure, a computer-readable storage medium is provided. Program instructions are stored on the computer-readable storage medium. When executed by a processor, the program instructions cause the processor to perform the method according to the second aspect described above. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the structural diagrams in the following drawings are not necessarily drawn to scale, but rather present the features in a simplified form. Furthermore, the following drawings only relate to some embodiments of this disclosure and are not intended to limit the scope of this disclosure.

[0025] Figure 1This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure; Figure 2 This is a block diagram illustrating an electronic device according to another embodiment of the present disclosure; Figure 3 This is a flowchart illustrating a method for timing the operating time of an electronic device according to an embodiment of the present disclosure; Figure 4 This is a flowchart illustrating a method for timing the operating time of an electronic device according to another embodiment of the present disclosure; Figure 5 This is a flowchart illustrating a method for timing the operating time of an electronic device according to yet another embodiment of the present disclosure; and Figure 6 This is a flowchart illustrating a method for timing the operating time of an electronic device according to yet another embodiment of the present disclosure. Detailed Implementation

[0026] For purposes of explanation, certain details are set forth in the following description to provide a thorough understanding of the disclosed embodiments. However, it will be apparent to those skilled in the art that the embodiments may be implemented without these specific details or using equivalent configurations.

[0027] As mentioned earlier, some electronic devices need to record their cumulative operating time. This can be easily achieved by the processor counting clock pulses. However, if this count is stored in volatile memory, it will be lost when power is off. Therefore, the counting operation needs to be performed in non-volatile memory.

[0028] Modern processors typically have built-in non-volatile memory. However, their write / erase cycle life is often only 100,000 times. If you write / erase every minute, you can reach 100,000 cycles in just 70 days. Therefore, directly operating the memory for counting is not a very suitable solution.

[0029] Currently, some existing technologies use external batteries to maintain the current count after a power outage. However, this approach requires additional components and incurs higher costs, reducing overall reliability. Other existing technologies use electrically erasable programmable read-only memory (EEPROM) to achieve a write / erase cycle life of 1 million times, but this only allows for continuous recording for two years.

[0030] This disclosure provides an improved electronic device and a method for timing the operating time of the electronic device. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1This is a block diagram illustrating an electronic device according to one embodiment of the present disclosure. The electronic device can be any electronic device that needs to keep track of its operating time. As an exemplary example, the electronic device can be a medical electronic device (e.g., a medical energy device that applies various types of energy, such as ultrasonic energy, thermal energy, etc., to a patient). Figure 1 As shown, the electronic device 10 includes a processor 12, in which a flash memory 121 is built-in. The flash memory 121 includes a first flash space 1211 for timing the running time of the processor 10, and a second flash space 1212 for storing a first count value representing the running time timed by the first flash space 1211. The capacity of the first flash space 1211 is N bits, where N is an integer greater than 1.

[0032] Flash memory, also known as FLASH memory, has the following characteristics: it erases an entire page at a time (e.g., 512 bytes; for some processors, the size of the built-in memory page can be up to 4096 bytes), after which all bits become 1. When writing, it can change from 1 to 0, but not from 0 to 1. This characteristic can be used to time the processor's runtime, and therefore the runtime of electronic devices.

[0033] The processor 12 is configured to perform the following operations in a loop: erase the first flash memory space 1211 so that N bits are all 1; change one of the N bits from 1 to 0 every M seconds, where M is an integer greater than or equal to 1; and increment the first count value stored in the second flash memory space 1212 by 1 when N bits are changed from 1 to 0.

[0034] Specifically, the initial value of the first counter can be 0. After performing the above three operations in the first loop, the first counter becomes 1. Then, the second loop begins, and the above three operations are performed again. After performing the above three operations in the second loop, the first counter becomes 2. Then, the above three operations continue to be performed in a loop, thereby accumulating the processor's running time.

[0035] Thus, since the flash memory is erased and written only once every N*M seconds, the recorded runtime can be N times longer than existing solutions that erase and write every M seconds, when using built-in flash memory with the same lifespan. Furthermore, this solution applies as long as the processor has built-in flash memory, eliminating the need for additional memory to record runtime.

[0036] When it is necessary to output the processor's runtime (e.g., in response to a query request from a user), the processor 12 is configured to determine the processor 12's runtime as the product of the following three factors: a first count value, M, and N.

[0037] As an option, N can be the quotient of the number of seconds in a day divided by M. Thus, the product of N and M is the number of seconds in a day, so the flash memory is only erased and written once per day. With a built-in flash memory lifespan of, for example, 100,000 erase / write cycles, the continuous recording time is 274 years, significantly extending the recordable runtime.

[0038] As an example of the above options, M can be 60, and N can be the quotient of the number of seconds in a day divided by M, which is 1440. That is, the capacity of the first flash memory space 1211 is 1440 bits, or 180 bytes. Thus, the processor sets one bit to 0 every minute, and all 1440 bits set to 0 equals 24 hours. After all 1440 bits are overwritten to 0, the page is erased, the accumulated days are incremented by 1, and written back to memory, then the operation of overwriting one bit every minute is repeated. This results in a maximum of 365 erase / write cycles per year, and a lifespan of 100,000 cycles, allowing for continuous recording for 274 years. Therefore, only 180 bytes or more of flash memory space are needed to achieve reliable non-volatile cumulative counting with accuracy to one minute or higher without adding extra components or costs.

[0039] As another exemplary example of the above options, M can be 1, and N can be the quotient of the number of seconds in a day divided by M, which is 86400. That is, the capacity of the first flash memory space 1211 is 86400 bits, or 10800 bytes. Thus, the flash memory is erased and written only once a day, enabling runtime timing accurate to one second. Therefore, only 10800 bytes or more of flash memory space is needed to achieve reliable non-volatile cumulative counting with accuracy to the second or higher without adding additional components or cost.

[0040] It should be noted that this disclosure is not limited to the options described above. Alternatively, N can be the quotient of the number of seconds contained in 1 / K of a day divided by M, where K can be, for example, an integer in the range [2, 24]. Thus, even if K is 24, the continuous recording time can reach approximately 11 years.

[0041] Figure 2 This is a block diagram illustrating an electronic device according to another embodiment of the present disclosure. Figure 2As shown, the electronic device 20 includes a processor 22, within which a flash memory 221 is built. The flash memory 221 includes a first flash space 2211 for timing the runtime of the processor 22, and a second flash space 2212 for storing a first count value representing the runtime time timed through the first flash space 2211. The first flash space 2211 has a capacity of N bits, where N is an integer greater than 1. The flash memory 221 also includes a third flash space 2213 for timing the runtime of the processor 22, and a fourth flash space 2214 for storing a second count value representing the runtime time timed through the third flash space 2213. The third flash space 2213 also has a capacity of N bits.

[0042] Processor 22 is configured to cyclically perform the following operations: erase a first flash memory space 2211 so that N bits are all 1; every M seconds, change one of the N bits from 1 to 0, where M is an integer greater than or equal to 1; when N bits are changed from 1 to 0, increment a first count value stored in the second flash memory space 2212 by 1. Processor 22 is also configured to cyclically perform the following operations: erase a third flash memory space 2213 so that N bits are all 1; every M seconds, change one of the N bits from 1 to 0; when N bits are changed from 1 to 0, increment a second count value stored in the fourth flash memory space 2214 by 1.

[0043] The first time period for operating on the second flash memory space 2212 and the second time period for operating on the fourth flash memory space 2214 are spaced apart on the time axis. For example, this can be achieved by executing the two loops in parallel, with the execution start time of one loop preceding the execution start time of the other loop. In this way, even if a power outage occurs during the storage of the first or second count value, since the power outage only affects the storage of one of the two count values, the accurate recording of the runtime can be ensured, reliability can be improved, and data loss due to power outage during the storage of the first or second count value can be avoided.

[0044] When the processor's runtime needs to be output (e.g., in response to a query request from a user), processor 22 is configured to determine the processor's runtime as the product of three factors: the larger of a first count value and a second count value, M, and N. If a discrepancy is found between the first and second count values, processor 22 can be configured to change the smaller count value to the larger of the two count values.

[0045] and Figure 1Similarly, as an option, N can be the quotient of the number of seconds in a day divided by M. Thus, the product of N and M is the number of seconds in a day, so the flash memory is erased and written only once per day. With a built-in flash memory lifespan of, for example, 100,000 erase / write cycles, the continuously recording runtime is 274 years, significantly extending the recordable runtime.

[0046] As an example of the above options, M can be 60, and N can be the quotient of the number of seconds in a day divided by M, which is 1440. That is, the capacity of both the first flash memory space 2211 and the third flash memory space 2213 is 1440 bits, or 180 bytes. Thus, the flash memory is erased and written only once a day, and runtime timing accurate to one minute can be achieved. As another example of the above options, M can be 1, and N can be the quotient of the number of seconds in a day divided by M, which is 86400. That is, the capacity of both the first flash memory space 2211 and the third flash memory space 2213 is 86400 bits, or 10800 bytes. Thus, the flash memory is erased and written only once a day, and runtime timing accurate to one second can be achieved.

[0047] As another option, N can also be the quotient of the number of seconds contained in 1 / K of a day divided by M, where K can be, for example, an integer in the range [2, 24]. In this way, even if K is 24, the continuous recording time can reach approximately 11 years.

[0048] Figure 3 This is a flowchart illustrating a method for timing the runtime of an electronic device according to an embodiment of the present disclosure. The method is applicable to electronic devices having a flash memory built into their processor and can be executed by the processor of the electronic device. The flash memory includes a first flash memory space for timing the runtime of the processor and a second flash memory space for storing a first count value representing the runtime time timed through the first flash memory space. The capacity of the first flash memory space is N bits, where N is an integer greater than 1.

[0049] like Figure 3 As shown, the method includes steps 302-306. In step 302, the processor erases the first flash memory space so that N bits are all 1. In step 304, the processor changes one bit from 1 to 0 every M seconds, where M is an integer greater than or equal to 1. In step 306, when N bits are changed from 1 to 0, the first count value stored in the second flash memory space is incremented by 1. Steps 302-306 can be executed cyclically. That is, after steps 302-306 are executed in the first loop, subsequent loops can be entered to execute steps 302-306 again.

[0050] for Figure 3 The method shown, because it only erases and writes the flash memory once every N*M seconds, can achieve a recorded runtime N times faster than existing methods that erase and write every M seconds, when using built-in flash memory with the same lifespan. Furthermore, this works as long as the processor has built-in flash memory. Figure 3 The method can be applied, so runtime timing can be achieved without adding other memory.

[0051] Figure 4 This is a flowchart illustrating a method for timing the operating time of an electronic device according to another embodiment of the present disclosure. Figure 4 As shown, the method includes steps 302-306 and step 408. In step 408, the processor determines the processor's runtime as the product of three factors: a first count value, M, and N. Step 408 can be executed when the processor's runtime needs to be output (e.g., in response to a query request from a user).

[0052] Figure 5 This is a flowchart illustrating a method for timing the runtime of an electronic device according to another embodiment of the present disclosure. The method is applicable to and can be executed by the processor of an electronic device having a built-in flash memory in its processor. The flash memory includes a first flash space for timing the runtime of the processor and a second flash space for storing a first count value representing the runtime time timed through the first flash space. The capacity of the first flash space is N bits, where N is an integer greater than 1. The flash memory also includes a third flash space for timing the runtime of the processor and a fourth flash space for storing a second count value representing the runtime time timed through the third flash space. The capacity of the third flash space is N bits.

[0053] like Figure 5 As shown, the method includes steps 302-306 and steps 510-514. As previously described, steps 302-306 can be executed cyclically. In step 510, the processor erases the third flash memory space so that N bits are all 1. In step 512, the processor changes one bit from 1 to 0 every M seconds. In step 514, when N bits are changed from 1 to 0, the processor increments the second count value stored in the fourth flash memory space by 1. Steps 510-514 can be executed cyclically.

[0054] The first time period for operating on the second flash memory space in step 306 and the second time period for operating on the fourth flash memory space in step 514 are spaced apart on the timeline. For example, this can be achieved by executing the two loops in parallel, with the execution start time of one loop preceding that of the other. In this way, even if a power outage occurs during the storage of the first or second count value, since the power outage only affects the storage of one of the two count values, accurate recording of the runtime can be ensured, reliability is improved, and data loss due to power outages during the storage of the first or second count value can be avoided. When the count values ​​read from the two flash memory spaces are inconsistent, it indicates that a power outage occurred when rewriting the count value. In this case, a larger count value can be used to overwrite a smaller count value to ensure consistency of the count values.

[0055] Figure 6 This is a flowchart illustrating a method for timing the operating time of an electronic device according to yet another embodiment of the present disclosure. Figure 6 As shown, the method includes steps 302-306, steps 510-514, and step 616. In step 616, the processor determines the processor's runtime as the product of three factors: the larger of a first count value and a second count value, M, and N. Step 616 can be executed when the processor's runtime needs to be output (e.g., in response to a query request from a user). It should be noted that two consecutively shown blocks (or steps) in the accompanying drawings of this disclosure can actually be executed substantially in parallel, or these blocks (or steps) can sometimes be executed in reverse order, depending on the functionality involved.

[0056] exist Figures 3 to 6 In the illustrated methods, the processor can implement these methods by executing program instructions. The program instructions can be stored in the aforementioned flash memory or in other non-volatile memory included in the electronic device. Therefore, at least one aspect of this disclosure also provides a computer-readable storage medium. Program instructions are stored on the computer-readable storage medium. When executed by a processor, the program instructions cause the processor to perform reference... Figures 3 to 6 The method described by any one of them.

[0057] In this disclosure, examples of processors include, but are not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), processors based on multi-core processor architectures, microcontroller units (MCUs), and so on. Examples of computer-readable storage media include, but are not limited to, hard disks, optical disks, removable storage media, solid-state drives, random access memory (RAM), and so on.

[0058] References to "an embodiment," "embodiment," etc., in this disclosure indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment must include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the art, whether or not it is explicitly described.

[0059] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. In this disclosure, the term “and / or” includes any one and all combinations of one or more of the associated listed terms. It should also be understood that the terms “comprising,” “having,” and / or “including,” when used herein, refer to the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. The term “connection” as used herein covers direct and / or indirect connections between two elements.

[0060] This disclosure includes any novel features or combinations of features explicitly disclosed herein or in any generalized form. Various modifications and adaptations to the exemplary embodiments of this disclosure will become apparent to those skilled in the art when read in conjunction with the accompanying drawings and based on the foregoing description. However, any and all modifications and adaptations will still fall within the scope of the non-limiting and exemplary embodiments of this disclosure.

Claims

1. An electronic device, comprising: The processor has a built-in flash memory, which includes a first flash space for timing the running time of the processor and a second flash space for storing a first count value representing the running time timed through the first flash space. The first flash space has a capacity of N bits, where N is an integer greater than 1. The processor is configured to perform the following operations in a loop: erase the first flash memory space so that all N bits are 1; change one of the N bits from 1 to 0 every M seconds, where M is an integer greater than or equal to 1; and increment the first count value stored in the second flash memory space by 1 when the N bits are changed from 1 to 0.

2. The electronic device according to claim 1, wherein, The processor is configured to determine the processor's runtime as the product of the following three factors: the first count value; M; and N.

3. The electronic device according to claim 1, wherein, N is the quotient obtained by dividing the number of seconds in a day by M.

4. The electronic device according to claim 1, wherein, The flash memory further includes a third flash space for timing the running time of the processor, and a fourth flash space for storing a second count value representing the running time timed through the third flash space, the third flash space having a capacity of N bits; The processor is further configured to cyclically perform the following operations: erasing the third flash memory space so that all N bits are 1; changing one of the N bits from 1 to 0 every M seconds; incrementing the second count value stored in the fourth flash memory space by 1 when the N bits are changed from 1 to 0; and The first time period for operating on the second flash memory space and the second time period for operating on the fourth flash memory space are spaced apart on the time axis.

5. The electronic device according to claim 4, wherein, The processor is configured to determine the processor's runtime as the product of the following three factors: the larger of the first count value and the second count value; M; and N.

6. The electronic device according to claim 4, wherein, N is the quotient obtained by dividing the number of seconds in a day by M.

7. A method for timing the operating time of an electronic device, wherein, The processor of the electronic device has a built-in flash memory, which includes a first flash space for timing the running time of the processor and a second flash space for storing a first count value representing the running time timed through the first flash space. The first flash space has a capacity of N bits, where N is an integer greater than 1. The method includes: The processor performs the following operations in a loop: erasing the first flash memory space so that all N bits are 1; changing one of the N bits from 1 to 0 every M seconds, where M is an integer greater than or equal to 1; and incrementing the first count value stored in the second flash memory space by 1 when the N bits are changed from 1 to 0.

8. The method according to claim 7, further comprising: The processor's runtime is determined as the product of the following three factors: the first count value; M； And N.

9. The method according to claim 7, wherein, The flash memory further includes a third flash space for timing the running time of the processor, and a fourth flash space for storing a second count value representing the running time timed through the third flash space, the third flash space having a capacity of N bits; The method further includes the processor cyclically performing the following operations: erasing the third flash memory space so that all N bits are 1; changing one of the N bits from 1 to 0 every M seconds; incrementing the second count value stored in the fourth flash memory space by 1 when the N bits are changed from 1 to 0; and The first time period for operating on the second flash memory space and the second time period for operating on the fourth flash memory space are spaced apart on the time axis.

10. The method of claim 9, further comprising: The processor's runtime is determined as the product of the following three values: the larger of the first count value and the second count value; M； And N.

11. A computer-readable storage medium having program instructions stored thereon, the program instructions causing the processor to perform the method according to any one of claims 7 to 10 when executed by a processor.

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