Cache controller verification method and device, computer equipment and readable storage medium

Abstract

The invention relates to a cache controller verification method and device, computer equipment and a readable storage medium. A control signal of a first cache controller is monitored, and a first request sequence is determined according to the control signal; a second cache controller is controlled to execute verification operation corresponding to the sequence of the control signals in the first request sequence, and a second verification result of simulation verification conducted by the second cache controller is obtained; the storage logic of the second cache controller is consistent with that of the first cache controller; monitoring verification operation performed by the first cache controller based on the first request sequence to obtain a first verification result; and performing period comparison on the first verification result and the second verification result to obtain a target verification result for positioning the abnormal period, thereby improving the verification fineness of the cache controller, and accurately positioning the abnormal position in the verification process under the condition that the abnormality occurs.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer storage controller, and particularly relates to a cache controller verification method and device, a computer device and a readable storage medium. BACKGROUND

[0002] In the current field of computer storage controller, in order to meet the increasing performance requirements of computer chips, the design of computer storage controller is becoming increasingly complex. In particular, as a kind of high-speed temporary storage controller of computer storage controller, the verification of cache controller is one of the core links to ensure the correctness of chip function and performance.

[0003] At present, when verifying the cache controller, mainly relies on the protocol interface verification method, by monitoring the interface signal outside the cache controller, and monitoring whether the response signal conforms to the predetermined communication protocol range, so as to determine whether the function of the cache controller is accurate. However, since the verification behavior of the protocol interface verification method only stays at the interface level, it is not possible to more accurately determine the request data and data sequence corresponding to the interface signal, therefore, the precision of the verification process of the cache controller is insufficient, and the abnormal position in the verification process cannot be accurately located. SUMMARY

[0004] Therefore, it is necessary to provide a cache controller verification method, device, computer device and readable storage medium, which can improve the precision of verifying the cache controller and accurately locate the abnormal position in the verification process.

[0005] In a first aspect, the present application provides a cache controller verification method, comprising:

[0006] listening to the control signal of the first cache controller, and determining the first request sequence according to the control signal;

[0007] controlling the second cache controller to perform a verification operation corresponding to the order of the control signal in the first request sequence, to obtain a second verification result of the second cache controller for simulation verification; wherein the first cache controller is a cache controller to be verified, the second cache controller is a virtual cache controller for simulating the verification of the first cache controller, and the storage logic of the second cache controller is consistent with that of the first cache controller;

[0008] listening to the verification operation of the first cache controller based on the first request sequence, to obtain a first verification result;

[0009] periodically comparing the first verification result and the second verification result to obtain a target verification result for locating an abnormal period.

[0010] In one of the embodiments, the storage logic comprises a storage architecture specification and storage data content, and before the step of listening to the control signals of the first cache controller, the cache controller verification method further comprises:

[0011] constructing a virtual original second cache controller according to the storage architecture specification of the first cache controller; wherein the data structure of the second cache controller comprises a cache line array and an address hit association array;

[0012] obtaining the storage data content in the first cache controller, the storage data content comprising a storage state and a hit state;

[0013] updating the storage state and the hit state in the first cache controller to the cache line array and the address hit association array in the original second cache controller respectively, to obtain the second cache controller.

[0014] In one of the embodiments, the first request sequence comprises a hit test request signal, the hit test request signal being used for hit test on the first cache controller;

[0015] The step of listening to the control signals of the first cache controller and determining the first request sequence according to the control signals comprises:

[0016] when it is listened that the first cache controller performs hit test in response to the hit test request signal in the first request sequence, obtaining the hit test request signal;

[0017] writing the hit test request signal into the second request sequence to obtain the first request sequence; wherein the second request sequence is the original request sequence, the second request sequence is a sequence comprising at least one control signal, and the first request sequence is a sequence comprising at least one control signal and the hit test request signal;

[0018] The step of controlling the second cache controller to perform the verification operation corresponding to the order of the control signals in the first request sequence to obtain the second verification result of the simulation verification of the second cache controller comprises:

[0019] controlling the second cache controller to perform the verification operation corresponding to each control signal according to the order of the at least one control signal in the first request sequence;

[0020] in response to the hit test request signal, controlling the second cache controller to perform hit test corresponding to the hit test request signal to determine the corresponding hit result, to obtain the second verification result.

[0021] In one of the embodiments, after the step of controlling the second cache controller to perform the hit test corresponding to the hit test request signal in response to the hit test request signal to determine the corresponding hit result to obtain the second verification result, the cache controller verification method further comprises:

[0022] listening to a return interface of the memory access of the first cache controller to obtain a first listening result; wherein the first listening result is used to determine the unfinished transaction in the memory access of the first cache controller;

[0023] determining the data return state corresponding to each cache line in the first cache controller according to the unfinished transaction in the memory access determined by the first listening result;

[0024] setting the working state corresponding to each cache line in the cache line array of the second cache controller according to the data return state of each cache line in the first cache controller, so as to maintain the working state of each cache line in the first cache controller consistent with that in the second cache controller.

[0025] In one of the embodiments, after the step of controlling the second cache controller to perform the hit test corresponding to the hit test request signal in response to the hit test request signal to determine the corresponding hit result to obtain the second verification result, the cache controller verification method further comprises:

[0026] listening to an interface reset event of the first cache controller to obtain a second listening result; wherein the second listening result comprises the address offset when the first cache controller performs data reading;

[0027] synchronizing the address offset to the offset grouping queue in the second cache controller, so as to maintain the address allocation state of the first cache controller consistent with that of the second cache controller.

[0028] In one of the embodiments, the step of controlling the second cache controller to perform the verification operation corresponding to the order of the control signal in the first request sequence to obtain the second verification result of the simulation verification of the second cache controller further comprises:

[0029] obtaining the historical request information of the second cache controller; wherein the historical request information comprises the historical address offset and the historical hit result corresponding to the historical hit test request signal in the first request sequence;

[0030] calculating the expected address offset and the expected hit result corresponding to the second cache controller according to the historical address offset and the historical hit result to obtain the second verification result; wherein the second verification result is the expected verification result of the second cache controller in the simulation of the verification process of the first cache controller, and the second verification result is used for the cycle comparison of the first verification result.

[0031] In one embodiment, after the step of controlling the second cache controller to perform the verification operation corresponding to the order of the control signals in the first request sequence to obtain the second verification result of the simulation verification of the second cache controller, the cache controller verification method further comprises:

[0032] According to the second verification result, the state information of the second cache controller is updated to maintain the state of the second cache controller consistent with the attribute state of the first cache controller; wherein the state information at least includes the calculation period information and the calculation path information corresponding to each cache line in the second cache controller.

[0033] In a second aspect, the present application further provides a cache controller verification device, comprising:

[0034] A first monitoring module is configured to monitor the control signals of the first cache controller and determine the first request sequence according to the control signals;

[0035] A simulation verification module is configured to control the second cache controller to perform the verification operation corresponding to the order of the control signals in the first request sequence to obtain the second verification result of the simulation verification of the second cache controller; wherein the first cache controller is the cache controller to be verified, the second cache controller is a virtual cache controller for simulating the verification of the first cache controller, and the storage logic of the second cache controller is consistent with that of the first cache controller.

[0036] A second monitoring module is configured to monitor the verification operation of the first cache controller based on the first request sequence to obtain the first verification result;

[0037] A comparison module is configured to perform period comparison on the first verification result and the second verification result to obtain the target verification result for locating the abnormal period.

[0038] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the cache controller verification method of the first aspect when executing the computer program.

[0039] In a fourth aspect, the present application further provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the steps of the cache controller verification method of the first aspect.

[0040] The cache controller verification method, device, computer device and readable storage medium verify the first request sequence according to the control signals of the first cache controller, control the second cache controller to perform a verification operation corresponding to the order of the control signals in the first request sequence, and obtain a second verification result of the second cache controller for simulation verification. The first cache controller is a cache controller to be verified, the second cache controller is a virtual cache controller for simulation verification of the first cache controller, and the storage logic of the second cache controller is consistent with that of the first cache controller. The first verification result is obtained by listening to the verification operation of the first cache controller based on the first request sequence. The first verification result and the second verification result are compared periodically to obtain a target verification result for positioning an abnormal period. In this way, the control signals of the first cache controller are tracked based on the second cache controller during the verification process of the first cache controller, the verification process is simulated, and the signals between the second cache controller and the first cache controller are consistent during the simulation verification process, ensuring the accuracy of the simulation verification process. In addition, the first verification result and the second verification result obtained by the first cache controller and the second cache controller are compared periodically to realize accurate verification of the internal logic of the controller. The verification depth and the accuracy of abnormal positioning are increased, thereby improving the accuracy of the cache controller verification, and accurately positioning the abnormal position in the verification process in the case of abnormality. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other related drawings can be obtained without creative labor on the basis of these drawings.

[0042] Figure 1 A flowchart of a cache controller verification method in an embodiment;

[0043] Figure 2 A specific scenario diagram of a cache controller verification method in an embodiment;

[0044] Figure 3 Another specific scenario diagram of a cache controller verification method in an embodiment;

[0045] Figure 4 A flowchart of an extension scheme of a cache controller verification method in an embodiment;

[0046] Figure 5A flowchart of a refinement of the cache controller verification method in one embodiment;

[0047] Figure 6 A flowchart of another refinement of the cache controller verification method in one embodiment;

[0048] Figure 7 An exemplary block diagram of a cache controller verification apparatus in one embodiment;

[0049] Figure 8 An exemplary internal block diagram of a computer device in one embodiment. DETAILED DESCRIPTION

[0050] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0051] It should be noted that the terms "first", "second", and the like used herein can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "include" and "have" and any variations thereof used herein are intended to cover non-exclusive inclusion. The term "multiple" used herein refers to two or more. The term "and / or" used herein refers to one of the options or any combination of multiple options.

[0052] In the cache controller verification process, the protocol interface verification method only verifies the function by monitoring the external interface signals. This method cannot obtain the internal request data and data sequence information corresponding to the interface signals, which leads to the inability to capture the request data and data sequence in the verification process, and the abnormal position cannot be located.

[0053] For example, in the cache controller verification scenario of a multi-core processor system, when the concurrent request sequence from multiple processing cores is processed by the first cache controller, the interface signals are monitored to comply with the communication protocol specification. However, since the request data and data sequence cannot be obtained, when a cache miss error occurs, the abnormal request or data sequence cannot be determined, thereby making it difficult to locate the abnormal position in the verification operation, and the uncertainty of the verification result is increased.

[0054] If the above problems are not solved, the request data and data sequence cannot be determined, which may lead to functional defects being discovered only after the chip is manufactured, which will increase the repair cost. In addition, insufficient verification may lead to functional errors in actual operation, affecting the reliability of the entire computer system.

[0055] In one embodiment, a cache controller verification method is provided. This embodiment illustrates the application of this method to a cache controller verification system. It is understood that this method can also be applied to other verification platforms and implemented through interaction between multiple modules in the cache controller verification system.

[0056] For ease of understanding, the key terms in this embodiment are explained below, wherein:

[0057] A cache controller is a hardware unit used to manage data transfer between cache memory and main memory. Its main function is to improve data access speed by storing frequently accessed data, thereby reducing access latency to main memory.

[0058] The first cache controller refers to the cache controller entity that is to be functionally and performance verified. The first cache controller is the object under test in the verification process, and its behavior and state are the objects that need to be monitored during verification.

[0059] The second cache controller is a virtual cache controller used to simulate and verify the first cache controller. The second cache controller is built in a software or hardware simulation environment, and its storage logic is consistent with that of the first cache controller. It is used to reproduce the behavior of the first cache controller in a controlled environment to simulate the verification process of the first cache controller.

[0060] In this embodiment, as Figure 1 As shown, the cache controller verification method includes steps 11 to 14. Wherein:

[0061] Step 11: Listen to the control signal of the first cache controller and determine the first request sequence based on the control signal.

[0062] Among them, control signals can refer to electrical or logical signals received or sent by the first cache controller to instruct the first cache controller to perform specific operations or change its state. These control signals constitute the basis for the interaction between the first cache controller and the external environment, and are also the basis for the first cache controller to perform the verification process.

[0063] The first request sequence refers to a series of request instructions arranged in chronological order, determined by control signals received or issued by the first cache controller. This sequence reflects the external requests received or pending processing by the first cache controller within a specific verification cycle.

[0064] It should be noted that listening to the control signals of the first cache controller and determining the first request sequence based on these control signals can be achieved by setting a hardware probe or logic analyzer at the interface of the first cache controller to capture its input and output electrical signals in real time.

[0065] Here, the read / write request, address, data, etc. can be recorded and arranged in the time sequence of their occurrence, thereby forming a request sequence reflecting the workload of the first cache controller.

[0066] For example, when the first cache controller receives a read request signal, the signal along with its corresponding address information can be recorded and serve as a sequence element in the first request sequence.

[0067] Step 12: Control the second cache controller to perform verification operations corresponding to the order of control signals in the first request sequence, obtaining a second verification result of the second cache controller for simulation verification.

[0068] Here, the first cache controller is the cache controller to be verified, and the second cache controller is a virtual cache controller simulating the first cache controller for verification. The storage logic of the second cache controller is consistent with that of the first cache controller.

[0069] Here, the second verification result refers to the simulation result obtained by controlling the second cache controller to simulate the first cache controller and performing verification operations synchronized with the order of control signals in the first request sequence of the first cache controller. Specifically, the simulation result can be the expected result of the second cache controller simulating the verification behavior of the first cache controller based on the first request sequence consistent with the execution order of at least one control signal in the first cache controller.

[0070] To achieve the simulation and synchronous execution of the second cache controller on the first cache controller, the first request sequence can be used as input to drive the second cache controller to perform corresponding operations in the simulation environment with the same time step or event order as the first cache controller.

[0071] For example, if the first request sequence contains a write operation to a specific address, the second cache controller will also perform a write operation to the address in the same cycle of simulation and record its internal state changes and output results, thereby obtaining the second verification result.

[0072] Step 13: Monitor the first cache controller to perform verification operations based on the first request sequence, obtaining a first verification result.

[0073] Here, the first verification result can refer to the running result obtained by monitoring the first cache controller to perform verification operations based on the first request sequence. This result reflects the performance of the first cache controller in actual operation.

[0074] It should be noted that the first cache controller performs verification operations based on the first request sequence and obtains a first verification result. The verification result of the first cache controller performing the verification operation can be detected by setting a monitoring point in the first cache controller or at a key interface thereof.

[0075] When the first cache controller performs cache lookup, data access, state update and other verification operation steps in response to the request in the first request sequence, the running output, internal state change or memory access behavior generated thereby can be recorded.

[0076] For example, when the first cache controller performs a read operation and hits the cache, the read data corresponding to the read operation performed by the hit test and the hit state can be recorded as the first verification result.

[0077] Step 14, period comparison of the first verification result and the second verification result is performed to obtain a target verification result for locating an abnormal period.

[0078] The target verification result refers to a result for locating an abnormal period obtained after period comparison. The result can indicate at which time point or operation link the first cache controller has an inconsistent behavior with the expectation.

[0079] It should be noted that the period comparison of the first verification result and the second verification result can refer to a process of comparing the first verification result and the second verification result one by one in each verification period. Through comparison, the behavior difference of the two controllers in a specific period can be found.

[0080] Here, since the first verification result and the second verification result are respectively obtained by the first cache controller and the second cache controller after performing the verification operation corresponding to the control signal in the first request sequence, the control signal in the first request sequence can include verification steps of multiple periods, and correspondingly, the first verification result and the second verification result can include verification results of each period corresponding to the control signal.

[0081] Therefore, after obtaining the first verification result and the second verification result, the two verification results can be compared one by one in each verification period. In the case of an abnormality, the specific verification period where the abnormality occurs can be determined.

[0082] For example, in a specific clock period, if the data output by the first cache controller is inconsistent with the data simulated by the second cache controller, or there is a difference in the internal state, the period will be marked as an abnormal period. Thus, the first cache controller can be identified as having an inconsistent behavior with the expectation in a specific operation period, thereby obtaining a target verification result for locating an abnormal period.

[0083] As an example, as shown inFigure 2 As shown, Figure 2 is a schematic diagram of a specific scenario. Among them, the second cache controller cache ref is a virtual model for simulating and verifying the first cache controller RTL Cache. The core data structure of cache ref includes an 8x8 cache line array CL_array, which is used to store the calculation period age, address addr and allocatable state can_allocate of each cache line Cache line; and an address hit association array addr_hit_array, whose key is the address, and the value value contains the hit / miss / hom state and the corresponding way index way_idx and set index set_idx.

[0084] The control signals specifically include the access request signal request received by the first cache controller RTL Cache, a plurality of pop valid signals rtl_pop_vld of the internal queue, and an interface reset signal, etc. These signals are monitored by a hardware probe or a logic analyzer, and are sorted into the first request sequence in time sequence.

[0085] Specifically, the request request obtained from the collection sequence sq is stored in the request queue queue, and the prefetch queue type2_prefetch_q is calculated based on the request type. Thus, the collected signals and the request together constitute the first request sequence reflecting the working load of RTL Cache. Here, it should be noted that cache ref can detect different pop valid signals of the first cache controller, including: the pop valid signal miss_req&rtl_pop_vld of the non-execution queue, the pop valid signal sq_req0&rtl_pop_vld of the execution queue with sequence number 0, the pop valid signal sq_req1&rtl_pop_vld of the execution queue with sequence number 1, the pop valid signal sq_req2&rtl_pop_vld of the execution queue with sequence number 2, and the pop valid signal sq_req3&rtl_pop_vld of the execution queue with sequence number 3. After collecting these signals and requests, the corresponding results and execution processes can be synchronized to the second cache controller cache ref.

[0086] To realize synchronization, the first request sequence is taken as input to drive the second cache controller Cache ReferenceModel The second cache controller performs operations in the same event order as RTL Cache.

[0087] For example, when the RTL Cache responds to a request and the request is not missed, the second cache controller, the Cache Reference Model (cache ref), can update the computation cycle `age_update` and computation path `way_allocate` recorded in the internal `CL_array` during the process of updating the states of the internal `CL_array` and `addr_hit_array`. When the RTL Cache responds to a request, but the request is missed, it can directly update the computation path `way_allocate` recorded in the internal `CL_array`.

[0088] To ensure consistency between the Cache Reference Model and the RTL Cache state, the offset group queues `offset_group0 / 1 / 2 / 3_queue` in the Cache Reference Model are modeled by collecting the `sq reset` signal from the RTL interface. Based on the collected pop_vld signals of the various FIFO queues within the RTL, such as `prefetch_fifo` and `miss_fifo`, the Cache Reference Model is controlled to synchronously access the cache during RTL cache access. This ensures that the internal states of both sides, such as cache line allocation, replacement strategy, and hit status, remain consistent at the time of access. For example, upon receiving the `sq reset` signal, the cache line allocation information can be updated to maintain consistency, and the corresponding record's computation branch `way_allocate` can be further updated.

[0089] As an example, such as Figure 3 As shown, Figure 3For another specific scenario. After determining the first verification result and the second verification result, the requests actually sent out by the RTL Cache can be collected and stored in the actual transaction queue act_il1_lsc_req_trans_queue, and the data in the queue is the first verification result of the actual behavior of the RTL Cache. The second verification result generated by the Cache Reference Model, i.e., the expected result, is stored in the expected transaction queue exp_il1_lsc_req_trans_queue. When there is data in the actual transaction queue (act_il1_lsc_req_trans_queue), a transaction is popped out from it, and a corresponding transaction is also popped out from the expected transaction queue (exp_il1_lsc_req_trans_queue). The two transactions are compared item by item, for example, the request type, target address, data content, timing, etc. If both parties are consistent in all comparison items, the verification passes, and the comparison result that the actual transaction queue is consistent with the expected transaction queue is obtained; if there is any inconsistency, an error is reported, and the abnormal verification period or specific operation step can be accurately located according to the comparison time.

[0090] In the above cache controller verification method, the embodiment of the application obtains the first verification result by simultaneously listening to the actual verification operation of the first cache controller based on the first request sequence, and performs period-by-period comparison on the two results to obtain the target verification result. In this way, the listening to the control signal of the first cache controller is introduced, and the first request sequence is determined according to the listened control signal, so that each request received by the first cache controller and the order in which it occurs can be captured. This makes the verification process no longer rely only on the compliance of the external protocol, but can go deep into the specific request content and execution order, and immediately identify and locate the abnormal period. This period-by-period and operation-by-operation comparison improves the accuracy of abnormal positioning, overcomes the defect that the existing method cannot locate the abnormal position, provides a more comprehensive, accurate and efficient cache controller verification method, and improves the depth of verification and the ability of problem positioning.

[0091] In an exemplary embodiment, the first cache controller and the second cache controller have the same storage logic, which includes a storage architecture specification and storage data content.

[0092] Here, the storage logic refers to the rules and mechanisms for managing data storage and access inside the cache controller. Among them, the storage architecture specification defines the physical and logical organization of the cache, such as the capacity of the cache, the size of the cache line, the degree of group association, the data replacement policy, and the write policy, etc. The storage data content refers to the data currently actually stored by the cache controller, including the specific data of each cache line, valid bits, and state information, etc.

[0093] It should be noted that the first cache controller and the second cache controller have the same storage logic, which is the basis for ensuring that the virtual controller behavior is consistent with the actual controller. Building a virtual original second cache controller means creating a simulated entity in a software or simulation environment according to the design specifications of the first cache controller before verification begins. This construction process can be implemented through programming, for example, using a hardware description language to describe the behavior of the cache controller, or using a high-level programming language to build a functional model. The design documents of the first cache controller need to be referred to during construction to ensure that the virtual controller is consistent with the controller to be verified in terms of structure and function.

[0094] In this embodiment, as shown in FIG. 1, before step 11, the cache controller verification method provided by the embodiment of the application further includes steps 101 and 103, wherein: Figure 4

[0095] Step 101, according to the storage architecture specifications of the first cache controller, a virtual original second cache controller is built.

[0096] The data structure of the second cache controller includes a cache line array and an address hit association array.

[0097] Here, the cache line array is a data structure used in the virtual cache controller to simulate the actual cache storage area, and each element represents a cache line, which can be used to record the read-write cycle and read-write address of the cache line and the like.

[0098] In addition, the address hit association array is an association array corresponding to the cache line array, which can be used to record the hit state of each cache line when read, that is, whether the read-write cycle and read-write address recorded in the cache line array are hit in the cache.

[0099] Step 102, the storage data content in the first cache controller is obtained.

[0100] The storage data content includes a storage state and a hit state.

[0101] Here, the current internal state of the storage data content in the actual first cache controller can be read through a specific interface or debugging mechanism, including the storage state and the hit state of the storage data content.

[0102] ​It should be noted that the storage state refers to the state information of the data in the cache line when the data is stored in the preset position in the cache data line. The storage state can be used to reflect the content and attributes of the data in each cache line. Specifically, the storage state can include the calculation period, address information, and information whether each cache line can be read. The hit state refers to whether the data in a certain address line exists in the cache when the address line is read, and whether the data is hit when the read is performed.

[0103] In step 103, the storage state and the hit state in the first cache controller are updated to the cache line array and the address hit association array in the original second cache controller respectively, to obtain the second cache controller.

[0104] After the virtual original second cache controller is constructed, and the storage state and the hit state of the storage data content in the first cache controller are obtained, the storage state and the hit state of each cache line obtained from the first cache controller can be written into the corresponding positions of the cache line array and the address hit association array of the virtual second cache controller, so as to synchronize the real-time state of the first cache controller to the second storage controller. In this way, it is ensured that the internal state of the virtual controller is completely consistent with that of the actual controller when the simulation verification starts.

[0105] Specifically, the address hit association array of the virtual second cache controller can be constructed or updated according to the mapping relationship between the cache line address obtained from the first cache controller and the hit state in the cache line address, so as to ensure that the virtual controller can correctly simulate the address search and hit judgment process.

[0106] As an example, a software-simulated hardware architecture with a data type of 8x8 can be constructed according to the storage architecture specification of the first cache controller, including a cache line array (CL_array) and an address hit association array (addr_hit_array). The CL_array can be used to store the age, addr, and can_allocate corresponding to the cache line, that is, the CL_array can be used to record the state information of the usage period, the read address, and whether the cache line can be allocated. The addr_hit_array as the association array of the CL_array includes two dimensions of key and value. The key dimension can record the address information address of each cache line in the CL_array, and the value dimension can record the hit state of the corresponding cache line and the memory address index information of the cache line in the overall storage structure. Here, the hit state of each cache line includes hit / miss / hom, and the memory address index information includes the way index way_idx and the set index set_idx.

[0107] In the embodiment of the application, before the verification starts, the virtual second cache controller can be accurately constructed according to the storage architecture specification of the first cache controller, and the initial storage data content of the first cache controller including the storage state and the hit state is completely synchronized to the corresponding data structure of the virtual controller. When the second cache controller starts the simulation verification, the internal state of the second cache controller is completely consistent with the first cache controller to be verified, thereby providing an accurate initial reference for subsequent synchronization verification operations. Thus, the deviation of the verification result caused by the mismatch of the initial state can be effectively avoided, the accuracy and reliability of the cache controller verification are significantly improved, and the positioning of the abnormal period is more accurate.

[0108] In an exemplary embodiment, the first request sequence includes a hit test request signal, and the hit test request signal is used for hit test on the first cache controller, as shown in Figure 5 As shown, by listening to the hit test request signal of the first cache controller, the corresponding first request sequence is generated, and the second cache controller is controlled to perform the simulation verification process synchronized with the first cache controller according to the first request sequence, to obtain the second verification result after the simulation verification of the second cache controller. The steps include step 11 and step 12, wherein step 11 includes step 111 to step 112, and step 12 includes step 121 and step 122. Wherein:

[0109] Step 111, when it is detected that the first cache controller performs the hit test in response to the hit test request signal in the first request sequence, the hit test request signal is acquired.

[0110] The hit test request signal is a control signal for triggering the cache controller to perform the hit test, and the hit test verification corresponding to the hit test request signal is one of the verification methods for the cache controller. The hit test request can be used to actively detect the hit or miss behavior of the cache controller under specific address access, and is a key means for verifying cache data consistency and address mapping logic.

[0111] The hit test request signal can be a specific instruction code, for example, a CACHE_HIT_TEST instruction defined in a bus protocol; or a specific address access mode, for example, accessing a preset test address range, which is recognized by the cache controller as a hit test request.

[0112] Step 112, the hit test request signal is written into the second request sequence to obtain the first request sequence.

[0113] The second request sequence is the original request sequence, and the second request sequence is a sequence including at least one control signal. The first request sequence is a sequence including at least one control signal and a hit test request signal.

[0114] Here, as a refinement of verifying the second cache controller, the first request sequence includes a plurality of control signals, and any control signal can be a hit test request signal. Before monitoring the hit test request signal of the first cache controller, the second request sequence currently verified by the first cache controller can be obtained, and at least one control signal in the second request sequence is used as at least one verification period of verifying the second cache controller. After monitoring the hit test request signal of the first cache controller, the hit test request signal can be updated in the second request sequence to obtain a new request sequence, that is, the first request sequence.

[0115] Step 121, according to the order of at least one control signal in the first request sequence, control the second cache controller to perform a verification operation corresponding to each control signal.

[0116] After determining the first request sequence, the second cache controller can be controlled to perform a verification operation corresponding to each control signal according to the order of the control signal in the first request sequence.

[0117] Step 122, in response to the hit test request signal, control the second cache controller to perform a hit test corresponding to the hit test request signal to determine a corresponding hit result, and obtain a second verification result.

[0118] After the virtual second cache controller receives the hit test request signal in the first request sequence, the hit test logic corresponding to the control signal in the first request sequence can be simulated and executed.

[0119] For example, the second cache controller can determine whether the request address hits the cache according to the internal simulated cache state, including cache line data, address tag, valid bit, etc., and generate a corresponding hit or miss result.

[0120] The above embodiment enhances the comprehensiveness and accuracy of cache controller verification by incorporating the hit test request signal into the first request sequence and ensuring that the second cache controller can respond synchronously and perform the corresponding hit test. Specifically, during the verification process, the control signals of the first cache controller can be continuously monitored. Once the hit test request signal issued by the first cache controller is detected, it can be integrated into the original request sequence to form a first request sequence containing general control signals and specific hit test request signals. The second cache controller will strictly follow the order of this first request sequence to perform the corresponding verification operation. For general control signals, the second cache controller performs regular simulation operations; when encountering a hit test request signal, the second cache controller simulates the first cache controller to perform the same hit test and generates the corresponding hit result. In this way, the second verification result not only contains the simulation behavior under the general control signal, but also contains the hit result under the specific hit test scenario. This ensures that the behavior of the first cache controller when performing the hit test can be accurately simulated and predicted by the second cache controller, which helps to improve the reliability and efficiency of cache controller verification and ensures the correctness of the cache controller under various operation scenarios.

[0121] In particular, during the process of simulating the second cache controller to perform verification operations synchronized with the first cache controller, the consistency of the state information of the second cache controller and the first cache controller in multiple aspects needs to be maintained, thereby improving the accuracy and effectiveness of the simulation verification of the second cache controller.

[0122] Specifically, before or after controlling the second cache controller to perform verification operations with the first cache controller, the working state of each cache line, the address allocation state of the memory, and the attribute state of the second cache controller and the first cache controller can be maintained consistent.

[0123] In addition, the access state of each line of the second cache controller and the first cache controller can also be maintained consistent.

[0124] Here, it should be noted that in order to ensure the accuracy of the verification results of the second cache controller and the first cache controller when performing verification operations, the consistency of more different aspects of the second cache controller and the first cache controller during operation can be maintained as much as possible, so that the second cache controller can simulate the verification environment and verification steps close to the first cache controller.

[0125] In a possible implementation of the first aspect of maintaining consistency of the state of the plurality of aspects, after the step of controlling the second cache controller to perform a hit test corresponding to the hit test request signal to determine a corresponding hit result, obtaining a second verification result in response to the hit test request signal, the cache controller verification method further comprises a step of maintaining consistency of the working state between the second cache controller and the first cache controller, comprising:

[0126] (1) monitoring a return interface of the memory access of the first cache controller to obtain a first monitoring result.

[0127] The first monitoring result is used to determine an uncompleted transaction in the memory access of the first cache controller.

[0128] Here, the return interface of the memory access is a channel for data interaction between the first cache controller and an external memory such as a main memory or a next-level cache, and the return interface of the memory access can receive response information, data return status and other key signals of the memory access request.

[0129] By monitoring the interface, the data flow and the control flow between the first cache controller and the memory can be obtained in real time, so that the dynamic information of the memory access of the first cache controller is obtained. For example, a dedicated bus protocol analyzer or a signal capture module can be deployed in the verification platform to monitor and record all signal activities on the return interface of the memory access in real time; or in a simulation environment, the return status of the memory access of the first cache controller model is obtained by accessing the corresponding port signal.

[0130] It should be noted that the first monitoring result is used to determine an uncompleted transaction in the memory access of the first cache controller, and the uncompleted transaction refers to a memory operation whose access request has been sent to the external memory but for which a complete response or data return has not been received. These uncompleted transactions usually make the related cache lines in an intermediate state, such as a data filling waiting state or a lock state.

[0131] The request ID, address, data valid signal and completion signal and other information that can be contained in the first monitoring result are key bases for identifying these uncompleted transactions. For example, by comparing the sent request and the received response, if the request has been sent but the corresponding response has not arrived, it can be determined as an uncompleted transaction; or a transaction tracking table is maintained to record all sent memory requests, and when a response is received, it is marked as completed, and the uncompleted request is an uncompleted transaction.

[0132] (2) determining a data return state corresponding to each cache line in the first cache controller according to the uncompleted transaction in the memory access determined by the first monitoring result.

[0133] The data return state can be used to reflect whether the cache line is waiting for the data returned by the external memory. When there are unfinished transactions, these transactions need to be associated with specific cache lines inside the first cache controller to determine which cache lines are in the state of waiting for data return.

[0134] For example, for each unfinished transaction, according to the memory address requested by it, the corresponding cache line in the first cache controller can be accurately located, and its data return state is marked as "waiting for data" or "data to be filled"; or by querying the cache line state register inside the first cache controller, combined with the address information of the unfinished transaction, the data return state of the corresponding cache line is updated or confirmed.

[0135] (3) According to the data return state of each cache line in the first cache controller, the working state of each cache line in the cache line array of the second cache controller is set to maintain the consistency of the working state of each cache line in the first cache controller and the second cache controller.

[0136] Here, the consistency of the working state of the cache line is a key link for accurate simulation verification. By synchronously mapping and updating the data return state of the cache line in the first cache controller due to memory access to the working state of the corresponding cache line in the second cache controller, it can be ensured that the second cache controller can accurately simulate the internal state of the first cache controller when processing memory access.

[0137] For example, if a cache line in the first cache controller is in the "waiting for data filling" state due to waiting for data, the corresponding cache line in the second cache controller should also be set to the same "waiting for data filling" allocation state.

[0138] In this way, by real-time monitoring the memory access return interface of the first cache controller, accurately identifying unfinished transactions, and synchronously updating the working state of the cache line of the second cache controller, the problem that the allocation state of the cache line of the first cache controller is inconsistent with the state of the second cache controller due to unfinished transactions caused by memory access of the first cache controller in the cache controller verification process is effectively solved, the accuracy and reliability of the cache controller verification are improved, the deviation of the verification result caused by the state mismatch is avoided, and the cycle comparison can more accurately locate the exception, thereby improving the verification efficiency and the accuracy of problem positioning.

[0139] In a possible implementation of the second aspect of maintaining consistency of the state of multiple aspects, after the step of controlling the second cache controller to perform a hit test corresponding to the hit test request signal in response to the hit test request signal to determine a corresponding hit result to obtain a second verification result, the cache controller verification method further includes a step of maintaining consistency of the address allocation state between the second cache controller and the first cache controller, including:

[0140] (1) Listen to the interface reset event of the first cache controller to obtain a second listening result.

[0141] The second listening result includes an address offset when the first cache controller performs data reading.

[0142] Here, in the cache controller verification process, especially after the to-be-verified unit in the first cache controller experiences an interface reset event, the address allocation state in the internal address allocation state of the first cache controller may change. If the second cache controller as a virtual simulation unit fails to timely perceive and synchronize these changes, the internal state will deviate from the first cache controller, resulting in distorted simulation verification results.

[0143] It should be noted that the address offset is a parameter used to accurately locate the data storage address in memory access. After the reset event occurs, the cache controller may reinitialize its internal address allocation logic, resulting in a change in the address offset. Obtaining the address offset can synchronize the change of the address offset in the first cache controller in the second cache controller.

[0144] (2) Synchronize the address offset to the offset grouping queue in the second cache controller to maintain consistency of the address allocation state between the first cache controller and the second cache controller.

[0145] The offset grouping queue is a data structure in the second cache controller for managing the address allocation state.

[0146] After obtaining the address offset of the first cache controller, the address offset can be synchronized to the offset grouping queue in the second cache controller. In this way, the virtual second cache controller is ensured to be consistent with the actual first cache controller in terms of address allocation logic, so that the address allocation state after the reset event can be consistent with the first cache controller.

[0147] Therefore, by synchronizing the address offset to the offset packet queue in the second cache controller, the problem that the address allocation states of the first cache controller and the second cache controller may not be consistent after a reset event is effectively solved, and it is ensured that the second cache controller can accurately simulate the internal address allocation behavior of the first cache controller, thereby significantly improving the accuracy and reliability of the entire cache controller verification process, and avoiding verification result deviation or misjudgment caused by inconsistent states.

[0148] In a possible implementation in the third aspect of maintaining consistency of the states, after the step of controlling the second cache controller to perform a hit test corresponding to the hit test request signal to determine a corresponding hit result to obtain a second verification result in response to the hit test request signal, the cache controller verification method further includes a step of maintaining consistency of the attribute states between the second cache controller and the first cache controller, including:

[0149] (1) updating the state information of the second cache controller according to the second verification result, so as to maintain consistency of the state of the second cache controller and the attribute state of the first cache controller.

[0150] The state information at least includes calculation period information and calculation path information corresponding to each cache line in the second cache controller.

[0151] The second verification result can reflect the output or behavior of the second cache controller after simulating the first cache controller to perform the verification operation.

[0152] After determining the second verification result, the state information of the second cache controller is updated according to the second verification result, which can use the result of simulation verification to calibrate or adjust the internal state of the virtual cache controller, so as to maintain consistency with the first cache controller.

[0153] It should be noted that the attribute state consistency between the first cache controller and the second cache controller can be used to indicate that at the end of each verification period, the key state variables in the second cache controller should match the state of the first cache controller at the end of the same period.

[0154] The calculation period information can be a cumulative verification period or a cumulative number of times of related operations of the cache line, and can be used to track the life cycle and verification timing behavior of the cache line. For example, when a cache line is allocated, when the cache line is written with data, and when the cache line is marked, a field can be added to the data structure of each cache line in the second cache controller to store the verification period number of the last time the cache line is modified or accessed. Alternatively, a global period counter can also be maintained, and the value of the current period counter is recorded into the corresponding cache line state information when the state of the cache line changes.

[0155] The computation path information can be a sequence of events or operation path that leads to the current state of the cache line, and can be used to understand the cause-effect relationship of the path link before and after the state change of the cache line, which is particularly useful for debugging and locating complex problems. For example, which type of request (read, write, prefetch) a cache line enters the cache through, and which state transitions it has experienced. This can be achieved by including a small history buffer in the data structure of each cache line, which stores the request type, address and result of the last few operations on the cache line. Alternatively, a state transition graph or event log can also be maintained for each cache line during the simulation process, recording all key transitions from the initial state to the current state.

[0156] In this way, by actively updating the state information of the second cache controller, especially the computation cycle information and the computation path information of each cache line, after the second cache controller completes the simulation verification and obtains the second verification result. In this way, it is ensured that the internal state of the second cache controller, including the content and operation history of its cache lines, can be continuously consistent with the actual cycle state of the first cache controller. By obtaining and updating these key computation cycle information and computation path information, it is possible to prevent the virtual model from accumulating state errors during long-time verification, making the cycle comparison between the first verification result and the second verification result more reliable and effective, so as to more accurately locate the actual existing abnormalities in the first cache controller.

[0157] In other possible implementations of maintaining consistency in multiple aspects, after the step of controlling the second cache controller to perform a hit test corresponding to the hit test request signal in response to the hit test request signal to determine the corresponding hit result to obtain the second verification result, the cache controller verification method further includes a step of maintaining access state consistency between the second cache controller and the first cache controller, including:

[0158] (1) Listen to the access request signal of the first cache controller.

[0159] The access request signal is a control instruction that triggers the cache controller to perform data read / write operations.

[0160] During the verification process, after the first cache controller receives an access request signal from the system or test environment, it can start the corresponding data access process and listen to the access request signal to capture the access request signal of all access activities of the first cache controller in time.

[0161] (2) When listening to the data access of the first cache controller in response to the access request signal, obtain the access request signal.

[0162] Here, the access request signal can be acquired to record the attribute information of the signal completely, for example, the signal type of reading or writing, the target address, the associated data content, and the timing information, etc. Each valid access of the first cache controller will change the state of its internal cache line. If the second cache controller fails to learn and reproduce these access operations in time, the internal cache state will gradually differ from the first cache controller, resulting in simulation misalignment in subsequent hit test or data consistency check.

[0163] It should be noted that the access request signal is the core input to drive the cache state change. By acquiring the signal in real time, the second cache controller can be provided with completely consistent access stimulus, which is the basis for maintaining the synchronization of the access logic of the two controllers.

[0164] (3) In response to the access request signal, the second cache controller is controlled to perform cache access synchronously to maintain the consistency of the access state between the first cache controller and the second cache controller.

[0165] Among them, the second control signal is a synchronization instruction generated by the verification environment according to the acquired access request signal, which is used to drive the second cache controller.

[0166] After acquiring the access request signal of the first cache controller, the second cache controller can be controlled to perform the same cache access operation as the first cache controller according to the access request signal, including reading or writing to the same address, updating the same cache line state, etc. In this way, it is ensured that the internal data content, replacement strategy state, consistency protocol state, and all other access-related states of the second cache controller are kept in real-time synchronization with the first cache controller after each access event.

[0167] In this way, by listening, acquiring and driving synchronous access operations, an access state synchronization link from the actual controller to the virtual controller is constructed. This method effectively solves the cumulative state deviation problem caused by asynchronous access events, ensures that the second cache controller can be an accurate mirror of the internal access state of the first cache controller at any time, and improves the reliability and accuracy of the verification result.

[0168] In an exemplary embodiment, the second verification result further includes an expected address offset and an expected hit result calculated by the second cache controller after performing the simulation verification process synchronized with the first cache controller. As Figure 6 shown, step 12 further includes steps 12A and 12B of calculating the expected address offset and the expected hit result, wherein:

[0169] Step 12A, acquiring the historical request information of the second cache controller.

[0170] The historical request information includes a historical address offset corresponding to a historical hit test request signal in the first request sequence and a historical hit result.

[0171] Here, the historical address offset refers to an offset of a request address relative to a certain cache line reference address when performing a hit test, and the historical address offset can be used to determine the specific position of data in a cache line. The historical hit result records whether the hit test result of the historical hit test is a hit or a miss.

[0172] The historical request information of the second cache controller can be obtained by obtaining data about past requests accumulated by the second cache controller during the simulation of the first cache controller performing the verification operation. For example, a first in first out (FIFO) queue or a ring buffer can be set inside the second cache controller to store the address, type, timestamp, and corresponding hit or miss result of each control signal. In addition, a special historical record module can also be used, which works in parallel with the second cache controller, captures and stores all the detailed information of the requests processed by the second cache controller in real time, and can be queried as needed.

[0173] Step 12B, according to the historical address offset and the historical hit result, calculating the expected address offset and the expected hit result corresponding to the second cache controller, obtaining the second verification result.

[0174] The second verification result is the expected verification result of the second cache controller during the simulation of the first cache controller performing the verification process, and the second verification result is used for periodic comparison with the first verification result.

[0175] Here, the expected address offset and the expected hit result are the expected behavior results of the second cache controller during the simulation of the first cache controller performing the verification process, which are used as a reference for periodic comparison with the first verification result, and can be used to find abnormal behavior of the first cache controller.

[0176] Specifically, the calculated expected address offset and expected hit result can be encapsulated into a data structure as part of the second verification result.

[0177] In addition, the second verification result can be a record containing multiple fields, in addition to the expected address offset and the expected hit result, it can also include other expected values related to the cache state, such as the expected data return state, the expected data content, etc.

[0178] The above embodiments obtain the historical request information accumulated by the second cache controller in the simulation process, which records the historical address offset corresponding to the past hit test request signal and the historical hit result, and based on the historical data and the storage logic consistent with the first cache controller, accurately calculate the expected address offset and the expected hit result of the second cache controller under the current or expected operation, so that the second verification result is no longer simply synchronized with the external behavior of the first cache controller, but goes deep into the internal logic of the second cache controller and is derived based on its historical state and expected behavior. Therefore, when the first verification result is periodically compared with the second verification result which is more accurate and internally consistent, the subtle abnormalities or errors related to the historical dependence or complex hit / mis-hit scenarios that may exist in the first cache controller can be more effectively identified, thereby significantly improving the accuracy and reliability of the verification.

[0179] It should be understood that, although each step in the flowchart involved in the above embodiments is shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in the above embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by the combination are within the scope of protection of the present application.

[0180] Based on the same inventive concept, the embodiments of the present application also provide a cache controller verification device for implementing the above-mentioned cache controller verification method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more cache controller verification device embodiments provided below can refer to the limitations of the cache controller verification method in the above text, which will not be repeated here.

[0181] In an exemplary embodiment, as shown in Figure 7 a cache controller verification device is provided, comprising: a first monitoring module, a simulation verification module, a second monitoring module and a comparison module, wherein:

[0182] The first monitoring module is configured to monitor the control signal of the first cache controller and determine the first request sequence according to the control signal.

[0183] The simulation verification module is configured to control the second cache controller to perform a verification operation corresponding to the order of the control signals in the first request sequence, to obtain a second verification result of the simulation verification of the second cache controller; the first cache controller is a cache controller to be verified, the second cache controller is a virtual cache controller for the simulation verification of the first cache controller, and the storage logic of the second cache controller is consistent with that of the first cache controller;

[0184] The second monitoring module is configured to monitor the verification operation of the first cache controller based on the first request sequence, to obtain a first verification result.

[0185] The comparison module is configured to periodically compare the first verification result and the second verification result, to obtain a target verification result for locating an abnormal period.

[0186] In one of the embodiments, the cache controller verification apparatus further comprises a creation module, which comprises a virtual construction unit, a data acquisition unit and a synchronization unit, wherein:

[0187] The virtual construction unit is configured to construct a virtual original second cache controller according to the storage architecture specification of the first cache controller; the data structure of the second cache controller comprises a cache line array and an address hit association array.

[0188] The data acquisition unit is configured to acquire storage data content in the first cache controller, the storage data content comprising a storage state and a hit state.

[0189] The synchronization unit is configured to update the storage state and the hit state in the first cache controller to the cache line array and the address hit association array in the original second cache controller respectively, to obtain the second cache controller.

[0190] In one of the embodiments, the first monitoring module comprises a pop request unit and a write sequence unit, wherein:

[0191] The pop request unit is configured to acquire a hit test request signal when it is monitored that the first cache controller performs a hit test in response to the hit test request signal in the first request sequence.

[0192] The write sequence unit is configured to write the hit test request signal into a second request sequence, to obtain the first request sequence; the second request sequence is an original request sequence, the second request sequence is a sequence comprising at least one control signal, and the first request sequence is a sequence comprising at least one control signal and the hit test request signal.

[0193] In one of the embodiments, the simulation verification module comprises a first control unit and a second control unit, wherein:

[0194] The first control unit is configured to control the second cache controller to perform a verification operation corresponding to each control signal in the first request sequence according to an order of the at least one control signal in the first request sequence.

[0195] The second control unit is configured to control the second cache controller to perform a hit test corresponding to the hit test request signal to determine a corresponding hit result and obtain a second verification result in response to the hit test request signal.

[0196] In one of the embodiments, the cache controller verification apparatus further comprises a state maintaining module, and the state maintaining module comprises a first maintaining unit, the first maintaining unit comprises a return state monitoring subunit, a return state confirming subunit and a working state maintaining subunit, wherein:

[0197] The return state monitoring subunit is configured to monitor a return interface of the memory access of the first cache controller to obtain a first monitoring result, and the first monitoring result is used to determine an uncompleted transaction in the memory access of the first cache controller.

[0198] The return state confirming subunit is configured to determine a data return state corresponding to each cache line in the first cache controller according to the uncompleted transaction in the memory access determined by the first monitoring result.

[0199] The working state maintaining subunit is configured to set a working state corresponding to each cache line in an array of cache lines of the second cache controller according to the data return state of each cache line in the first cache controller, so as to maintain the working state of each cache line in the first cache controller consistent with the working state of each cache line in the second cache controller.

[0200] In one of the embodiments, the cache controller verification apparatus further comprises a state maintaining module, and the state maintaining module comprises a second maintaining unit, the second maintaining unit comprises an interface reset monitoring subunit and an interface reset maintaining subunit, wherein:

[0201] The interface reset monitoring subunit is configured to monitor an interface reset event of the first cache controller to obtain a second monitoring result, and the second monitoring result comprises an address offset when the first cache controller performs data reading.

[0202] The interface reset maintaining subunit is configured to synchronize the address offset to an offset grouping queue in the second cache controller, so as to maintain the address allocation state of the first cache controller consistent with the address allocation state of the second cache controller.

[0203] In one of the embodiments, the simulation verification module further comprises a calculation unit, and the calculation unit comprises a historical data obtaining subunit and an expected data calculating subunit, wherein:

[0204] The historical data obtaining subunit is configured to obtain historical request information of the second cache controller; wherein the historical request information comprises a historical address offset corresponding to a historical hit test request signal in the first request sequence and a historical hit result;

[0205] The expected data calculating subunit is configured to calculate an expected address offset and an expected hit result corresponding to the second cache controller according to the historical address offset and the historical hit result, to obtain a second verification result; wherein the second verification result is an expected verification result of the second cache controller in the verification process simulated by the first cache controller, and the second verification result is used for period comparison of the first verification result.

[0206] In one of the embodiments, the cache controller verification apparatus further comprises a state maintaining module, and the state maintaining module comprises a third maintaining unit, and the second maintaining unit comprises an attribute state maintaining subunit, wherein:

[0207] The attribute state maintaining subunit is configured to update state information of the second cache controller according to the second verification result, to maintain the state of the second cache controller consistent with the attribute state of the first cache controller; wherein the state information at least comprises calculation period information and calculation path information corresponding to each cache line in the second cache controller.

[0208] The modules in the above cache controller verification apparatus can be realized by software, hardware and combinations thereof in whole or in part. The modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the modules.

[0209] In one exemplary embodiment, a computer device is provided, which can be a server, and an internal structure diagram of the computer device can be as shown in Figure 8 The computer device comprises a processor, a memory, an input / output interface (I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The database of the computer device is configured to store matrix data. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external terminals through network connection. The computer program is executed by the processor to implement a cache controller verification method.

[0210] Those skilled in the art can understand that Figure 8 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0211] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the cache control method in each embodiment.

[0212] In one embodiment, a readable storage medium is provided, which can be a computer readable storage medium, and the readable storage medium stores a computer program, and the processor executing the computer program to implement the steps of the cache controller verification method in each embodiment.

[0213] In one embodiment, a computer program product is provided, including a computer program, and the computer program is executed by the processor to implement the steps of the cache controller verification method in each embodiment.

[0214] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0215] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0216] The above embodiments only express several implementation ways of the present application, and the description is specific and detailed, but it should not be understood as a limitation to the patent scope of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A cache controller verification method, characterized in that, The cache controller verification method includes: Listen to the control signals of the first cache controller and determine the first request sequence based on the control signals; The second cache controller is controlled to perform a verification operation corresponding to the order of control signals in the first request sequence, and a second verification result is obtained by the second cache controller performing simulated verification; wherein, the first cache controller is the cache controller to be verified, the second cache controller is a virtual cache controller that performs simulated verification on the first cache controller, and the storage logic of the second cache controller is consistent with that of the first cache controller; The first cache controller performs a verification operation based on the first request sequence to obtain a first verification result. The first verification result and the second verification result are compared periodically to obtain the target verification result used to locate the abnormal period.

2. The cache controller verification method according to claim 1, characterized in that, The storage logic includes storage architecture specifications and storage data content. Before the step of listening to the control signal of the first cache controller, the cache controller verification method further includes: Based on the storage architecture specifications of the first cache controller, a virtual, original second cache controller is constructed; wherein, the data structure of the second cache controller includes a cache line array and an address hit association array; Obtain the stored data content in the first cache controller, the stored data content including storage status and hit status; The storage state and hit state in the first cache controller are updated to the cache line array and the address hit association array in the original second cache controller, respectively, to obtain the second cache controller.

3. The cache controller verification method according to claim 1, characterized in that, The first request sequence includes a hit test request signal, which is used to perform a hit test on the first cache controller; The step of monitoring the control signals of the first cache controller and determining the first request sequence based on the control signals includes: When the first cache controller detects that it is performing a hit test in response to a hit test request signal in the first request sequence, the hit test request signal is acquired. The hit test request signal is written into a second request sequence to obtain a first request sequence; wherein, the second request sequence is the original request sequence, the second request sequence is a sequence including at least one control signal, and the first request sequence is a sequence including at least one control signal and the hit test request signal; The step of controlling the second cache controller to perform a verification operation corresponding to the order of control signals in the first request sequence, and obtaining a second verification result from the simulated verification performed by the second cache controller, includes: The second cache controller is controlled to perform a verification operation corresponding to each of the control signals in the order of at least one control signal in the first request sequence. In response to the hit test request signal, the second cache controller is controlled to perform a hit test corresponding to the hit test request signal in order to determine the corresponding hit result and obtain a second verification result.

4. The cache controller verification method according to claim 3, characterized in that, After the step of controlling the second cache controller to perform a hit test corresponding to the hit test request signal in response to the hit test request signal, in order to determine the corresponding hit result and obtain the second verification result, the cache controller verification method further includes: Listen to the return interface of the memory access of the first cache controller to obtain a first listening result; wherein, the first listening result is used to determine the incomplete transactions in the memory access of the first cache controller; Based on the incomplete transactions in memory access determined by the first monitoring result, determine the data return status corresponding to each cache line in the first cache controller; Based on the data return status of each cache line in the first cache controller, the working status of each cache line in the cache line array of the second cache controller is set to maintain the working status of each cache line in the first cache controller and the second cache controller consistent.

5. The cache controller verification method according to claim 3, characterized in that, After the step of controlling the second cache controller to perform a hit test corresponding to the hit test request signal in response to the hit test request signal, in order to determine the corresponding hit result and obtain the second verification result, the cache controller verification method further includes: Listen for the interface reset event of the first cache controller and obtain a second listening result; wherein, the second listening result includes the address offset when the first cache controller reads data; The address offset is synchronized to the offset group queue in the second cache controller to maintain the address allocation status of the first cache controller and the second cache controller consistent.

6. The cache controller verification method according to claim 1, characterized in that, The step of controlling the second cache controller to synchronously execute the verification operation corresponding to the control signal with the first cache controller according to the order of the control signals in the first request sequence, and obtaining the second verification result, further includes: Obtain historical request information of the second cache controller; wherein, the historical request information includes the historical address offset and historical hit result corresponding to the historical hit test request signal in the first request sequence; Based on the historical address offset and historical hit results, the expected address offset and expected hit results corresponding to the second cache controller are calculated to obtain the second verification result; wherein, the second verification result is the expected verification result of the second cache controller in simulating the verification process of the first cache controller, and the second verification result is used to periodically compare the first verification result.

7. The cache controller verification method according to any one of claims 1 to 6, characterized in that, After the step of controlling the second cache controller to synchronously execute the verification operation corresponding to the control signal according to the order of the control signals in the first request sequence, and obtaining the second verification result, the cache controller verification method further includes: Based on the second verification result, the attribute status information of the second cache controller is updated to maintain the status of the second cache controller consistent with the attribute status of the first cache controller; wherein, the status information includes at least the computation cycle information and computation path information corresponding to each cache line in the second cache controller.

8. A cache controller verification device, characterized in that, The cache controller verification device includes: The first listening module is used to listen to the control signals of the first cache controller and determine the first request sequence based on the control signals; The simulation verification module is used to control the second cache controller to perform verification operations corresponding to the order of control signals in the first request sequence, and obtain a second verification result of the simulation verification performed by the second cache controller; wherein, the first cache controller is the cache controller to be verified, the second cache controller is a virtual cache controller for simulating verification of the first cache controller, and the storage logic of the second cache controller is consistent with that of the first cache controller. The second monitoring module is used to monitor the first cache controller's verification operation based on the first request sequence and obtain the first verification result. The comparison module is used to periodically compare the first verification result and the second verification result to obtain the target verification result for locating abnormal periods.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

Images