Method for performing decoding error correction by using additional information and data transmission system

Abstract

A method for performing decoding error correction by using additional information and a data transmission system, the data transmission system comprising a decoder, an encoder and a memory, the operating method comprising: in a decoding stage, obtaining encoded feature information from a predetermined block of the memory, and obtaining encoded information from the predetermined block, then, a decoding core performs a first decoding algorithm on the encoded information to obtain decoded information, and a feature information decoding circuit of a decoder performs a second decoding algorithm to decode the encoded feature information to obtain feature information. Then, the decoding information can be verified through the decoding core according to the feature information, the decoding parameter of the first decoding algorithm is adjusted by referring to the verification result, and then the encoding information is decoded by the first decoding algorithm for adjusting the decoding parameter in one or more iterations to obtain the information.

Description

Technical Field

[0001] The specification discloses a decoding and error correction method, specifically a method and data transmission system that uses additional information to perform decoding and error correction by utilizing memory space to store additional information in order to improve error correction capabilities. Background Technology

[0002] In computing, telecommunications, information theory, and coding theory, error correction codes (ECCs) are tools for error detection and correction during information transmission. Low-density parity-check codes (LDPC codes) are a highly efficient type of error correction code, widely used in fields requiring stable data transmission. Their applications span various modern communication and storage systems demanding high-reliability data transmission, including wireless communication, 4G / 5G mobile communication networks, high-speed fiber optic networks, digital broadcasting, and data storage. For example, they are used as error correction codes in hard drives and solid-state drives (SSDs) to improve the reliability of data read and write operations.

[0003] Today, the demand for data transfer is increasing, and with semiconductor processes becoming more complex and smaller, the demand for memory capacity is also increasing. For example, flash memory (such as NAND flash) technology is gradually moving towards quad-level cell (QLC) or 3D technology. The more layers these technologies stack, the higher the probability of errors in the memory cells. Therefore, to address the problem of increasing data transfer demands and rising errors in memory (such as NAND flash), it is urgent to propose an optimized scheme for error correction code algorithms. Summary of the Invention

[0004] The specification discloses a method and data transmission system for performing decoding error correction using additional information. In the process of decoding and storing information, basic decoding is combined with feature information for auxiliary analysis, which can improve the error correction capability during decoding.

[0005] According to an embodiment, the proposed data transmission system includes a decoder, an encoder, and a memory. The method for performing decoding error correction using additional information includes, during the decoding phase, retrieving encoded feature information from a predetermined block of the memory and retrieving encoded information from a main block therein. Then, the decoder's decoding core executes a first decoding algorithm on the encoded information to obtain decoded information. Next, the decoder's feature information processor executes a second decoding algorithm to decode the encoded feature information to obtain feature information. Subsequently, in the error correction process, the decoding core verifies the decoded information using the feature information, and the decoding parameters of the first decoding algorithm are adjusted based on the verification result. Then, in one or more iterations, the first decoding algorithm with adjusted decoding parameters decodes the encoded information, ultimately obtaining the information.

[0006] Furthermore, in the decoding core, the decoding information obtained by the first decoding algorithm with one or more adjustments to the decoding parameters is verified by the feature information one or more times, and the information obtained by one or more iterations of decoding is obtained.

[0007] In one embodiment, the feature information may be the number of bits with a value of 0 and / or the number of bits with a value of 1 in the initially prepared information, which is then encoded and stored in a predetermined block of the memory. Alternatively, in another embodiment, the feature information may be the number of bytes with one or more fixed patterns in the information. Therefore, the feature information can be used to verify the decoded information obtained by decoding the encoded information through a decoding algorithm. The difference between the two is used to adjust the decoding parameters of the decoding algorithm, enabling rapid convergence of the number of iterations in the decoding algorithm.

[0008] Furthermore, the predetermined block for storing the encoded feature information can be the remaining space after the encoded information is stored in the memory, or it can be an additional specific storage space predetermined by the data transmission system in this memory.

[0009] Furthermore, the predetermined block can store multiple sets of encoded feature information. During the encoding stage, the information is grouped, and statistics are performed on each group to obtain corresponding statistical information, forming feature information. The grouped information is then encoded to form multiple sets of encoded information of the same or different lengths, and the multiple sets of feature information are encoded to form multiple sets of encoded feature information.

[0010] Furthermore, the encoder in the data transmission system includes a feature information acquirer and a feature information encoder. The feature information acquirer is used to count the bit values ​​in the information to obtain statistical information, i.e. feature information, while the feature information encoder is used to encode this feature information.

[0011] Furthermore, the method for generating encoded feature information and encoded information stored in memory by an encoder includes, during the encoding stage, preparing the information and deriving feature information from bit values ​​in feature information acquisition statistics; on the other hand, the feature information encoder may execute a second encoding algorithm to encode the feature information to obtain encoded feature information. Subsequently, the encoded information is stored in a main block of memory, and the encoded feature information is stored in a predetermined block of memory.

[0012] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0013] Figure 1 This diagram illustrates an embodiment of a data transmission system architecture that utilizes additional information to perform decoding and error correction. Figure 2 A schematic diagram illustrating an embodiment of the encoder and block configuration in the memory; Figure 3 A schematic diagram showing another embodiment of the block configuration in the display memory; Figure 4 A flowchart illustrating an example of generating encoded and feature information during the encoding stage; Figure 5 An example diagram showing the generation of encoded information and feature information during the encoding stage is displayed; Figure 6 A flowchart illustrating an embodiment of a method for performing decoding error correction using additional information during the decoding phase; Figure 7 This diagram illustrates an example of using feature information to perform decoding error correction during the decoding phase. Figure 8 A schematic diagram illustrating an embodiment of grouping and encoding information and obtaining statistical information; and Figure 9 This diagram illustrates an example of performing decoding and error correction using feature information with a fixed pattern in the encoded information. Detailed Implementation To provide a technical solution that improves the performance of decoding and error correction for encoded information in data transmission systems, this specification discloses a method for performing decoding and error correction using additional information. This additional information can be feature information derived from statistical information. One implementation of the feature information is to count the codewords in the information, such as calculating the number of bits with a value of 0, the number of bits with a value of 1, or both in a binary codeword. The feature information can then be used to verify the decoded information obtained in each decoding iteration. If the difference between the decoded information and the feature information meets the decoding standard, it indicates successful decoding. Thus, referring to the feature information during decoding can effectively reduce the number of decoding iterations.

[0014] The method of using additional information to perform decoding and error correction can be applied to data transmission systems, and can be referred to for further information. Figure 1 The diagram shows an embodiment of a data transmission system architecture that utilizes additional information to perform decoding and error correction.

[0015] The main components of a data transmission system include, for example: Figure 2 The displayed encoder, Figure 1 The decoder 100 and memory 110 shown are, for example, flash memory, plus other components implemented in collaboration with circuitry and software.

[0016] During the encoding phase, information is encoded (e.g., by executing a first encoding algorithm) to form a codeword (which can refer to the encoded signal) and stored in memory 110. A page in the memory is divided into a predetermined block for storing the encoded information and a dummy block for error correction. Simultaneously with information encoding, characteristics are acquired, such as quantity statistics (e.g., counting the number of bits with values ​​of 0 and / or 1 in binary information, or the number of bytes arranged in a specific fixed pattern). These characteristics are also encoded (e.g., by a second encoding algorithm) and stored in a specific memory block in memory 110, referred to as a predetermined block. The first and second encoding algorithms, which encode the information and characteristic information respectively, can be the same encoding algorithm (requiring the same decoding algorithm for decoding) or different encoding algorithms (requiring different first and second decoding algorithms for decoding).

[0017] according to Figure 1 The schematic diagram of the decoder 100 architecture shown shows that the main block encoding information and the encoded feature information in the predetermined block are obtained from the memory 110. The encoded feature information is then decoded by the feature information decoding circuit 103 (which may include a feature information acquirer and a feature information encoder related circuit, firmware or software element) to obtain the feature information.

[0018] Next, after the decoding core 107 of the decoder 100 obtains the encoded information, it decodes the information using a specific decoding algorithm. It can verify the decoded information with the feature information and then perform error correction. After completing the error correction, the decoding is completed. That is, the information obtained through decoding is stored in the data buffer 120 of the data transmission system and can be provided to the host 130 for use in the information decoded from the memory 110.

[0019] The decoder architecture described in the above embodiments utilizes predetermined blocks of memory to store additional information (such as feature information) to enhance the decoder's error correction capability, and is applicable to various NAND flash memory storage systems.

[0020] Various types of information are stored using memory blocks. Besides utilizing the remaining space after storing encoded information, pre-defined storage spaces within the memory can also be used. (See reference...) Figure 2 The diagram shows an embodiment of the encoder and the block configuration in the memory.

[0021] For error correction codes in memory (such as inverse-array flash memory), current methods involve block-by-block error correction encoding and decoding. It's worth noting that the basic storage unit (i.e., page) of inverse-array flash memory is generally not an integer multiple of the codeword length in a block. Thus, for example, in low-density parity-check codes (LDPC codes), often a type of quasi-cyclic low-density parity-check code (QC-LDPC code), where the codeword length is an integer multiple of a certain cycle length, and the page size of inverse-array flash memory is not an integer multiple of this cycle length, a small amount of unused storage space will remain. This unused storage space is typically filled with dummy data during processing.

[0022] like Figure 2 The schematic diagram shows the block configuration of one of the memory pages of memory 20, including a predetermined block (i.e., the main block) for storing the codeword portion 201 of encoded information and a predetermined block for storing the remaining portion 203 of the encoded information. The information 210 prepared by the data transmission system is encoded by the encoder 200, and feature information is extracted from the bit values ​​in the information. The encoded information is then stored in the main block, corresponding to the codeword portion 201, and the feature information is encoded and stored, corresponding to the remaining portion 203 in the diagram.

[0023] remove Figure 2 In addition to demonstrating the full utilization of storage resources (such as remaining space) in memory for error correction purposes, another embodiment may refer to Figure 3 The schematic diagram of the block configuration in the memory shown shows that, in addition to setting a specific block (called the main block) to store the codeword portion 301, the memory 30 also plans a predetermined block, as shown in the figure, the extra space 303, to store additional information, such as feature information obtained at the same time as the encoded information, in order to improve the decoding speed of the error correction decoding circuit.

[0024] then Figure 4This flowchart illustrates an implementation example of a data transmission system generating encoded and feature information during the encoding phase, and can be used in conjunction with... Figure 5 This diagram illustrates an example of how encoded information and feature information are generated during the encoding phase.

[0025] During the encoding phase of the data transmission system, the information 511 to be encoded is prepared first (step S401). The data transmission system provides an encoder 517. One embodiment can be an encoder using a low-density parity check code. While the encoder 517 encodes the information 511, a feature information acquisition device 513 implemented by software, firmware or in cooperation with hardware counts the bit values ​​of the information 511 in the encoding to obtain statistical information, i.e. feature information (step S403).

[0026] According to the embodiment, encoder 517 executes a specific encoding algorithm (first encoding algorithm) on information 511, that is, encodes codeword 501 stored in a predetermined block in memory 50 to form encoded information (step S405); at the same time, feature information encoder 515 executes a specific encoding algorithm (second encoding algorithm) to encode feature information, resulting in encoded feature information 503 (step S407). The encoded codeword 501 (forming encoded information) is stored in the main block of memory 50 (step S409), and the encoded feature information 503 is stored in additional space in memory 50, such as the predetermined block defined above (step S411).

[0027] During the decoding stage of the data transmission system, refer to Figure 6 The flowchart shown illustrates an embodiment of a method for performing decoding error correction using additional information during the decoding stage. Reference can also be made to... Figure 7 The diagram shows an example of using feature information to perform decoding error correction during the decoding stage.

[0028] During the decoding stage, the data transmission system uses its control procedures to obtain the encoded feature information from a predetermined block of the memory 70 (step S601), and decodes the feature information by the feature information decoding circuit 710 implemented in software, firmware or in cooperation with hardware. According to the embodiment, the algorithm for decoding the feature information can be another decoding algorithm different from the decoding information (such as a second decoding algorithm) (step S603).

[0029] Additionally, the decoder 720 retrieves the encoded information from the main block in the memory 70 (step S605), and executes the decoding algorithm 721 (such as the first decoding algorithm) on the encoded information using the decoder 720. According to the embodiment, during the decoding calculation process using the decoder 720, one or more iterative decoding processes are used to implement the codeword hard decision 725. As shown in the flowchart, the nth decoding algorithm 721 is executed, where n is an integer greater than or equal to 1, to obtain the nth decoding information (step S611). In this embodiment, it starts from the first time, corresponding to obtaining the first decoding information first. Thus, after each decoding calculation, the decoder 720 determines whether the decoding was successful through the program running within it (step S613). If the decoding is successful (yes), the data transmission system obtains the decoding information (step S615); otherwise, if the decoding fails (no), it will determine whether this is the last iteration (step S617). If the number of iterations has reached the system's default maximum number of iterations (yes), it indicates that the decoding has failed, and this process will end (step S619); conversely, if the number of iterations has not reached the maximum number after the decoding fails, it is not the last iteration (no), and the next iteration calculation (n=n+1) will be performed (step S621). After the next iteration 723, the codeword hard decision 725 is performed to obtain the decoding information.

[0030] After obtaining the encoded feature information from the predetermined block of the memory 70 in step S601, and decoding the feature information in step S603, the decoder 720 will use the obtained feature information to verify each (nth) decoding information, that is, to verify the decoding information obtained from the first decoding to the nth decoding (step S607), so that the decoding parameters of the decoding algorithm 721 can be adjusted according to the verification results in each iteration (step S609), that is, to adjust the decoding parameters according to the difference between the feature information and the statistical results of the nth decoding information. After each adjustment of the decoding parameters, the next iteration (n=n+1) 723 is performed, and the decoding algorithm 721 with the adjusted decoding parameters performs the codeword hard decision 725 (step S615), and the decoding steps of step S611 are repeated until the decoding is successful and the decoding information is output (step S615), or until the upper limit of the number of iterations is reached and the decoding is still unsuccessful and the process needs to be terminated (step S619).

[0031] Thus, because each iteration verifies the decoded information obtained each time with information involving the original information (i.e., feature information), and thereby adjusts the decoding parameters of the decoding algorithm, the number of iterations can be effectively reduced, increasing the error correction efficiency. In this way, the decoded information obtained by using the feature information to verify the decoding information obtained by the decoding algorithm 721 (such as the first decoding algorithm) with its decoding parameters adjusted one or more times is obtained after one or more iterations of decoding, finally yielding the decoded information (step S615).

[0032] Here is an example of a decoding algorithm used on the decoding end. When performing each iteration of decoding, comparing with feature information that contains real information can effectively improve decoding performance. One of the steps is to dynamically adjust the decoding parameters of the decoding algorithm when verifying the decoding information obtained in each iteration with feature information. A log-likelihood ratio (LLR) mapping strategy can be adopted. For example, the decoding coefficients in the min-sum algorithm (MinSum) can be dynamically adjusted.

[0033] For example, in the min-sum algorithm of low-density parity-check codes (LDPC), the information (Q) passed from the variable node to the check node is used... ji ) Calculate the extrinsic information (R) of variable nodes ij When performing decoding, a soft decoding coefficient "α" is typically introduced, which is one of the decoding parameters mentioned in the above embodiments, to obtain the decoded information R. ij When calculating, follow the procedure below, where "i" refers to the iteration number and "j" refers to the group number: .

[0034] Based on the group in which j falls, the feature information corresponding to this group is obtained. Therefore, the adjustment of the current soft decoding coefficient "α" is determined based on the difference between the feature information and the current decoding result, thereby improving the success probability and convergence speed of the basic decoding.

[0035] According to the above embodiments, the method of storing encoded information in memory pages in the memory can not only use the entire main block to store encoded information, but also divide the information into multiple groups during the encoding stage. The length and size of these groups may not be the same, and statistics are also performed on each group to obtain multiple statistical information entries. (See reference...) Figure 8 The diagram shows an example of grouping and encoding information to obtain statistical information.

[0036] During the information preparation stage of encoding, the information is divided into multiple groups. Each group of information is statistically analyzed during encoding, resulting in multiple statistical records. Each statistical record can count the number of bits with a value of 0 and / or the number of bits with a value of 1 in each group of information. Similarly, according to the above embodiment, each statistical record can also count the number of bytes with one or more fixed patterns in each group of information.

[0037] Thus, as Figure 8The displayed memory 80 is divided into multiple blocks (1, 2, ... n) in its main area, which respectively store each group of encoded information (group 1, group 2, ... group n). The lengths of the multiple groups of encoded information formed during the encoding stage can be different (but it is not excluded that they can be planned to be the same length). As shown in the figure, it includes group 1 encoded information 801, group 2 encoded information 802 and group n encoded information 803. When encoding each group of information, statistics are performed simultaneously, and corresponding to each group of encoded information, the first statistical information 811, the second statistical information 812 and the nth statistical information 813 are obtained. After the multiple statistical information is encoded, multiple groups of encoded feature information are stored in the predetermined blocks of the memory 80, including the first encoded statistical information 821, the second encoded statistical information 822 and the nth encoded statistical information 823.

[0038] According to yet another embodiment, reference Figure 9 The diagram illustrates an example of using fixed-pattern feature information in encoded information to perform decoding and error correction. This example shows that during the encoding stage, the data transmission system can use software methods to analyze whether there are fixed-pattern permutations in the bit sequence of the information, i.e., fixed patterns formed by multiple arrangements of 0 and 1 bits, such as 000111, 0101010, 1100000111, etc. When binary information has one or more fixed-pattern byte combinations, the number of these fixed-pattern byte combinations can also be used as feature information for error correction.

[0039] During the encoding phase of the data transmission system, fixed-pattern feature information 911 is statistically derived and stored in a predetermined block of memory while encoding information is being encoded. In the decoding phase, the fixed-pattern feature information 911 can be decoded first and used to verify the decoded information obtained in each iteration of the decoding algorithm 917. After the next iteration 919, a hard codeword decision 913 is performed, which can be matched with the fixed-pattern feature information 911 for a matching decision 915. Error correction can even be performed directly based on the fixed-pattern feature information 911 without executing the decoding algorithm 917. Therefore, the fixed-pattern feature information 911 can also effectively reduce the number of iterations in the decoding phase, thereby improving decoding performance.

[0040] An implementation example is proposed here, in which the fixed-style feature information 911 can dynamically adjust the decoding parameters in the decoding algorithm through a verification process. For example, if the information to be encoded contains 3000 1s, but only 2000 1s are decoded during the decoding stage, an offset value can be introduced into the decoding algorithm to increase the probability of decoding 1s. This is a concept of weighting. Because the decoding process is a probabilistic operation, when it is known from the feature information that there are not enough 1s in the decoded information, the offset value is adjusted to make the decoding algorithm probabilistically biased towards 1s, thus increasing the decoding probability of 1s.

[0041] The feature information obtained during the encoding process described above can be represented by counts of bit values ​​0 and 1, fixed-style feature information, or a combination of both. Furthermore, it can utilize grouped feature information obtained from the separate statistical analysis of multiple sets of information. Actual implementation requires consideration of the specific application requirements. Moreover, considering the encoder's hardware capabilities, the decoding method can perform statistical analysis on only a portion of the information, without needing to analyze all the information, thus achieving the goal of improving error correction efficiency.

[0042] In summary, according to the above embodiments of the method for performing decoding error correction using additional information, when using feature information for error correction, since the feature information is relatively short, the error correction code used is relatively simple to design in hardware and does not affect the efficiency of the basic encoding, and can also be decoded quickly at the decoding end. Thus, the disclosed method for performing decoding error correction using additional information can improve the error correction capability and speed of the basic error correction algorithm with only a small increase in hardware cost, and is suitable for data transmission systems with high error correction requirements.

[0043] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.

Claims

1. A method for performing decoding and error correction using additional information, operating in a data transmission system, characterized in that, The method includes: In a decoding stage, an encoded feature information is obtained from a predetermined block of a memory of the data transmission system, and an encoded information is obtained from a main block; The encoded information is decoded using a first decoding algorithm to obtain decoded information; The encoded feature information is decoded using a second decoding algorithm to obtain feature information, wherein the feature information is used to represent the features of the encoded information; The decoding parameters of the first decoding algorithm are adjusted based on the result of verifying the decoding information with the feature information; The encoded information is decoded using the first decoding algorithm with adjusted decoding parameters; The following information was obtained.

2. The method for performing decoding and error correction using additional information as described in claim 1, characterized in that, The decoding information obtained by the first decoding algorithm with one or more adjusted decoding parameters is verified one or more times using the feature information, and the information is obtained by one or more iterative decodings.

3. The method for performing decoding and error correction using additional information as described in claim 1, characterized in that, The feature information is a count of the number of bits with a value of 0 and / or the number of bits with a value of 1.

4. The method for performing decoding and error correction using additional information as described in claim 1, characterized in that, The feature information is the count of bytes with one or more fixed patterns in the information.

5. The method for performing decoding and error correction using additional information as described in claim 1, characterized in that, The predetermined block for storing the encoded feature information is either a remaining space after the encoded information has been stored in the memory of the data transmission system, or a predetermined storage space in the memory.

6. The method for performing decoding and error correction using additional information as described in claim 1, characterized in that, The predetermined block stores multiple sets of encoded feature information. During the encoding stage, the information is grouped into multiple sets of information. After feature acquisition of the bit values ​​of each set of information, multiple sets of feature information are obtained and then encoded to generate the multiple sets of encoded feature information.

7. The method for performing decoding and error correction using additional information as described in claim 6, characterized in that, The lengths of the multiple groups of encoded information formed during the encoding stage are different.

8. The method for performing decoding error correction using additional information as described in any one of claims 1 to 7, characterized in that, The encoded feature information stored in the memory and the method for generating the encoded information include: Prepare the information, and perform feature acquisition on the information to obtain the feature information; The information is encoded using a first encoding algorithm to obtain the encoded information; The feature information is encoded using a second encoding algorithm to obtain the encoded feature information; and The main block of the memory stores the encoded information, and the predetermined block of the memory stores the encoded feature information.

9. A data transmission system, comprising a decoder and a memory, characterized in that, The data transmission system includes: A feature information decoding circuit receives encoded feature information from a predetermined block of the memory, executes a second decoding algorithm, and decodes the encoded feature information to obtain feature information; and A decoding core, electrically connected to the feature information decoding circuit, receives encoded information from a main block. A first decoding algorithm is executed to decode the encoded information to obtain decoded information; wherein the feature information is used to represent the features of the encoded information; The decoding parameters of the first decoding algorithm are adjusted based on the result of verifying the decoded information with the feature information; the encoded information is then decoded using the first decoding algorithm with the adjusted decoding parameters. The following information was obtained.

10. The data transmission system as described in claim 9, characterized in that, In the decoding core, the feature information is used to verify the decoding information obtained by the first decoding algorithm with one or more adjustments to the decoding parameters, and the information is obtained by one or more iterative decodings.

11. The data transmission system as described in claim 10, characterized in that, The feature information is the number of bits with a value of 0 and / or the number of bits with a value of 1.

12. The data transmission system as described in claim 10, characterized in that, The feature information is the count of bytes with one or more fixed patterns in the information.

13. The data transmission system as described in claim 9, characterized in that, The predetermined block for storing the encoded feature information is either a remaining space after the encoded information has been stored in the memory, or a predetermined storage space in the memory.

14. The data transmission system as described in claim 9, characterized in that, The predetermined block stores multiple sets of encoded feature information. In the encoding stage, the information is grouped into multiple sets of information. After statistical analysis of the bit values ​​of each set of information to obtain multiple sets of feature information, the multiple sets of encoded feature information are generated through encoding.

15. The data transmission system as described in any one of claims 9 to 14, characterized in that, The data transmission system further includes an encoder, which includes a feature information acquirer and a feature information encoder. The feature information acquirer is used to acquire the features of the bit values ​​in the information to obtain the feature information, and the feature information encoder is used to encode the feature information.

16. The data transmission system as described in claim 15, characterized in that, The method for generating the encoded feature information and the encoded information stored in the memory using the encoder includes: The information is prepared, and the feature information is obtained by statistically analyzing the bit values ​​in the information using the feature information acquirer; The information is encoded using a first encoding algorithm to obtain the encoded information; The feature information encoder performs a second encoding algorithm to encode the feature information to obtain the encoded feature information; and The encoded information is stored in the predetermined block of the memory, and the encoded feature information is also stored in the predetermined block of the memory.

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