Adaptive output operational amplifier circuit for image signal processor

Abstract

The application discloses an adaptive output operational amplifier circuit for an image signal processor, comprising a differential amplifier circuit, a voltage detection circuit, a shift control circuit and an adaptive output array, the adaptive output array comprising N output units which are identical, N=2 j , j is an integer greater than or equal to 2, the output units have static and non-static states, the current output in the static state is less than the current output in the non-static state, the differential amplifier circuit and the adaptive output array form a feedback loop, and the voltage detection circuit adjusts the working state of each output unit in the adaptive output array in real time according to the output voltage of the differential amplifier circuit and drives the shift control circuit correspondingly; the adaptive output operational amplifier circuit has the advantages that a dynamic load adaptive adjustment mechanism is provided, the driving capacity can be adaptively adjusted according to the load, high driving capacity is achieved under high load, low power consumption is achieved under low load, and energy consumption and driving capacity are compatible.

Description

Technical Field

[0001] This invention relates to operational amplifier circuits, and more particularly to an adaptive output operational amplifier circuit for an image signal processor. Background Technology

[0002] With the rapid development of applications such as smartphone cameras, security monitoring, vehicle imaging, and industrial inspection, image sensors (CMOS image sensors, CIS) and their associated image signal processors (ISPs) are placing higher demands on the performance of operational amplifier circuits.

[0003] In practical applications, the operational amplifier circuit in the image signal processor must provide powerful output driving capabilities in high-load (or large-load) scenarios such as high-speed progressive scanning and high-definition video acquisition, while reducing energy consumption in low-load (or small-load) scenarios such as still photography and low frame rate preview, in order to meet the requirements of portable devices where the image signal processor is located for battery life and energy efficiency.

[0004] However, existing operational amplifier circuit designs for image signal processors generally struggle to balance low power consumption under low load with high drive capability under high load. For example, Chinese patent application CN201510854791.9 proposes an operational amplifier circuit with high capacitive load and low noise suitable for image sensors. This operational amplifier circuit enhances drive capability by introducing a source follower structure at the output stage and adds two additional feedback paths at the output to form a multi-stage operational amplifier circuit, thereby meeting the fast readout requirements of image sensors under high drive current conditions. However, due to the presence of the additional feedback circuit, the overall power consumption of the circuit further increases, and the output of this operational amplifier circuit is fixed, i.e., the drive capability is constant, and it cannot flexibly adjust its drive capability according to real-time changes in load conditions, ultimately leading to a contradiction between power consumption and drive capability. Another example is a programmable gain amplifier circuit for image sensors disclosed in Chinese patent application CN202010381462.8. This programmable gain amplifier circuit achieves multi-level programmable gain adjustment by introducing a sampling capacitor at the input of the operational transconductance amplifier and connecting a feedback capacitor, a switch, and multiple adjustment capacitors in parallel between the input and output of the operational transconductance amplifier, along with a dual-signal channel with a switching structure. However, the output stage of this operational transconductance amplifier has a fixed structure. While it can provide high drive capability in high-load applications, it cannot effectively reduce redundant power consumption in low-load applications, thus presenting a trade-off between power consumption and drive capability. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an adaptive output operational amplifier circuit for an image signal processor with a dynamic load adaptive adjustment mechanism, which can adaptively adjust the driving capability according to the load level, so as to have high driving capability under high load and low power consumption under low load, and achieve energy consumption and driving capability compatibility.

[0006] The technical solution adopted by this invention to solve the above-mentioned technical problem is as follows: an adaptive output operational amplifier circuit for an image signal processor, comprising a differential amplifier circuit, a voltage detection circuit, a shift control circuit, and an adaptive output array; the adaptive output array comprises N identical output units, N=2 j , j is an integer greater than or equal to 2; the output unit has two operating states, static and non-static, and when it is in non-static state, it has two operating modes, PMOS mode and NMOS mode; the output current of the output unit in static state is less than the output current in non-static state; the sum of the output currents of N output units is the drive current of the adaptive output array; the initial operating state of N output units is static; the differential amplifier circuit is used to amplify its input voltage to obtain the amplified voltage signal, i.e., its output voltage, which is output to the voltage detection circuit, and feedback adjustment is performed according to its output voltage and the output voltage of the adaptive output array; the voltage detection circuit is used to determine whether the drive capability of the adaptive output operational amplifier circuit matches the load according to the output voltage of the differential amplifier circuit, and drives the shift control circuit accordingly; the shift control circuit is used to adjust the operating state and non-static operating mode of each output unit in the adaptive output array under the drive of the voltage detection circuit, so as to match the drive current with the load.

[0007] Compared with the prior art, the advantages of the present invention are: an adaptive output operational amplifier circuit is constructed by using a differential amplifier circuit, a voltage detection circuit, a shift control circuit, and an adaptive output array, wherein the adaptive output array includes N identical output units, N=2. jj is an integer greater than or equal to 2; the output unit has two working states, static and non-static, and when it is in non-static state, it has two working modes, PMOS mode and NMOS mode; the current output by the output unit in static state is less than the current output in non-static state; the sum of the currents output by N output units is the drive current output by the adaptive output array; the initial working state of N output units is static; the differential amplifier circuit and the adaptive output array form a feedback loop, and the differential amplifier circuit adjusts its output voltage in real time according to the output voltage of the adaptive output array so that its output voltage can represent the real-time load condition. The voltage detection circuit determines whether the drive capability of the adaptive output operational amplifier circuit matches the load in real time according to the output voltage of the differential amplifier circuit, and drives the shift control circuit accordingly, so that the shift control circuit adjusts the working state and non-static working mode of each output unit in the adaptive output array accordingly, ensuring that the drive current (i.e., drive capability) matches the load level. Thus, this invention has a dynamic load adaptive adjustment mechanism, which can adaptively adjust the drive capability according to the load level, so that it has high drive capability under high load and low power consumption under low load, achieving energy consumption and drive capability compatibility.

[0008] Furthermore, the voltage detection circuit is preset with a high threshold voltage, a common-mode threshold voltage, a low threshold voltage, a working cycle, and a detection cycle. The high threshold voltage is greater than the common-mode threshold voltage, and the common-mode threshold voltage is greater than the low threshold voltage. The shift control circuit is set with a control cycle, and the detection cycle is K times the control cycle, where K = N / 2 - 1. In each working cycle, the voltage detection circuit performs two detection cycles, and in each detection cycle, the shift control circuit performs K control cycles. In each working cycle, when entering the previous detection cycle, the voltage detection circuit determines the output state of the adaptive output operational amplifier circuit (stable, current-carrying, or current-sinking) based on the output voltage of the differential amplifier circuit, and generates a corresponding drive signal output to the shift control circuit, driving it to perform the first stage adjustment of the adaptive output array within K control cycles. When entering the next detection cycle, the voltage detection circuit determines the load level of the current working cycle based on the output voltage of the differential amplifier circuit, and generates a corresponding drive signal output to the shift control circuit, driving it to perform the second stage adjustment of the adaptive output array within K control cycles.

[0009] Furthermore, in the detection cycle preceding each operating cycle, the voltage detection circuit samples the output voltage of the differential amplifier circuit and compares it with the high threshold voltage and the low threshold voltage to determine the output state of the adaptive output operational amplifier circuit in the current operating cycle. If the output voltage is less than or equal to the high threshold voltage and greater than or equal to the low threshold voltage, the output state of the adaptive output operational amplifier circuit in the current operating cycle is a stable state. In this case, the voltage detection circuit drives the shift control circuit to maintain the current state of the adaptive output array for K control cycles. If the output voltage is greater than the high threshold voltage, the output state of the adaptive output operational amplifier circuit in the current operating cycle is a current-sinking state. In each of the K control cycles, the detection circuit drives the shift control circuit to switch one static output unit to NMOS mode relative to the previous control cycle, causing the output voltage of the differential amplifier circuit to drop to less than or equal to the high threshold voltage and greater than or equal to the low threshold voltage. If the output voltage is less than the low threshold voltage, the output state of the adaptive output operational amplifier circuit in the current working cycle is in a current-carrying state. At this time, the voltage detection circuit drives the shift control circuit to switch one static output unit to PMOS mode in each of the K control cycles relative to the previous control cycle, causing the output voltage of the differential amplifier circuit to increase to greater than or equal to the low threshold voltage and less than or equal to the high threshold voltage.

[0010] Furthermore, in the subsequent detection cycle of each operating cycle, the voltage detection circuit samples the output voltage of the differential amplifier circuit and compares it with the common-mode threshold voltage. Combined with the output state of the adaptive output operational amplifier circuit in the current operating cycle, it determines the load level. If the current operating cycle is in a current-sinking state and the output voltage is greater than or equal to the common-mode threshold voltage, it indicates a high load. In this case, the voltage detection circuit drives the shift control circuit to control one static output unit to switch to NMOS mode in each of the K control cycles relative to the previous control cycle. This causes the output voltage of the differential amplifier circuit to decrease and become greater than or equal to the low threshold voltage. Simultaneously, the drive current increases, improving the drive capability. If the current operating cycle is in a current-sinking state and the output voltage is less than the common-mode threshold voltage, it indicates a low load. In this case, the voltage detection circuit drives the shift control circuit to control one NMOS mode output unit to switch to static mode in each of the K control cycles relative to the previous control cycle. This causes the output voltage of the differential amplifier circuit to increase and become less than or equal to the high threshold voltage. Simultaneously, the drive current increases, improving the drive capability. A decrease in current reduces the driving capability. If the current operating cycle is in a current-pull state and the output voltage is less than or equal to the common-mode threshold voltage, it indicates a high load. In this case, the voltage detection circuit drives the shift control circuit to control one static output unit to switch to PMOS mode in each of the K control cycles, relative to the previous control cycle. This increases the output voltage of the differential amplifier circuit, ensuring it is less than or equal to the high threshold voltage. Simultaneously, the driving current increases, improving the driving capability. If the current operating cycle is in a current-pull state and the output voltage is greater than the common-mode threshold voltage, it indicates a low load. In each of the K control cycles, the shift control circuit controls one PMOS mode output unit to switch to static mode, relative to the previous control cycle. This increases the output voltage of the differential amplifier circuit, ensuring it is less than or equal to the high threshold voltage. Simultaneously, the driving current decreases, reducing the driving capability. If the current operating cycle is in a steady state, it indicates that the driving capability matches the load. Regardless of whether the output voltage is greater than or equal to the common-mode threshold voltage or less than the common-mode threshold voltage, the shift control circuit controls the adaptive output array to maintain its current state in all K control cycles.

[0011] Furthermore, the differential amplifier circuit has a positive input terminal, a negative input terminal, and an output terminal; the voltage detection circuit has an input terminal, a first output terminal, a second output terminal, and a third output terminal; the shift control circuit has a first input terminal, a second input terminal, a third input terminal, a first N-bit output terminal, and a second N-bit output terminal; the adaptive output array has a first N-bit input terminal, a second N-bit input terminal, and an output terminal; the positive input terminal of the differential amplifier circuit is used to receive an externally input voltage signal, the output terminal of the differential amplifier circuit is connected to the input terminal of the voltage detection circuit, and the negative input terminal of the differential amplifier circuit is connected to its output terminal and the output terminal of the adaptive output array, respectively; the first output terminal of the voltage detection circuit is connected to the first input terminal of the shift control circuit, and is used to output a first drive signal to the shift control circuit; the second output terminal of the voltage detection circuit is connected to the shift control circuit... The second input terminal of the voltage detection circuit is connected to the third input terminal of the shift control circuit, and is used to output the second drive signal to the shift control circuit. The third output terminal of the voltage detection circuit is connected to the third input terminal of the shift control circuit, and is used to output the third drive signal to the shift control circuit. The first N-bit output terminal of the shift control circuit is connected to the first N-bit input terminal of the adaptive output array, and is used to output the first N-bit control signal to the adaptive output array. The second N-bit output terminal of the shift control circuit is connected to the second N-bit input terminal of the adaptive output array, and is used to output the second N-bit control signal to the adaptive output array. The output terminal of the adaptive output array is used to output the drive current. In each working cycle, the level combination of the first drive signal and the second drive signal is used to indicate the output status of the current working cycle, and the third drive signal is used to indicate the load level in the next detection cycle.

[0012] Furthermore, each output unit has a first input terminal, a second input terminal, and an output terminal; the first input terminals of the N output units constitute the first N-bit input terminal of the adaptive output array; the second input terminals of the N output units constitute the second N-bit input terminal of the adaptive output array; the output terminals of the N output units are connected, and their connection terminals are the output terminals of the adaptive output array; each output unit includes a first single-pole double-throw switch, a second single-pole double-throw switch, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; the first single-pole double-throw switch and the second single-pole double-throw switch each have a common terminal, a first connection terminal, a second connection terminal, and a control terminal; the control terminal of the first single-pole double-throw switch is the first input terminal of the output unit, and the common terminal of the first single-pole double-throw switch is connected to a PMOS bias voltage, which is used to enable the first PMOS transistor and the second PMOS transistor to operate normally and generate... The second single-pole double-throw switch is the control terminal of the output unit, and the common terminal of the second single-pole double-throw switch is connected to the NMOS bias voltage. The NMOS bias voltage is used to enable the first NMOS transistor and the second NMOS transistor to work normally and generate a sinking current. The first connection terminal of the first single-pole double-throw switch is connected to the gate of the second PMOS transistor, and the second connection terminal is connected to the gate of the first PMOS transistor. The first connection terminal of the second single-pole double-throw switch is connected to the gate of the second NMOS transistor, and the second connection terminal is connected to the gate of the first NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage VDD. The sources of the first NMOS transistor and the second NMOS transistor are both grounded. The drains of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected, and their connection terminals are the output terminals of the output unit.

[0013] Furthermore, the first single-pole double-throw switch includes a first selector, a second selector, a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a first inverter; both the first and second selectors are 2-to-1 multiplexers, having a first input terminal, a second input terminal, a selection terminal, and an output terminal; the selection terminal of the first selector, the selection terminal of the second selector, the gate of the third NMOS transistor, the input terminal of the first inverter, and the gate of the fourth NMOS transistor are connected, and their connection terminal is the control terminal of the first single-pole double-throw switch; the output terminal of the first inverter, the gate of the third PMOS transistor, and the gate of the fourth PMOS transistor are connected; the source of the third NMOS transistor and the input terminal of the third PMOS transistor... The drain of the first selector is connected to the first input terminal of the first selector; the drain of the third NMOS transistor, the source of the third PMOS transistor, the drain of the fourth PMOS transistor, and the source of the fourth NMOS transistor are connected, and their connection terminals are the common terminals of the first single-pole double-throw switch; the source of the fourth PMOS transistor, the drain of the fourth NMOS transistor, and the first input terminal of the second selector are connected; the second input terminal of the first selector and the second input terminal of the second selector are connected, and their connection terminals are connected to the power supply voltage VDD; the output terminal of the first selector is the first connection terminal of the first single-pole double-throw switch, and the output terminal of the second selector is the second connection terminal of the first single-pole double-throw switch; the circuit structure of the second single-pole double-throw switch is the same as that of the first single-pole double-throw switch.

[0014] Furthermore, the shift control circuit includes two bidirectional shift registers, each having one input terminal, one control terminal, and N parallel output terminals; the two bidirectional shift registers are a first bidirectional shift register and a second bidirectional shift register; the input terminal of the first bidirectional shift register is the first input terminal of the shift control circuit, and the input terminal of the second bidirectional shift register is the second input terminal of the shift control circuit; the control terminals of the first and second bidirectional shift registers are connected, and their connection terminal is the third input terminal of the shift control circuit; the N parallel output terminals of the first bidirectional shift register are the first N-bit output terminals of the shift control circuit; and the N parallel output terminals of the second bidirectional shift register are the second N-bit output terminals of the shift control circuit.

[0015] Furthermore, the voltage detection circuit includes a third selector, a fourth selector, an XOR gate, an AND gate, a first comparator, a second comparator, a third comparator, a first counter, and a second counter; the third and fourth selectors are both 2-to-1 multiplexers, each with a first input terminal, a second input terminal, a selection terminal, and an output terminal; the XOR gate and the AND gate each have a first input terminal, a second input terminal, and an output terminal; the first, second, and third comparators each have a non-inverting input terminal, an inverting input terminal, and an output terminal; the first and second counters each have an input terminal, a control terminal, and an output terminal; the non-inverting input terminal of the first comparator is used to connect to a high threshold voltage, the inverting input terminal of the second comparator is used to connect to a low threshold voltage, and the non-inverting input terminal of the third comparator is used to connect to a common-mode voltage; the inverting input terminals of the first, second, and third comparators are connected, and the connection point of the three is the input terminal of the voltage detection circuit; the first The output of the comparator is connected to the first input of the XOR gate; the output of the second comparator is connected to the second input of the XOR gate; the output of the third comparator is connected to the second input of the third selector and the selection terminal of the fourth selector, with the first input of the third selector grounded; the output of the XOR gate is the first output of the voltage detection circuit; the selection terminal of the third selector is connected to the output of the XOR gate, and the output of the third selector is the second output of the voltage detection circuit; the first input of the fourth selector is connected to the output of the XOR gate, and the second input of the fourth selector is connected to the output of the third selector; the output of the fourth selector is connected to the control terminals of the first and second counters; the inputs of the first and second counters are connected; the output of the first counter is connected to the first input of the AND gate; the output of the second counter is connected to the second input of the AND gate; the output of the AND gate is the third output of the voltage detection circuit. Attached Figure Description

[0016] Figure 1 This is a block diagram of the adaptive output operational amplifier circuit for an image signal processor according to the present invention.

[0017] Figure 2 This is a block diagram of the adaptive output array of the adaptive output operational amplifier circuit for an image signal processor according to the present invention;

[0018] Figure 3 This is a circuit diagram of the adaptive output unit of the adaptive output operational amplifier circuit for an image signal processor according to the present invention;

[0019] Figure 4 This is a circuit diagram of a single-pole double-throw switch for an adaptive output operational amplifier circuit for an image signal processor according to the present invention.

[0020] Figure 5This is a structural diagram of the shift control circuit for the adaptive output operational amplifier circuit of an image signal processor according to the present invention;

[0021] Figure 6 This is a circuit diagram of the voltage detection circuit for the adaptive output operational amplifier circuit of an image signal processor according to the present invention.

[0022] Figure 7 This is a schematic diagram of the test platform for the adaptive output operational amplifier circuit for an image signal processor according to the present invention;

[0023] Figure 8 The simulation results of the voltage detection circuit for the adaptive output operational amplifier circuit of the image signal processor of the present invention are shown in the figure.

[0024] Figure 9 The simulation result diagram of the first bidirectional shift register of the adaptive output operational amplifier circuit for an image signal processor of the present invention is shown.

[0025] Figure 10 The figure shows the simulation results of the adaptive output operational amplifier circuit for an image signal processor according to the present invention. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0027] Example 1: As Figure 1 and Figure 2 As shown, an adaptive output operational amplifier circuit for an image signal processor includes a differential amplifier circuit, a voltage detection circuit, a shift control circuit, and an adaptive output array; the adaptive output array includes N identical output units, where N=2. j , j is an integer greater than or equal to 2; the output unit has two operating states, static and non-static, and when it is in non-static state, it has two operating modes, PMOS mode and NMOS mode; the output current of the output unit in static state is less than the output current in non-static state; the sum of the output currents of N output units is the drive current of the adaptive output array; the initial operating state of N output units is static; the differential amplifier circuit is used to amplify its input voltage to obtain the amplified voltage signal, i.e., its output voltage, which is output to the voltage detection circuit, and feedback adjustment is performed according to its output voltage and the output voltage of the adaptive output array; the voltage detection circuit is used to determine whether the driving capability of the adaptive output operational amplifier circuit matches the load according to the output voltage of the differential amplifier circuit, and drives the shift control circuit accordingly; the shift control circuit is used to adjust the operating state and non-static operating mode of each output unit in the adaptive output array under the drive of the voltage detection circuit, so as to match the drive current with the load.

[0028] In this embodiment, the differential amplifier circuit and the adaptive output array form a feedback loop. The differential amplifier circuit adjusts its output voltage in real time according to the output voltage of the adaptive output array so that its output voltage can represent the real-time load condition. The voltage detection circuit determines whether the driving capability of the adaptive output operational amplifier circuit matches the load in real time according to the output voltage of the differential amplifier circuit, and drives the shift control circuit accordingly. The shift control circuit adjusts the working state and non-static working mode of each output unit in the adaptive output array to ensure that the driving current (i.e. driving capability) matches the load level, so that it has high driving capability under high load and low power consumption under low load, achieving compatibility between energy consumption and driving capability.

[0029] Example 2: This example is basically the same as Example 1, except that: In this example, the voltage detection circuit is preset with a high threshold voltage RefH, a common-mode threshold voltage RefM, a low threshold voltage RefL, a working cycle, and a detection cycle. The high threshold voltage RefH is greater than the common-mode threshold voltage RefM, and the common-mode threshold voltage RefM is greater than the low threshold voltage RefL. The shift control circuit is set with a control cycle, and the detection cycle is K times the control cycle, where K = N / 2 - 1. In each working cycle, the voltage detection circuit performs two detection cycles, and in each detection cycle, the shift control circuit performs K control cycles. In the cycle, when entering the previous detection cycle, the voltage detection circuit determines the output state of the adaptive output operational amplifier circuit (whether it is in a stable state, a current-carrying state, or a current-sinking state) based on the output voltage of the differential amplifier circuit, and generates a corresponding drive signal to output to the shift control circuit, driving it to perform the first stage adjustment of the adaptive output array within K control cycles. When entering the next detection cycle, the voltage detection circuit determines the load level of the current working cycle based on the output voltage of the differential amplifier circuit, and generates a corresponding drive signal to output to the shift control circuit, driving it to perform the second stage adjustment of the adaptive output array within K control cycles.

[0030] In this embodiment, in the detection cycle preceding each operating cycle, the voltage detection circuit samples the output voltage of the differential amplifier circuit and compares it with the high threshold voltage RefH and the low threshold voltage RefL to determine the output state of the adaptive output operational amplifier circuit in the current operating cycle. If the output voltage is less than or equal to the high threshold voltage RefH and greater than or equal to the low threshold voltage RefL, the output state of the adaptive output operational amplifier circuit in the current operating cycle is a stable state. At this time, the voltage detection circuit drives the shift control circuit to control the adaptive output array to maintain its current state for K control cycles. If the output voltage is greater than the high threshold voltage RefH, the output state of the adaptive output operational amplifier circuit in the current operating cycle is a current-sinking state. In each of the K control cycles, the voltage detection circuit drives the shift control circuit to sequentially switch one static output unit to NMOS mode relative to the previous control cycle. This causes the output voltage of the differential amplifier circuit to drop to less than or equal to the high threshold voltage RefH and greater than or equal to the low threshold voltage RefL. If the output voltage is less than the low threshold voltage RefL, the output state of the adaptive output operational amplifier circuit in the current working cycle is in a current-pull state. At this time, in each of the K control cycles, the voltage detection circuit drives the shift control circuit to sequentially switch one static output unit to PMOS mode relative to the previous control cycle. This causes the output voltage of the differential amplifier circuit to increase to greater than or equal to the low threshold voltage RefL and less than or equal to the high threshold voltage RefH.

[0031] In this embodiment, in the last detection cycle of each operating cycle, the voltage detection circuit samples the output voltage of the differential amplifier circuit and compares it with the common-mode threshold voltage RefM. Combined with the output state of the adaptive output operational amplifier circuit in the current operating cycle, it determines the load level. If the current operating cycle is in a current-sinking state and the output voltage is greater than or equal to the common-mode threshold voltage RefM, it indicates a high load. In this case, the voltage detection circuit drives the shift control circuit to control one static output unit to switch to NMOS mode in each of the K control cycles relative to the previous control cycle, causing the output voltage of the differential amplifier circuit to decrease and become greater than or equal to the low threshold voltage RefL. Simultaneously, the drive current increases, improving the driving capability. If the current operating cycle is in a current-sinking state and the output voltage is less than the common-mode threshold voltage RefM, it indicates a low load. In this case, the voltage detection circuit drives the shift control circuit to control one NMOS mode output unit to switch to static mode in each of the K control cycles relative to the previous control cycle, causing the output voltage of the differential amplifier circuit to increase and become less than or equal to the high threshold voltage RefH. Simultaneously, the drive current increases. The smaller the voltage, the lower the driving capability. If the current operating cycle is in a current-sucking state and the output voltage is less than or equal to the common-mode threshold voltage RefM, it is a high load. In this case, the voltage detection circuit drives the shift control circuit to control one static output unit to switch to PMOS mode in each of the K control cycles, relative to the previous control cycle. This increases the output voltage of the differential amplifier circuit and makes it less than or equal to the high threshold voltage RefH. At the same time, the driving current increases, and the driving capability improves. If the current operating cycle is in a current-sucking state and the output voltage is greater than the common-mode threshold voltage RefM, it is a low load. In each of its K control cycles, the load shift control circuit sequentially controls one output unit in PMOS mode to switch to static mode relative to the previous control cycle. This increases the output voltage of the differential amplifier circuit, ensuring it is less than or equal to the high threshold voltage RefH. Simultaneously, the drive current decreases, reducing the drive capability. If the current operating cycle is in a stable state, it indicates that the drive capability is matched to the load. Regardless of whether the output voltage is greater than or equal to the common-mode threshold voltage RefM or less than the common-mode threshold voltage RefM, the shift control circuit controls the adaptive output array to maintain its current state for all K control cycles.

[0032] Example 3: This example is basically the same as Example 2, except that: In this example, the differential amplifier circuit has a positive input terminal, a negative input terminal, and an output terminal; the voltage detection circuit has an input terminal, a first output terminal, a second output terminal, and a third output terminal; the shift control circuit has a first input terminal, a second input terminal, a third input terminal, a first N-bit output terminal, and a second N-bit output terminal; the adaptive output array has a first N-bit input terminal, a second N-bit input terminal, and an output terminal; the positive input terminal of the differential amplifier circuit is used to receive an externally input voltage signal, the output terminal of the differential amplifier circuit is connected to the input terminal of the voltage detection circuit, and the negative input terminal of the differential amplifier circuit is connected to its output terminal and the output terminal of the adaptive output array, respectively; the first output terminal of the voltage detection circuit is connected to the first input terminal of the shift control circuit, and is used to output a first drive signal to the shift control circuit. The second output terminal is connected to the second input terminal of the shift control circuit, and is used to output the second drive signal to the shift control circuit. The third output terminal of the voltage detection circuit is connected to the third input terminal of the shift control circuit, and is used to output the third drive signal to the shift control circuit. The first N-bit output terminal of the shift control circuit is connected to the first N-bit input terminal of the adaptive output array, and is used to output the first N-bit control signal to the adaptive output array. The second N-bit output terminal of the shift control circuit is connected to the second N-bit input terminal of the adaptive output array, and is used to output the second N-bit control signal to the adaptive output array. The output terminal of the adaptive output array is used to output the drive current. In each working cycle, the level combination of the first drive signal and the second drive signal is used to indicate the output status of the current working cycle, and the third drive signal is used to indicate the load level in the next detection cycle.

[0033] Example 4: This example is basically the same as Example 3, except that: Figure 3As shown, in this embodiment, each output unit has a first input terminal, a second input terminal, and an output terminal; the first input terminals of N output units constitute the first N-bit input terminal of the adaptive output array; the second input terminals of N output units constitute the second N-bit input terminal of the adaptive output array; the output terminals of N output units are connected, and their connection terminals are the output terminals of the adaptive output array; each output unit includes a first single-pole double-throw switch S1, a second single-pole double-throw switch S2, a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, and a second PMOS transistor P2; the first single-pole double-throw switch S1 and the second single-pole double-throw switch S2 each have a common terminal, a first connection terminal, a second connection terminal, and a control terminal; the control terminal of the first single-pole double-throw switch S1 is the first input terminal of the output unit, and the common terminal of the first single-pole double-throw switch S1 is connected to the PMOS bias voltage P-DC. The PMOS bias voltage P-DC is used to enable the first PMOS transistor P1 and the second PMOS transistor P2 to work normally and generate a pull-up current; The control terminal of the second single-pole double-throw switch S2 is the second input terminal of the output unit. The common terminal of the second single-pole double-throw switch S2 is connected to the NMOS bias voltage N-DC. The NMOS bias voltage N-DC is used to enable the first NMOS transistor N1 and the second NMOS transistor N2 to work normally and generate sink current. The first connection terminal of the first single-pole double-throw switch S1 is connected to the gate of the second PMOS transistor P2, and the second connection terminal is connected to the gate of the first PMOS transistor P1. The first connection terminal of the second single-pole double-throw switch S2 is connected to the gate of the second NMOS transistor N2, and the second connection terminal is connected to the gate of the first NMOS transistor N1. The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are both connected to the power supply voltage VDD. The source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 are both grounded. The drain of the first PMOS transistor P1, the drain of the second PMOS transistor P2, the drain of the first NMOS transistor N1 and the drain of the second NMOS transistor N2 are connected, and their connection terminals are the output terminals of the output unit.

[0034] In this embodiment, when the first input terminal of the output unit is connected to a low level and the second input terminal is connected to a low level, the common terminal of the first single-pole double-throw switch S1 is connected to its second connection terminal, and the common terminal of the second single-pole double-throw switch S2 is connected to its first connection terminal. At this time, the first PMOS transistor P1 and the second NMOS transistor N2 are both disconnected. The second PMOS transistor P2 is connected to the PMOS bias voltage P-DC to generate current output, and the first NMOS transistor N1 is connected to the NMOS bias voltage N-DC to generate current output. The current output by the output terminal of the output unit is the sum of the currents output by the second PMOS transistor P2 and the first NMOS transistor N1. At this time, the output unit is in non-static PMOS mode, and the output current is relatively large. When the first input terminal and the second input terminal of the output unit are connected to a high level, the common terminal of the first single-pole double-throw switch S1 is connected to its first connection terminal, and the common terminal of the second single-pole double-throw switch S2 is connected to its second connection terminal. At this time, the second PMOS transistor P2 and the first NMOS transistor N1 are both disconnected. The first PMOS transistor P1 is connected to the PMOS bias voltage P-DC to generate current output, and the second NMOS transistor N2 is connected to the NMOS bias voltage N-DC to generate current output. The current output by the output terminal of the output unit is the sum of the currents output by the first PMOS transistor P1 and the second NMOS transistor N2. At this time, the output unit is in non-static NMOS mode, and the output current is relatively large. When the first input terminal of the output unit is connected to a high level and the second input terminal is connected to a low level, the common terminal of the first single-pole double-throw switch S1 is connected to its first connection terminal, and the common terminal of the second single-pole double-throw switch S2 is connected to its first connection terminal. At this time, the second PMOS transistor P2 and the second NMOS transistor N2 are both disconnected. The first PMOS transistor P1 is connected to the PMOS bias voltage P-DC to generate current output, and the first NMOS transistor N1 is connected to the NMOS bias voltage N-DC to generate current output. The current output by the output terminal of the output unit is the sum of the currents output by the first PMOS transistor P1 and the first NMOS transistor N1. At this time, the output unit is in a static state and the output current is small.

[0035] Example 5: This example is basically the same as Example 4, except that: Figure 4As shown, in this embodiment, the first single-pole double-throw switch S1 includes a first selector M1, a second selector M2, a third NMOS transistor N3, a fourth NMOS transistor N4, a third PMOS transistor P3, a fourth PMOS transistor P4, and a first inverter inv1; both the first selector M1 and the second selector M2 are 2-to-1 selectors, having a first input terminal, a second input terminal, a selection terminal, and an output terminal; the selection terminal of the first selector M1, the selection terminal of the second selector M2, the gate of the third NMOS transistor N3, the input terminal of the first inverter inv1, and the gate of the fourth NMOS transistor N4 are connected, and their connection terminal is the control terminal of the first single-pole double-throw switch S1; the output terminal of the first inverter inv1, the gate of the third PMOS transistor P3, and the gate of the fourth PMOS transistor P4 are connected; the source of the third NMOS transistor N3, the second NMOS transistor P4, the third NMOS transistor P3, the fourth PMOS transistor P4, and the third NMOS transistor P4 are connected; the first inverter inv1, the second NMOS transistor P3, the third NMOS transistor P4, the third ... The drain of the third PMOS transistor P3 is connected to the first input terminal of the first selector M1; the drain of the third NMOS transistor N3, the source of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4, and the source of the fourth NMOS transistor N4 are connected, and their connection terminals are the common terminals of the first single-pole double-throw switch S1; the source of the fourth PMOS transistor P4, the drain of the fourth NMOS transistor N4, and the first input terminal of the second selector M2 are connected; the second input terminal of the first selector M1 and the second input terminal of the second selector M2 are connected, and their connection terminals are connected to the power supply voltage VDD; the output terminal of the first selector M1 is the first connection terminal of the first single-pole double-throw switch S1, and the output terminal of the second selector M2 is the second connection terminal of the first single-pole double-throw switch S1; the circuit structure of the second single-pole double-throw switch S2 is the same as that of the first single-pole double-throw switch S1.

[0036] In this embodiment, when the control terminal of the first single-pole double-throw switch S1 is connected to a high level, the output terminal of the first selector M1 is connected to its second input terminal, and the output terminal of the second selector M2 is connected to its first input terminal. Since the third PMOS transistor P3 and the third NMOS transistor N3 are disconnected at this time, the common terminal of the first single-pole double-throw switch S1 is connected to its second connection terminal. When the control terminal of the first single-pole double-throw switch S1 is connected to a low level, the output terminal of the first selector M1 is connected to its first input terminal, and the output terminal of the second selector M2 is connected to its second input terminal. At this time, the output terminal of the first single-pole double-throw switch S1 is connected to its first connection terminal. Since the second input terminals of the first selector M1 and the second selector M2 are both pre-connected to the power supply voltage VDD, when the first PMOS transistor P1 or the second PMOS transistor P2 in the output unit is disconnected, the first PMOS transistor P1 or the second PMOS transistor P2 is completely turned off because its gate is connected to the power supply voltage VDD, thus completely eliminating the weak conduction and leakage current of the first PMOS transistor P1 or the second PMOS transistor P2 and reducing power consumption.

[0037] Example 6: This example is basically the same as Example 5, except that: Figure 5As shown, in this embodiment, the shift control circuit includes two bidirectional shift registers, each having one input terminal, one control terminal, and N output terminals. The two bidirectional shift registers are a first bidirectional shift register and a second bidirectional shift register, respectively. The input terminal of the first bidirectional shift register is the first input terminal of the shift control circuit, and the input terminal of the second bidirectional shift register is the second input terminal of the shift control circuit. The control terminals of the first and second bidirectional shift registers are connected, and their connection terminal is the third input terminal of the shift control circuit. The N output terminals of the first bidirectional shift register are the first N-bit output terminals of the shift control circuit, and the N output terminals of the second bidirectional shift register are the second N-bit output terminals of the shift control circuit.

[0038] In this embodiment, the N output units are referred to as the 1st output unit to the Nth output unit. The kth output terminal of the first bidirectional shift register is connected to the first input terminal of the kth output unit, and the kth output terminal of the second bidirectional shift register is connected to the second input terminal of the kth output unit, where k = 1, 2, ..., N. The signal output from the kth output terminal of the first bidirectional shift register is denoted as Q(k-1), and the signal output from the kth output terminal of the second bidirectional shift register is denoted as Qb(k-1). When the first bidirectional shift register and the second bidirectional shift register are powered on or reset, both enter the initial state. In this initial state, all N output terminals of the first bidirectional shift register output a high level, and all N output terminals of the second bidirectional shift register output a low level.

[0039] In this embodiment, when the adaptive output operational amplifier circuit enters a certain operating cycle, the voltage detection circuit enters the previous detection cycle of that operating cycle, and the shift control circuit enters the first control cycle of that detection cycle, starting periodic operation. If at this time, both the first and second input terminals of the shift control circuit are connected to a high level, and the third input terminal is connected to an invalid signal, that is, both the input terminals of the first bidirectional shift register and the second bidirectional shift register are connected to a high level, then the first output terminal of the N output terminals of the first bidirectional shift register outputs a low level, and the second to Nth output terminals maintain their current output level unchanged. The N output terminals of the second bidirectional shift register are reset to their initial state, causing the first output unit to switch to non-static PMOS mode. Afterwards, the first and second bidirectional shift registers implement the right shift operation of the bidirectional shift registers. Each time a control cycle is executed, one output unit is sequentially controlled to enter the non-static PMOS mode until the end of the current detection cycle. If at this time, the first input terminal of the shift control circuit is connected to a high level, the second input terminal is connected to a low level, and the third input terminal is connected to an invalid signal, that is, the input terminal of the first bidirectional shift register is connected to a high level and the input terminal of the second bidirectional shift register is connected to a low level, then the N output terminals of the first bidirectional shift register are reset to the initial state, the first output terminal of the N output terminals of the second bidirectional shift register outputs a high level, and the second to Nth output terminals maintain the current output unchanged, so that the first output unit switches to non-static NMOS mode; then, the first bidirectional shift register and the second bidirectional shift register implement the right shift operation of the bidirectional shift register. Each time the operation of one control cycle is performed, one output unit is controlled to enter non-static NMOS mode in sequence until the end of the current detection cycle. If the first input terminal of the shift control circuit is connected to a low level, the second input terminal is connected to a low level, and the third input terminal is connected to an invalid signal, that is, the input terminals of the first bidirectional shift register and the second bidirectional shift register are both connected to a low level, then the N output terminals of the first bidirectional shift register and the N output terminals of the second bidirectional shift register will maintain their current output level unchanged until the current detection cycle ends.

[0040] In this embodiment, when the adaptive output operational amplifier circuit is in a certain operating cycle, and the voltage detection circuit enters the next detection cycle under that operating cycle, the shift control circuit enters the first control cycle under that detection cycle and begins periodic operation. If the first input terminal, the second input terminal, and the third input terminal of the shift control circuit are all connected to a high level, that is, the input terminals of the first bidirectional shift register and the second bidirectional shift register are all connected to a high level, and the control terminals are all connected to a high level, then the first output terminal of the N output terminals of the first bidirectional shift register outputs a low level, and the second to Nth output terminals maintain their current output unchanged. The N output terminals of the second bidirectional shift register are reset to their initial state, causing the first output unit to enter the non-static PMOS mode. Afterwards, the first bidirectional shift register and the second bidirectional shift register implement the right shift operation of the bidirectional shift register. Each time a control cycle is executed, one output unit is sequentially controlled to enter the non-static PMOS mode until the end of the current detection cycle. If the first and second input terminals of the shift control circuit are both connected to a high level, and the third input terminal is connected to a low level, that is, if the input terminals of the first and second bidirectional shift registers are both connected to a high level and the control terminals are both connected to a low level, then the Nth output terminal of the first bidirectional shift register outputs a high level, and the first to (N-1)th output terminals maintain their current output unchanged; the Nth output terminal of the second bidirectional shift register outputs a low level, and the first to (N-1)th output terminals maintain their current output unchanged, causing the Nth output unit to enter a static state; then, the first and second bidirectional shift registers implement the left shift operation of the bidirectional shift registers, and each time a control cycle is executed, one output unit is sequentially controlled to enter a static state until the current detection cycle ends. If the first and second input terminals of the shift control circuit are both connected to a low level, and the third input terminal is connected to a low level, that is, if the input terminals of the first and second bidirectional shift registers are both connected to a low level, and the control terminals are both connected to a low level, then the N output terminals of the first and second bidirectional shift registers will maintain their current output levels unchanged until the current detection cycle ends.If the first input of the shift control circuit is connected to a high level, the second input is connected to a low level, and the third input is connected to a high level (i.e., both the input and control terminals of the first bidirectional shift register are connected to a high level, the input of the second bidirectional shift register is connected to a low level, and the control terminal is connected to a high level), then the first to Nth outputs of the first bidirectional shift register are reset to their initial state, the first output of the second bidirectional shift register outputs a high level, and the second to Nth outputs maintain their current outputs, causing the first output unit to enter the non-static NMOS mode. Afterward, the first and second bidirectional shift registers implement the right shift operation of the bidirectional shift registers. Each time a control cycle is executed, one output unit is sequentially controlled to enter the non-static NMOS mode until the current detection cycle ends. If the first input of the shift control circuit is connected to a high level, the second input is connected to a low level, and the third input is connected to a low level, that is, if the input of the first bidirectional shift register is connected to a high level and the control terminal is connected to a low level, and the input of the second bidirectional shift register is connected to a low level and the control terminal is connected to a low level, then the Nth output of the N outputs of the first bidirectional shift register will output a high level, and the first to (N-1)th outputs will maintain their current output unchanged; the Nth output of the N outputs of the second bidirectional shift register will output a low level, and the first to (N-1)th outputs will maintain their current output unchanged, causing the Nth output unit to enter a static state; then, the first and second bidirectional shift registers will perform a left shift operation of the bidirectional shift registers, and each time a control cycle is executed, one output unit will be controlled to enter a static state in sequence until the current detection cycle ends. If the first and second input terminals of the shift control circuit are both connected to a low level, and the third input terminal is connected to a high level, that is, if the input terminals of the first and second bidirectional shift registers are both connected to a low level and the control terminals are both connected to a high level, then the N output terminals of the first and second bidirectional shift registers will maintain their current output levels unchanged until the current detection cycle ends.

[0041] Example 7: This example is basically the same as Example 6, except that: Figure 6As shown, in this embodiment, the voltage detection circuit includes a third selector M3, a fourth selector M4, an XOR gate XOR1, an AND gate B1, a first comparator C1, a second comparator C2, a third comparator C3, a first counter A1, and a second counter A2. The third selector M3 and the fourth selector M4 are both 2-to-1 multiplexers, each with a first input terminal, a second input terminal, a selection terminal, and an output terminal. The XOR gate XOR1 and the AND gate B1 each have a first input terminal, a second input terminal, and an output terminal. The first comparator C1, the second comparator C2, and the third comparator C3 each have... It has a non-inverting input terminal, an inverting input terminal, and an output terminal; the first counter A1 and the second counter A2 both have input terminals, control terminals, and output terminals; the non-inverting input terminal of the first comparator C1 is used to connect to the high threshold voltage RefH, the inverting input terminal of the second comparator C2 is used to connect to the low threshold voltage RefL, and the non-inverting input terminal of the third comparator C3 is used to connect to the common-mode voltage; the inverting input terminals of the first comparator C1, the non-inverting input terminals of the second comparator C2, and the inverting input terminals of the third comparator C3 are connected, and the connection terminal of the three is the input terminal of the voltage detection circuit; the first... The output of comparator C1 is connected to the first input of XOR gate XOR1; the output of comparator C2 is connected to the second input of XOR gate XOR1; the output of comparator C3 is connected to the second input of third selector M3 and the selection terminal of fourth selector M4, with the first input of third selector M3 grounded; the output of XOR gate XOR1 is the first output of the voltage detection circuit; the selection terminal of third selector M3 is connected to the output of XOR gate XOR1, and the output of third selector M3 is the second output of the voltage detection circuit; the first input of fourth selector M4 is connected to the output of XOR gate XOR1, and the second input of fourth selector M4 is connected to the output of third selector M3; the output of fourth selector M4 is connected to the control terminals of first counter A1 and second counter A2; the input terminals of first counter A1 and second counter A2 are connected; the output of first counter A1 is connected to the first input of AND gate B1; the output of second counter A2 is connected to the second input of AND gate B1; the output of AND gate B1 is the third output of the voltage detection circuit.

[0042] In this embodiment, during each operating cycle of the adaptive output operational amplifier circuit, when the voltage detection circuit is in the previous detection cycle, the fourth selector M4, the first counter A1, the second counter A2, and the AND gate B1 are all in a sleep state and do not participate in operation. At this time, the input terminal of the voltage detection circuit samples the voltage signal output from the output terminal of the differential amplifier circuit (i.e., the output voltage of the differential amplifier circuit). The first comparator C1 compares the output voltage of the differential amplifier circuit with the high threshold voltage RefH. When the output voltage of the differential amplifier circuit is less than the high threshold voltage RefH, the output terminal of the first comparator C1 outputs a high level; when the output voltage of the differential amplifier circuit is greater than the high threshold voltage RefH, the output terminal of the first comparator C1 outputs a low level. The second comparator C2 compares the output voltage of the differential amplifier circuit with the low threshold voltage RefL. When the output voltage of the differential amplifier circuit is less than the low threshold voltage RefL, the output terminal of the second comparator C2 outputs a low level; when the output voltage of the differential amplifier circuit is greater than the low threshold voltage RefL, the output terminal of the second comparator C2 outputs a high level. The third comparator C3 samples the output voltage of the differential amplifier circuit... Compared with the common-mode threshold voltage RefM, when the output voltage of the differential amplifier circuit is greater than the common-mode threshold voltage RefM, the output of the third comparator C3 is low; when the output voltage of the differential amplifier circuit is less than the common-mode threshold voltage RefM, the output of the third comparator C3 is high. When the output of the first comparator C1 and the output of the second comparator C2 are both high, the output of the XOR gate XOR1 is low. However, since the first input of the third selector M3 is grounded, its selection terminal is connected to the output of the XOR gate XOR1. At this time, regardless of whether the output of the third comparator C3 is high or low, the output of the third selector M3 will always be low. That is, the first output of the voltage detection circuit is low, the second output is low, and the third output is an invalid signal. At this time, the output state of the adaptive output operational amplifier circuit is stable. When the output of the first comparator C1 is low, the output of the second comparator C2 is high, and the output of the third comparator C3 is low, the output of the XOR gate XOR1 is high, and the output of the third selector M3 is low. That is, the first output of the voltage detection circuit is high, the second output is low, and the third output is an invalid signal. At this time, the output state of the adaptive output operational amplifier circuit is the current sinking state.When the output of the first comparator C1 is high, the output of the second comparator C2 is low, and the output of the third comparator C3 is high, the output of the XOR gate XOR1 is high, and the output of the third selector M3 is high. That is, the first output of the voltage detection circuit is high, the second output is high, and the third output is an invalid signal. At this time, the output state of the adaptive output operational amplifier circuit is the current-pull state.

[0043] In this embodiment, during each operating cycle of the adaptive output operational amplifier circuit, when the voltage detection circuit is in the next detection cycle, the outputs of the first comparator C1, the second comparator C2, the XOR gate XOR1, and the third selector M3 will maintain the output level of the previous detection cycle. The input of the voltage detection circuit samples the voltage signal output by the output of the differential amplifier circuit (i.e., the output voltage of the differential amplifier circuit). The third comparator C3 compares the output voltage of the differential amplifier circuit with the common-mode threshold voltage RefM. When the output voltage of the differential amplifier circuit is greater than the common-mode threshold voltage RefM, the output of the third comparator C3 outputs a low level. When the output voltage of the differential amplifier circuit is less than the common-mode threshold voltage RefM, the output of the third comparator C3 outputs a high level. When the XOR gate (XOR1), the third selector (M3), and the third comparator (C3) all output a high level, the first counter (A1), the second counter (A2), and the AND gate (B1) also output a high level. In this case, the adaptive output operational amplifier circuit is connected to a high load (output state is current-carrying). The driving capability of the adaptive output operational amplifier circuit is mismatched with the load level, and its driving capability needs to be adjusted. Conversely, when the XOR gate (XOR1), the third selector (M3), and the third comparator (C3) all output a low level, the first counter (A1), the second counter (A2), and the AND gate (B1) also output a low level. In this case, the adaptive output operational amplifier circuit is connected to a low load (output state is current-carrying). The driving capability of the adaptive output operational amplifier circuit is also mismatched with the load level, and its driving capability needs to be adjusted. When the XOR gate XOR1 outputs a high level, the third selector M3 outputs a low level, and the third comparator C3 outputs a high level, the fourth selector M4 outputs a high level, the first counter A1 and the second counter A2 output a low level, and the AND gate B1 outputs a low level. At this time, the adaptive output operational amplifier circuit is connected to a low load (output state is current sinking). The driving capability of the adaptive output operational amplifier circuit is mismatched with the load level, and its driving capability needs to be adjusted. Conversely, when the XOR gate XOR1 outputs a high level, the third selector M3 outputs a low level, and the third comparator C3 outputs a low level, the first counter A1 outputs a high level, the second counter A2 outputs a high level, and the AND gate B1 outputs a high level. At this time, the adaptive output operational amplifier circuit is connected to a high load (output state is current sinking). The driving capability of the adaptive output operational amplifier circuit is mismatched with the load level, and its driving capability needs to be adjusted.When the XOR gate (XOR1) outputs a low level, the third selector (M3) outputs a low level, and the third comparator (C3) outputs a high level, the first counter (A1), the second counter (A2), and the AND gate (B1) all output a high level. At this time, the adaptive output operational amplifier circuit is connected to a high load (the output state is stable), and its driving capability is matched to the load level. Conversely, when the XOR gate (XOR1) outputs a low level, the third selector (M3), and the third comparator (C3) output a low level, the first counter (A1), the second counter (A2), and the AND gate (B1) all output a low level. At this time, the adaptive output operational amplifier circuit is connected to a low load (the output state is stable), and its driving capability is matched to the load level.

[0044] To verify the performance of the adaptive output operational amplifier circuit of this invention, simulation tests were performed on the Cadence platform using the VirtuosoEDA tool. Since the adaptive output operational amplifier circuit of this invention only has one output state during normal operation, and the current-source state and current-sinking state cannot coexist, and the current-sinking state operates in the opposite direction to the current-source state, only the current-source state was simulated. The current-sinking state is not described in detail, nor is the simulation of the second shift register related to the current-sinking state. The simulation test platform for the current-source state is as follows: Figure 7 As shown. Figure 7 In this invention, the adaptive output operational amplifier circuit is configured in unity-gain form, wherein A mp This diagram represents the adaptive output operational amplifier circuit of the present invention. VCM represents the voltage signal connected to the positive input terminal of the differential amplifier circuit, i.e., its input voltage, which is 1.5V. RL represents the connected load. Iout represents the drive current from the operational amplifier circuit of the present invention to the load RL. Vout is the output voltage from the adaptive output operational amplifier circuit of the present invention to the load RL, i.e., the output voltage of the adaptive output array. The power supply voltage VDD of the adaptive output operational amplifier circuit of the present invention is set to 3V, the high threshold voltage RefH to 1.51V, the low threshold voltage RefL to 1.49V, and the common-mode threshold voltage RefM to 1.5V. The driving capability requirements of the adaptive output operational amplifier circuit of the present invention are simulated by changing the resistance value of the load RL. Based on... Figure 7 The simulation test platform shown was used for simulation. When the number of output units was 4, the following results were obtained: Figure 8 The simulation results of the voltage detection circuit shown are as follows: Figure 9 The simulation results of the first bidirectional shift register shown are as follows: Figure 10 The simulation results of the overall circuit are shown in the figure.

[0045] Figure 8 In this diagram, Vout represents the voltage signal acquired at the input of the voltage detection circuit, i.e., the output voltage of the differential amplifier circuit; XOR represents the logic value output by the XOR gate XOR1; ComH represents the logic value output by the first comparator C1; and ComL represents the logic value output by the second comparator C2. Analysis Figure 8 Simulation results show that in the previous detection cycle of a working cycle, when the output voltage of the differential amplifier circuit is higher than the high threshold voltage RefH or lower than the low threshold voltage RefL, the output of the XOR gate XOR1 outputs a high level; in the next detection cycle of a working cycle, when the output voltage of the differential amplifier circuit is greater than the low threshold voltage RefL and less than the high threshold voltage RefH, the output of the XOR gate XOR1 outputs a low level, and the first comparator C1 and the second comparator C2 can quickly flip when the output voltage of the differential amplifier circuit changes, thus realizing the setting function.

[0046] Figure 9 In the diagram, XOR represents the logic value output by the XOR gate XOR1, ComH represents the logic value output by the first comparator C1, and Q0, Q1, Q2, and Q3 represent the signals output by the four terminals of the first bidirectional shift register. Analysis Figure 9 It can be seen that during one working cycle, in the previous detection cycle, when the voltage detection circuit determines that the output voltage of the differential amplifier circuit is between the low threshold voltage RefL and the high threshold voltage RefH, the output of the XOR gate XOR1 outputs a low level, and all four outputs of the first bidirectional shift register maintain their current output unchanged. At this time, the output state of the operational amplifier circuit of the present invention is a stable state, that is... Figure 9 The T1 stage is shown. During the next detection cycle, when the voltage detection circuit determines that the output voltage of the differential amplifier circuit is less than the low threshold voltage RefL, the output of the XOR gate XOR1 outputs a high level. At this time, the first of the four outputs of the first bidirectional shift register outputs a low level, while the second to fourth outputs maintain their current output state. Figure 9 The T2 stage is shown. Figure 9 In the diagram, P1 indicates that the first of the four outputs of the first bidirectional shift register is low, while the second to fourth outputs remain unchanged, thus enabling the first bidirectional shift register to perform a right shift function; P2 indicates that the fourth of the four outputs of the first bidirectional shift register is high, while the first to third outputs remain unchanged, thus enabling the first bidirectional shift register to perform a left shift function.

[0047] Figure 10In this diagram, Vout represents the output voltage of the adaptive operational amplifier circuit of this invention, i.e., the output voltage of the adaptive output array. Iout represents the current output from the adaptive operational amplifier circuit of this invention to the load, i.e., the drive current output by the adaptive output array. Control represents the third drive signal output from the third output terminal of the voltage detection circuit, and CLK is the clock signal for the operating cycle of the adaptive operational amplifier circuit of this invention. Figure 10 As shown in T3, the voltage detection circuit determines the output state to be current-generating in the previous detection cycle of one operating cycle, and continuously switches the output unit to enter PMOS mode; as shown in T3. Figure 10 As shown in T4, the voltage detection circuit determines a high load (current pulling state) in the last detection cycle of one operating cycle and continuously switches the output unit into PMOS mode. Figure 10 As shown in T5, during the previous detection cycle of a working cycle, the voltage detection circuit determines that the output voltage of the differential amplifier circuit is less than the low threshold voltage RefL. When a high level is applied to the input of the first bidirectional shift register and an invalid signal is applied to the control terminal, the first of the four outputs of the first bidirectional shift register outputs a low level, while the second to fourth outputs maintain their current output state. After switching the output unit to enter PMOS mode, the output voltage of the differential amplifier circuit recovers to between the low threshold voltage RefL and the high threshold voltage RefH, and the output voltage of the differential amplifier circuit stabilizes. Figure 10 As shown in T6, in the later detection cycle of a working cycle, the output voltage of the differential amplifier circuit is greater than the common-mode threshold voltage RefM. The fourth output of the four output terminals of the first bidirectional shift register goes high, causing the first bidirectional shift register to shift left, switching the corresponding output unit into a static state. Figure 10 As shown in T7, the voltage detection circuit determines that the output voltage of the differential amplifier circuit is less than the low threshold voltage RefL, and the input terminal of the first bidirectional shift register is connected to a high level, the control terminal is connected to a high level, the first of the four output terminals of the first bidirectional shift register outputs a low level, and the second to fourth output terminals maintain their current output state. After switching the first output unit into PMOS mode, the output voltage of the differential amplifier circuit recovers to between the low threshold voltage RefL and the high threshold voltage RefH, and the output voltage of the differential amplifier circuit stabilizes. Figure 10The overall simulation results show that when the output current of the adaptive operational amplifier circuit of the present invention continuously increases, the output of the second comparator C2 continuously outputs a low level, causing the first bidirectional shift register to continuously shift to the right. After continuously switching the output unit into PMOS mode, the output voltage of the differential amplifier circuit satisfies the condition of being greater than the low threshold voltage RefL and less than the high threshold voltage RefH. The first bidirectional shift register then continuously shifts to the left, switching the output unit from PMOS mode to static mode. In this simulation result, the required pull-up current is 400mA. During the right shift of the first bidirectional shift register, the output current of the adaptive operational amplifier circuit of the present invention increases. Ultimately, the output current of the adaptive operational amplifier circuit of the present invention can be stably controlled at 400.0876mA, and the output voltage is controlled at around 1.5061V. Furthermore, when the required drive current decreases, the output unit switches from PMOS mode to static mode, saving power consumption.

[0048] In summary, the adaptive output operational amplifier circuit for an image signal processor of the present invention forms a feedback loop with the adaptive output array through a differential amplifier circuit. The output voltage of the differential amplifier circuit can characterize the real-time load condition. The voltage detection circuit determines whether the driving capability of the adaptive output operational amplifier circuit matches the load based on the output voltage of the differential amplifier circuit in real time, and drives the shift control circuit accordingly. This causes the shift control circuit to adjust the working state and non-static working mode of each output unit in the adaptive output array, ensuring that the driving current matches the load level and the corresponding driving capability matches the load level, thus achieving compatibility between energy consumption and driving capability.

Claims

1. An adaptive output operational amplifier circuit for an image signal processor, characterized in that: It includes a differential amplifier circuit, a voltage detection circuit, a shift control circuit, and an adaptive output array; The adaptive output array consists of N identical output units, where N=2 j j is an integer greater than or equal to 2; each output unit has a first input terminal, a second input terminal, and an output terminal; the first and second input terminals of the N output units constitute the first N-bit input terminal and the second N-bit input terminal of the adaptive output array; the output terminals of the N output units are connected as the output terminals of the adaptive output array; the output units have two operating states, static and non-static, and when they are in non-static state, they have two operating modes, PMOS mode and NMOS mode; the current output by the output unit in static state is less than the current output in non-static state; the sum of the currents output by the N output units is the drive current output by the adaptive output array; the initial operating state of the N output units is static; the differential amplifier circuit is used to amplify the input voltage connected to its positive input terminal to obtain the amplified voltage signal, i.e., its output voltage, which is output to the voltage detection circuit, and the negative output terminal is adjusted according to its output voltage and the output voltage of the adaptive output array; the voltage detection circuit is used to determine whether the driving capability of the adaptive output operational amplifier circuit matches the load according to the output voltage of the differential amplifier circuit, and drive the shift control circuit accordingly; The shift control circuit is used to adjust the operating state and non-static operating mode of each output unit in the adaptive output array under the drive of the voltage detection circuit, so as to match the drive current with the load.

2. The adaptive output operational amplifier circuit for an image signal processor according to claim 1, characterized in that: The voltage detection circuit is preset with a high threshold voltage, a common-mode threshold voltage, a low threshold voltage, a working cycle, and a detection cycle. The high threshold voltage is greater than the common-mode threshold voltage, and the common-mode threshold voltage is greater than the low threshold voltage. The shift control circuit is set with a control cycle, and the detection cycle is K times the control cycle, where K = N / 2 - 1. In each working cycle, the voltage detection circuit performs two detection cycles, and in each detection cycle, the shift control circuit performs K control cycles. In each working cycle, upon entering the previous detection cycle, the voltage detection circuit determines the output state of the adaptive output operational amplifier circuit (steady state, current-carrying state, or current-sinking state) based on the output voltage of the differential amplifier circuit, and generates a corresponding drive signal output to the shift control circuit, driving it to perform the first stage adjustment of the adaptive output array within K control cycles. Upon entering the next detection cycle, the voltage detection circuit determines the load level based on the output voltage of the differential amplifier circuit, and generates a corresponding drive signal output to the shift control circuit, driving it to perform the second stage adjustment of the adaptive output array within K control cycles.

3. The adaptive output operational amplifier circuit for an image signal processor according to claim 2, characterized in that: In the detection cycle preceding each working cycle, the voltage detection circuit is used to acquire the output voltage of the differential amplifier circuit and compare it with the high threshold voltage and the low threshold voltage respectively to determine the output state of the current working cycle. If the output voltage is less than or equal to the high threshold voltage and greater than or equal to the low threshold voltage, the current working cycle is in a stable state. At this time, the voltage detection circuit is used to drive the shift control circuit to control the adaptive output array to maintain the current state unchanged for K control cycles. If the output voltage is greater than the high threshold voltage, the current operating cycle is in the sinking current state. At this time, the voltage detection circuit drives the shift control circuit to control one static output unit to switch to NMOS mode in each of the K control cycles, relative to the previous control cycle, so that the output voltage of the differential amplifier circuit drops to less than or equal to the high threshold voltage and greater than or equal to the low threshold voltage. If the output voltage is less than the low threshold voltage, the current operating cycle is in the sourcing current state. At this time, the voltage detection circuit drives the shift control circuit to control one static output unit to switch to PMOS mode in each of the K control cycles, relative to the previous control cycle, so that the output voltage increases to greater than or equal to the low threshold voltage and less than or equal to the high threshold voltage.

4. The adaptive output operational amplifier circuit for an image signal processor according to claim 3, characterized in that: In the subsequent detection cycle of each operating cycle, the voltage detection circuit collects the output voltage of the differential amplifier circuit and the output state of the current operating cycle to determine the load level: If it is in a current-sinking state, a high load occurs when the output voltage is greater than or equal to the common-mode threshold voltage. In this case, the shift control circuit, in each of the K control cycles, sequentially controls one static output unit to switch to NMOS mode relative to the previous control cycle. Conversely, a low load occurs when the output voltage is less than the common-mode threshold voltage. In this case, the shift control circuit, in each of the K control cycles, sequentially controls one output unit in NMOS mode to switch to NMOS mode relative to the previous control cycle. In a static state, the output voltage of the differential amplifier circuit increases. In a current-carrying state, when the output voltage is less than or equal to the common-mode threshold voltage, it is a high load. In this case, the shift control circuit controls one static output unit to switch to PMOS mode in each of the K control cycles, relative to the previous control cycle. When the output voltage is greater than the common-mode threshold voltage, it is a low load. In this case, the shift control circuit controls one PMOS mode output unit to switch to static mode in each of the K control cycles, relative to the previous control cycle. In a steady state, the shift control circuit controls the adaptive output array to maintain its current state in all K control cycles.

5. The adaptive output operational amplifier circuit for an image signal processor according to claim 4, characterized in that: The differential amplifier circuit has a positive input terminal, a negative input terminal, and an output terminal; the voltage detection circuit has an input terminal, a first output terminal, a second output terminal, and a third output terminal; the shift control circuit has a first input terminal, a second input terminal, a third input terminal, a first N-bit output terminal, and a second N-bit output terminal; the adaptive output array has a first N-bit input terminal, a second N-bit input terminal, and an output terminal; the output terminal of the differential amplifier circuit is connected to the input terminal of the voltage detection circuit, and the negative input terminal is connected to its output terminal and the output terminal of the adaptive output array, respectively; the first output terminal of the voltage detection circuit is connected to the first input terminal of the shift control circuit, outputting a first drive signal; the second output terminal is connected to the second input terminal of the shift control circuit, outputting a second drive signal; and the third output terminal is connected to the third input terminal of the shift control circuit, outputting a third drive signal. The first N-bit output terminal of the shift control circuit is connected to the first N-bit input terminal of the adaptive output array to output the first N-bit control signal, and the second N-bit output terminal is connected to the second N-bit input terminal of the adaptive output array to output the second N-bit control signal. The output terminal of the adaptive output array outputs the drive current; in each working cycle, the level combination of the first drive signal and the second drive signal indicates the output status of the current working cycle, and the third drive signal indicates the load level in the next detection cycle.

6. The adaptive output operational amplifier circuit for an image signal processor according to claim 5, characterized in that: Each output unit includes a first single-pole double-throw (SPD) switch, a second SPD switch, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. Both the first and second SPD switches have a common terminal, a first connection terminal, a second connection terminal, and a control terminal. The control terminal of the first SPD switch is the first input terminal of the output unit, and its common terminal is connected to the PMOS bias voltage. The control terminal of the second SPD switch is the second input terminal of the output unit, and its common terminal is connected to the NMOS bias voltage. The first connection terminal of the first SPD switch is connected to the gate of the second PMOS transistor, and its second connection terminal is connected to the gate of the first PMOS transistor. The first connection terminal of the second SPD switch is connected to the gate of the second NMOS transistor, and its second connection terminal is connected to the gate of the first NMOS transistor. The sources of both the first and second PMOS transistors are connected to the power supply voltage VDD. The sources of both the first and second NMOS transistors are grounded. The drains of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected as the output terminals of the output unit.

7. The adaptive output operational amplifier circuit for an image signal processor according to claim 6, characterized in that: The first single-pole double-throw switch includes a first selector, a second selector, a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a first inverter; both the first selector and the second selector are 2-to-1 selectors, having a first input terminal, a second input terminal, a selection terminal, and an output terminal; the selection terminals of the first and second selectors, the gate of the third NMOS transistor, the input terminal of the first inverter, and the gate of the fourth NMOS transistor are connected as the control terminals of the first single-pole double-throw switch; The output of the first inverter, the gate of the third PMOS transistor, and the gate of the fourth PMOS transistor are connected; the source of the third NMOS transistor, the drain of the third PMOS transistor, and the first input of the first selector are connected; the drain of the third NMOS transistor, the source of the third PMOS transistor, the drain of the fourth PMOS transistor, and the source of the fourth NMOS transistor are connected, and their connection point is the common terminal of the first single-pole double-throw switch; the source of the fourth PMOS transistor, the drain of the fourth NMOS transistor, and the first input of the second selector are connected; the second inputs of both the first and second selectors are connected to the power supply voltage VDD; the output of the first selector is the first connection terminal of the first single-pole double-throw switch, and the output of the second selector is the second connection terminal of the first single-pole double-throw switch; the circuit structure of the second single-pole double-throw switch is the same as that of the first single-pole double-throw switch.

8. The adaptive output operational amplifier circuit for an image signal processor according to claim 6, characterized in that: The shift control circuit includes two bidirectional shift registers, each with one input, one control, and N parallel outputs. The two bidirectional shift registers are designated as a first bidirectional shift register and a second bidirectional shift register. The input of the first bidirectional shift register is the first input of the shift control circuit, and the input of the second bidirectional shift register is the second input of the shift control circuit. The control terminals of the first and second bidirectional shift registers are connected, and this connection is the third input of the shift control circuit. The N parallel outputs of the first bidirectional shift register are the first N-bit outputs of the shift control circuit, and the N parallel outputs of the second bidirectional shift register are the second N-bit outputs of the shift control circuit.

9. The adaptive output operational amplifier circuit for an image signal processor according to claim 6, characterized in that: The voltage detection circuit includes a third selector, a fourth selector, an XOR gate, an AND gate, first to third comparators, a first counter, and a second counter; the third and fourth selectors are 2-to-1 multiplexers; the XOR gate and the AND gate have a first input terminal, a second input terminal, and an output terminal; the first to third comparators have a non-inverting input terminal, an inverting input terminal, and an output terminal; the first and second counters have input terminals, control terminals, and output terminals; the non-inverting input terminal of the first comparator is used to connect to a high threshold voltage, the inverting input terminal of the second comparator is used to connect to a low threshold voltage, and the non-inverting input terminal of the third comparator is used to connect to a common-mode threshold voltage; the inverting input terminals of the first and third comparators and the non-inverting input terminal of the second comparator are connected as the input terminals of the voltage detection circuit; the first comparator... The outputs of the first and second comparators are connected to the first and second inputs of the XOR gate; the output of the third comparator, the second input of the third selector, and the selection terminal of the fourth selector are connected, and the first input of the third selector is grounded; the output of the XOR gate is the first output of the voltage detection circuit; the selection terminal of the third selector is connected to the output of the XOR gate, and the output of the third selector is the second output of the voltage detection circuit; the first input of the fourth selector is connected to the output of the XOR gate, the second input is connected to the output of the third selector, and the output is connected to the control terminals of the first and second counters; the inputs of the first and second counters are connected; the outputs of the first and second counters are respectively connected to the first and second inputs of the AND gate; the output of the AND gate is the third output of the voltage detection circuit.

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