Memory device and method of manufacturing the same

Abstract

The invention provides a memory device and a manufacturing method thereof. The memory device comprises a first semiconductor body, a second semiconductor body and a third semiconductor body which extend in a first direction and a second direction and are arranged in a third direction, and a first conductive wire extending in the third direction; the first semiconductor main body and the second semiconductor main body are located on the same side of two opposite sides of the third semiconductor main body along the third direction, and the first conductive line is at least located on one side of two opposite sides of the first semiconductor main body, the second semiconductor main body and the third semiconductor main body along the second direction; the size of the third semiconductor main body in the second direction is larger than that of the second semiconductor main body in the second direction and smaller than that of the first semiconductor main body in the second direction; the second direction and the third direction intersect and are both perpendicular to the first direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and for example to a memory device and a method of manufacturing the same. Background Technology

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a storage device is provided, the storage device comprising a first semiconductor body, a second semiconductor body, and a third semiconductor body, all extending along a first direction and a second direction and arranged along a third direction, and a first conductive line extending along the third direction; the first semiconductor body and the second semiconductor body are located on the same side of two opposing sides of the third semiconductor body along the third direction, and the first conductive line is located at least on one side of two opposing sides of the first semiconductor body, the second semiconductor body, and the third semiconductor body along the second direction; the dimension of the third semiconductor body along the second direction is greater than the dimension of the second semiconductor body along the second direction and smaller than the dimension of the first semiconductor body along the second direction; the second direction intersects the third direction and is perpendicular to the first direction.

[0004] According to a second aspect of the present disclosure, a storage device is provided, the storage device including a first region and a second region; the first region includes a plurality of first semiconductor bodies and a plurality of second semiconductor bodies, the second region includes a plurality of third semiconductor bodies, the plurality of first semiconductor bodies, the plurality of second semiconductor bodies and the plurality of third semiconductor bodies all extend along a first direction and a second direction and are arranged along a third direction, the plurality of first semiconductor bodies and the plurality of second semiconductor bodies are arranged alternately along the third direction, and the first region and the second region are arranged side by side along the third direction; the first region and the second region also include a first conductive line extending along the third direction, the first conductive line being at least located on one side of one of the plurality of first semiconductor bodies, the plurality of second semiconductor bodies and the plurality of third semiconductor bodies opposite each other along the second direction; the second direction intersects the third direction and is perpendicular to the first direction; the distance between two adjacent third semiconductor bodies in the second region is greater than the distance between adjacent first semiconductor bodies and second semiconductor bodies in the first region.

[0005] According to a third aspect of the present disclosure, a method for manufacturing a memory device is provided, comprising: forming a first semiconductor body, a second semiconductor body, and a third semiconductor body, all extending along a first direction and a second direction and arranged along a third direction, and a first conductive line extending along the third direction; the first semiconductor body and the second semiconductor body are located on the same side of two opposing sides of the third semiconductor body along the third direction, and the first conductive line is located at least on one side of two opposing sides of the first semiconductor body, the second semiconductor body, and the third semiconductor body along the second direction; the dimension of the third semiconductor body along the second direction is greater than the dimension of the second semiconductor body along the second direction and smaller than the dimension of the first semiconductor body along the second direction; the second direction intersects the third direction and is perpendicular to the first direction.

[0006] In the technical solution provided in this disclosure, the first semiconductor body, the second semiconductor body, and the third semiconductor body, which extend along the first direction and the second direction and are arranged along the third direction, have different dimensions along the second direction. The first semiconductor body and the second semiconductor body are located on the same side of opposite sides of the third semiconductor body along the third direction. The dimension of the third semiconductor body along the second direction is larger than that of the second semiconductor body along the second direction, and the dimension of the third semiconductor body along the second direction is smaller than that of the first semiconductor body along the second direction. In this embodiment of the disclosure, based on reserving a certain space for the conductive connection structure, the environmental difference between the area where the third semiconductor body is located and the areas where the second semiconductor body and the first semiconductor body are located is reduced, thereby improving the etching load effect when etching to form the semiconductor body. Attached Figure Description

[0007] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this disclosure.

[0008] Figure 2 A schematic diagram of DRAM provided in an embodiment of this disclosure.

[0009] Figure 3 This is a schematic diagram of the composition structure of the storage device provided in the embodiments of this disclosure.

[0010] Figure 4 Schematic diagram of the composition structure of the storage block provided in the embodiments of this disclosure Figure 1 .

[0011] Figure 5 This is a top view of the semiconductor body in the transistor of a memory cell located at the corner of a memory block or memory cell.

[0012] Figure 6Partial top view of the storage device provided in the embodiments of this disclosure Figure 1 .

[0013] Figure 7 This is a partial three-dimensional structural diagram of a storage device provided in an embodiment of this disclosure.

[0014] Figure 8 Partial top view of the storage device provided in the embodiments of this disclosure Figure 2 .

[0015] Figure 9 Partial top view of the storage device provided in the embodiments of this disclosure Figure 3 .

[0016] Figure 10 Partial top view of the storage device provided in the embodiments of this disclosure Figure 4 .

[0017] Figure 11 Partial top view of the storage device provided in the embodiments of this disclosure Figure 5 .

[0018] Figure 12 Schematic diagram of the composition structure of the storage block provided in the embodiments of this disclosure Figure 2 .

[0019] Figure 13 A schematic diagram of a partial cross-sectional structure of a storage device provided in an embodiment of this disclosure. Figure 1 .

[0020] Figure 14 Partial top view of the storage device provided in the embodiments of this disclosure Figure 6 .

[0021] Figure 15 Partial top view of the storage device provided in the embodiments of this disclosure Figure 7 .

[0022] Figure 16 A schematic diagram of a partial cross-sectional structure of a storage device provided in an embodiment of this disclosure. Figure 2 .

[0023] Figure 17 This is a schematic flowchart illustrating a method for fabricating a storage device according to an embodiment of the present disclosure.

[0024] Figures 18 to 27 This is a schematic diagram of the fabrication process of the storage device provided in the embodiments of this disclosure. Detailed Implementation

[0025] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0026] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0027] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0028] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] Figure 1This is a schematic diagram of an electronic device provided in an embodiment of this disclosure. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0031] like Figure 1 As shown, electronic device 1 may include a memory system 10 and a host 20. The memory system 10 may include a controller 110 and a memory 120. The host 20 may include a processor of electronic device 1, such as a central processing unit (CPU) or a system-on-chip (SoC) (e.g., an application processor (AP)). The controller 110 is coupled to both the host 20 and the memory 120, and the controller 110 may be configured to communicate with the host 20 and control the memory 120.

[0032] In some embodiments, controller 110 may be configured to control operations of memory 120, such as read operations, erase operations, write operations, refresh operations, etc. In some embodiments, controller 110 is also configured to process error correction codes (ECCs) regarding data read from or written to memory 120. In other embodiments, controller 110 may also be configured to perform any other suitable operation, such as formatting memory 120.

[0033] In some embodiments, controller 110 can receive data, commands, and addresses from host 20, and can send data, commands, and addresses to memory 120. Specifically, controller 110 may include command generator 111, address generator 112, device interface 113, and host interface 114. Controller 110 can receive data, commands, and addresses from host 20 through host interface 114, decode commands received from host 20 through command generator 111 to generate access command CMD, and provide access command CMD to memory 120 through device interface 113. Controller 110 can decode addresses received from host interface 114 through address generator 112 to generate address ADDR to be accessed in memory array 121, and provide the address ADDR to be accessed to memory 120 through device interface 113. The access command may be a signal instructing memory 120 to write or read data by accessing one or more memory cells in memory array 121 corresponding to address ADDR. In addition, the controller 110 can also send a refresh command to the memory 120. The refresh command can be a signal instructing the memory 120 to read and rewrite data by accessing one or more memory cells of the memory array 121 corresponding to the address ADDR.

[0034] In some specific examples, memory 120 can be random access memory (RAM), such as dynamic random access memory, synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), double data rate SDRAM (DDR SDRAM), phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), etc. The following explanation will use DRAM as an example.

[0035] In some embodiments, Figure 2 This is a schematic diagram of a DRAM according to an embodiment of the present disclosure. (Referring to...) Figure 1 and Figure 2The DRAM includes a memory array 121 and peripheral circuitry 122 coupled to the memory array 121. The peripheral circuitry 122 may include a sense amplifier circuit, a row decoder, a column decoder, a data input / output buffer, etc. The memory array 121 includes multiple memory cells arranged in an array. Multiple memory cells in the same row are coupled to a word line WL, and multiple memory cells in the same column are coupled to a bit line BL. Each memory cell includes a transistor T and a capacitor C. The word line WL is connected to the gate of transistor T, the bit line BL is connected to one of the source and drain of transistor T, and the other of the source and drain of transistor T is connected to one electrode of capacitor C. The other electrode of capacitor C is connected to a fixed voltage. The memory cell is configured to store 1 or 0 by using more or less charge stored in capacitor C. By specifying the row address and column address, each memory cell in the DRAM chip can be accessed independently, and read, write, or refresh operations can be performed on the stored data.

[0036] like Figure 3 as well as Figure 4 As shown, the memory 120 includes at least one chip 210, each chip 210 includes at least one bank group 211, each bank group 211 includes at least one bank 212, and each bank 212 includes at least one block 213. Each block includes a storage area 214 and a virtual area 215. The virtual area 215 is located at the edge region of the block, and the virtual area 215 can be located on opposite sides of the storage area 214 along the X direction and on opposite sides of the storage area along the Y direction. The storage cells in the storage area 214 can be used for storage, while the storage cells in the virtual area 215 can be not used for storage.

[0037] In some embodiments, each memory block includes a plurality of rows of memory cells arranged along the Y direction and a plurality of columns of memory cells arranged along the axial direction. Each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line. Word lines of adjacent memory blocks are separated by corresponding isolation structures, and bit lines of adjacent memory blocks are separated by corresponding isolation structures. Word lines of adjacent memory banks are separated by corresponding isolation structures, and bit lines of adjacent memory banks are separated by corresponding isolation structures.

[0038] Figure 5 This is a top view schematic diagram of the semiconductor body in the transistor of a memory cell located at the corner of a memory block or memory cell. For example, Figure 5 It can be Figure 4 The structure at point A within the dashed box. Figure 4 The area within the dashed box represents the virtual region near the corner of the storage block. For example... Figure 5 As shown, the virtual area near the corner of the storage block includes a first region 305 and a second region 306 arranged along the X direction, with the second region 306 being the region near the edge. From Figure 5 It can be seen that the dimensions of the multiple semiconductor bodies 327 arranged along the X direction in the first region and the second region are not consistent along the Y direction. Specifically, the semiconductor bodies 327 in the first region 305 have different lengths along the Y direction, and the long semiconductor bodies and the short semiconductor bodies are arranged alternately along the X direction. In order to reserve space for the setting of the corresponding conductive connection structure, the semiconductor bodies in the second region 306 located at the edge have shorter dimensions along the Y axis and are equal to the dimensions of the short semiconductor bodies in the first region 305 along the Y direction.

[0039] In some embodiments, the semiconductor bodies and word lines in the memory described above can be formed as follows: etching is performed on the first surface of the semiconductor layer to form a plurality of semiconductor bodies arranged in an array along the X and Y directions, and initial word lines are formed from the first surface of the semiconductor layer; then, the semiconductor layer is thinned from the second surface of the semiconductor layer to cut the initial word lines, so that one initial word line corresponds to two word lines, and the first and second surfaces are two opposite surfaces of the semiconductor layer along the thickness direction of the semiconductor layer. On the one hand, since... Figure 5 As shown, the virtual regions (second regions) at the corners of the memory block or the memory cell contain only short semiconductor bodies, while the semiconductor bodies in the virtual regions (second regions) in the middle part vary in length. On the other hand, there are more isolation structures in the virtual regions at the corners of the memory block or the memory cell, which makes the virtual regions at the corners of the memory block or the memory cell significantly different from their surrounding environment. As a result, when etching the semiconductor layer to form the semiconductor bodies, the etching load effect in different regions is greater, and the etching depth in the virtual regions at the corners is shallower than that in the virtual regions in the middle part. This means that when thinning the semiconductor layer from the second side of the semiconductor layer, the semiconductor layers between adjacent semiconductor bodies in the virtual regions at the corners of the memory block or the memory cell are not separated, which affects the cutting of the initial word lines in subsequent processes.

[0040] The present disclosure provides the following implementation methods.

[0041] This disclosure provides a storage device, Figure 6 This is a partial top view of the storage device provided in an embodiment of the present disclosure. Figure 7 This is a partial three-dimensional structural diagram of the storage device provided in the embodiments of this disclosure, such as... Figure 6 as well as Figure 7As shown, the storage device includes a first semiconductor body 300, a second semiconductor body 301, and a third semiconductor body 302, all extending along a first direction and a second direction and arranged along a third direction, and a first conductive line 303 extending along the third direction; the first semiconductor body 300 and the second semiconductor body 301 are located on the same side of the third semiconductor body 302 on opposite sides along the third direction, and the first conductive line 303 is located on at least one side of the first semiconductor body 300, the second semiconductor body 301, and the third semiconductor body 302 on opposite sides along the second direction; the dimension of the third semiconductor body 302 along the second direction is larger than the dimension of the second semiconductor body 301 along the second direction, and smaller than the dimension of the first semiconductor body 300 along the second direction; the second direction intersects the third direction and is perpendicular to the first direction.

[0042] Figure 6 as well as Figure 7 Specifically, it could be Figure 4 A schematic diagram of the structure at point B within the dashed box.

[0043] It should be noted that the third semiconductor body can be located not only in the edge region of the memory, and the above embodiments can be for optimizing the edge region of the memory; the third semiconductor body can also be located in the edge region of the memory block in the memory, and the above embodiments can be for optimizing the edge region of the memory block in the memory. Furthermore, the third semiconductor body can be located in the edge region of at least some of the memory blocks in the memory, and the third semiconductor body can be located in the internal region of the memory.

[0044] In this embodiment, the first semiconductor body 300, the second semiconductor body 301, and the third semiconductor body 302, which extend along the first direction and the second direction and are arranged along the third direction, have different dimensions along the second direction. The first semiconductor body 300 and the second semiconductor body 301 are located on the same side of the opposite sides of the third semiconductor body 302 along the third direction. The dimension of the third semiconductor body 302 along the second direction is larger than that of the second semiconductor body 301 along the second direction, and the dimension of the third semiconductor body 302 along the second direction is smaller than that of the first semiconductor body 300 along the second direction. In this embodiment, by reserving a certain space for the conductive connection structure, the environmental difference between the area where the third semiconductor body is located and the areas where the second semiconductor body and the first semiconductor body are located is reduced, thereby improving the etching load effect when etching to form the semiconductor body.

[0045] In this embodiment of the disclosure, the first direction can be the Z-axis direction shown in the figure, the second direction can be the Y-axis direction shown in the figure, and the third direction can be the X-axis direction shown in the figure.

[0046] In some specific examples, the materials of the first semiconductor body 300, the second semiconductor body 301, the third semiconductor body 302, and the fourth semiconductor body (described below) include, but are not limited to, elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The materials of the first semiconductor body 300, the second semiconductor body 301, the third semiconductor body 302, and the fourth semiconductor body are the same.

[0047] In this embodiment, the semiconductor body extends along the Z-direction, and the transistors of the memory cells are vertical transistors. The semiconductor body includes a source, a channel region, and a drain arranged along the Z-direction, and the first conductive line 303 is located on one of the opposite sides of the channel region along the Y-direction. Figure 6 as well as Figure 7 As shown, in this embodiment of the present disclosure, the storage device further includes a plurality of fifth semiconductor bodies 326 located in the storage area 214. The plurality of fifth semiconductor bodies 326 are arranged in an array along a second direction and a third direction, and all fifth semiconductor bodies 326 extend along a first direction. The dimensions of the plurality of fifth semiconductor bodies 326 along the second direction may be equal. In this embodiment of the present disclosure, the storage device also includes a plurality of first conductive lines 303 located in the storage area 214, arranged along the second direction and all extending along a third direction. The first conductive lines 303 in the storage area 214 are located at least on one side of the plurality of fifth semiconductor bodies 326 arranged along the third direction opposite to each other along the second direction. The first conductive lines 303 may be word lines. It should be noted that... Figure 6 as well as Figure 7 The present disclosure takes as an example that the first conductive line 303 is located on one side of one of the multiple fifth semiconductor bodies 326 arranged along the third direction and opposite to each other along the second direction, and the first conductive line is located on at least one side of one of the first semiconductor body, the second semiconductor body and the third semiconductor body and opposite to each other along the second direction, but the present disclosure is not limited thereto.

[0048] In some specific examples, the material of the first conductive line 303 includes at least one of conductive materials, such as doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0049] In some specific examples, such as Figure 6 as well as Figure 7 As shown, a gate dielectric layer 304 is further disposed between the first conductive line 303 and the corresponding semiconductor body. The gate dielectric layer 304 may be located between the first conductive line 303 and the channel region of the corresponding semiconductor body. The gate dielectric layer 304 may include at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride. The high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0050] In some embodiments, such as Figure 6 as well as Figure 7 As shown, the storage device includes a first region 305 and a second region 306 arranged side-by-side along the third direction. The storage device includes a plurality of first semiconductor bodies 300, a plurality of second semiconductor bodies 301, and a plurality of third semiconductor bodies 302 arranged along the third direction. The plurality of first semiconductor bodies 300 and the plurality of second semiconductor bodies 301 are located in the first region 305, and the plurality of third semiconductor bodies 302 are located in the second region 306. The plurality of first semiconductor bodies 300 and the plurality of second semiconductor bodies 301 are arranged alternately along the third direction.

[0051] In this embodiment, a plurality of first semiconductor bodies 300 and a plurality of second semiconductor bodies 301 in the first region 305 are arranged alternately along the third direction, that is, long and short semiconductor bodies are arranged alternately, which makes the subsequent conductive connection structure more flexible. It should be noted that this disclosure also applies to the case where the dimensions of the first semiconductor bodies in the first region along the second direction are equal to the dimensions of the second semiconductor bodies along the second direction.

[0052] In some embodiments, the storage device includes a plurality of memory cells, and the second region 306 is a region at the corner of the memory cell; or, the storage device includes a plurality of memory blocks, and the second region 306 is a region at the corner of the memory block.

[0053] It should be noted that, Figure 7It can be just a single storage block or a single storage volume, such as Figure 4 A partial structural diagram at the dashed line. In this embodiment, the first region 305 and the second region 306 can be regions in a virtual area, and the arrangement direction of the first region 305 and the second region 306 is the same as the extension direction of the first conductive line 303, and the second region 306 is located at the corner of the memory cell or the corner of the memory block.

[0054] In this embodiment, the dimensions of the semiconductor body at the corner of a portion of the memory block along the second direction can be optimized accordingly, for example, the semiconductor body at the corner of the memory block can be optimized accordingly; alternatively, the dimensions of the semiconductor body at the corner of all memory blocks along the second direction can be optimized accordingly. The appropriate selection can be made by comprehensively considering the space required for the corresponding conductive connection structure and the influence of the load effect.

[0055] In this embodiment of the present disclosure, the dimension of the third semiconductor body 302 in the second region 306 at the corner of the memory cell or the second region 306 at the corner of the memory block along the second direction is set between the dimension of the first semiconductor body 300 along the second direction and the dimension of the second semiconductor body 301 along the second direction, thereby reducing the environmental difference between the second region 306 and the first region 305, thereby reducing the load effect during the etching process and improving the problem that the final initial word line cannot be cut due to the etching load effect.

[0056] In some embodiments, such as Figure 8 As shown, the storage device further includes a third region 307 located between the first region 305 and the second region 306; a portion of the plurality of first semiconductor bodies 300 are located in the third region 307; the storage device further includes a plurality of fourth semiconductor bodies 308 located in the third region 307, each extending along the first direction and the second direction and arranged along the third direction; the first semiconductor bodies 300 and the fourth semiconductor bodies 308 in the third region 307 are arranged alternately along the third direction; the dimension of the fourth semiconductor body 308 along the second direction is greater than the dimension of the second semiconductor body 301 along the second direction, and less than or equal to the dimension of the third semiconductor body 302 along the second direction.

[0057] In this embodiment of the present disclosure, the dimension of the fourth semiconductor body 308 in the third region 307 along the second direction is less than or equal to the dimension of the third semiconductor body 302 along the second direction, which may include several cases: 1. The dimensions of the fourth semiconductor body 308 in the third region 307 along the second direction may all be less than the dimension of the third semiconductor body 302 along the second direction; 2. Alternatively, the dimensions of the fourth semiconductor body 308 near the first region 305 in the third region 307 along the second direction may be less than the dimension of the third semiconductor body 302 along the second direction, and the dimensions of the fourth semiconductor body 308 near the second region 306 in the third region 307 along the second direction may be equal to the dimension of the third semiconductor body 302 along the second direction; 3. The dimensions of the fourth semiconductor body 308 in the third region 307 along the second direction may all be equal to the dimension of the third semiconductor body 302 along the second direction.

[0058] In this embodiment of the present disclosure, by setting the size of the fourth semiconductor body 308 in the third region 307 along the second direction to be larger than the size of the second semiconductor body 301 in the first region 305 along the second direction, the difference between the first region and the surrounding environment can be further reduced, thereby further reducing the load effect during the etching process.

[0059] In some embodiments, such as Figure 8 As shown, along the direction from the first region 305 to the second region 306, the dimensions of the plurality of fourth semiconductor bodies 308 increase sequentially along the second direction; or, as... Figure 9 As shown, along the direction from the first region 305 to the second region 306, the dimensions of the fourth semiconductor bodies 308 closer to the first region 305 increase sequentially along the second direction, and the dimensions of the fourth semiconductor bodies 308 farther from the first region 305 are equal along the second direction.

[0060] In the above embodiments, the direction from the first region 305 to the second region 306 can be Figure 8 as well as Figure 9 The arrows shown indicate the direction. Along the direction from the first region 305 to the second region 306, the dimensions of at least some of the fourth semiconductor bodies 308 in the third region 307 are set to increase sequentially in the second direction, so that the difference between the second region and the surrounding environment can be further reduced, thereby further reducing the load effect during the etching process.

[0061] In some embodiments, such as Figure 8 as well as Figure 9As shown, the plurality of third semiconductor bodies 302 have equal dimensions along the second direction, and the dimensions of the plurality of third semiconductor bodies 302 along the second direction are equal to the dimensions of the fourth semiconductor body 308 closest to the third semiconductor body 302 along the second direction.

[0062] In this embodiment of the disclosure, the dimensions of the plurality of third semiconductor bodies 302 along the second direction are equal, and the dimensions of the plurality of third semiconductor bodies 302 along the second direction can be equal to the dimensions of the fourth semiconductor body 308 closest to the third semiconductor body 302 along the second direction. The dimensions of the plurality of third semiconductor bodies 302 along the second direction can also be greater than the dimensions of the fourth semiconductor body 308 closest to the third semiconductor body 302 along the second direction.

[0063] In some embodiments, the plurality of first semiconductor bodies 300 have equal dimensions along the second direction, and the plurality of second semiconductor bodies 301 have equal dimensions along the second direction.

[0064] It should be noted that the equal dimensions of multiple third semiconductor bodies 302 along the second direction means that their dimensions are substantially equal within the allowable process error range; the equal dimensions of multiple first semiconductor bodies 300 along the second direction means that their dimensions are substantially equal within the allowable process error range; and the equal dimensions of multiple second semiconductor bodies 301 along the second direction means that their dimensions are substantially equal within the allowable process error range.

[0065] In some embodiments, such as Figure 10 As shown, the distance between two adjacent third semiconductor bodies 302 in the second region 306 is greater than the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305.

[0066] In the above embodiments, based on the optimization of the dimensions of the third semiconductor body 302 in the second region 306 along the second direction, the distance between two adjacent third semiconductor bodies 302 in the second region 306 is also optimized accordingly. Specifically, the distance between two adjacent third semiconductor bodies 302 in the second region 306 is set differently from the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305, and the distance between two adjacent third semiconductor bodies 302 in the second region 306 is set larger. This allows the difference between the second region 306 and the surrounding environment to be further reduced, thereby further reducing the load effect during the etching process.

[0067] In some embodiments, the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is greater than the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305, and the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is less than or equal to the distance between adjacent third semiconductor bodies 302 in the second region 306.

[0068] In this embodiment of the present disclosure, the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is less than or equal to the distance between adjacent third semiconductor bodies 302 in the second region 306, which may include several situations: 1. The distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is less than the distance between adjacent third semiconductor bodies 302 in the second region 306; 2. The distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is equal to the distance between adjacent third semiconductor bodies 302 in the second region 306; 3. The distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 that are closer to the first region 305 is less than the distance between adjacent third semiconductor bodies 302 in the second region 306, and the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 that are closer to the second region 306 is equal to the distance between adjacent third semiconductor bodies 302 in the second region 306.

[0069] In the above embodiments, the distance between the adjacent first semiconductor body 300 and fourth semiconductor body 308 in the third region 307 is optimized accordingly, so that the difference between the second region 306 and the surrounding environment can be further reduced, thereby further reducing the load effect during the etching process.

[0070] In some embodiments, along the direction from the first region 305 to the second region 306, the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 increases sequentially.

[0071] In the above embodiments, the distance between the adjacent first semiconductor body 300 and fourth semiconductor body 308 in the third region 307 is further optimized, so that the difference between the second region 306 and the surrounding environment can be further reduced while saving the area of ​​the memory device, thereby further reducing the load effect during the etching process.

[0072] In some embodiments, along the direction from the first region 305 to the second region 306, the distance between adjacent third semiconductor bodies 302 in the second region 306 increases sequentially; or, the distance between adjacent third semiconductor bodies 302 in the second region 306 is equal.

[0073] In some specific examples, the distance between adjacent third semiconductor bodies 302 in the portion of the plurality of third semiconductor bodies 302 in the second region 306 that are closer to the first region 305 increases sequentially from the first region 305 toward the second region 306, while the distance between adjacent third semiconductor bodies 302 in the portion of the plurality of third semiconductor bodies 302 in the second region 306 that are farther away from the first region 305 is equal.

[0074] In some embodiments, the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is D1, the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305 is D2, and the range of (D1-D2) / D2 is 0 to 50%; the distance between adjacent third semiconductor bodies 302 in the second region 306 is D3, and the range of (D3-D2) / D2 is 0 to 50%.

[0075] It should be noted that the ranges of (D1-D2) / D2 and (D3-D2) / D2 given in the above embodiments are merely examples and are not intended to limit the ranges of (D1-D2) / D2 and (D3-D2) / D2 in the embodiments of this disclosure. In some specific examples, the ranges of (D1-D2) / D2 and (D3-D2) / D2 can be set by combining the area of ​​the memory and the etching load effect.

[0076] In some embodiments, the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305 is equal.

[0077] It should be noted that the equal distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305 means that the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 is substantially equal within the allowable process error range.

[0078] In some embodiments, such as Figure 11As shown, the storage device further includes a plurality of second conductive lines 309, a plurality of third conductive lines 310, and a plurality of fourth conductive lines 311, all extending along the second direction and arranged along the third direction; one end of one of the opposite ends of a first semiconductor body 300 along the first direction is connected to a second conductive line 309, one end of one of the opposite ends of a second semiconductor body 301 along the first direction is connected to a third conductive line 310, and one end of one of the opposite ends of a third semiconductor body 302 along the first direction is connected to a fourth conductive line 311; the portion of the fourth conductive line 311 located in the second region 306 has a dimension along the second direction that is larger than the portion of the third conductive line 310 located in the first region 305 along the second direction, and smaller than the portion of the second conductive line 309 located in the first region 305 along the second direction.

[0079] In some embodiments, such as Figure 11 As shown, the side of the second conductive line 309 connected to the first semiconductor body 300 that is opposite to the storage region 214 along the second direction is aligned with the side of the first semiconductor body 300 that is opposite to the storage region 214 along the second direction. The side of the third conductive line 310 connected to the second semiconductor body 301 that is opposite to the storage region 214 along the second direction is aligned with the side of the second semiconductor body 301 that is opposite to the storage region 214 along the second direction. The side of the fourth conductive line 311 connected to the third semiconductor body 302 that is opposite to the storage region 214 along the second direction is aligned with the side of the third semiconductor body 302 that is opposite to the storage region 214 along the second direction.

[0080] In other embodiments, the dimensions of the portions of the plurality of second conductive lines 309 located in the first region 305 along the second direction, the dimensions of the portions of the plurality of third conductive lines 310 located in the first region 305 along the second direction, and the dimensions of the portions of the plurality of fourth conductive lines 311 located in the second region 306 along the second direction may all be equal.

[0081] The second conductive line 309, the third conductive line 310, and the fourth conductive line 311 can be bit lines in a storage device. The materials of the second conductive line 309, the third conductive line 310, and the fourth conductive line 311 can include conductive materials, including but not limited to metal materials and metal silicides. Metal materials include but are not limited to tungsten, titanium, tantalum, and aluminum. Metal silicides include but are not limited to tungsten silicide, nickel silicide, cobalt silicide, and titanium silicide.

[0082] In some specific examples, the distances between the second conductive line 309, the third conductive line 310, and the fourth conductive line 311 in each region can follow a consistent trend with the distances between the corresponding connected first semiconductor body 300, second semiconductor body 301, and third semiconductor body 302.

[0083] Figure 12 This is a schematic diagram of the composition structure of a storage block. (For example...) Figure 4 as well as Figure 12 As shown, the memory block includes a memory area 214 and a virtual area surrounding the memory area 214. The first region 305, the second region 306, and the third region 307 can be located in the virtual area on one side of the memory block opposite each other along the second direction, or the first region 305, the second region 306, and the third region 307 can be provided on both sides of the memory block opposite each other along the second direction. Furthermore, for one side of the first region 305, the second region 306, and the third region 307 of a memory block opposite each other along the second direction, the second region 306 can be located on both sides of the first region 305 opposite each other along the third direction, or the second region 306 can be located on both sides of the first region 305 opposite each other along the third direction, forming a whole, and the third region 307 can be located on both sides of the first region 305 opposite each other along the third direction. In other words, in this embodiment, the dimensions of the semiconductor bodies at at least some of the four corners of the memory block along the second direction and the distance between adjacent semiconductor bodies can be optimized accordingly.

[0084] Figure 13 for Figure 11 A schematic diagram of the cross-sectional structure at position AA'. In some embodiments, such as Figure 13 As shown, the storage device further includes a plurality of first semiconductor lines 312, a plurality of second semiconductor lines 313, and a plurality of third semiconductor lines 314 extending along the second direction and arranged along the third direction; the first semiconductor lines 312 are located between the first semiconductor body 300 and the second conductive line 309, the second semiconductor lines 313 are located between the second semiconductor body 301 and the third conductive line 310, and the third semiconductor lines 314 are located between the third semiconductor body 302 and the fourth conductive line 311; the dimension of the first semiconductor line 312 along the second direction is equal to the dimension of the second conductive line 309 along the second direction, the dimension of the second semiconductor line 313 along the second direction is equal to the dimension of the third conductive line 310 along the second direction, and the dimension of the third semiconductor line 314 along the second direction is equal to the dimension of the fourth conductive line 311 along the second direction.

[0085] In some specific examples, the materials of the first semiconductor line 312, the second semiconductor line 313, and the third semiconductor line 314 are the same as the materials of the first semiconductor body 300, the second semiconductor body 301, and the third semiconductor body 302.

[0086] Based on a concept similar to the storage device described above, this disclosure also provides a storage device. Figure 14 This is a partial structural diagram of a storage device, such as... Figure 14 As shown, the storage device includes a first region 305 and a second region 306; the first region 305 includes a plurality of first semiconductor bodies 300 and a plurality of second semiconductor bodies 301, and the second region 306 includes a plurality of third semiconductor bodies 302. The plurality of first semiconductor bodies 300, the plurality of second semiconductor bodies 301, and the plurality of third semiconductor bodies 302 extend along a first direction and a second direction and are arranged along a third direction. The plurality of first semiconductor bodies 300 and the plurality of second semiconductor bodies 301 are arranged alternately along the third direction. The first region 305 and the second region 306 are arranged along the third direction. The arrangement is as follows: the first region 305 and the second region 306 also include a first conductive line 303 extending along the third direction, the first conductive line 303 being located at least on one side of the plurality of first semiconductor bodies 300, the plurality of second semiconductor bodies 301 and the plurality of third semiconductor bodies 302 opposite to each other along the second direction; the second direction intersects with the third direction and is perpendicular to the first direction; the distance between two adjacent third semiconductor bodies 302 in the second region 306 is greater than the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305.

[0087] In this embodiment of the disclosure, Figure 14 It can be Figure 4 The diagram shows the structure at point B within the dashed box. The first direction can be... Figure 14 The Z-axis direction shown in the figure can be the second direction, which can be the Y-axis direction shown in the figure, and the third direction can be the X-axis direction shown in the figure.

[0088] In some specific examples, the materials of the first semiconductor body 300, the second semiconductor body 301, the third semiconductor body 302, and the fourth semiconductor body 308 include, but are not limited to, elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The materials of the first semiconductor body 300, the second semiconductor body 301, the third semiconductor body 302, and the fourth semiconductor body 308 are the same.

[0089] In this embodiment of the present disclosure, the distance between two adjacent third semiconductor bodies 302 in the second region 306 is optimized accordingly. The distance between two adjacent third semiconductor bodies 302 in the second region 306 is set differently from the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305. The distance between two adjacent third semiconductor bodies 302 in the second region 306 is set to be larger. This reduces the difference between the second region 306 and the surrounding environment, thereby reducing the load effect during the etching process.

[0090] In some specific examples, such as Figure 14 As shown, a gate dielectric layer 304 is further disposed between the first conductive line 303 and the corresponding semiconductor body. The gate dielectric layer 304 may be located between the first conductive line 303 and the channel region of the corresponding semiconductor body. The gate dielectric layer 304 may include at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride. The high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0091] In some embodiments, such as Figure 15As shown, the storage device further includes a third region 307 located between the first region 305 and the second region 306, and a portion of the plurality of first semiconductor bodies 300 are located in the third region 307. The storage device also includes a plurality of fourth semiconductor bodies 308 located in the third region 307, each extending along the first direction and the second direction and arranged along the third direction. The first semiconductor bodies 300 and the fourth semiconductor bodies 308 in the third region 307 are arranged alternately along the third direction. The distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is greater than the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305, and the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is less than or equal to the distance between adjacent third semiconductor bodies 302 in the second region 306.

[0092] In this embodiment of the present disclosure, the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is less than or equal to the distance between adjacent third semiconductor bodies 302 in the second region 306, which may include several situations: 1. The distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is less than the distance between adjacent third semiconductor bodies 302 in the second region 306; 2. The distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is equal to the distance between adjacent third semiconductor bodies 302 in the second region 306; 3. The distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 that are closer to the first region 305 is less than the distance between adjacent third semiconductor bodies 302 in the second region 306, and the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 that are closer to the second region 306 is equal to the distance between adjacent third semiconductor bodies 302 in the second region 306.

[0093] In the above embodiments, the distance between the adjacent first semiconductor body 300 and fourth semiconductor body 308 in the third region 307 is optimized accordingly, so that the difference between the second region 306 and the surrounding environment can be further reduced, thereby further reducing the load effect during the etching process.

[0094] In some embodiments, along the direction from the first region 305 to the second region 306, the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 increases sequentially.

[0095] In the above embodiments, the distance between the adjacent first semiconductor body 300 and fourth semiconductor body 308 in the third region 307 is further optimized, so that the difference between the second region 306 and the surrounding environment can be further reduced while saving the area of ​​the memory device, thereby further reducing the load effect during the etching process.

[0096] In some embodiments, along the direction from the first region 305 to the second region 306, the distance between adjacent third semiconductor bodies 302 in the second region 306 increases sequentially; or, the distance between adjacent third semiconductor bodies 302 in the second region 306 is equal.

[0097] In some specific examples, the distance between adjacent third semiconductor bodies 302 in the portion of the plurality of third semiconductor bodies 302 in the second region 306 that are closer to the first region 305 increases sequentially from the first region 305 toward the second region 306, while the distance between adjacent third semiconductor bodies 302 in the portion of the plurality of third semiconductor bodies 302 in the second region 306 that are farther away from the first region 305 is equal.

[0098] In some embodiments, the distance between adjacent first semiconductor bodies 300 and fourth semiconductor bodies 308 in the third region 307 is D1, the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305 is D2, and the range of (D1-D2) / D2 is 0 to 50%; the distance between adjacent third semiconductor bodies 302 in the second region 306 is D3, and the range of (D3-D2) / D2 is 0 to 50%.

[0099] In some embodiments, the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305 is equal.

[0100] It should be noted that the equal distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 in the first region 305 means that the distance between adjacent first semiconductor bodies 300 and second semiconductor bodies 301 is substantially equal within the allowable process error range.

[0101] In some embodiments, such as Figure 16As shown, the storage device further includes a plurality of second conductive lines 309, a plurality of third conductive lines 310, and a plurality of fourth conductive lines 311, all extending along the second direction and arranged along the third direction; one end of one of the opposite ends of a first semiconductor body 300 along the first direction is connected to a second conductive line 309, one end of one of the opposite ends of a second semiconductor body 301 along the first direction is connected to a third conductive line 310, and one end of one of the opposite ends of a third semiconductor body 302 along the first direction is connected to a fourth conductive line 311; the distance between two adjacent fourth conductive lines 311 is greater than the distance between adjacent second conductive lines 309 and third conductive lines 310.

[0102] In some embodiments, the storage device includes a plurality of memory cells, and the second region 306 is a region at the corner of the memory cell; or, the storage device includes a plurality of memory blocks, and the second region 306 is a region at the corner of the memory block.

[0103] In some embodiments, such as Figure 16 As shown, the storage device further includes a plurality of first semiconductor lines 312, a plurality of second semiconductor lines 313, and a plurality of third semiconductor lines 314 extending along the second direction and arranged along the third direction; the first semiconductor lines 312 are located between the first semiconductor body 300 and the second conductive line 309, the second semiconductor lines 313 are located between the second semiconductor body 301 and the third conductive line 310, and the third semiconductor lines 314 are located between the third semiconductor body 302 and the fourth conductive line 311; the distance between two adjacent third semiconductor lines 314 is greater than the distance between adjacent first semiconductor lines 312 and second semiconductor lines 313.

[0104] Based on the above-described storage device, this disclosure also provides a method for manufacturing the storage device. Figure 17 A schematic flowchart illustrating a method for manufacturing a storage device according to an embodiment of this disclosure is shown below. Figure 17 As shown, the method for manufacturing this storage device includes the following steps:

[0105] Step S10: Form a first semiconductor body, a second semiconductor body, and a third semiconductor body that extend along a first direction and a second direction and are arranged along a third direction, and a first conductive line extending along the third direction; the first semiconductor body and the second semiconductor body are located on the same side of the opposite sides of the third semiconductor body along the third direction, and the first conductive line is located on at least one side of the opposite sides of the first semiconductor body, the second semiconductor body, and the third semiconductor body along the second direction; the dimension of the third semiconductor body along the second direction is greater than the dimension of the second semiconductor body along the second direction and smaller than the dimension of the first semiconductor body along the second direction; the second direction intersects the third direction and is perpendicular to the first direction.

[0106] In some embodiments, the storage device includes a first region and a second region arranged side by side along the second direction, the storage device including a plurality of first semiconductor bodies, a plurality of second semiconductor bodies and a plurality of third semiconductor bodies; the plurality of first semiconductor bodies and the plurality of second semiconductor bodies are located in the first region, and the plurality of third semiconductor bodies are located in the second region; the plurality of first semiconductor bodies and the plurality of second semiconductor bodies are arranged alternately along the second direction.

[0107] In some embodiments, the storage device includes a plurality of memory cells, and the second region 306 is a region at the corner of the memory cell; or, the storage device includes a plurality of memory blocks, and the second region 306 is a region at the corner of the memory block.

[0108] Figures 18 to 27 The diagram below illustrates the fabrication process of the storage device according to an embodiment of this disclosure. Figures 18 to 27 A method for manufacturing a storage device provided in the embodiments of this disclosure will be described.

[0109] It should be noted that, Figures 18 to 27 Only illustrative examples are shown. Figure 4 A schematic diagram of the formation process of the structure corresponding to the dashed box A. In this embodiment, the first region 305 and the second region 306 can be regions in a virtual area, and the arrangement direction of the first region 305 and the second region 306 is the same as the extension direction of the first conductive line, and the second region 306 is located at the corner of the memory cell or the corner of the memory block.

[0110] In some embodiments, forming a plurality of first semiconductor bodies, a plurality of second semiconductor bodies, and a plurality of third semiconductor bodies includes: providing a plurality of initial first semiconductor bodies, a plurality of initial second semiconductor bodies, and a plurality of initial third semiconductor bodies located in the first region; the plurality of initial first semiconductor bodies, the plurality of initial second semiconductor bodies, and the plurality of initial third semiconductor bodies all extend along the first direction and the second direction and are arranged along the third direction, and the plurality of initial first semiconductor bodies and the plurality of initial second semiconductor bodies are arranged alternately along the third direction.

[0111] In some embodiments, the storage device further includes a third region located between the first region and the second region.

[0112] In some embodiments, a portion of the plurality of initial first semiconductor bodies are located in the third region; the method further includes: providing a plurality of initial fourth semiconductor bodies located in the third region, each extending along the first direction and the second direction and arranged along the third direction.

[0113] Figures 18 to 24 A schematic diagram illustrating the structure for forming multiple initial first semiconductor bodies, multiple initial second semiconductor bodies, multiple initial third semiconductor bodies, and multiple initial fourth semiconductor bodies. The following will combine... Figures 18 to 24 Further details.

[0114] In some embodiments, forming the plurality of initial first semiconductor bodies, the plurality of initial second semiconductor bodies, the plurality of initial third semiconductor bodies, and the plurality of initial fourth semiconductor bodies includes: as follows Figure 18 As shown, an initial semiconductor layer 315 is provided in the first region 305, the second region 306, and the third region 307; Figure 20 for Figure 19 A schematic diagram of the cross-sectional structure at BB' is shown below. Figure 19 as well as Figure 20 As shown, a second mask layer 316 is formed on the initial semiconductor layer 315; a second mask pattern is formed in the second mask layer 316, the second mask pattern including a plurality of mask lines 318 extending along the second direction and arranged along the third direction; the distance between two adjacent mask lines 318 in the second region 306 is greater than the distance between adjacent mask lines 318 in the first region 305, and the size of the mask lines 318 in the second region 306 along the third direction is greater than the size of the mask lines 318 in the first region 305 along the third direction.

[0115] In some embodiments, forming the plurality of initial first semiconductor bodies, the plurality of initial second semiconductor bodies, the plurality of initial third semiconductor bodies, and the plurality of initial fourth semiconductor bodies further includes: as... Figure 21 As shown, a third mask layer 319 is formed to conformally cover the second mask layer 316 and the initial semiconductor layer 315; as Figure 22 As shown, a portion of the third mask layer 319 is removed, leaving the remaining third mask layer 319 covering the sidewalls of the mask line 318; as Figure 23 As shown, remove the mask lines 318 in the second mask layer 316; as Figure 24 As shown, the initial semiconductor layer 315 is etched using the remaining third mask layer 319 as a mask to form a plurality of initial first semiconductor bodies 320, a plurality of initial second semiconductor bodies 321, a plurality of initial third semiconductor bodies 322, and a plurality of initial fourth semiconductor bodies 323.

[0116] In some embodiments, the initial first semiconductor body 320 and the initial fourth semiconductor body 323 in the third region 307 are arranged alternately along the third direction.

[0117] In some embodiments, the distance between adjacent mask lines 318 in the third region 307 is greater than the distance between adjacent mask lines 318 in the first region 305, and the dimension of the mask line 318 in the third region 307 along the third direction is greater than the dimension of the mask line 318 in the first region 305 along the third direction; and the distance between adjacent mask lines 318 in the third region 307 is less than or equal to the distance between adjacent mask lines 318 in the second region 306, and the dimension of the mask line 318 in the third region 307 along the third direction is less than or equal to the dimension of the mask line 318 in the second region 306 along the third direction.

[0118] In some embodiments, along the direction from the first region 305 to the second region 306, the distance between adjacent mask lines 318 in the third region 307 increases sequentially, and the size of the mask lines 318 in the third region 307 increases sequentially along the third direction.

[0119] In some embodiments, along the direction from the first region 305 to the second region 306, the distance between adjacent mask lines 318 in the second region 306 increases sequentially, and the size of the mask lines 318 in the second region 306 increases sequentially along the third direction; or, the distance between adjacent mask lines 318 in the second region 306 is equal, and the size of the mask lines 318 in the second region 306 is equal along the third direction.

[0120] Figures 25 to 27 This is a schematic diagram illustrating the structure of multiple first semiconductor bodies, multiple second semiconductor bodies, multiple third semiconductor bodies, and multiple fourth semiconductor bodies formed based on multiple initial first semiconductor bodies, multiple initial second semiconductor bodies, multiple initial third semiconductor bodies, and multiple initial fourth semiconductor bodies. The following will combine... Figures 25 to 27 Further details.

[0121] In some embodiments, forming a plurality of first semiconductor bodies, a plurality of second semiconductor bodies, and a plurality of third semiconductor bodies further includes: Figure 26 for Figure 25 A schematic diagram of the cross-sectional structure at CC', as shown below. Figure 25 as well as Figure 26 As shown, a first mask layer 324 is formed on the plurality of initial first semiconductor bodies 320, the plurality of initial second semiconductor bodies 321, and the plurality of third initial semiconductor bodies; a first mask pattern 325 is formed in the first mask layer 324, and the size of the first mask pattern 325 directly above the initial third semiconductor body 322 along the second direction is larger than the size of the first mask pattern 325 directly above the initial second semiconductor body 321 along the second direction, and smaller than the size of the first mask pattern 325 directly above the initial first semiconductor body 320 along the second direction.

[0122] like Figure 27 As shown, the plurality of initial first semiconductor bodies 320, the plurality of initial second semiconductor bodies 321, and the plurality of third initial semiconductor bodies are etched based on the first mask pattern 325 to form the plurality of first semiconductor bodies 300, the plurality of second semiconductor bodies 301, and the plurality of third semiconductor bodies 302.

[0123] In some embodiments, such as Figure 25 as well as Figure 26 As shown, while the first mask layer 324 is formed on the plurality of initial first semiconductor bodies 320, the plurality of initial second semiconductor bodies 321, and the plurality of third initial semiconductor bodies, the first mask layer 324 is also formed on the plurality of initial fourth semiconductor bodies 323; the size of the first mask pattern 325 directly above the initial fourth semiconductor body 323 along the second direction is larger than the size of the first mask pattern 325 directly above the initial second semiconductor body 321 along the second direction, and smaller than or equal to the size of the first mask pattern 325 directly above the initial third semiconductor body 322 along the second direction.

[0124] In this embodiment of the disclosure, the above-mentioned initial semiconductor layer 315, second mask layer 316, third mask layer 319, and first mask layer 324 can be formed by a deposition process.

[0125] In the embodiments disclosed herein, the deposition processes include, but are not limited to, Chemical Vapor Deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD). Etching processes include, but are not limited to, Plasma Etching (PE), Sputtering Etching (SE), Ion Beam Etching (IBE), and Reactive Ion Etching (RIE).

[0126] In some specific examples, the initial semiconductor layer includes a first surface and a second surface opposite each other along the thickness direction of the initial semiconductor layer. The formation of the initial first semiconductor body, the initial second semiconductor body, the initial third semiconductor body, and the initial fourth semiconductor body may be performed from the first surface of the initial semiconductor layer. Figures 25 to 27 The process can be performed from the first side of the initial semiconductor layer or from the second side of the initial semiconductor layer. For example... Figure 26 As shown, after forming the first semiconductor body, second semiconductor body, third semiconductor body, and fourth semiconductor body, a portion of the initial semiconductor layer 315 remains at the bottom of each of the three semiconductor bodies. In subsequent processes, the initial semiconductor layer 315 can be thinned from its second surface to remove the initial semiconductor layer 315 at the bottom of the first semiconductor body, second semiconductor body, third semiconductor body, and fourth semiconductor body.

[0127] In some embodiments, along the direction from the first region 305 to the second region 306, the size of the first mask pattern 325 directly above the plurality of initial fourth semiconductor bodies 323 increases sequentially along the second direction; or, along the direction from the first region 305 to the second region 306, the size of the first mask pattern 325 directly above the portion of the plurality of initial fourth semiconductor bodies 323 closest to the first region 305 increases sequentially along the second direction, and the size of the first mask pattern 325 directly above the portion of the plurality of initial fourth semiconductor bodies 323 furthest from the first region 305 is equal along the first direction.

[0128] In some embodiments, the dimensions of the first mask patterns 325 directly above the plurality of initial third semiconductor bodies 322 along the second direction are equal, and the dimensions of the first mask patterns 325 directly above the plurality of initial third semiconductor bodies 322 along the second direction are equal to the dimensions of the first mask pattern 325 directly above the initial fourth semiconductor body 323 closest to the initial third semiconductor body 322 along the second direction.

[0129] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0130] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0131] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A storage device, characterized in that, The storage device includes a first semiconductor body, a second semiconductor body, and a third semiconductor body, all extending along a first direction and a second direction and arranged along a third direction, and a first conductive line extending along the third direction; the first semiconductor body and the second semiconductor body are located on the same side of the opposite sides of the third semiconductor body along the third direction, and the first conductive line is located on at least one side of the opposite sides of the first semiconductor body, the second semiconductor body, and the third semiconductor body along the second direction; the dimension of the third semiconductor body along the second direction is larger than the dimension of the second semiconductor body along the second direction and smaller than the dimension of the first semiconductor body along the second direction; the second direction intersects the third direction and is perpendicular to the first direction.

2. The storage device according to claim 1, characterized in that, The storage device includes a first region and a second region arranged side by side along the third direction, and the storage device includes a plurality of first semiconductor bodies, a plurality of second semiconductor bodies and a plurality of third semiconductor bodies arranged along the third direction; The plurality of first semiconductor bodies and the plurality of second semiconductor bodies are located in the first region, and the plurality of third semiconductor bodies are located in the second region; The plurality of first semiconductor bodies and the plurality of second semiconductor bodies are arranged alternately along the third direction.

3. The storage device according to claim 2, characterized in that, The storage device further includes a third region located between the first region and the second region; a portion of the plurality of first semiconductor bodies are located in the third region; the storage device further includes a plurality of fourth semiconductor bodies located in the third region, each extending along the first direction and the second direction and arranged along the third direction; the first semiconductor bodies and the fourth semiconductor bodies in the third region are alternately arranged along the third direction; the dimension of the fourth semiconductor body along the second direction is greater than the dimension of the second semiconductor body along the second direction, and less than or equal to the dimension of the third semiconductor body along the second direction.

4. The storage device according to claim 3, characterized in that, Along the direction from the first region to the second region, the dimensions of the plurality of fourth semiconductor bodies increase sequentially along the second direction; or, along the direction from the first region to the second region, the dimensions of the fourth semiconductor bodies closer to the first region among the plurality of fourth semiconductor bodies increase sequentially along the second direction, and the dimensions of the fourth semiconductor bodies farther from the first region among the plurality of fourth semiconductor bodies are equal along the second direction.

5. The storage device according to claim 4, characterized in that, The plurality of third semiconductor bodies have equal dimensions along the second direction, and the dimensions of the plurality of third semiconductor bodies along the second direction are equal to the dimensions of the fourth semiconductor body closest to the third semiconductor body along the second direction.

6. The storage device according to claim 2, characterized in that, The plurality of first semiconductor bodies have equal dimensions along the second direction, and the plurality of second semiconductor bodies have equal dimensions along the second direction.

7. The storage device according to claim 2, characterized in that, The storage device includes multiple memory cells, and the second region is the region at the corner of the memory cell; or, the storage device includes multiple memory blocks, and the second region is the region at the corner of the memory block.

8. The storage device according to any one of claims 3 to 5, characterized in that, The distance between two adjacent third semiconductor bodies in the second region is greater than the distance between adjacent first semiconductor bodies and second semiconductor bodies in the first region.

9. The storage device according to claim 8, characterized in that, The distance between adjacent first semiconductor bodies and fourth semiconductor bodies in the third region is greater than the distance between adjacent first semiconductor bodies and second semiconductor bodies in the first region, and the distance between adjacent first semiconductor bodies and fourth semiconductor bodies in the third region is less than or equal to the distance between adjacent third semiconductor bodies in the second region.

10. The storage device according to claim 9, characterized in that, Along the direction from the first region to the second region, the distance between adjacent first semiconductor bodies and fourth semiconductor bodies in the third region increases sequentially.

11. The storage device according to claim 9, characterized in that, Along the direction from the first region to the second region, the distance between adjacent third semiconductor bodies in the second region increases sequentially; or, the distance between adjacent third semiconductor bodies in the second region is equal.

12. The storage device according to claim 9, characterized in that, The distance between adjacent first semiconductor bodies and fourth semiconductor bodies in the third region is D1, the distance between adjacent first semiconductor bodies and second semiconductor bodies in the first region is D2, and the range of (D1-D2) / D2 is 0 to 50%; the distance between adjacent third semiconductor bodies in the second region is D3, and the range of (D3-D2) / D2 is 0 to 50%.

13. The storage device according to claim 8, characterized in that, The distance between adjacent first semiconductor bodies and second semiconductor bodies in the first region is equal.

14. The storage device according to claim 2, characterized in that, The storage device further includes a plurality of second conductive lines, a plurality of third conductive lines, and a plurality of fourth conductive lines, all extending along the second direction and arranged along the third direction; one end of one of the opposite ends of a first semiconductor body along the first direction is connected to a second conductive line, one end of one of the opposite ends of a second semiconductor body along the first direction is connected to a third conductive line, and one end of one of the opposite ends of a third semiconductor body along the first direction is connected to a fourth conductive line. The portion of the fourth conductive line located in the second region along the second direction has a dimension greater than the portion of the third conductive line located in the first region along the second direction, but less than the portion of the second conductive line located in the first region along the second direction.

15. The storage device according to claim 14, characterized in that, The storage device further includes a plurality of first semiconductor lines, a plurality of second semiconductor lines, and a plurality of third semiconductor lines extending along the second direction and arranged along the third direction; the first semiconductor lines are located between the first semiconductor body and the second conductive lines, the second semiconductor lines are located between the second semiconductor body and the third conductive lines, and the third semiconductor lines are located between the third semiconductor body and the fourth conductive lines; the dimension of the first semiconductor line along the second direction is equal to the dimension of the second conductive lines along the second direction, the dimension of the second semiconductor line along the second direction is equal to the dimension of the third conductive lines along the second direction, and the dimension of the third semiconductor line along the second direction is equal to the dimension of the fourth conductive lines along the second direction.

16. A storage device, characterized in that, The storage device includes a first region and a second region; the first region includes a plurality of first semiconductor bodies and a plurality of second semiconductor bodies, and the second region includes a plurality of third semiconductor bodies. The plurality of first semiconductor bodies, the plurality of second semiconductor bodies, and the plurality of third semiconductor bodies extend along a first direction and a second direction and are arranged along a third direction. The plurality of first semiconductor bodies and the plurality of second semiconductor bodies are arranged alternately along the third direction. The first region and the second region are arranged side-by-side along the third direction. The first region and the second region also include a first conductive line extending along the third direction. The first conductive line is located at least on one side of one of the plurality of first semiconductor bodies, the plurality of second semiconductor bodies, and the plurality of third semiconductor bodies opposite each other along the second direction. The second direction intersects the third direction and is perpendicular to the first direction. The distance between two adjacent third semiconductor bodies in the second region is greater than the distance between adjacent first semiconductor bodies and second semiconductor bodies in the first region.

17. The storage device according to claim 16, characterized in that, The storage device further includes a third region located between the first region and the second region, wherein a portion of the plurality of first semiconductor bodies are located in the third region; the storage device further includes a plurality of fourth semiconductor bodies located in the third region, each extending along the first direction and the second direction and arranged along the third direction. The first semiconductor body and the fourth semiconductor body in the third region are arranged alternately along the third direction; The distance between adjacent first semiconductor bodies and fourth semiconductor bodies in the third region is greater than the distance between adjacent first semiconductor bodies and second semiconductor bodies in the first region, and the distance between adjacent first semiconductor bodies and fourth semiconductor bodies in the third region is less than or equal to the distance between adjacent third semiconductor bodies in the second region.

18. The storage device according to claim 17, characterized in that, Along the direction from the first region to the second region, the distance between adjacent first semiconductor bodies and fourth semiconductor bodies in the third region increases sequentially.

19. The storage device according to claim 17, characterized in that, Along the direction from the first region to the second region, the distance between adjacent third semiconductor bodies in the second region increases sequentially; or, the distance between adjacent third semiconductor bodies in the second region is equal.

20. The storage device according to claim 17, characterized in that, The distance between adjacent first semiconductor bodies and fourth semiconductor bodies in the third region is D1, the distance between adjacent first semiconductor bodies and second semiconductor bodies in the first region is D2, and the range of (D1-D2) / D2 is 0 to 50%; the distance between adjacent third semiconductor bodies in the second region is D3, and the range of (D3-D2) / D2 is 0 to 50%.

21. The storage device according to claim 16, characterized in that, The distance between adjacent first semiconductor bodies and second semiconductor bodies in the first region is equal.

22. The storage device according to claim 16, characterized in that, The storage device further includes a plurality of second conductive lines, a plurality of third conductive lines, and a plurality of fourth conductive lines, all extending along the second direction and arranged along the third direction; one end of one of the opposite ends of a first semiconductor body along the first direction is connected to a second conductive line, one end of one of the opposite ends of a second semiconductor body along the first direction is connected to a third conductive line, and one end of one of the opposite ends of a third semiconductor body along the first direction is connected to a fourth conductive line. The distance between two adjacent fourth conductive lines is greater than the distance between adjacent second and third conductive lines.

23. The storage device according to claim 16, characterized in that, The storage device includes multiple memory cells, and the second region is the region at the corner of the memory cell; or, the storage device includes multiple memory blocks, and the second region is the region at the corner of the memory block.

24. A method for manufacturing a storage device, characterized in that, include: A first semiconductor body, a second semiconductor body, and a third semiconductor body are formed, each extending along a first direction and a second direction and arranged along a third direction, and a first conductive line extending along the third direction is formed. The first semiconductor body and the second semiconductor body are located on the same side of the opposite sides of the third semiconductor body along the third direction, and the first conductive line is located on at least one side of the opposite sides of the first semiconductor body, the second semiconductor body, and the third semiconductor body along the second direction. The dimension of the third semiconductor body along the second direction is larger than the dimension of the second semiconductor body along the second direction and smaller than the dimension of the first semiconductor body along the second direction. The second direction intersects the third direction and is perpendicular to the first direction.

25. The manufacturing method according to claim 24, characterized in that, The storage device includes a first region and a second region arranged side by side along the second direction, and the storage device includes a plurality of first semiconductor bodies, a plurality of second semiconductor bodies and a plurality of third semiconductor bodies; The plurality of first semiconductor bodies and the plurality of second semiconductor bodies are located in the first region, and the plurality of third semiconductor bodies are located in the second region; The plurality of first semiconductor bodies and the plurality of second semiconductor bodies are arranged alternately along the second direction.

26. The manufacturing method according to claim 25, characterized in that, Forming a plurality of first semiconductor bodies, a plurality of second semiconductor bodies, and a plurality of third semiconductor bodies includes: A plurality of initial first semiconductor bodies, a plurality of initial second semiconductor bodies, and a plurality of initial third semiconductor bodies located in the first region are provided; the plurality of initial first semiconductor bodies, the plurality of initial second semiconductor bodies, and the plurality of initial third semiconductor bodies all extend along the first direction and the second direction and are arranged along the third direction, and the plurality of initial first semiconductor bodies and the plurality of initial second semiconductor bodies are arranged alternately along the third direction; A first mask layer is formed on the plurality of initial first semiconductor bodies, the plurality of initial second semiconductor bodies, and the plurality of third initial semiconductor bodies; a first mask pattern is formed in the first mask layer, and the size of the first mask pattern directly above the initial third semiconductor body along the second direction is larger than the size of the first mask pattern directly above the initial second semiconductor body along the second direction, and smaller than the size of the first mask pattern directly above the initial first semiconductor body along the second direction. Based on the first mask pattern, the plurality of initial first semiconductor bodies, the plurality of initial second semiconductor bodies, and the plurality of third initial semiconductor bodies are etched to form the plurality of first semiconductor bodies, the plurality of second semiconductor bodies, and the plurality of third semiconductor bodies.

27. The manufacturing method according to claim 26, characterized in that, The storage device further includes a third region located between the first region and the second region; a portion of the plurality of initial first semiconductor bodies is located in the third region. The method further includes: A plurality of initial fourth semiconductor bodies are provided in the third region, each extending along the first direction and the second direction and arranged along the third direction; the initial first semiconductor bodies and the initial fourth semiconductor bodies in the third region are arranged alternately along the third direction; While forming the first mask layer on the plurality of initial first semiconductor bodies, the plurality of initial second semiconductor bodies, and the plurality of third initial semiconductor bodies, the first mask layer is also formed on the plurality of initial fourth semiconductor bodies; the size of the first mask pattern directly above the initial fourth semiconductor body along the second direction is greater than the size of the first mask pattern directly above the initial second semiconductor body along the second direction, and less than or equal to the size of the first mask pattern directly above the initial third semiconductor body along the second direction.

28. The manufacturing method according to claim 27, characterized in that, Along the direction from the first region to the second region, the size of the first mask pattern directly above the plurality of initial fourth semiconductor bodies increases sequentially along the second direction; or, along the direction from the first region to the second region, the size of the first mask pattern directly above the portion of the plurality of initial fourth semiconductor bodies closest to the first region increases sequentially along the second direction, and the size of the first mask pattern directly above the portion of the plurality of initial fourth semiconductor bodies furthest from the first region is equal along the first direction.

29. The manufacturing method according to claim 28, characterized in that, The dimensions of the first mask patterns directly above the plurality of initial third semiconductor bodies along the second direction are equal, and the dimensions of the first mask patterns directly above the plurality of initial third semiconductor bodies along the second direction are equal to the dimensions of the first mask pattern directly above the initial fourth semiconductor body closest to the initial third semiconductor body along the second direction.

30. The manufacturing method according to any one of claims 27 to 29, characterized in that, The formation of the plurality of initial first semiconductor bodies, the plurality of initial second semiconductor bodies, the plurality of initial third semiconductor bodies, and the plurality of initial fourth semiconductor bodies includes: An initial semiconductor layer is provided in the first region, the second region, and the third region; A second mask layer is formed on the initial semiconductor layer; a second mask pattern is formed in the second mask layer, the second mask pattern including a plurality of mask lines extending along the second direction and arranged along the third direction; the distance between two adjacent mask lines in the second region is greater than the distance between adjacent mask lines in the first region, and the dimension of the mask lines in the second region along the third direction is greater than the dimension of the mask lines in the first region along the third direction; A third mask layer is formed to conformally cover the second mask layer and the initial semiconductor layer; Remove part of the third mask layer, leaving the remaining third mask layer covering the sidewalls of the mask line; The initial semiconductor layer is etched using the remaining third mask layer as a mask to form a plurality of initial first semiconductor bodies, a plurality of initial second semiconductor bodies, a plurality of initial third semiconductor bodies, and a plurality of initial fourth semiconductor bodies.

31. The manufacturing method according to claim 30, characterized in that, The distance between adjacent mask lines in the third region is greater than the distance between adjacent mask lines in the first region, and the dimension of the mask line in the third region along the third direction is greater than the dimension of the mask line in the first region along the third direction; and the distance between adjacent mask lines in the third region is less than or equal to the distance between adjacent mask lines in the second region, and the dimension of the mask line in the third region along the third direction is less than or equal to the dimension of the mask line in the second region along the third direction.

32. The manufacturing method according to claim 31, characterized in that, Along the direction from the first region to the second region, the distance between adjacent mask lines in the third region increases sequentially, and the size of the mask lines in the third region increases sequentially along the third direction.

33. The manufacturing method according to claim 31, characterized in that, Along the direction from the first region to the second region, the distance between adjacent mask lines in the second region increases sequentially, and the size of the mask lines in the second region increases sequentially along the third direction; or, the distance between adjacent mask lines in the second region is equal, and the size of the mask lines in the second region is equal along the third direction.

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