Shield gate field effect transistor manufacturing method and shield gate field effect transistor

Abstract

The invention provides a manufacturing method of a shield gate field effect transistor and the shield gate field effect transistor, and relates to the technical field of semiconductors. The manufacturing method of the shield gate field effect transistor comprises the steps of providing a substrate, wherein the substrate comprises a first surface and a second surface; forming a groove in the first surface; forming a field oxide layer, an insulating isolation layer and a source polysilicon layer in the groove, wherein the field oxide layer exposes at least part of the side wall of the groove; in a direction far away from the substrate, the heights of the insulating isolation layer and the source polysilicon layer are greater than the height of the field oxide layer; gate oxide layers are formed on the side wall of the trench exposed by the field oxide layer and one side, far away from the substrate, of the source polysilicon layer; the gate polysilicon layer is formed on the side, away from the substrate, of the field oxide layer, so that extrusion force on the field oxide layer due to the gate oxide layer formed on the side wall of the source polysilicon layer can be avoided, and deformation and warping of a wafer are prevented.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a manufacturing method of a shield gate field effect transistor and the shield gate field effect transistor. BACKGROUND

[0002] The shield gate field effect transistor has low on-resistance and low gate-drain capacitance, reduces the on-loss and switching loss of the system, improves the use efficiency of the system, and is widely used in various fields.

[0003] However, in the manufacturing process of the existing shield gate field effect transistor, a large internal stress is easily generated, which can cause the wafer to deform and warp, thereby reducing the yield and reliability of the product. SUMMARY

[0004] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a manufacturing method of a shield gate field effect transistor and the shield gate field effect transistor.

[0005] In a first aspect, the present application provides a manufacturing method of a shield gate field effect transistor, which comprises:

[0006] providing a substrate, the substrate comprising a first surface and a second surface arranged oppositely;

[0007] forming a groove on the first surface of the substrate;

[0008] forming a field oxide layer, an insulating isolation layer and a source polysilicon layer in the groove, the orthogonal projection of the field oxide layer on the substrate being located within the orthogonal projection of the groove on the substrate, the orthogonal projection of the insulating isolation layer on the substrate being located within the orthogonal projection of the field oxide layer on the substrate, and the orthogonal projection of the source polysilicon layer on the substrate being located within the orthogonal projection of the insulating isolation layer on the substrate; the field oxide layer exposes at least part of the sidewall of the groove; in the direction away from the substrate, the height of the insulating isolation layer and the source polysilicon layer is greater than the height of the field oxide layer;

[0009] forming a gate oxide layer on the sidewall of the groove exposed by the field oxide layer and the side of the source polysilicon layer away from the substrate;

[0010] forming a gate polysilicon layer on the side of the field oxide layer away from the substrate; the orthogonal projection of the gate polysilicon layer on the substrate is located within the orthogonal projection of the groove on the substrate.

[0011] In a possible implementation, a projection of the gate oxide layer on the substrate, which is located on a side of the source polysilicon layer away from the substrate, is located within a projection of the insulating isolation layer on the substrate.

[0012] In a possible implementation, the step of forming the field oxide layer, the insulating isolation layer and the source polysilicon layer in the trench comprises:

[0013] forming an oxide material layer on the first surface of the substrate and in the trench;

[0014] forming an insulating material layer on a side of the oxide material layer away from the substrate;

[0015] forming a source material layer on a side of the insulating material layer away from the substrate;

[0016] etching back the source material layer to obtain a source polysilicon layer, a projection of the source polysilicon layer on the substrate is located within a projection of the trench on the substrate;

[0017] performing etching treatment on the insulating material layer to obtain an insulating isolation layer, a projection of the insulating isolation layer on the substrate is located within a projection of the trench on the substrate;

[0018] performing etching treatment on the oxide material layer to obtain a field oxide layer, the field oxide layer covers a bottom surface and at least part of a sidewall of the trench.

[0019] In a possible implementation, the step of etching back the source material layer to obtain a source polysilicon layer comprises:

[0020] performing etching back treatment on the source material layer, so that a surface of the source material layer away from the substrate is flush with the first surface of the substrate;

[0021] performing photolithography treatment on the source material layer, so that a height of the source material layer in a direction away from the substrate is less than a height of the trench in the direction away from the substrate, to obtain the source polysilicon layer.

[0022] In a possible implementation, in the direction away from the substrate, a difference between the height of the source polysilicon layer and the height of the insulating isolation layer is less than 0.1 microns.

[0023] In a possible implementation, a material of the insulating isolation layer comprises silicon nitride.

[0024] In a possible implementation, a material of the source polysilicon layer comprises heavily doped polysilicon.

[0025] In a possible implementation, after the step of forming the gate polysilicon layer on the side of the field oxide layer away from the substrate, the method further includes:

[0026] performing first-conductivity-type impurity implantation and second-conductivity-type impurity implantation on the first surface of the substrate respectively to form a body region and a source region; the source region is located on the side of the body region away from the substrate;

[0027] forming an interlayer dielectric layer on the side of the source region and the gate polysilicon layer away from the substrate;

[0028] performing etching on the interlayer dielectric layer to form a contact hole.

[0029] In a second aspect, the embodiments of the present application further provide a shield gate field effect transistor, which is manufactured by the manufacturing method of the shield gate field effect transistor as in any of the above aspects.

[0030] In a third aspect, the embodiments of the present application further provide an electronic device, which includes the shield gate field effect transistor as in any of the above aspects.

[0031] Based on any of the above aspects, the manufacturing method of the shield gate field effect transistor and the shield gate field effect transistor provided by the embodiments of the present application can form a field oxide layer, an insulating isolation layer and a source polysilicon layer in a groove, so that the insulating isolation layer covers the sidewall of the source polysilicon layer, which can avoid the extrusion force on the field oxide layer due to the sidewall of the source polysilicon layer forming a gate oxide layer, thereby preventing the wafer from deforming and warping, and improving the yield and reliability of the product. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be invoked in the embodiments will be briefly introduced as follows, and it should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0033] Figure 1a is a structural schematic diagram of a shield gate field effect transistor in the prior art;

[0034] Figure 1b is a structural schematic diagram of a shield gate field effect transistor in the prior art;

[0035] Figure 2 is a flowchart of the manufacturing method of the shield gate field effect transistor provided by the embodiments of the present application;

[0036] Figure 3This is one of the schematic diagrams illustrating the fabrication process of the shielded gate field-effect transistor provided in this embodiment;

[0037] Figure 4 This is one of the structural schematic diagrams of the shielded gate field-effect transistor provided in this embodiment;

[0038] Figure 5a This is the second schematic diagram of the shielded gate field-effect transistor provided in this embodiment;

[0039] Figure 5b This is the third schematic diagram of the shielded gate field-effect transistor provided in this embodiment;

[0040] Figure 6a This is the second schematic diagram of the fabrication process of the shielded gate field-effect transistor provided in this embodiment;

[0041] Figure 6b This is the third schematic diagram illustrating the fabrication process of the shielded gate field-effect transistor provided in this embodiment;

[0042] Figure 7 This is a schematic diagram of the sub-steps of step S130 provided in this embodiment;

[0043] Figure 8 The fourth schematic diagram illustrates the fabrication process of the shielded gate field-effect transistor provided in this embodiment;

[0044] Figure 9 Fifth schematic diagram of the fabrication process of the shielded gate field-effect transistor provided in this embodiment;

[0045] Figure 10 This is a schematic diagram of the sub-steps of step S134 provided in this embodiment;

[0046] Figure 11 This is the sixth schematic diagram illustrating the fabrication process of the shielded gate field-effect transistor provided in this embodiment;

[0047] Figure 12 This is the second schematic flowchart illustrating the fabrication method of the shielded gate field-effect transistor provided in this embodiment;

[0048] Figure 13a This is the seventh schematic diagram illustrating the fabrication process of the shielded gate field-effect transistor provided in this embodiment;

[0049] Figure 13b This is the eighth schematic diagram illustrating the fabrication process of the shielded gate field-effect transistor provided in this embodiment;

[0050] Figure 14a This is the fourth schematic diagram of the shielded gate field-effect transistor provided in this embodiment;

[0051] Figure 14bThis is the fifth schematic diagram of the shielded gate field-effect transistor provided in this embodiment;

[0052] Figure 15a This is the sixth schematic diagram of the shielded gate field-effect transistor provided in this embodiment;

[0053] Figure 15b This is the seventh schematic diagram of the shielded gate field-effect transistor provided in this embodiment.

[0054] Icons: 100-Substrate; 110-Substrate layer; 120-Epipolar layer; 130-Trench; 140-Bulk region; 150-Source region; 101-First surface; 102-Second surface; 210-Mask layer; 220-Photoresist layer; 230-Sacrificial oxide layer; 201-Groove; 310-Field oxide layer; 311-Oxide material layer; 320-Insulating isolation layer; 321-Insulating material layer; 330-Source polysilicon layer; 331-Source material layer; 340-Gate oxide layer; 350-Gate polysilicon layer; 400-Interlayer dielectric layer; 410-Contact hole; 500-Passivation layer. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0056] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0057] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0058] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0059] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0060] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0061] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0062] The inventor discovered through research that... (Please refer to...) Figure 1a and Figure 1b During the fabrication of the shielded gate field-effect transistor, when forming the gate oxide layer 340', due to the high concentration of the source polysilicon layer 330' and the fact that the gate oxide layer 340' is formed through a wet oxidation process, the thickness of the gate oxide layer 340' formed based on the source polysilicon layer 330' (position A) is greater than the thickness of the gate oxide layer 340' formed based on the trench sidewall (position B). Furthermore, the thickness of the gate oxide layer 340' formed based on the source polysilicon layer 330' (position A) is 2 to 3 times the thickness of the gate oxide layer 340' formed based on the trench sidewall (position B). The gate oxide layer 340' formed based on the source polysilicon layer 330' will also exert an outward squeezing force on the field oxide layer 310' in the trench, thereby generating outward stress inside the shielded gate field effect transistor, causing the wafer to deform and warp, thus affecting the wafer fabrication process. This prevents the suction holes on the wafer fabrication equipment from effectively adsorbing the wafer, causing the wafer to be unable to be fixed in the wafer fabrication position, thereby reducing the yield and reliability of the product.

[0063] In view of this, this embodiment provides a solution that can reduce the risks of the above-mentioned problems. The solution provided in this embodiment will be described in detail below.

[0064] Please refer to Figure 2 , Figure 2 This example illustrates a flowchart of the method for fabricating a shielded gate field-effect transistor (SFET). The method for fabricating a shielded gate SFET may include the following steps.

[0065] Step S110: Provide a substrate 100, the substrate 100 including a first surface 101 and a second surface 102 disposed opposite to each other.

[0066] In this embodiment, the substrate 100 may include a substrate layer 110 and an epitaxial layer 120 located on one side of the substrate layer 110. The surface of the epitaxial layer 120 away from the substrate layer 110 is the first surface 101, and the surface of the substrate layer 110 away from the epitaxial layer 120 is the second surface 102. In some examples, both the substrate layer 110 and the epitaxial layer 120 are N-type doped, and the doping concentration of the substrate layer 110 may be higher than that of the epitaxial layer 120. That is, the substrate layer 110 may be an N+ type substrate 100, and the epitaxial layer 120 may be an N- type epitaxial layer 120. The substrate layer 110 may be a silicon wafer, and the dopant of the substrate layer 110 may be arsenic (As).

[0067] In some examples, an N-type epitaxial layer 120 can be grown on an N+-doped arsenic substrate 100 with a (100) crystal orientation to form a drift region. The (100) crystal orientation has the lowest interface state density between silicon dioxide and silicon during thermal oxidation, which can improve the reliability of the gate oxide. Furthermore, the (100) crystal orientation has the highest electron mobility, which helps to reduce on-resistance. Here, (100) crystal orientation means that the wafer surface is perpendicular to the

[100] direction of the cubic lattice.

[0068] Step S120: A groove 130 is formed on the first surface 101 of the substrate 100.

[0069] In this embodiment, please refer to Figure 3 A mask layer 210 can be formed on the first surface 101 of the substrate 100. Then, a photoresist layer 220 is formed on the side of the mask layer 210 away from the substrate 100, and a photolithographic pattern is formed by exposure and development processes. Next, the mask layer 210 is etched to form a groove 201 that exposes a portion of the first surface 101. Finally, the substrate 100 is etched based on the groove 201 to form a trench 130. After forming the trench 130, the mask layer 210 is removed. The trench 130 can be U-shaped with a rounded bottom to reduce electric field concentration, avoid the generation of tip discharge, and improve the device's withstand voltage capability.

[0070] Specifically, when forming the mask layer 210, tetraethyl orthosilicate (TEOS) can be deposited on the first surface 101 of the substrate 100 as the mask layer 210 using a low-pressure chemical vapor deposition (LPCVD) device, wherein the thickness of the tetraethyl orthosilicate (TEOS) is [missing information]. arrive When forming a photolithographic pattern on the mask layer 210, a positive photoresist can be coated on the side of the mask layer 210 away from the substrate 100, and the photolithographic pattern can be formed on the mask layer 210 through exposure and development processes. This photolithographic pattern is used to define the subsequent etching area, wherein the thickness of the photoresist is [missing information]. arrive When etching the mask layer 210, a dry etching process can be used to copy the photolithographic pattern onto the mask layer 210, forming a groove 201 that exposes a portion of the first surface 101 of the substrate 100. The dry etching process reduces dimensional loss, thereby allowing for more precise control over the morphology of the trench 130. When forming the trench 130, the substrate 100 can be etched based on the groove 201 to form a U-shaped trench 130, wherein the etching depth can be from 5 micrometers to 7 micrometers.

[0071] After forming trench 130, please refer to Figure 4 A sacrificial oxide layer 230 can be formed on the first surface 101 of the substrate 100 and within the trench 130. The sacrificial oxide layer 230 can completely cover the first surface 101 of the substrate 100 and the sidewalls and bottom surface of the trench 130. After the sacrificial oxide layer 230 is formed, it is removed to eliminate dangling bonds and residual stress on the surface of the trench 130. Specifically, when forming the sacrificial oxide layer 230, the silicon wafer can be placed in a diffusion furnace, the temperature controlled at 1000°C to 1200°C, and a gas carrying trichloroethylene can be introduced to generate a layer with a thickness of [missing information]. arrive Silica is used as the sacrificial oxide layer 230. Trichloroethylene reacts with metal impurity ions in the silicon wafer to form volatile chlorides, effectively removing metal contamination and improving the electrical performance of the substrate 100. Additionally, chlorine atoms passivate interface state charges, reducing dangling bonds and thus lowering interface defect density and improving device reliability. The sacrificial oxide layer 230 can be removed using a wet etching process.

[0072] In step S130, a field oxide layer 310, an insulating isolation layer 320, and a source polysilicon layer 330 are formed within the trench 130. The orthographic projection of the field oxide layer 310 onto the substrate 100 lies within the orthographic projection of the trench 130 onto the substrate 100. The orthographic projection of the insulating isolation layer 320 onto the substrate 100 lies within the orthographic projection of the field oxide layer 310 onto the substrate 100. The orthographic projection of the source polysilicon layer 330 onto the substrate 100 lies within the orthographic projection of the insulating isolation layer 320 onto the substrate 100. The field oxide layer 310 exposes at least a portion of the sidewalls of the trench 130. In the direction away from the substrate 100, the height of the insulating isolation layer 320 and the source polysilicon layer 330 is greater than the height of the field oxide layer 310.

[0073] Currently, shielded gate field-effect transistors (SFETs) can be classified into top-bottom structures and left-right structures based on the different arrangements of the source polysilicon layer 330 and the gate polysilicon layer 350 in the trench 130. In the top-bottom structure, the source polysilicon layer 330 is located at the lower part of the trench 130, and the gate polysilicon layer 350 is located at the upper part of the trench 130, with the source polysilicon layer 330 and the gate polysilicon layer 350 having a top-bottom structural relationship. In the left-right structure, the source polysilicon layer 330 typically extends from the bottom to the top of the trench 130, while the gate polysilicon layer 350 is disposed on the left and right sides of the source polysilicon layer 330 in the top region of the trench 130. The gate polysilicon layer 350 in the same trench 130 is thus divided into two gate structures, left and right.

[0074] In this embodiment, please refer to Figure 5a and Figure 5b A field oxide layer 310, an insulating isolation layer 320, and a source polysilicon layer 330 can be sequentially stacked within a trench 130. The field oxide layer 310 covers the bottom surface and part of the sidewalls of the trench 130, exposing some of the sidewalls. The insulating isolation layer 320 completely covers the sidewalls and bottom surface of the field oxide layer 310 facing the trench 130, and the source polysilicon layer 330 completely covers the sidewalls and bottom surface of the insulating isolation layer 320 facing the trench 130. The insulating isolation layer 320 can be located between the source polysilicon layer 330 and the field oxide layer 310, and covers the sidewalls of the source polysilicon layer 330, preventing oxidation of the sidewalls of the source polysilicon layer 330 and avoiding pressure on the field oxide layer 310 due to oxidation of the sidewalls of the source polysilicon layer 330.

[0075] In the direction away from the substrate 100, the heights of both the source polysilicon layer 330 and the insulating isolation layer 320 are greater than the height of the field oxide layer 310. Please refer again. Figure 5aFor a shielded gate field-effect transistor with an upper and lower structure, the height of the source polysilicon layer 330 and the insulating isolation layer 320 is less than the height of the trench 130. That is, there is a distance between the source polysilicon layer 330 and the insulating isolation layer 320 and the top of the trench 130, and the minimum distance between the field oxide layer 310 and the top of the trench 130 is greater than the minimum distance between the source polysilicon layer 330 and the insulating isolation layer 320 and the top of the trench 130. Please refer again. Figure 5b For a shielded gate field-effect transistor with a left-right structure, the surface of the source polysilicon layer 330 away from the substrate 100 can be flush with the top of the trench 130, while there is a distance between the field oxide layer 310 and the top of the trench 130.

[0076] In step S140, a gate oxide layer 340 is formed on the sidewall of the trench 130 exposed in the field oxide layer 310 and on the side of the source polysilicon layer 330 away from the substrate 100.

[0077] In this embodiment, please refer to Figure 6a and Figure 6b A gate oxide layer 340 can be formed on the first surface 101 of the substrate 100, the sidewalls of the trench 130 exposed by the field oxide layer 310, and the side of the source polysilicon layer 330 away from the substrate 100 using a wet oxidation process. The process temperature can be from 800°C to 1000°C, and the thickness of the gate oxide layer 340 can be [missing information]. arrive Furthermore, the thickness of the gate oxide layer 340 located on the side of the source polysilicon layer 330 away from the substrate 100 can be greater than the thickness of the gate oxide layer 340 located on the sidewall of the trench 130 and the first surface 101 of the substrate 100.

[0078] In some examples, the thickness of the silicon layer required to form the gate oxide layer 340 on the sidewalls of the trench 130 and the first surface 101 of the substrate 100 can be 0.46 times the thickness of the formed gate oxide layer 340. For example, if the thickness of the gate oxide layer 340 located on the sidewalls of the trench 130 and the first surface 101 of the substrate 100 is... The thickness of the consumed trench 130 sidewalls and the first surface 101 of the substrate 100 can be

[0079] In the above design, by forming the gate oxide layer 340 on the side of the source polysilicon layer 330 away from the substrate 100, the oxide layer between the source polysilicon layer 330 and the gate polysilicon layer 350 can be made thicker, thereby improving the Vgs withstand voltage capability of the device.

[0080] In step S150, a gate polysilicon layer 350 is formed on the side of the field oxide layer 310 away from the substrate 100; the orthogonal projection of the gate polysilicon layer 350 on the substrate 100 is located within the orthogonal projection of the trench 130 on the substrate 100.

[0081] In this embodiment, please refer again. Figure 6a For a shielded gate field-effect transistor with an upper and lower structure, since the height of the source polysilicon layer 330 and the insulating isolation layer 320 is less than the height of the trench 130, when forming the gate polysilicon layer 350, the gate polysilicon layer 350 can be located at the upper part of the trench 130 and completely cover the field oxide layer 310 and the gate oxide layer 340. Specifically, polycrystalline material can be filled into the trench 130 using in-situ doping technology, so that the polycrystalline material completely fills the space inside the trench 130 to form a thickness of arrive The polycrystalline material is deposited and then annealed. Then the gate oxide layer 340 and the polycrystalline material on the first surface 101 of the substrate 100 are removed, and the polycrystalline material is dry etched back. During etching, the gate polycrystalline silicon layer 350 is etched to a depth within 0.1 micrometers from the top of the trench 130 by means of optical emission (OE) endpoint detection method.

[0082] Please refer to this again. Figure 6b For a shielded gate field-effect transistor with a left-right structure, since the height of the source polysilicon layer 330 is flush with the top of the trench 130, the gate polysilicon layer 350 can be arranged around the source polysilicon layer 330 and completely cover the field oxide layer 310 when forming the gate polysilicon layer 350. Specifically, polycrystalline material can be filled into the trench 130 using in-situ doping technology, so that the polycrystalline material completely fills the space inside the trench 130 to form a thickness of arrive The polycrystalline material is deposited and then annealed. Furthermore, since the gate polycrystalline silicon layer 350 has a small width, it is difficult to directly etch the contact holes for the gate onto the gate polycrystalline silicon layer 350. Therefore, the gate polycrystalline silicon layer 350 can be fixed in position using photolithography to form the contact holes for the gate. Then, the gate oxide layer 340 and the polycrystalline material on the first surface 101 of the substrate 100 are removed, and the polycrystalline material is dry-etched back. During etching, the gate polycrystalline silicon layer 350 is etched to a depth within 0.1 micrometers from the top of the trench 130 using optical emission (OE) endpoint detection. Finally, the photoresist is removed.

[0083] Based on the above design, in the method for fabricating a shielded gate field-effect transistor provided in this embodiment, by forming a field oxide layer 310, an insulating isolation layer 320, and a source polysilicon layer 330 in the trench 130, and by having the insulating isolation layer 320 cover the sidewall of the source polysilicon layer 330, the pressure exerted on the field oxide layer 310 due to the formation of a gate oxide layer 340 on the sidewall of the source polysilicon layer 330 can be avoided, thereby preventing wafer deformation and warping, and improving product yield and reliability.

[0084] In one possible implementation, the orthographic projection of the gate oxide layer 340 on the substrate 100, located on the side of the source polysilicon layer 330 away from the substrate 100, can lie within the orthographic projection of the insulating isolation layer 320 on the substrate 100.

[0085] In this embodiment, please refer again. Figure 6a and Figure 6b In a direction parallel to the substrate 100, the width W1 of the insulating isolation layer 320 can be greater than or equal to the width W2 of the gate oxide layer 340. The width W2 of the gate oxide layer 340 can refer to the thickness of the gate oxide layer 340 grown on the sidewall of the trench 130 exposed by the field oxide layer 310. Simultaneously, the width of the insulating isolation layer 320 can also be greater than the thickness of the gate oxide layer 340 grown on the source polysilicon layer 330. This avoids the insulating dielectric between the source polysilicon layer 330 and the gate polysilicon layer 350 becoming too thin, thereby improving the device's Vgs withstand voltage capability.

[0086] In one possible implementation, please refer to Figure 7 Step S130 may include the following sub-steps.

[0087] Step S131: An oxide material layer 311 is formed on the first surface 101 of the substrate 100 and in the trench 130.

[0088] In this embodiment, please refer to Figure 8 An oxide material layer 311 can be grown on the first surface 101 and the surface of the trench 130 of the substrate 100 by thermal oxidation. The oxide material layer 311 can completely cover the first surface 101 and the surface of the trench 130 of the substrate 100. The process temperature can be from 1000℃ to 1200℃, and the thickness of the formed oxide material layer 311 can be [missing information]. arrive In this way, the Vds withstand voltage capability of the device can be avoided due to the oxide material layer 311 being too thin.

[0089] In step S132, an insulating material layer 321 is formed on the side of the oxide material layer 311 away from the substrate 100.

[0090] In this embodiment, please refer again.Figure 8 An insulating material layer 321 can be deposited on the side of the oxide layer 311 away from the substrate 100 using a low-pressure chemical vapor deposition (LPCVD) device. The thickness of the insulating material layer 321 should be greater than or equal to the thickness of the gate oxide layer 340. This avoids affecting the device's Vgs withstand voltage due to the insulating material layer 321 being too thin. Furthermore, the orthographic projection of the insulating material layer 321 onto the substrate 100 can completely coincide with the orthographic projection of the oxide layer 311 onto the substrate 100.

[0091] Step S133: A source material layer 331 is formed on the side of the insulating material layer 321 away from the substrate 100.

[0092] In this embodiment, please refer again. Figure 8 A source material layer 331 can be deposited on the side of the insulating material layer 321 away from the substrate 100, wherein the thickness of the source material layer 331 can be [missing information]. arrive After the source material layer 331 is formed, annealing can be performed to repair the tiny gaps in the polycrystalline material.

[0093] Step S134: The source material layer 331 is etched back to obtain the source polysilicon layer 330, and the orthographic projection of the source polysilicon layer 330 on the substrate 100 is located within the orthographic projection of the trench 130 on the substrate 100.

[0094] In this embodiment, please refer to Figure 9 The source material layer 331 formed in step S133 can be etched back so that the orthogonal projection of the source material layer 331 on the substrate 100 is located within the orthogonal projection of the trench 130 on the substrate 100, thereby obtaining the source polysilicon layer 330.

[0095] Step S135: The insulating material layer 321 is etched to obtain an insulating isolation layer 320. The orthographic projection of the insulating isolation layer 320 on the substrate 100 is located within the orthographic projection of the trench 130 on the substrate 100.

[0096] In this embodiment, please refer again. Figure 9 The insulating material layer 321 formed in step S132 can be etched using hot phosphoric acid, leaving only the insulating material layer 321 located in the trench 130. The etching depth of the insulating material layer 321 in the trench 130 can be adjusted according to the height of the source polysilicon layer 330, thereby forming an insulating isolation layer 320.

[0097] Step S136: The oxide material layer 311 is etched to obtain a field oxide layer 310, which covers the bottom surface and at least part of the sidewalls of the trench 130.

[0098] In this embodiment, please refer again. Figure 9 The oxide material layer 311 formed in step S131 can be subjected to wet etching treatment, retaining only the oxide material layer 311 in the trench 130, and the etching depth of the oxide material layer 311 in the trench 130 can be 1.0 micrometer to 1.5 micrometer, so as to form a field oxide layer 310 that only covers the bottom surface and part of the sidewall of the trench 130.

[0099] In one possible implementation, please refer to Figure 10 For a shielded gate field-effect transistor with an upper and lower structure, step S134 may include the following sub-steps.

[0100] Step S134a: The source material layer 331 is etched back so that the surface of the source material layer 331 away from the substrate 100 is flush with the first surface 101 of the substrate 100.

[0101] Step S134b: Photolithography is performed on the source material layer 331 so that the height of the source material layer 331 in the direction away from the substrate 100 is less than the height of the trench 130 in the direction away from the substrate 100, so as to obtain the source polycrystalline silicon layer 330.

[0102] In this embodiment, please refer to Figure 11 First, the source material layer 331 can be etched back to make the surface of the source material layer 331 away from the substrate 100 flush with the top of the trench 130. Then, the source material layer 331 can be photolithographically processed. Specifically, photoresist can be coated on the terminal surface to expose the active region 150, and then the source material layer 331 in the active region 150 can be etched to a depth of 1.0 micrometer to 1.3 micrometer to form the source polysilicon layer 330.

[0103] In another possible implementation, for the shielded gate field-effect transistor with left and right structure, in step S134, the source material layer 331 can be directly etched back so that the surface of the source material layer 331 away from the substrate 100 is flush with the top of the trench 130, thereby forming the source polysilicon layer 330.

[0104] In one possible implementation, the height difference between the source polysilicon layer 330 and the insulating isolation layer 320 in the direction away from the substrate 100 is less than 0.1 micrometers.

[0105] In this embodiment, please refer again.Figure 5a For a shielded gate field-effect transistor with an upper and lower structure, when etching to form the insulating isolation layer 320, since the distance between the surface of the source polysilicon layer 330 away from the substrate 100 and the top of the trench 130 is 1.0 micrometer to 1.3 micrometers, the etching depth of the insulating material layer 321 in the trench 130 can be 1.0 micrometer to 1.4 micrometers to ensure that the distance L between the surface of the formed insulating isolation layer 320 away from the substrate 100 and the surface of the source polysilicon layer 330 away from the substrate 100 is less than 0.1 micrometers.

[0106] Please refer to this again. Figure 5b For a shielded gate field-effect transistor with a left-right structure, since the surface of the source polysilicon layer 330 away from the substrate 100 is flush with the top of the trench 130, the etching depth of the insulating material layer 321 in the trench 130 can be less than 0.1 micrometers, so as to ensure that the distance L between the surface of the formed insulating isolation layer 320 away from the substrate 100 and the surface of the source polysilicon layer 330 away from the substrate 100 is less than 0.1 micrometers.

[0107] Specifically, in the direction parallel to the substrate 100, the width of the insulating isolation layer 320 is smaller than the width of the field oxide layer 310. Therefore, at the location where the insulating isolation layer 320 does not cover the sidewall of the source polysilicon layer 330, even if the sidewall of the source polysilicon layer 330 is oxidized and exerts a compressive force on the insulating isolation layer 320, causing the insulating isolation layer 320 to exert a compressive force on the field oxide layer 310, the compressive force is very small and will not cause wafer deformation.

[0108] In one possible implementation, the material of the insulating layer 320 may include silicon nitride (Si3N4).

[0109] It should be noted that the material of the insulating layer 320 is not limited to silicon nitride (Si3N4), but can also be other insulating materials, which are not specifically limited here.

[0110] In one possible implementation, the material of the source polysilicon layer 330 may include heavily doped polysilicon, which can make the thickness of the gate oxide layer 340 at the top of the source polysilicon layer 330 greater than the thickness of the gate oxide layer 340 on the sidewall of the trench 130, thereby improving the breakdown voltage capability of the device.

[0111] In some cases, the polysilicon concentration of the source polysilicon layer 330 can be greater than 5e. 20 cm -3 .

[0112] In one possible implementation, please refer to Figure 12 After step S150, the method for fabricating a shielded gate field-effect transistor may further include the following steps.

[0113] In step S210, a first conductivity type impurity implantation and a second conductivity type impurity implantation are performed on the first surface 101 of the substrate 100 to form a body region 140 and a source region 150; the source region 150 is located on the side of the body region 140 away from the substrate 100.

[0114] In this embodiment, please refer to Figure 13a and Figure 13b First, a first conductivity type impurity can be implanted and pushed onto the first surface 101 of the substrate 100 to form a body region 140. The first conductivity type impurity is P-type; in some examples, the first conductivity type impurity can be boron (B).

[0115] It should be noted that the dosage and energy of the injected boron (B), as well as the temperature and time of the bonding, can be adjusted according to actual needs, and no specific limitations are made here.

[0116] After forming the body region 140, a second conductivity type impurity can be implanted and annealed on the first surface 101 of the substrate 100 to form the source region 150. The second conductivity type impurity is N-type, and in some examples, the first conductivity type impurity can be arsenic (As).

[0117] It should be noted that the dosage and energy of the injected arsenic (As), as well as the temperature and time of annealing, can be adjusted according to actual needs, and no specific limitations are made here.

[0118] In step S220, an interlayer dielectric layer 400 is formed on the side of the source region 150 and the gate polysilicon layer 350 away from the substrate 100.

[0119] In this embodiment, an interlayer dielectric layer 400 can be deposited on the side of the source region 150 and the gate polysilicon layer 350 away from the substrate 100, and a reflow process is performed to make the surface of the interlayer dielectric layer 400 on the side away from the substrate 100 more flat. The thickness of the interlayer dielectric layer 400 can be... arrive The interlayer dielectric layer 400 may include a first dielectric sublayer and a second dielectric sublayer sequentially stacked in a direction away from the substrate 100. In some examples, the material of the first dielectric sublayer may be undoped silicate glass (USG) or tetraethyl orthosilicate (TEOS), and the material of the second dielectric sublayer may be borophosphosilicate glass (BPSG).

[0120] In the above design, by setting the interlayer dielectric layer 400, the silicon surface states can be optimized and the device stability can be improved.

[0121] Step S230: Etch the interlayer dielectric layer 400 to form contact holes 410.

[0122] In this embodiment, please refer to Figure 14a and Figure 14b The pattern can be formed on the interlayer dielectric layer 400 by photolithography and development using a preset contact hole pattern. Then, the interlayer dielectric layer 400 is subjected to dry etching to expose a portion of the source region 150. Next, the source region 150 and the body region 140 are etched to form the contact hole 410. The etching depth of the source region 150 and the body region 140 can be from 0.3 micrometers to 0.5 micrometers. After forming the contact hole 410, implantation and annealing can be performed within the contact hole 410. In some examples, boron difluoride (BF2) and boron (B) can be implanted into the contact hole 410 to improve contact with the metal and reduce on-resistance.

[0123] Please refer to Figure 15a and Figure 15b After forming the contact hole 410, metal deposition can be performed on the front side. Specifically, titanium (Ti) and titanium nitride (TiN) can be deposited sequentially on the side of the source region 150 away from the body region 140. Then, the contact hole 410 is filled using a tungsten plug process, followed by aluminum (Al) deposition. Finally, metal photolithography and etching are performed to distinguish the source and gate of the device. Annealing is also performed to optimize the surface states of the metal and silicon. Titanium (Ti) directly contacts the silicon, exhibiting good adhesion and preventing metal layer detachment. Titanium nitride (TiN) effectively prevents upper metal (such as Al or W) atoms from diffusing into the silicon, thus preventing device performance degradation. Simultaneously, it can also form excellent ohmic contacts with silicon together with titanium (Ti). Tungsten (W) is mainly used to fill the contact hole 410, possessing excellent morphology. Aluminum (Al) has low resistivity, strong anti-electromigration ability, stable performance, and is not easily oxidized; therefore, it can be used for soldering.

[0124] After the front metal is formed, a passivation layer 500 can be formed on the side of the front metal away from the substrate 100. The material of the passivation layer 500 can be polyimide. The passivation layer 500 can be used to protect the device surface to improve device reliability.

[0125] After forming the passivation layer 500, back-side thinning and back-side metal deposition can be performed to reduce the device's on-resistance. Next, back-side metal evaporation can be performed, using titanium (Ti), nickel (Ni), and silver (Ag) to form a multilayer metal, thereby forming the device drain.

[0126] This application also provides a shielded gate field-effect transistor, which can be manufactured using the method for manufacturing a shielded gate field-effect transistor provided in this embodiment.

[0127] This application also provides an electronic device, which may include the shielded gate field-effect transistor provided in this embodiment.

[0128] In summary, this embodiment provides a method for fabricating a shielded gate field-effect transistor and the shielded gate field-effect transistor. By forming a field oxide layer, an insulating isolation layer, and a source polysilicon layer in a trench, and making the insulating isolation layer cover the sidewall of the source polysilicon layer, the extrusion pressure on the field oxide layer caused by the formation of a gate oxide layer on the sidewall of the source polysilicon layer can be avoided, thereby preventing wafer deformation and warping, and improving product yield and reliability.

[0129] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0130] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a shielded gate field-effect transistor, characterized in that, The method includes: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other; A groove is formed on the first surface of the substrate; A field oxide layer, an insulating isolation layer, and a source polysilicon layer are formed within the trench. The orthographic projection of the field oxide layer onto the substrate lies within the orthographic projection of the trench onto the substrate. The orthographic projection of the insulating isolation layer onto the substrate lies within the orthographic projection of the field oxide layer onto the substrate. The orthographic projection of the source polysilicon layer onto the substrate lies within the orthographic projection of the insulating isolation layer onto the substrate. The field oxide layer exposes at least a portion of the sidewalls of the trench. In the direction away from the substrate, the height of the insulating isolation layer and the source polysilicon layer is greater than the height of the field oxide layer. A gate oxide layer is formed on the sidewalls of the trench exposed by the field oxide layer and on the side of the source polysilicon layer away from the substrate; A gate polysilicon layer is formed on the side of the field oxide layer away from the substrate; the orthogonal projection of the gate polysilicon layer on the substrate lies within the orthogonal projection of the trench on the substrate.

2. The method for fabricating a shielded gate field-effect transistor according to claim 1, characterized in that, The orthogonal projection of the gate oxide layer on the substrate, located on the side of the source polysilicon layer away from the substrate, lies within the orthogonal projection of the insulating isolation layer on the substrate.

3. The method for fabricating a shielded gate field-effect transistor according to claim 1, characterized in that, The steps of forming a field oxide layer, an insulating isolation layer, and a source polysilicon layer within the trench include: An oxide material layer is formed on the first surface of the substrate and within the trench; An insulating material layer is formed on the side of the oxide material layer away from the substrate; A source material layer is formed on the side of the insulating material layer away from the substrate; The source material layer is etched back to obtain a source polysilicon layer, wherein the orthogonal projection of the source polysilicon layer on the substrate is located within the orthogonal projection of the trench on the substrate; The insulating material layer is etched to obtain an insulating isolation layer, wherein the orthographic projection of the insulating isolation layer on the substrate is located within the orthographic projection of the trench on the substrate; The oxide material layer is etched to obtain a field oxide layer, which covers the bottom surface and at least part of the sidewalls of the trench.

4. The method for fabricating a shielded gate field-effect transistor according to claim 3, characterized in that, The step of etching back the source material layer to obtain the source polycrystalline silicon layer includes: The source material layer is etched back so that the surface of the source material layer away from the substrate is flush with the first surface of the substrate. The source material layer is subjected to photolithography so that the height of the source material layer in the direction away from the substrate is less than the height of the trench in the direction away from the substrate, so as to obtain the source polycrystalline silicon layer.

5. The method for fabricating a shielded gate field-effect transistor according to claim 1, characterized in that, In the direction away from the substrate, the difference between the height of the source polysilicon layer and the height of the insulating isolation layer is less than 0.1 micrometers.

6. The method for fabricating a shielded gate field-effect transistor according to claim 1, characterized in that, The insulating layer is made of silicon nitride.

7. The method for fabricating a shielded gate field-effect transistor according to claim 1, characterized in that, The source polycrystalline silicon layer is made of heavily doped polycrystalline silicon.

8. The method for fabricating a shielded gate field-effect transistor according to claim 1, characterized in that, After the step of forming a gate polysilicon layer on the side of the field oxide layer away from the substrate, the method further includes: A first conductivity type impurity implantation and a second conductivity type impurity implantation are performed on the first surface of the substrate to form a body region and a source region; the source region is located on the side of the body region away from the substrate; An interlayer dielectric layer is formed on the side of the source region and the gate polysilicon layer away from the substrate; The interlayer dielectric layer is etched to form contact holes.

9. A shielded gate field-effect transistor, characterized in that, The shielded gate field-effect transistor is manufactured using the method for manufacturing a shielded gate field-effect transistor according to any one of claims 1-8.

10. An electronic device, characterized in that, Includes the shielded gate field-effect transistor as described in any one of claims 9.

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