MOS transistor and manufacturing method thereof

Abstract

The MOS transistor has a gate insulating film and a gate electrode disposed in the trench. The semiconductor substrate has: a plurality of bottom p-type layers that are in contact with the gate insulating film on the bottom surfaces of the corresponding trenches; a plurality of intermediate n-type layers respectively disposed in the intervals of the bottom p-type layer; and a super junction layer disposed below each of the bottom p-type layers. And each p-type column layer of the super junction layer is connected with the corresponding middle n-type layer from the lower side. Each n-type column layer of the super junction layer is connected with the corresponding bottom p-type layer and the middle n-type layers on the two sides of the bottom p-type layer from the lower side.

Description

TECHNICAL FIELD

[0001] The technology disclosed in this specification relates to a MOS transistor and a manufacturing method thereof. BACKGROUND

[0002] A trench gate type MOS transistor is disclosed in Patent Literature 1. In the MOS transistor, a bottom p-type layer (also referred to as a gate bottom protection region) is provided in contact with a gate insulating film at a bottom surface of a trench. According to the bottom p-type layer, concentration of an electric field on the gate insulating film in the trench can be suppressed. Further, an intermediate n-type layer (also referred to as a current diffusion layer) is provided around each bottom p-type layer. The intermediate n-type layer has a higher n-type impurity concentration than a drift layer in a lower portion thereof. The intermediate n-type layer is provided in a space between each bottom p-type layer. Further, the intermediate n-type layer is provided in a range wider than each bottom p-type layer in the up-and-down direction, in contact with a lower surface of each bottom p-type layer. When the intermediate n-type layer is provided, the resistance of a current path is reduced, and the on-resistance of the MOS transistor is reduced.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2024-082458 SUMMARY

[0006] As described above, in the technology of Patent Literature 1, the on-resistance is reduced by the intermediate n-type layer. On the other hand, in the technology of Patent Literature 1, the current is diffused by the intermediate n-type layer, and thus flows in a wider range in the drift layer in a lower portion of the intermediate n-type layer. Therefore, the saturation current flowing when an overvoltage is applied to the MOS transistor is high. Thus, the short-circuit withstand capacity of the MOS transistor is low. In this specification, a technology for reducing the saturation current in a MOS transistor having an intermediate n-type layer is proposed.

[0007] A MOS transistor disclosed in this specification has: a semiconductor substrate provided with a plurality of trenches in an upper surface; and a gate insulating film and a gate electrode disposed in each of the trenches. The semiconductor substrate has: a plurality of bottom p-type layers disposed at intervals along a direction intersecting the trenches, respectively in contact with the gate insulating film at a bottom surface of a corresponding one of the trenches; a plurality of intermediate n-type layers respectively disposed in a corresponding one of the intervals; and a super junction layer disposed at a position lower than the bottom p-type layers, having a configuration in which a p-type pillar layer and an n-type pillar layer are alternately disposed along the direction. The n-type impurity concentration of the intermediate n-type layer is higher than the n-type impurity concentration of the n-type pillar layer. Each of the p-type pillar layers is in contact with the intermediate n-type layer from a lower side. Each of the n-type pillar layers is in contact with the bottom p-type layer and the intermediate n-type layers on both sides thereof from a lower side.

[0008] In the MOS transistor, a super junction layer is provided on a lower side than each bottom p-type layer. When the MOS transistor is turned on, electrons that have passed through the trench flow to the n-type pillar layer of the super junction layer via the intermediate n-type layer. The p-type pillar layer is in contact with the intermediate n-type layer from the lower side, so in a range in which the p-type pillar layer is provided, electrons do not flow from the intermediate n-type layer to the super junction layer. In addition, since the n-type pillar layer is in contact with the bottom p-type layer from the lower side, in a range in which the bottom p-type layer exists, electrons do not flow from the upper side to the n-type pillar layer. Therefore, the region in which electrons flow from the intermediate n-type layer to the n-type pillar layer is limited in the lateral direction to a region between the p-type pillar layer and the bottom p-type layer (i.e., a region in which the intermediate n-type layer is in direct contact with the n-type pillar layer). In this way, the region in which current flows is limited, and thus the saturation current is reduced.

[0009] In addition, the present specification proposes a manufacturing method of a MOS transistor. The manufacturing method has the following steps: forming a plurality of grooves at intervals in a certain direction on an upper surface of a semiconductor substrate, and exposing a reference n-type layer on the upper surface; forming a bottom p-type layer in a range exposed on the upper surface and a p-type pillar layer in a range exposed on a bottom of each groove by implanting p-type impurities into the upper surface and the bottom of each groove; etching a side surface and a bottom surface of each groove in which the p-type pillar layer is located on the bottom; epitaxially growing an intermediate n-type layer having a higher n-type impurity concentration than the reference n-type layer on the upper surface, wherein the intermediate n-type layer is epitaxially grown in a manner such that each groove is buried by the intermediate n-type layer; forming a plurality of trenches at intervals in the certain direction on the upper surface of the semiconductor substrate, wherein the plurality of trenches are formed in a manner such that the bottom p-type layer is exposed on a bottom surface of each trench; and forming a gate insulating film and a gate electrode in each trench.

[0010] In the manufacturing method, after the plurality of grooves are formed on the upper surface in which the reference n-type layer is exposed, the bottom p-type layer and the p-type pillar layer are formed by implantation of p-type impurities. The reference n-type layer remaining between the p-type pillar layers becomes the n-type pillar layer. Next, after the grooves are etched, the intermediate n-type layer is epitaxially grown in a manner such that the grooves are buried. If the intermediate n-type layer is thus formed, the intermediate n-type layer is in contact with the p-type pillar layer in the center of the groove, and is in contact with the n-type pillar layer on both sides of the p-type pillar layer in the groove. Next, the trenches are formed on the upper surface of the semiconductor substrate in a manner such that the bottom p-type layer is exposed on the bottom of each trench, and then the gate insulating film and the gate electrode are formed in each trench. By thus forming the MOS transistor, a configuration is obtained in which a current path is limited in the lateral direction to a region between the p-type pillar layer and the bottom p-type layer. Therefore, according to the manufacturing method, it is possible to manufacture a MOS transistor having an intermediate n-type layer and a low saturation current. In addition, according to the manufacturing method, it is possible to simultaneously form the bottom p-type layer and the p-type pillar layer, and thus it is possible to efficiently manufacture the MOS transistor. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a cross-sectional view of a MOS transistor of an embodiment.

[0012] Figure 2 is a cross-sectional view of a MOS transistor of a comparative example.

[0013] Figure 3 is an explanatory view of a manufacturing process of a MOS transistor of an embodiment.

[0014] Figure 4 is an explanatory view of a manufacturing process of a MOS transistor of an embodiment.

[0015] Figure 5 is an explanatory view of a manufacturing process of a MOS transistor of an embodiment. DETAILED DESCRIPTION

[0016] In the MOS transistor of one example disclosed in the present specification, it can also be that the intermediate n-type layer is distributed to a position lower than the lower end of the bottom p-type layer.

[0017] In the MOS transistor of one example disclosed in the present specification, it can also be that the corner between the side surface of the intermediate n-type layer and the lower surface is composed of a curved surface that smoothly connects the side surface of the intermediate n-type layer and the lower surface. The respective n-type pillar layers can also be in contact with the corner of the intermediate n-type layer.

[0018] According to this configuration, the electric field generated at the corner of the intermediate n-type layer can be reduced.

[0019] In the manufacturing method of the MOS transistor of one example disclosed in the present specification, it can also be that, in the process of etching the side surface and the bottom surface of the respective grooves, the corner between the side surface and the bottom surface of the respective grooves is etched in such a manner that the corner becomes a curved surface that smoothly connects the side surface and the bottom surface of the respective grooves.

[0020] According to this configuration, the corner between the side surface and the lower surface of each intermediate n-type layer becomes a curved surface, and thus the electric field generated at the corner can be reduced.

[0021] Figure 1A MOS transistor 10 of an embodiment is shown. The MOS transistor 10 of the embodiment is a MOSFET (metal-oxide-semiconductor field effect transistor). The MOS transistor 10 has a semiconductor substrate 12, a gate insulating film 14, a gate electrode 16, an interlayer insulating film 18, a source electrode 20, and a drain electrode 22. The semiconductor substrate 12 is composed of SiC (i.e., silicon carbide). The semiconductor substrate 12 has an upper surface 12a and a lower surface 12b as main surfaces. Hereinafter, one direction parallel to the upper surface 12a is referred to as an x direction, and a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as a y direction. A plurality of trenches 24 is provided on the upper surface 12a of the semiconductor substrate 12. The plurality of trenches 24 is arranged at intervals in the x direction. Each trench 24 extends linearly along the y direction on the upper surface 12a. The gate insulating film 14 covers inner surfaces of the trenches 24. The gate electrode 16 is arranged in each trench 24. The gate electrode 16 is insulated from the semiconductor substrate 12 by the gate insulating film 14. The interlayer insulating film 18 covers an upper surface of the gate electrode 16. The source electrode 20 covers the upper surface 12a of the semiconductor substrate 12 and an upper surface of the interlayer insulating film 18. The source electrode 20 is insulated from the gate electrode 16 by the interlayer insulating film 18. The drain electrode 22 covers the lower surface 12b of the semiconductor substrate 12. Hereinafter, a region between two trenches 24 is referred to as an inter-trench region A.

[0022] The semiconductor substrate 12 has a plurality of source layers 30, a plurality of body layers 32, a plurality of bottom p-type layers 34, a plurality of intermediate n-type layers 36, a super junction layer 38, a lower drift layer 40, and a drain layer 42.

[0023] Each source layer 30 is arranged in a corresponding inter-trench region A. Each source layer 30 is arranged in a range including the upper surface 12a of the semiconductor substrate 12. Each source layer 30 is in ohmic contact with the source electrode 20. Each source layer 30 contacts the gate insulating film 14 at an upper end of a side surface of a corresponding trench 24.

[0024] Each body layer 32 is arranged in a corresponding inter-trench region A. Each body layer 32 is arranged on a lower side of a source layer 30. Each body layer 32 contacts the gate insulating film 14 at a side surface of a corresponding trench 24. Each body layer 32 is connected to the source electrode 20 by a p-type contact layer provided at a position not shown.

[0025] Each bottom p-type layer 34 is arranged at intervals in the x direction. Each bottom p-type layer 34 is arranged at a lower portion of a corresponding trench 24. Each bottom p-type layer 34 contacts the gate insulating film 14 at a bottom surface of a corresponding trench 24. Hereinafter, an interval between two bottom p-type layers 34 is referred to as an interval region B.

[0026] Each intermediate n-type layer 36 is distributed from the trench region A to the spacer region B. Each intermediate n-type layer 36 extends from its contact with the lower surface of the body layer 32 to a depth lower than the lower end of the bottom p-type layer 34. No intermediate n-type layer 36 is disposed below each bottom p-type layer 34. Each intermediate n-type layer 36 is in contact with the gate insulating film 14 on the side of the corresponding trench 24. Each intermediate n-type layer 36 is in contact with the side of each bottom p-type layer 34 located on either side of it. The corner 36a between the side of each intermediate n-type layer 36 and the lower surface is formed by a curved surface that smoothly connects the side and the lower surface.

[0027] The superstructure 38 is disposed below the bottom p-type layer 34 and the intermediate n-type layer 36. The superstructure 38 has a structure in which p-type columnar layers 38a and n-type columnar layers 38b are alternately arranged along the x-direction.

[0028] Each p-type column layer 38a is disposed below the corresponding intermediate n-type layer 36 and connects to the corresponding intermediate n-type layer 36 from the bottom. The width of each p-type column layer 38a is narrower than the width of the intermediate n-type layer 36 above it. Each p-type column layer 38a is connected to the central part of the intermediate n-type layer 36 above it.

[0029] Each n-type column layer 38b is disposed below the corresponding bottom p-type layer 34. The width of each n-type column layer 38b is wider than the width of the bottom p-type layer 34 above it. Each n-type column layer 38b is connected from its bottom side to the bottom p-type layer 34 above it and to the intermediate n-type layers 36 on both sides of the bottom p-type layer 34. Each n-type column layer 38b is connected to the entire lower surface area of ​​the bottom p-type layer 34 above it. Each n-type column layer 38b is connected to the corner 36a of each intermediate n-type layer 36 above it.

[0030] The n-type impurity concentration in each intermediate n-type layer 36 is higher than that in each n-type column layer 38b. For example, the n-type impurity concentration in each intermediate n-type layer 36 is 1.0 × 10⁻⁶. 17 cm -3 The n-type impurity concentration in each n-type column 38b is less than 1.0 × 10⁻⁶. 17 cm -3 Therefore, the boundary (e.g., corner 36a) between the intermediate n-type layer 36 and the n-type column layer 38b has a ratio of 1.0 × 10⁻⁶. 17 cm -3 Consistent n-type impurity concentration.

[0031] The lower drift layer 40 is an n-type layer with the same n-type impurity concentration as each n-type columnar layer 38b. The lower drift layer 40 is disposed below the superjunction layer 38. The lower drift layer 40 is continuous with each n-type columnar layer 38b. The lower drift layer 40 is connected to each p-type columnar layer 38a from below.

[0032] The drain layer 42 is an n-type layer with a higher n-type impurity concentration than the lower drift layer 40. The drain layer 42 is disposed below the lower drift layer 40. The drain layer 42 is in contact with the lower drift layer 40 from the bottom. The drain layer 42 is in ohmic contact with the drain electrode 22 on the lower surface 12b of the semiconductor substrate 12.

[0033] Next, the operation of the MOS transistor 10 will be explained. The MOS transistor 10 is used in series with a load (e.g., a motor). A voltage is applied to the series circuit of the MOS transistor 10 and the load. The voltage is applied to the MOS transistor 10 with the drain electrode 22 at a higher potential than the source electrode 20. Additionally, the potential of the gate electrode 16 is controlled by a gate drive circuit (not shown).

[0034] If a potential above the gate threshold is applied to the gate electrode 16, trenches are formed in the region near the gate insulating film 14 of each body layer 32. Each source layer 30 is connected to each intermediate n-type layer 36 through the trenches. Therefore, as Figure 1 As indicated by arrow 100, electrons flow from the source electrode 20 through the source layer 30, the trench, the intermediate n-type layer 36, the n-type pillar layer 38b, the lower drift layer 40, and the drain layer 42 to the drain electrode 22. That is, the MOS transistor 10 is turned on. By providing an intermediate n-type layer 36 with a higher n-type impurity concentration than the n-type pillar layer 38b in each spacer region B, the resistance of each spacer region B is reduced. Therefore, electrons can flow through the narrow spacer regions B with low loss. Furthermore, as described later, when the MOS transistor 10 is turned off, it is easily depleted in each n-type pillar layer 38b, so even with a high n-type impurity concentration in each n-type pillar layer 38b, sufficient breakdown voltage can be ensured. Therefore, the n-type impurity concentration in each n-type pillar layer 38b is higher than that of a typical MOS transistor drift layer. This reduces the resistance of each n-type pillar layer 38b. Therefore, electrons can flow through each n-type pillar layer 38b with low loss. Therefore, the on-resistance of MOS transistor 10 is low.

[0035] When the potential of the gate electrode 16 is lowered to a potential smaller than the gate threshold value, the trench disappears, and the MOS transistor 10 is turned off. Then, the depletion layer extends from each p-type pillar layer 38a toward each n-type pillar layer 38b. In addition, since each bottom p-type layer 34 is in direct contact with the n-type pillar layer 38b below it, the depletion layer extends from each bottom p-type layer 34 toward each n-type pillar layer 38b. In this way, the depletion layer extends from both the p-type pillar layer 38a and the bottom p-type layer 34 toward the n-type pillar layer 38b, so the n-type pillar layer 38b is easily depleted. Therefore, the MOS transistor 10 has a high withstand voltage. In this way, by adopting the configuration in which each bottom p-type layer 34 is in direct contact with the n-type pillar layer 38b below it, the withstand voltage of the MOS transistor 10 can be increased. Therefore, even if the n-type impurity concentration of each n-type pillar layer 38b is increased, a sufficient withstand voltage can be obtained. In addition, by increasing the n-type impurity concentration of each n-type pillar layer 38b, as described above, a lower on-resistance can be achieved.

[0036] In addition, if the MOS transistor is turned off, not only each n-type pillar layer 38b but also each intermediate n-type layer 36 is depleted. If there is a curved portion at the boundary between the n-type pillar layer 38b and the intermediate n-type layer 36, the electric field is concentrated at the curved portion due to the influence of the fixed charge (i.e., donors) in the depletion layer when the n-type pillar layer 38b and the intermediate n-type layer 36 are depleted. In contrast, in the present embodiment, the boundary between the n-type pillar layer 38b and the intermediate n-type layer 36 is constituted by the corner portion 36a having a smooth curved surface shape. Therefore, the electric field generated at the boundary is small when each n-type pillar layer 38b and each intermediate n-type layer 36 are depleted. Thus, the withstand voltage of the MOS transistor 10 is further increased.

[0037] Next, the saturated current flowing through the MOS transistor at the time of load short-circuit will be described while comparing the comparative example and the embodiment. Figure 2 The MOS transistor of the comparative example is shown. In the MOS transistor of the comparative example, the intermediate n-type layer 36 is distributed to the lower portion of each bottom p-type layer 34, and the intermediate n-type layer 36 is in contact with the lower surface of each bottom p-type layer 34. Each n-type pillar layer 38b is separated from the bottom p-type layer 34 by the intermediate n-type layer 36. When the MOS transistor of the comparative example is turned on, as shown by the arrow 200, electrons flow. That is, in the normal on state, the current path (i.e., the arrow 200) of the MOS transistor of the comparative example is as narrow as the current path (i.e., the arrow 100) of the MOS transistor 10 of the embodiment. Figure 2 Figure 2 The arrow 200) of the MOS transistor of the comparative example is as narrow as the current path (i.e., the arrow 100) of the MOS transistor 10 of the embodiment. When the load is short-circuited in the on state of the MOS transistor of the comparative example, an overvoltage is applied to the MOS transistor. Then, as shown by the arrow 300, the current path is changed. That is, in the state of load short-circuit, the current path (i.e., the arrow 300) of the MOS transistor of the comparative example is as wide as the current path (i.e., the arrow 200) of the MOS transistor of the embodiment. Figure 1 Figure 2 ​​As indicated by arrow 210, electrons diffuse laterally within the intermediate n-type layer 36 below each bottom p-type layer 34. Therefore, as shown by arrows 200 and 210, the electron flow path widens below the intermediate n-type layer 36. Consequently, in the comparative example MOS transistor, a high saturation current flows when the load is short-circuited.

[0038] In contrast, in the MOS transistor 10 of this embodiment, since there is no intermediate n-type layer 36 below each bottom p-type layer 34, electrons are difficult to diffuse laterally below each bottom p-type layer 34 when the load is short-circuited. Therefore, as Figure 1 As indicated by arrow 100, the electron flow path is narrow during a load short circuit, just as it is normally. That is, even during a load short circuit, the main electron flow path is confined in the x-direction to the region between the bottom p-type layer 34 and the p-type pillar layer 38a. Therefore, in the MOS transistor 10 of this embodiment, the saturation current flowing during a load short circuit is low. As explained above, the saturation current can be reduced according to the construction of the MOS transistor 10 of this embodiment.

[0039] Next, the manufacturing method of the MOS transistor 10 according to the embodiment will be described. First, as... Figure 3 As shown in (a), a reference n-type layer 41 is formed on the drain layer 42 by epitaxial growth. The reference n-type layer 41 is an n-type layer having the same n-type impurity concentration as each n-type pillar layer 38b and the lower drift layer 40. In this state, the reference n-type layer 41 is exposed on the upper surface 12a of the semiconductor substrate 12. Next, as... Figure 3 As shown in (b), the upper surface 12a of the semiconductor substrate 12 is selectively etched by anisotropic etching, thereby forming a plurality of trenches 50 on the upper surface 12a. Here, the plurality of trenches 50 are formed at intervals in the x direction.

[0040] Next, as Figure 4 As shown in (a), p-type impurities are implanted into the semiconductor substrate 12 from the top. This forms a bottom p-type layer 34 exposed on the upper surface 12a and a p-type pillar layer 38a exposed at the bottom of the trench 50. A reference n-type layer 41 remaining between the p-type pillar layers 38a becomes an n-type pillar layer 38b. Furthermore, the reference n-type layer 41 remaining below the p-type pillar layers 38a becomes a lower drift layer 40.

[0041] Furthermore, as an example, Figure 4 (a) shows the case where the injection depth of the p-type impurity is shallower than the depth of the groove 50. However, as Figure 4 As shown in (b), the injection depth of p-type impurities can be equal to the depth of groove 50, such as Figure 4As shown in (c), the injection depth of p-type impurities can also be deeper than the depth of groove 50. Figure 4 In case (c), the bottom p-type layer 34 and the p-type column layer 38a are formed in a connected manner.

[0042] Next, as Figure 5 As shown in (a), the upper surface 12a and the inner surface of the groove 50 (i.e., the sides and bottom of the groove where the p-type pillar layer is located) are etched by isotropic etching. This increases the width of the groove 50. Furthermore, in... Figure 4 In the case where the bottom p-type layer 34 is connected to the p-type pillar layer 38a as in (c), the bottom p-type layer 34 is separated from the p-type pillar layer 38a by etching the groove 50. In addition, by etching the inner surface of the groove 50, the corner 50a of the groove 50 becomes a curved surface that smoothly connects the side and bottom surfaces.

[0043] Next, as Figure 5 As shown in (b), an intermediate n-type layer 36 is epitaxially grown on the upper surface of the semiconductor substrate 12. The n-type impurity concentration of the intermediate n-type layer 36 is higher than that of the reference n-type layer 41 (i.e., the n-type pillar layer 38b and the lower drift layer 40). Here, the intermediate n-type layer 36 is epitaxially grown such that each trench 50 is embedded in the intermediate n-type layer 36. Therefore, in each trench 50, the corner 36a between the side surface and the lower surface of the intermediate n-type layer 36 becomes a smooth curved surface. The intermediate n-type layer 36 contacts each p-type pillar layer 38a at the center of the bottom surface of each trench 50, and contacts each n-type pillar layer 38b at each corner 36a. After the intermediate n-type layer 36 is formed, the surface of the intermediate n-type layer 36 (i.e., the upper surface 12a) is planarized by CMP (Chemical Mechanical Polishing).

[0044] Next, ion implantation is performed on the upper surface 12a of the semiconductor substrate 12, such as... Figure 5 As shown in (c), a body layer 32 and a source layer 30 are formed on the upper part of the intermediate n-type layer 36.

[0045] Next, as Figure 5 As shown in (d), the upper surface 12a of the semiconductor substrate 12 is selectively etched by anisotropic etching, thereby forming a plurality of trenches 24 on the upper surface 12a. Here, the plurality of trenches 24 are formed at intervals in the x-direction. Here, trenches 24 are formed above the bottom p-type layer 34, penetrating the source layer 30, the body layer 32, and the intermediate n-type layer 36 to reach the bottom p-type layer 34. Therefore, the bottom p-type layer 34 is exposed at the bottom surface of each trench 24.

[0046] Next, as Figure 5The gate insulating film 14 is formed in a manner so as to cover the inner surfaces of the respective trenches 24, as shown in (e). Next, the gate electrode 16 composed of polysilicon is formed in the respective trenches 24. Next, the interlayer insulating film 18 is formed on the gate electrode 16. Then, the source electrode 20 is formed in a manner so as to cover the upper surface 12a, and the drain electrode 22 is formed in a manner so as to cover the lower surface 12b. Thus, the MOS transistor 10 shown in (f) is completed. Figure 1 The MOS transistor 10 shown in (f) is completed.

[0047] According to the manufacturing method, the bottom p-type layer 34 and the p-type pillar layer 38a can be formed at the same time by ion implantation, so the MOS transistor 10 can be manufactured efficiently. In addition, according to the manufacturing method, the corner portions 36a of the respective intermediate n-type layers 36 can be given a curved surface shape, and concentration of electric field can be suppressed.

[0048] The embodiments have been described in detail, but these are only examples and do not limit the claims. The technology recited in the claims includes technology obtained by various modifications, changes, and the like of the above-described examples. The technical elements described in the specification or the drawings singly or through various combinations exert technical usefulness, and are not limited to the combinations recited in the claims at the time of filing. In addition, the technology exemplified in the specification or the drawings simultaneously achieves multiple objects, and achieving one of the objects itself has technical usefulness.

Claims

1. A MOS transistor, characterized in that, have: A semiconductor substrate has multiple trenches formed on its upper surface; and The gate insulating film and gate electrode are disposed within each trench. The semiconductor substrate has: Multiple bottom p-type layers are arranged at intervals along the direction intersecting with each trench, and are respectively in contact with the gate insulating film on the bottom surface of the corresponding trench; Multiple intermediate n-type layers are respectively configured within the corresponding intervals; as well as The superstructure layer, positioned below each of the bottom p-type layers, has a structure in which p-type columnar layers and n-type columnar layers are alternately arranged along the stated direction. The concentration of n-type impurities in the intermediate n-type layer is higher than that in the n-type column layer. Each p-type column layer is connected to the intermediate n-type layer from the bottom. Each n-type column layer is connected from the bottom to the bottom p-type layer and the intermediate n-type layers on both sides.

2. The MOS transistor according to claim 1, characterized in that, The intermediate n-type layer is distributed to a position lower than the lower end of the bottom p-type layer.

3. The MOS transistor according to claim 2, characterized in that, The corner between the side surface and the lower surface of the intermediate n-type layer is formed by a curved surface that smoothly connects the side surface and the lower surface of the intermediate n-type layer. Each n-type column layer is connected to the corner of the corresponding intermediate n-type layer.

4. A method for manufacturing a MOS transistor, characterized in that, It has the following processes: Multiple trenches are formed at intervals along a specific direction on the upper surface of a semiconductor substrate, exposing a reference n-type layer on the upper surface; By injecting p-type impurities into the upper surface and the bottom of each groove, a bottom p-type layer is formed in the area exposed on the upper surface, and a p-type columnar layer is formed in the area exposed at the bottom of each groove. The sides and bottom surfaces of each groove where the p-shaped column layer is located are etched; An intermediate n-type layer having a higher n-type impurity concentration than the reference n-type layer is epitaxially grown on the upper surface, wherein the intermediate n-type layer is epitaxially grown such that each trench is embedded in the intermediate n-type layer; A plurality of trenches are formed at intervals along the specific direction on the upper surface of the semiconductor substrate, wherein the trenches are formed such that the bottom p-type layer is exposed at the bottom surface of each trench; and A gate insulating film and a gate electrode are formed in each of the trenches.

5. The manufacturing method according to claim 4, characterized in that, In the process of etching the side surface and the bottom surface of each groove, the corner is etched in such a way that the corner between the side surface and the bottom surface of each groove becomes a curved surface that smoothly connects the side surface and the bottom surface of each groove.

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