SiC EPITAXIAL WAFER AND SiC DEVICE

Abstract

The invention relates to a SiC epitaxial wafer and a SiC device. A SiC epitaxial wafer according to an embodiment of the present invention is provided with a SiC substrate and a SiC epitaxial layer positioned on one surface of the SiC substrate. The SiC epitaxial layer has a buffer layer and a drift layer. The buffer layer is located between the drift layer and the SiC substrate and has a higher impurity concentration than the drift layer. The impurity concentration of the buffer layer is 2.0 * 10 < 18 > cm <-3 > or more. The uniformity of the impurity concentration of the buffer layer is 50% or less when the impurity concentration at the center in plan view from the lamination direction is measured in the lamination direction.

Description

TECHNICAL FIELD

[0001] The present application relates to a SiC epitaxial wafer and a SiC device.

[0002] This application is based on patent application No. 2024-134794 filed in Japan on August 13, 2024, the content of which is hereby incorporated by reference. BACKGROUND

[0003] Silicon carbide (SiC) has an insulating breakdown electric field that is one order of magnitude larger than that of silicon (Si), and a band gap that is three times larger than that of silicon (Si). In addition, silicon carbide (SiC) has a thermal conductivity that is about three times higher than that of silicon (Si), and the like. Therefore, it is expected that silicon carbide (SiC) will be applied to power devices, high-frequency devices, high-temperature operating devices, and the like. In recent years, SiC epitaxial wafers have been used for semiconductor devices such as those described above.

[0004] A SiC epitaxial wafer is obtained by laminating a SiC epitaxial layer on a surface of a SiC substrate. Hereinafter, the substrate before the SiC epitaxial layer is laminated will be referred to as a SiC substrate, and the substrate after the SiC epitaxial layer is laminated will be referred to as a SiC epitaxial wafer. The SiC substrate is cut from a SiC ingot.

[0005] In a SiC epitaxial wafer, basal plane dislocations (BPDs) are known as one of device-killing defects that cause fatal defects in SiC devices. For example, when a current flows in a forward direction in a bipolar device, a portion of a basal plane dislocation inherited from a SiC substrate into a SiC epitaxial layer moves and expands by recombination energy of a flowing carrier, and forms a high-resistance stacking fault. The high-resistance portion generated in the device becomes a cause of a decrease in reliability of the device (forward degradation).

[0006] Research has been conducted to reduce basal plane dislocations inherited into a SiC epitaxial layer. For example, it is described in Patent Literature 1 that by growing a SiC epitaxial layer at a high speed (for example, by making the growth rate 50 μm / h or more), it is possible to reduce the proportion of basal plane dislocations inherited into the SiC epitaxial layer.

[0007] In addition, for example, it is described in Patent Literature 2 that by co-doping boron, titanium, vanadium, or the like in addition to a main element that is an n-type dopant, it is possible to suppress the generation of a high-resistance stacking fault.

[0008] [Patent Literature]

[0009] [Patent Literature]

[0010] [Patent Literature 1] Japanese Patent Application Publication No. 2018-113303

[0011] [Patent Document 2] Japanese Patent Application Publication No. 2019-134046 Summary of the Invention

[0012] To improve the conversion rate of basal plane dislocations to threading edge dislocations (TED) along the buffer layer, it is preferable to accelerate the growth rate of the SiC epitaxial layer. However, accelerating the growth rate of the SiC epitaxial layer can sometimes cause variations in the impurity concentration along the stacking direction of the SiC epitaxial layer. For example, Patent Document 2 also describes a variation in impurity concentration at the interface between the SiC substrate and the SiC epitaxial layer. This variation in impurity concentration along the stacking direction occurs when the impurity concentration in the buffer layer is less than 2.0 × 10⁻⁶. 18 cm -3 In most cases, impurities are almost nonexistent, and even if they do occur, they are negligible. In contrast, if the impurity concentration in the buffer layer is as high as 2.0 × 10⁻⁶... 18 cm -3 At concentrations above these levels, and with rapid growth of the SiC epitaxial layer, the variation in impurity concentration along the stacking direction becomes significant and cannot be ignored. Slowing down the growth rate of the SiC epitaxial layer can suppress the variation in impurity concentration along the stacking direction, but it reduces the conversion rate of basal dislocations to through-edge dislocations.

[0013] This disclosure was made in view of the above-mentioned problems, and its purpose is to provide a SiC epitaxial wafer with small variation in impurity concentration of the buffer layer in the stacking direction.

[0014] To address the aforementioned issues, this disclosure provides the following means.

[0015] (1) The SiC epitaxial wafer according to the first embodiment includes a SiC substrate and a SiC epitaxial layer located on one side of the SiC substrate. The SiC epitaxial layer has a buffer layer and a drift layer. The buffer layer is located between the drift layer and the SiC substrate and has a higher impurity concentration than the drift layer. The impurity concentration of the buffer layer is 2.0 × 10⁻⁶. 18 cm -3 The above. When measuring the impurity concentration at the center when viewed from above along the stacking direction, the uniformity of the impurity concentration in the buffer layer is 50% or less. The uniformity of the impurity concentration in the buffer layer is determined by (I max -I min ) / I ave Find the answer. max It is the maximum value of the impurity concentration of the buffer layer in the stacking direction. min It is the minimum impurity concentration of the buffer layer in the stacking direction. ave It is the average value of the impurity concentration of the buffer layer in the stacking direction.

[0016] (2) When measuring the impurity concentration at the first peripheral point 5 mm away from the outermost periphery when viewed from the stacking direction along the stacking direction of the SiC epitaxial wafer, the uniformity of the impurity concentration of the buffer layer can be less than 50%.

[0017] (3) When measuring the impurity concentration at any point when viewed from above along the stacking direction, the uniformity of the impurity concentration in the buffer layer of the SiC epitaxial wafer described above can be less than 50%.

[0018] (4) When measuring the impurity concentration at the center of the SiC epitaxial wafer viewed from the stacking direction along the stacking direction, the variation range of the impurity concentration in the region near the interface within 3 μm from the interface between the SiC substrate and the buffer layer can be less than 50% of the average impurity concentration of the buffer layer in the stacking direction.

[0019] (5) When measuring the impurity concentration at the first peripheral point 5 mm away from the outermost periphery when viewed from the stacking direction along the stacking direction of the SiC epitaxial wafer, the variation range of the impurity concentration in the region near the interface within 3 μm from the interface between the SiC substrate and the buffer layer can be less than 50% of the average impurity concentration of the buffer layer in the stacking direction.

[0020] (6) In the SiC epitaxial wafer described above, the in-plane uniformity of the impurity concentration in the buffer layer can be less than 50%. The in-plane uniformity of the impurity concentration in the buffer layer is calculated using |I1-I2| / {(I1+I2) / 2}. I1 is the impurity concentration of the buffer layer at the center when viewed from above in the stacking direction. I2 is the impurity concentration of the buffer layer at the first peripheral point, located 5 mm from the outermost periphery when viewed from above in the stacking direction.

[0021] (7) In the SiC epitaxial wafer described above, the impurity concentration of the drift layer can be 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×10 18 cm -3 the following.

[0022] (8) In the SiC epitaxial wafer involved in the above manner, the conversion rate of basal dislocations in the buffer layer is above 99.997%.

[0023] (9) In the SiC epitaxial wafer described above, the basal dislocation density in the drift layer can be 0.25 cm⁻¹. -2 the following.

[0024] (10) In the SiC epitaxial wafer described above, the basal dislocation density in the SiC substrate can be 9000 cm⁻¹. -2 the following.

[0025] (11) The diameter of the SiC epitaxial wafer involved in the above method can be 149 mm or more.

[0026] (12) The diameter of the SiC epitaxial wafer involved in the above method can be 199 mm or more.

[0027] (13) The SiC device according to the second embodiment includes a SiC substrate and a SiC epitaxial layer located on one side of the SiC substrate. The SiC epitaxial layer has a buffer layer and a drift layer. The buffer layer is located between the drift layer and the SiC substrate and has a higher impurity concentration than the drift layer. The impurity concentration of the buffer layer is 2.0 × 10⁻⁶. 18 cm -3 The uniformity of impurity concentration in the buffer layer is below 50%. The uniformity of impurity concentration in the buffer layer is determined by (I... max -I min ) / I ave Find the answer. max It is the maximum value of the impurity concentration of the buffer layer in the stacking direction. min It is the minimum impurity concentration of the buffer layer in the stacking direction. ave It is the average value of the impurity concentration of the buffer layer in the stacking direction.

[0028] (14) In the SiC device described above, when measuring the impurity concentration at the center when viewed from above along the stacking direction, the variation range of the impurity concentration in the region near the interface within 3 μm from the interface between the SiC substrate and the buffer layer can be less than 50% of the average impurity concentration of the buffer layer in the stacking direction.

[0029] (15) In the SiC device described above, the impurity concentration of the drift layer can be 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×10 18 cm -3 the following.

[0030] (16) In the SiC device described above, the conversion rate of basal dislocations in the buffer layer is above 99.997%.

[0031] (17) In the SiC device described above, the basal dislocation density in the drift layer can be 0.25 cm⁻¹. -2 the following.

[0032] (18) In the SiC device described above, the basal dislocation density in the SiC substrate can be 9000 cm⁻¹. -2 the following.

[0033] The SiC epitaxial wafers and SiC devices involved in the above methods exhibit small variations in impurity concentration in the buffer layer along the stacking direction. Attached Figure Description

[0034] Figure 1 This is a top view of the SiC epitaxial wafer according to the first embodiment.

[0035] Figure 2 This is a cross-sectional view of the SiC epitaxial wafer according to the first embodiment.

[0036] Figure 3 This is a cross-sectional view of the SiC epitaxial wafer manufacturing apparatus according to the first embodiment.

[0037] Figure 4 This is a schematic diagram illustrating the manufacturing method of SiC epitaxial wafer according to the first embodiment.

[0038] Figure 5 This is a top view used to illustrate the SiC device according to the first embodiment.

[0039] Explanation of reference numerals in the attached figures

[0040] 10…SiC substrate; 20…SiC epitaxial layer; 21…Buffer layer; 21A…Region near interface; 22…Drift layer; 100…SiC epitaxial wafer; 31…First period; 31A…Early stage of crystal growth; 31B…Second stage of crystal growth; St1…First stage; St2…Second stage; St3…Third stage; 200…SiC device; 201…Center. Detailed Implementation

[0041] Hereinafter, this embodiment will be described in detail with appropriate reference to the accompanying drawings. In the drawings used in the following description, for ease of understanding of the features of this embodiment, sometimes the feature parts are shown enlarged for convenience, and the size ratios of each component may differ from the actual dimensions. The materials, dimensions, etc., illustrated in the following description are examples, and this disclosure is not limited to them; appropriate modifications can be made without changing its spirit.

[0042] First, the directions are defined. One direction within the extended plane of the SiC substrate is designated as the X direction, and the direction orthogonal to the X direction within the same plane is designated as the Y direction. The X direction is, for example, the <11-20> direction. The Y direction is, for example, the <1-100> direction. The Z direction is perpendicular to the SiC substrate and orthogonal to both the X and Y directions. The Z direction aligns with the thickness direction of the SiC substrate and the stacking direction of the SiC epitaxial layers.

[0043] Figure 1 This is a top view of the SiC epitaxial wafer 100 according to the first embodiment. The top view shape of the SiC epitaxial wafer 100 is approximately circular. The SiC epitaxial wafer 100 may also have an orientation plane OF or a notch for guiding the direction of the crystal axis.

[0044] The diameter of the SiC epitaxial wafer 100 is not particularly limited. For example, the diameter of the SiC epitaxial wafer 100 may be 140 mm or more, or 149 mm or more. For example, the diameter of the SiC epitaxial wafer 100 may be 149 mm or more and 151 mm or less. Alternatively, the diameter of the SiC epitaxial wafer 100 may be 190 mm or more, or 199 mm or more. For example, the diameter of the SiC epitaxial wafer 100 may be 199 mm or more and 201 mm or less. For example, the diameter of the SiC epitaxial wafer 100 may be 240 mm or more, or 249 mm or more. For example, the diameter of the SiC epitaxial wafer 100 may be 249 mm or more and 251 mm or less. For example, the diameter of the SiC epitaxial wafer 100 may be 290 mm or more, or 299 mm or more. Alternatively, the diameter of the SiC epitaxial wafer 100 may be 301 mm or less. For example, the diameter of the SiC epitaxial wafer 100 may be 299 mm or more and 301 mm or less.

[0045] Figure 2 This is a cross-sectional view of the SiC epitaxial wafer 100 according to the first embodiment. The SiC epitaxial wafer 100 has a SiC substrate 10 and a SiC epitaxial layer 20.

[0046] The SiC substrate 10 is made of SiC. The crystal structure of SiC can be any of the following: 4H, 6H, 3C, or 15R. The SiC substrate 10 can be n-type, p-type, or a semi-insulating substrate. For example, the SiC substrate 10 is an n-type SiC substrate doped with nitrogen as an impurity. The impurity concentration of the SiC substrate 10 is, for example, 1.0 × 10⁻⁶. 18 cm -3 Above and 2.0×10 19 cm -3 The following are examples of impurities, such as nitrogen, phosphorus, aluminum, and boron.

[0047] The SiC substrate 10 can be an offset substrate. An offset substrate is a substrate whose crystal plane is tilted relative to the surface of the SiC substrate 10. The angle formed by the crystal plane and the surface is called the offset angle. The offset angle θ of the offset substrate is, for example, 0.5° or more and 10° or less. Alternatively, the SiC substrate 10 can also be a just substrate. A just substrate is a substrate whose crystal plane is almost not tilted relative to the surface of the SiC substrate 10. Therefore, the offset angle θ of the just substrate is, for example, 0° or more and 0.5° or less.

[0048] The SiC substrate 10 may also have basal dislocations. The basal dislocations of the SiC substrate 10 exist along the (0001) plane (c plane). Preferably, the number of basal dislocations exposed on the growth surface of the SiC substrate 10 is small. The basal dislocation density in the SiC substrate 10 is preferably 9000 cm⁻¹. -2 The following is more preferably 5000 cm -2 The following is more preferably 2000 cm -2 The following is a further preferred size: 1000 cm. -2 The following is particularly preferred: 500 cm -2 Below. Additionally, the basal dislocation density in the SiC substrate 10 can be 0 cm⁻¹. -2 It can also be greater than 0 cm -2 .

[0049] The SiC epitaxial layer 20 is in contact with one side of the SiC substrate 10. The SiC epitaxial layer 20 is stacked all over one side of the SiC substrate 10.

[0050] The SiC epitaxial layer 20 has a buffer layer 21 and a drift layer 22. The buffer layer 21 is located between the drift layer 22 and the SiC substrate 10. The buffer layer 21 is formed on the SiC substrate 10, and the drift layer 22 is formed on the buffer layer 21.

[0051] The buffer layer 21 is designed to convert basal plane dislocations present in the SiC substrate 10 into through-edge dislocations. Furthermore, the buffer layer 21 also prevents minority carriers from reaching the basal plane dislocations present in the SiC substrate 10 when a bipolar device with basal plane dislocations is subjected to forward-flowing current. The buffer layer 21 prevents the formation and propagation of Schockley-type stacking faults within the SiC epitaxial layer 20.

[0052] The impurity concentration in buffer layer 21 is higher than that in drift layer 22. The impurity concentration in buffer layer 21 is 2.0 × 10⁻⁶. 18 cm -3 The above. The preferred impurity concentration of the buffer layer 21 is 5.0 × 10⁻⁶. 18 cm -3The above. The impurity concentration of buffer layer 21 is, for example, 2 × 10⁻⁶. 19 cm -3 The impurity concentration of the buffer layer 21 is, for example, the average of the average impurity concentration in the Z direction at center 1 and the average impurity concentration in the Z direction at the first peripheral point 2. Center 1 is the center when viewed from above in the Z direction of the epitaxial wafer 100. The first peripheral point 2 is located 5 mm from the outermost periphery when viewed from above in the SiC epitaxial wafer 100. The first peripheral point 2 is, for example, located at a position after moving from center 1 in the X direction. The impurity concentration can be determined using secondary ion mass spectrometry (SIMS). Impurities include, for example, nitrogen, phosphorus, aluminum, and boron.

[0053] When the impurity concentration at the center 1 was measured along the stacking direction, the uniformity of the impurity concentration in the buffer layer 21 was 50% or less. When the impurity concentration at the center 1 was measured along the stacking direction, the uniformity of the impurity concentration in the buffer layer 21 was preferably 45% or less, more preferably 30% or less, more preferably 20% or less, and more preferably 10% or less.

[0054] The uniformity of impurity concentration in buffer layer 21 is determined by (I max -I min ) / I ave Find the answer.

[0055] I max It is the maximum value of the impurity concentration in the buffer layer 21 in the Z direction.

[0056] I min It is the minimum impurity concentration of the buffer layer 21 in the Z direction.

[0057] I ave It is the average impurity concentration of the buffer layer 21 in the Z direction.

[0058] Furthermore, the impurity concentration tends to vary near the interface between the SiC substrate 10 and the buffer layer 21. Hereinafter, the region within 3 μm from the interface between the SiC substrate 10 and the buffer layer 21 toward the buffer layer 21 will be referred to as the interface vicinity region 21A. The interface vicinity region 21A is a region contained within the buffer layer 21. When the thickness of the buffer layer 21 is less than 3 μm, the entire buffer layer 21A constitutes the interface vicinity region 21A. When the impurity concentration at the center 1 is measured in the Z direction, the variation range of the impurity concentration in the interface vicinity region 21A is preferably 50% or less, more preferably 45% or less, more preferably 35% or less, even more preferably 20% or less, and particularly preferably 10% or less. The variation range of the impurity concentration in the interface vicinity region 21A refers to the difference between the maximum and minimum values ​​of the impurity concentration in the interface vicinity region 21A.

[0059] Furthermore, when the impurity concentration at the first peripheral point 2 is measured along the Z-direction, the uniformity of the impurity concentration in the buffer layer 21 is preferably 50% or less, more preferably 45% or less, more preferably 35% or less, more preferably 25% or less, even more preferably 15% or less, and particularly preferably 10% or less. Since the film-forming gas expands from the center 1 of the SiC substrate 10 toward the periphery, the deviation of the impurity concentration in the Z-direction at the first peripheral point 2 is more often smaller than the deviation of the impurity concentration in the Z-direction at the center 1. Moreover, by implementing the conditions set in this application, the deviation at the center 1 can be reduced, and the difference between the deviation of the impurity concentration in the Z-direction at the first peripheral point 2 and the deviation of the impurity concentration in the Z-direction at the center 1 can be further reduced. This difference is preferably 18% or less, more preferably 10% or less, even more preferably 5% or less, and particularly preferably 1% or less.

[0060] Furthermore, when the impurity concentration at the first peripheral point 2 is measured along the Z direction, the variation range of the impurity concentration in the region 21A near the interface is preferably less than 50% of the average value of the impurity concentration of the buffer layer 21 in the Z direction, more preferably less than 45%, more preferably less than 35%, more preferably less than 20%, further preferably less than 15%, and particularly preferably less than 10%.

[0061] Furthermore, when measuring the impurity concentration at any point when viewed from above along the Z direction, the uniformity of the impurity concentration in the buffer layer 21 is preferably 50% or less, more preferably 45% or less, more preferably 40% or less, and even more preferably 30% or less.

[0062] Furthermore, the in-plane uniformity of impurity concentration in the buffer layer 21 is preferably 50% or less, more preferably 30% or less, more preferably 25% or less, even more preferably 20% or less, and even more preferably 10% or less. The in-plane uniformity of impurity concentration in the buffer layer 21 is calculated using |(I1-I2)| / {(I1+I2) / 2}. I1 is the impurity concentration at the center 1. I2 is the impurity concentration at the first outer peripheral point 2. That is, the in-plane uniformity of impurity concentration in the buffer layer 21 is calculated by dividing the absolute value of the difference between the impurity concentration at the center 1 and the impurity concentration at the first outer peripheral point 2 by the median of the impurity concentrations at the center 1 and the first outer peripheral point 2. Here, I1 and I2 are values ​​measured at the same depth in the Z direction within the buffer layer 21. For example, I1 and I2 are values ​​measured at the interface between the buffer layer 21 and the drift layer 22 (i.e., the surface of the buffer layer 21). Furthermore, I1 and I2 are preferably within 30% of the median values ​​of I1 and I2, respectively, and more preferably within 20%.

[0063] The thickness of the buffer layer 21 is, for example, 0.1 μm or more, preferably 1 μm or more, and more preferably 3 μm or more. The thickness of the buffer layer 21 is, for example, 10 μm or less.

[0064] Drift layer 22 is a layer in which drift current flows and components such as transistors are formed during the fabrication of SiC devices. Drift current refers to the current generated by the flow of charge carriers when a voltage is applied to a semiconductor.

[0065] The impurity concentration of drift layer 22 is, for example, 1 × 10⁻⁶. 15 cm -3 That's all. The impurity concentration of drift layer 22 is, for example, 1×10⁻⁶. 18 cm -3 The thickness of the drift layer 22 is, for example, 5 μm or more. The impurity concentration of the drift layer 22 is the average of the average impurity concentration in the Z direction at the center 1 and the average impurity concentration in the Z direction at the first peripheral point 2.

[0066] The basal dislocation density in drift layer 22 is, for example, 0.25 cm⁻¹. -2 The following applies. The basal dislocation density in drift layer 22 is preferably 0.10 cm⁻¹. -2 The following is more preferably 0.05 cm. -2 The following is a further preferred value of 0.03 cm. -2 The following is particularly preferred: 0.01 cm -2 The optimal value is 0 cm. -2 The basal dislocation density in drift layer 22 can be measured on the surface of drift layer 22.

[0067] Most of the basal dislocations in the SiC substrate 10 are converted into through-edge dislocations within the buffer layer 21. Basal dislocations are converted into through-edge dislocations at the interface between the SiC substrate 10 and the buffer layer 21, along the middle of the buffer layer 21, and at the interface between the buffer layer 21 and the drift layer 22. The conversion rate of basal dislocations in the buffer layer 21 is preferably 99.997% or more, more preferably 99.999% or more, and most preferably 100%. The conversion rate of basal dislocations in the buffer layer 21 is obtained by dividing the basal dislocation density in the drift layer 22 by the basal dislocation density in the SiC substrate and subtracting from 1. A high conversion rate from basal dislocations to through-edge dislocations in the buffer layer 21 can be achieved by rapidly growing the SiC epitaxial layer.

[0068] Next, the manufacturing method of the SiC epitaxial wafer 100 according to this embodiment will be described. Figure 3 This is a cross-sectional view of the manufacturing apparatus 50 for the SiC epitaxial wafer 100 according to this embodiment.

[0069] The manufacturing apparatus 50 includes a housing 51, a support 52, a gas inlet 53, a gas outlet 54, and a mass flow controller 55. The housing 51 surrounds the film-forming space. During film formation, a SiC substrate 10 is placed on the support 52.

[0070] The gas inlet 53 is the supply port for the film-forming gas. The film-forming gas can be Si-based, C-based, dopant, or carrier gas. Si-based gases are raw material gases containing Si molecules. Examples of Si-based gases include silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and tetrachlorosilane (SiCl4). Examples of C-based gases include propane (C3H8) and ethylene (C2H4). Dopant gases are gases containing elements that act as charge carriers. An example of a dopant gas is nitrogen. The purge gas is the gas that supplies these gases to the SiC substrate 10; it is hydrogen or similar gases that are inactive relative to SiC.

[0071] The gas inlet 53 has, for example, an inner peripheral gas supply port 53A, an intermediate gas supply port 53B, and an outer peripheral gas supply port 53C. The inner peripheral gas supply port 53A is the gas supply port located radially innermost when viewed from the Z direction. The outer peripheral gas supply port 53C is the gas supply port located radially outermost when viewed from the Z direction. The intermediate gas supply port 53B is the gas supply port located radially between the inner peripheral gas supply port 53A and the outer peripheral gas supply port 53C when viewed from the Z direction. The gas supply amounts from the inner peripheral gas supply port 53A, the intermediate gas supply port 53B, and the outer peripheral gas supply port 53C are controlled separately by a mass flow controller 55. The types of gas supplied from the inner peripheral gas supply port 53A, the intermediate gas supply port 53B, and the outer peripheral gas supply port 53C can be the same or different. For example, C-based gases can be supplied from the inner peripheral gas supply port 53A and the outer peripheral gas supply port 53C, while Si-based gases can be supplied from the intermediate gas supply port 53B.

[0072] The gas exhaust section 54 is located below the mounting surface of the SiC substrate 10 on the support 52. For example, the gas exhaust section 54 is located on the side wall of the housing 51. The film-forming gas supplied from the gas inlet section 53 recrystallizes on the surface of the SiC substrate 10, and the remaining gas is discharged from the gas exhaust section 54.

[0073] The outer peripheral gas supply port 53C is closer to the gas discharge section 54 than the inner peripheral gas supply port 53A and the intermediate gas supply port 53B, and is therefore more susceptible to the influence of the gas discharged from the gas discharge section 54. Gas supplied from the first end of the inner peripheral gas supply port 53A flows straight toward the SiC substrate 10, while gas supplied from the first end of the outer peripheral gas supply port 53 flows outwards. Therefore, the length of the flow path from the first end of the inner peripheral gas supply port 53A to the SiC substrate 10 is shorter than the length of the flow path from the first end of the outer peripheral gas supply port 53C to the SiC substrate 10. The first end is the end of the gas supply port on the film-forming space side.

[0074] To mitigate the difference in gas flow path length within the film-forming space, the distances between the mass flow controller 55 and the first end in each of the inner peripheral gas supply port 53A, intermediate gas supply port 53B, and outer peripheral gas supply port 53C are varied. For example, the distance L1 between the mass flow controller 55 and the first end in the inner peripheral gas supply port 53A is longer than the distance L2 between the mass flow controller 55 and the first end in the intermediate gas supply port 53B, and the distance L3 between the mass flow controller 55 and the first end in the outer peripheral gas supply port 53C. Furthermore, the distance L2 between the mass flow controller 55 and the first end in the intermediate gas supply port 53B is longer than the distance L3 between the mass flow controller 55 and the first end in the outer peripheral gas supply port 53C.

[0075] The specific lengths of distances L1, L2, and L3 are adjusted according to the conditions set later. The gas supply state at the surface of the SiC substrate 10 varies according to distances L1, L2, and L3. By changing distances L1, L2, and L3, the effective C / Si ratio at the surface of the SiC substrate 10 can be changed. The effective C / Si ratio refers to the ratio of C-based gas to Si-based gas near the formed film.

[0076] Next, the specific lengths of distances L1, L2, and L3 are determined. First, the SiC substrate 10 for setting the conditions is placed on the support 52. The SiC substrate 10 for setting the conditions is preferably the same as the SiC substrate 10 used in the actual film deposition. For example, a substrate with a dislocation density of 9000 cm⁻¹ is used. -2 The following substrate is used as SiC substrate 10.

[0077] Figure 4 This describes the various conditions used to form the SiC epitaxial layer 20. During the growth of the SiC epitaxial layer 20, there is a first period 31 for the crystallization growth of the buffer layer 21 and a second period 32 for the crystallization growth of the drift layer 22. In the condition settings, distances L1, L2, and L3 are set by performing film formation (i.e., film formation of the buffer layer 21) multiple times during the first period 31. The film formation conditions in the first period 31 are made identical to the actual film formation conditions.

[0078] The first period 31 is divided into the initial crystal growth period 31A and the stable crystal growth period 31B. The initial crystal growth period 31A is the period until the flow rates of Si-based gas and C-based gas during crystal growth become constant. The stable crystal growth period 31B is the period after the flow rates of Si-based gas and C-based gas become constant.

[0079] In addition, during the initial stage of crystal growth 31A, the gas flow rates of Si-based and C-based gases are gradually increased. The nitrogen flow rate is kept constant in each of the three stages after dividing the initial stage of crystal growth 31A into three phases.

[0080] Hereinafter, the initial stage of the initial crystal growth period 31A will be referred to as stage 1 St1, the next stage as stage 2 St2, and the final stage as stage 3 St3. For example, the initial crystal growth period 31A can be divided equally and designated as stage 1 St1, stage 2 St2, and stage 3 St3 respectively. Alternatively, the initial crystal growth period 31A can be divided at different ratios and designated as stage 1 St1, stage 2 St2, and stage 3 St3 respectively.

[0081] The nitrogen supply rates in stages St1, St2, and St3 can be the same or different. For example, the nitrogen supply rate in St1 can be set to 100 sccm, in St2 to 200 sccm, and in St3 to 300 sccm. Furthermore, the nitrogen supply rate in earlier stages can be less or more than that in later stages. For example, the maximum nitrogen flow rate can be supplied in St1, and the nitrogen supply rate can be reduced as we move into St2 and St3. Alternatively, the nitrogen supply rate in St1 can be set to 300 sccm, in St2 to 200 sccm, and in St3 to 100 sccm.

[0082] In each of stages St1, St2, and St3, the C / Si ratio is set to constant. The ease with which impurities (e.g., nitrogen) are incorporated into the crystallized SiC epitaxial layer 20 varies depending on the C / Si ratio. The supply amounts of C-based and Si-based gases are adjusted according to the nitrogen supply amounts in each of stages St1, St2, and St3.

[0083] The C / Si ratios in each of the three stages (St1, St2, and St3) can be the same or different. The rate at which the gas flow rates of the Si and C gases increase (the slope of the gas flow rate change over time) can also be varied in each of these three stages.

[0084] Here, an example is shown where the initial stage of crystal growth 31A is divided into three stages, but the number of stages for the initial stage of crystal growth 31A can also be four or more. Preferably, the number of stages for the initial stage of crystal growth 31A is eight or less.

[0085] Regarding the settings of distances L1, L2, and L3, the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10 is confirmed and set during each film formation at each stage of the initial crystal growth period 31A.

[0086] Since the film-forming gas expands radially from the inner side to the outer side of the film-forming apparatus 50, a distance L1 is initially set. For example, the initial setting of distance L1 is 100 mm. Under these conditions, film formation in the first stage St1 is performed, and the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10 is measured. If the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10 exceeds 50%, distance L1 is changed. If the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10 is less than 50%, distance L1 is temporarily set. If the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10 exceeds 50%, the film formation in the first stage St1, the measurement of impurity concentration uniformity in the stacking direction at the center 1 of the SiC substrate 10, and the change of distance L1 are repeated. Then, when the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10 becomes less than 50%, distance L1 is temporarily set.

[0087] If distance L1 is temporarily set, then distance L2 is set. Distance L2 is also temporarily set by repeatedly performing film formation in stage 1 (St1), measuring the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10, and changing distance L1. Distance L2 is temporarily set when the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10 becomes 50% or less.

[0088] If distance L2 is temporarily set, then distance L3 is set. Distance L3 is also temporarily set by repeatedly performing film formation in stage 1 (St1), measuring the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10, and changing distance L1. Distance L3 is temporarily set when the uniformity of impurity concentration in the stacking direction at the center 1 of the SiC substrate 10 becomes 50% or less.

[0089] Next, film deposition in the first stage (St1) is performed at temporarily set distances L1, L2, and L3, and the uniformity of impurity concentration in the stacking direction at the first outer peripheral point 2 of the SiC substrate 10 is measured. If the uniformity of impurity concentration in the stacking direction at the first outer peripheral point 2 of the SiC substrate 10 exceeds 50%, the temporarily set distances L1, L2, and L3 are adjusted. The adjustments of distances L1, L2, and L3 are performed in the order of distances L1, L2, and L3.

[0090] In each of the second and third stages, St2 and St3, the same processing as that performed in the first stage, St1, for distances L1, L2, and L3 is carried out. Finally, distances L1, L2, and L3 are set such that the uniformity of impurity concentration in the stacking direction between the center 1 and the first peripheral point 2 is less than 50% regardless of whether it is the first stage, St1, the second stage, or the third stage, St3.

[0091] If distances L1, L2, and L3 are set, film formation verification is performed under these conditions. During film formation verification, the gas flow rate is adjusted to regulate the in-plane distribution of the gas in the in-plane direction of the SiC substrate 10. Furthermore, during film formation verification, the uniformity of impurity concentration in the stacking direction between the center 1 and the first outer peripheral point 2 is reconfirmed to be 50% or less.

[0092] For each device, distances L1, L2, and L3, as well as the gas flow rate, are set. This is because there are deviations between the devices. In addition, conditions may change even after the film-forming device 50 has been cleaned, so it is preferable to set these conditions.

[0093] Based on the conditions determined using the steps described above, formal film formation is performed. During formal film formation, under the set conditions, the buffer layer 21 in the first period 31 and the drift layer 22 in the second period 32 are formed. The growth rate of the SiC epitaxial layer 20 in the initial crystal growth period 31A is set to 5 μm / h or more and 80 μm / h or less. The growth rate of the SiC epitaxial layer 20 in the stable crystal growth period 31B is set to 50 μm / h or more. In the second period 32, for example, the C / Si ratio is made higher than in the first period 31.

[0094] During the initial stage of crystal growth, 31A exhibits unstable crystal growth and fluctuating impurity concentration. By precisely controlling the crystal growth conditions of 31A during the initial stage of crystal growth, large fluctuations in the impurity concentration during this period can be suppressed, enabling the fabrication of the SiC epitaxial wafer 100 according to this embodiment.

[0095] As described above, the SiC epitaxial wafer 100 of this embodiment exhibits minimal variation in impurity concentration in the Z-direction of its buffer layer 21. Furthermore, the SiC epitaxial wafer 100 of this embodiment demonstrates a high conversion rate from basal dislocations to through-edge dislocations in its buffer layer 21. In other words, the SiC epitaxial wafer 100 of this embodiment can suppress variations in impurity concentration in the Z-direction and achieves a high conversion rate from basal dislocations to through-edge dislocations. Therefore, by using the SiC epitaxial wafer 100 of this embodiment, high-quality SiC devices can be fabricated.

[0096] SiC devices can be obtained from the SiC epitaxial wafer 100 according to this embodiment. Figure 5 This is a top view used to illustrate the SiC device 200 according to the first embodiment. The SiC device 200 can be fabricated by forming devices such as transistors on a SiC epitaxial wafer 100 and miniaturizing it. Figure 5 In this context, the various devices obtained by dividing the SiC epitaxial wafer 100 into rectangles are SiC devices. The SiC device 200 can also be fabricated by forming devices such as transistors after miniaturizing the SiC epitaxial wafer 100.

[0097] The SiC device 200 according to this embodiment includes a miniaturized SiC substrate and a SiC epitaxial layer located on one side of the miniaturized SiC substrate. Devices such as transistors are formed on the drift layer of the SiC epitaxial layer. The impurity concentration and basal dislocation density of the SiC substrate, buffer layer, and drift layer in the SiC device 200 are the same as those of the SiC epitaxial wafer 100 before miniaturization.

[0098] For example, when measuring the impurity concentration in the SiC device 200 along the Z-direction, the uniformity of the impurity concentration in the buffer layer is 50% or less, preferably 45% or less, more preferably 30% or less, more preferably 20% or less, more preferably 15% or less, and even more preferably 10% or less. The impurity concentration in the SiC device 200 is measured, for example, at the center 201 of each SiC device 200. The impurity concentration in the SiC device 200 is the average value along the Z-direction at the center 201.

[0099] Additionally, for example, when measuring the impurity concentration at the center 201 of the SiC device 200 along the Z direction, the variation range of the impurity concentration in the region near the interface is preferably less than 50% of the average impurity concentration of the buffer layer in the Z direction, more preferably less than 45%, more preferably less than 35%, further preferably less than 20%, and particularly preferably less than 10%.

[0100] Additionally, for example, the impurity concentration of the drift layer in the SiC device 200 can be 1.0 × 10⁻⁶. 15 cm -3Above and 1.0×10 18 cm -3 Below. Additionally, for example, the basal dislocation density in the drift layer of the SiC device 200 can be 0.25 cm⁻¹. -2 The impurity concentration of the buffer layer in SiC device 200 is 2.0 × 10⁻⁶. 18 cm -3 That's all. Additionally, for example, the impurity concentration of the buffer layer in the SiC device 200 can be 1.0 × 10⁻⁶. 19 cm -3 Furthermore, for example, the basal plane dislocation conversion rate in the buffer layer of the SiC device 200 can be 99.997% or higher. Additionally, for example, the basal plane dislocation density in the SiC substrate can be 9000 cm⁻¹. -2 the following.

[0101] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to specific embodiments and various modifications and alterations can be made within the scope of the spirit of the present invention as described in the claims.

[0102] [Example]

[0103] Example 1

[0104] A SiC substrate 10 with a diameter of 150 mm (6 inches) and an offset angle of 4° was prepared. The basal dislocation density of the SiC substrate 10 is 9000 cm⁻¹. -2 The nitrogen concentration of the SiC substrate 10 is 6.0 × 10⁻⁶. 18 cm -2 .

[0105] Next, a buffer layer 21 and a drift layer 22 were sequentially stacked on the SiC substrate 10. During the formation of the buffer layer 21, the initial crystal growth period 31A was divided into three stages. In each of these three stages, the nitrogen supply was kept constant. The C-based gas and Si-based gas were gradually increased during the initial crystal growth period 31A.

[0106] Furthermore, during the formation of the SiC epitaxial layer 20, the gas supply ports are divided into an inner peripheral gas supply port, an intermediate gas supply port, and an outer peripheral gas supply port, and the gas supply amount from each supply port is controlled separately. The distances of the inner peripheral gas supply port, the intermediate gas supply port, and the outer peripheral gas supply port from the mass flow controller, as well as the gas supply amounts from the inner peripheral gas supply port, the intermediate gas supply port, and the outer peripheral gas supply port, are set through prior research. The growth rate of the SiC epitaxial layer 20 during film formation is set to a range of 5 μm / h or more and 80 μm / h or less during the initial stage of crystal growth 31A, and to 50 μm / h or more during the stable crystal growth period 31B.

[0107] The nitrogen concentrations in the Z direction at the center 1 and the first peripheral point 2 of the fabricated SiC epitaxial layer 20 were determined using SIMS.

[0108] The maximum impurity concentration I of the buffer layer 21 at center 1 max 6.0×10 18 cm -3 The minimum impurity concentration I in the buffer layer 21 at center 1. min 3.4×10 18 cm -3 The average impurity concentration I of the buffer layer 21 at center 1. ave 5.3×10 18 cm -3 The uniformity of impurity concentration in the buffer layer 21 at center 1 is 49%, which is below 50%.

[0109] The maximum impurity concentration I at the buffer layer 21 at the first outer perimeter point 2 max 5.0×10 18 cm -3 The minimum impurity concentration I of the buffer layer 21 at the first outer peripheral point 2. min 3.5×10 18 cm -3 The average impurity concentration I of the buffer layer 21 at the first outer peripheral point 2. ave 4.7×10 18 cm -3 The uniformity of impurity concentration in the buffer layer 21 at the first peripheral point 2 is 32%, which is below 35%.

[0110] The average impurity concentration of the buffer layer 21 in Example 1 is 5.0 × 10⁻⁶. 18 cm -3 The average impurity concentration of buffer layer 21 is determined by the average impurity concentration I at the center 1 of buffer layer 21. ave The average impurity concentration I of the buffer layer 21 at the first peripheral point 2 ave Add them together and then divide by 2 to find the answer.

[0111] Furthermore, the basal dislocation density on the surface of the SiC epitaxial layer 20, fabricated under the same conditions, was measured. Specifically, the basal dislocation density in the drift layer 22 was 0.24 cm⁻¹. -2 The conversion rate of basal dislocations in buffer layer 21, obtained by dividing the basal dislocation density in drift layer 22 by the basal dislocation density of SiC substrate 10 and subtracting from 1, is 99.997%. The in-plane uniformity of impurity concentration in buffer layer 21 is 18%. The in-plane uniformity is measured at the interface between buffer layer 21 and drift layer 22.

[0112] Example 2

[0113] The difference between Example 2 and Example 1 is that a SiC substrate with a diameter of 200 mm (8 inches) and an offset angle of 4° was used instead. All other conditions were the same as in Example 1, and the same measurements were performed as in Example 1.

[0114] In Example 2, the maximum impurity concentration I of the buffer layer 21 at center 1 is... max It is 5.7 × 10 18 cm -3 The minimum impurity concentration I in the buffer layer 21 at center 1. min 3.5×10 18 cm -3 The average impurity concentration I of the buffer layer 21 at center 1. ave It is 5.1×10 18 cm -3 The uniformity of impurity concentration in the buffer layer 21 at center 1 is 43%.

[0115] In Example 2, the maximum value I of the impurity concentration in the buffer layer 21 at the first outer peripheral point 2 is... max 4.5×10 18 cm -3 The minimum impurity concentration I of the buffer layer 21 at the first outer peripheral point 2. min 2.7×10 18 cm -3 The average impurity concentration I of the buffer layer 21 at the first outer peripheral point 2. ave 4.1×10 18 cm -3 The uniformity of impurity concentration in the buffer layer 21 at the first outer peripheral point 2 is 44%.

[0116] The average impurity concentration of the buffer layer 21 in Example 2 is 4.6 × 10⁻⁶. 18 cm -3 .

[0117] Furthermore, the basal dislocation density on the surface of the SiC epitaxial layer 20, fabricated under the same conditions, was measured. Specifically, the basal dislocation density in the drift layer 22 was 0.24 cm⁻¹. -2 The conversion rate of basal dislocations in buffer layer 21, obtained by dividing the basal dislocation density in drift layer 22 by the basal dislocation density of SiC substrate 10 and subtracting from 1, is 99.997%. The in-plane uniformity of impurity concentration in buffer layer 21 is 22%.

[0118] Comparative Example 1

[0119] Comparative Example 1 did not specifically segment and control the initial crystal growth period 31A; during this initial growth period, the nitrogen supply was increased. Furthermore, in Comparative Example 1, the gas supply ports were not divided into inner, intermediate, and outer peripheral gas supply ports, nor were the distances between the inner, intermediate, and outer peripheral gas supply ports and the mass flow controller adjusted. In Comparative Example 1, the gas supply from each gas supply port was uniformly controlled. Other conditions were the same as in Example 1.

[0120] The nitrogen concentrations in the Z direction at the center 1 and the first peripheral point 2 of the SiC epitaxial layer of Comparative Example 1 were measured using SIMS.

[0121] The maximum impurity concentration I at the center 1 of Comparative Example 1 max 6.0×10 18 cm -3 The minimum impurity concentration I in the buffer layer at center 1 of Comparative Example 1. min 1.5×10 18 cm -3 The average impurity concentration I at the center 1 of Comparative Example 1 ave It is 5.1×10 18 cm -3 The uniformity of impurity concentration in the buffer layer at center 1 of Comparative Example 1 was 88%, which was below 90%.

[0122] The maximum impurity concentration I at the first peripheral point 2 of Comparative Example 1 max 4.0×10 18 cm -3 The minimum impurity concentration I of the buffer layer 21 at the first outer peripheral point 2 of Comparative Example 1. min 1.5×10 18 cm -3 The average impurity concentration I at the first peripheral point 2 of Comparative Example 1 in the buffer layer 21. ave 3.6×10 18 cm -3 The uniformity of impurity concentration in the buffer layer 21 at the first peripheral point 2 of Comparative Example 1 is 69%, which is below 70%.

[0123] The average impurity concentration of buffer layer 21 in Comparative Example 1 was 4.4 × 10⁻⁶. 18 cm -3 .

[0124] Furthermore, the basal plane dislocation density on the surface of the SiC epitaxial layer fabricated under the same conditions was measured. Specifically, the basal plane dislocation density in the drift layer of Comparative Example 1 was 0.24 cm⁻¹. -2The conversion rate of basal dislocations in Comparative Example 1 was 99.997%. The in-plane uniformity of impurity concentration in the buffer layer of Comparative Example 1 was 40%.

[0125] Reference Example 1

[0126] The difference between Reference Example 1 and Comparative Example 1 is that the impurity concentration of the buffer layer 21 was changed. Additionally, in Reference Example 1, the nitrogen concentration of the SiC substrate 10 was set to 1.0 × 10⁻⁶. 18 cm -2 The other conditions are the same as in Comparative Example 1.

[0127] The nitrogen concentrations in the Z direction at the center 1 and the first outer peripheral point 2 of the SiC epitaxial layer of Reference Example 1 were determined using SIMS.

[0128] The maximum impurity concentration I at the center 1 of Reference Example 1 max 7.0×10 17 cm -3 Referring to Example 1, the minimum impurity concentration I in the buffer layer at center 1 is... min 4.5×10 17 cm -3 The average impurity concentration I at the center 1 of Reference Example 1. ave 5.5×10 17 cm -3 The uniformity of impurity concentration in the buffer layer at center 1 of Reference Example 1 is 45%.

[0129] The maximum impurity concentration I of the buffer layer at point 2 on the first outer periphery of Example 1. max 1.2×10 18 cm -3 Referring to Example 1, the minimum impurity concentration I of the buffer layer 21 at the first outer peripheral point 2 is... min 7.0×10 17 cm -3 The average impurity concentration I at the buffer layer 21 at the first outer peripheral point 2 of Reference Example 1. ave 1.0×10 18 cm -3 The uniformity of impurity concentration in the buffer layer 21 at the first outer peripheral point 2 of Reference Example 1 is 50%.

[0130] The average impurity concentration of buffer layer 21 in Reference Example 1 is 7.75 × 10⁻⁶. 17 cm -3 .

[0131] Furthermore, the basal plane dislocation density on the surface of the SiC epitaxial layer fabricated under the same conditions was measured. Specifically, the basal plane dislocation density in the drift layer of Reference Example 1 was 0.24 cm⁻¹.-2 The conversion rate of basal dislocations in Reference Example 1 is 99.997%. The in-plane uniformity of impurity concentration in the buffer layer of Reference Example 1 is 58%.

[0132] In Reference Example 1, the average impurity concentration of buffer layer 21 is less than 2.0 × 10⁻⁶. 18 cm -3 Even without focusing on manufacturing methods, the variation in impurity concentration in the Z direction is small. Based on this result, it can be confirmed that when the average impurity concentration of the buffer layer 21 is 2.0 × 10⁻⁶... 18 cm -3 The above results in a larger variation in impurity concentration in the Z direction.

Claims

1. A SiC epitaxial wafer comprising a SiC substrate and a SiC epitaxial layer located on one side of the SiC substrate, The SiC epitaxial layer has a buffer layer and a drift layer. The buffer layer is located between the drift layer and the SiC substrate, and its impurity concentration is higher than that of the drift layer. The impurity concentration of the buffer layer is 2.0 × 10⁻⁶. 18 cm -3 above, When measuring the impurity concentration at the center when viewed from above along the stacking direction, the uniformity of the impurity concentration in the buffer layer is less than 50%. The uniformity of impurity concentration in the buffer layer is determined by (I max -I min ) / I ave Find out, I max It is the maximum value of the impurity concentration of the buffer layer in the stacking direction. I min It is the minimum impurity concentration of the buffer layer in the stacking direction. I ave It is the average value of the impurity concentration of the buffer layer in the stacking direction.

2. The SiC epitaxial wafer according to claim 1, When measuring the impurity concentration at the first peripheral point, located 5 mm from the outermost periphery when viewed from above along the stacking direction, the uniformity of the impurity concentration in the buffer layer is less than 50%.

3. The SiC epitaxial wafer according to claim 1, When measuring the impurity concentration at any point along the stacking direction when viewed from above, the uniformity of the impurity concentration in the buffer layer is less than 50%.

4. The SiC epitaxial wafer according to claim 1, When measuring the impurity concentration at the center when viewed from above along the stacking direction, in the region near the interface within 3 μm from the interface between the SiC substrate and the buffer layer toward the buffer layer side, the variation range of the impurity concentration is less than 50% of the average impurity concentration of the buffer layer in the stacking direction.

5. The SiC epitaxial wafer according to claim 1, When measuring the impurity concentration at the first peripheral point, located 5 mm from the outermost periphery when viewed from above along the stacking direction, the variation range of the impurity concentration in the region near the interface within 3 μm from the interface between the SiC substrate and the buffer layer is less than 50% of the average impurity concentration of the buffer layer in the stacking direction.

6. The SiC epitaxial wafer according to claim 1, The in-plane uniformity of impurity concentration in the buffer layer is below 50%. The in-plane uniformity of impurity concentration in the buffer layer is determined using |I1-I2| / {(I1+I2) / 2}. I1 is the impurity concentration of the buffer layer at its center when viewed from above in the stacking direction. I2 is the impurity concentration of the buffer layer at the first peripheral point, located 5 mm from the outermost periphery, when viewed from above in the stacking direction.

7. The SiC epitaxial wafer according to claim 1, The impurity concentration of the drift layer is 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×10 18 cm -3 the following.

8. The SiC epitaxial wafer according to claim 1, The conversion rate of basal dislocations in the buffer layer is above 99.997%.

9. The SiC epitaxial wafer according to claim 1, The basal dislocation density in the drift layer is 0.25 cm⁻¹. -2 the following.

10. The SiC epitaxial wafer according to claim 1, The basal dislocation density in the SiC substrate is 9000 cm⁻¹. -2 the following.

11. The SiC epitaxial wafer according to any one of claims 1 to 10, Its diameter is over 149mm.

12. The SiC epitaxial wafer according to any one of claims 1 to 10, Its diameter is over 199mm.

13. A SiC device comprising a SiC substrate and a SiC epitaxial layer located on one side of the SiC substrate. The SiC epitaxial layer has a buffer layer and a drift layer. The buffer layer is located between the drift layer and the SiC substrate, and its impurity concentration is higher than that of the drift layer. The impurity concentration of the buffer layer is 2.0 × 10⁻⁶. 18 cm -3 above, When measuring the impurity concentration along the stacking direction, the uniformity of the impurity concentration in the buffer layer is less than 50%. The uniformity of impurity concentration in the buffer layer is determined by (I max -I min ) / I ave Find out, I max It is the maximum value of the impurity concentration of the buffer layer in the stacking direction. I min It is the minimum impurity concentration of the buffer layer in the stacking direction. I ave It is the average value of the impurity concentration of the buffer layer in the stacking direction.

14. The SiC device according to claim 13, When measuring the impurity concentration at the center when viewed from above along the stacking direction, in the region near the interface within 3 μm from the interface between the SiC substrate and the buffer layer toward the buffer layer side, the variation range of the impurity concentration is less than 50% of the average impurity concentration of the buffer layer in the stacking direction.

15. The SiC device according to claim 13, The impurity concentration of the drift layer is 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×10 18 cm -3 the following.

16. The SiC device according to claim 13, The conversion rate of basal dislocations in the buffer layer is above 99.997%.

17. The SiC device according to claim 13, The basal dislocation density in the drift layer is 0.25 cm⁻¹. -2 the following.

18. The SiC device according to claim 13, The basal dislocation density in the SiC substrate is 9000 cm⁻¹. -2 the following.

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