Semiconductor module device

Abstract

Disclosed is a semiconductor module apparatus including: a first substrate including a dielectric insulating layer and a first metallization layer disposed on a surface of the dielectric insulating layer, where the first metallization layer includes a first portion, a second portion, a third portion, and a fourth portion; two or more controllable semiconductor elements, each controllable semiconductor element comprising a first contact pad, a second contact pad, and a third contact pad; wherein: the second contact pads of the two or more controllable semiconductor elements are electrically coupled to the first portion, and the first contact pad of each of the two or more controllable semiconductor elements is electrically coupled to the second portion through one or more electrical connection elements, the third contact pad of each of the two or more controllable semiconductor elements is electrically coupled to the third portion through one or more electrical connection elements, and the first contact pad of each of the two or more controllable semiconductor elements is electrically coupled to the fourth portion through one or more electrical connection elements.

Description

Technical Field

[0001] This disclosure relates to semiconductor module devices. Background Technology

[0002] Power semiconductor module devices typically include at least one semiconductor substrate disposed within a housing. Semiconductor devices comprising multiple controllable semiconductor elements (e.g., IGBTs, MOSFETs, HEMTs, etc.) are disposed on each of the at least one substrate. Each substrate typically includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and optionally a second metallization layer deposited on a second side of the substrate layer. Controllable semiconductor elements are mounted, for example, on the first metallization layer. The second metallization layer may optionally be attached to a substrate or a heat sink. In many applications, two or more individual controllable semiconductor elements are electrically coupled in parallel to each other to meet current-capacity requirements of the device. However, oscillations can occur when the parallel-coupled controllable semiconductor elements are turned on and off. One type of oscillation that can occur is so-called inter-chip oscillation, in which the parasitic capacitance of a controllable semiconductor element oscillates in opposition to the parasitic inductance present between the respective controllable semiconductor elements. Such oscillations can lead to EMI (electromagnetic interference) problems and / or undesirable voltage spikes that may damage the chip gate oxide.

[0003] Therefore, a semiconductor module device is typically required in which oscillations (and especially inter-chip oscillations) are significantly reduced. Summary of the Invention

[0004] A semiconductor module device includes: a first substrate including a dielectric insulating layer and a first metallization layer disposed on the surface of the dielectric insulating layer, wherein the first metallization layer includes a first portion, a second portion, a third portion, and a fourth portion; two or more controllable semiconductor elements, each of the two or more controllable semiconductor elements including a first contact pad, a second contact pad, and a third contact pad, wherein the second contact pads of the two or more controllable semiconductor elements are electrically coupled to the first portion, the first contact pads of the two or more controllable semiconductor elements are electrically coupled to the second portion via one or more electrical connection elements, the third contact pads of the two or more controllable semiconductor elements are electrically coupled to the third portion via one or more electrical connection elements, and the first contact pads of the two or more controllable semiconductor elements are electrically coupled to the fourth portion via one or more electrical connection elements.

[0005] The present disclosure can be better understood by referring to the following figures and description. The components in the figures are not necessarily drawn to scale, but rather the emphasis is on illustrating the principles of the present disclosure. In the figures, the same reference numerals denote corresponding parts in different views. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view of a semiconductor module device.

[0007] Figure 2 A top view of a conventional semiconductor module device is shown schematically.

[0008] Figure 3 This is the circuit diagram of a half-bridge device.

[0009] Figure 4 A top view of a semiconductor module device according to an embodiment of the present disclosure is shown schematically.

[0010] Figure 5 A top view of a semiconductor module device according to another embodiment of the present disclosure is shown schematically.

[0011] Figure 6 yes Figure 5 A three-dimensional view of a portion of a semiconductor module device.

[0012] Figure 7 A top view of a semiconductor module device according to a further embodiment of the present disclosure is shown schematically. Detailed Implementation

[0013] In the following detailed description, reference is made to the accompanying drawings. The drawings illustrate specific examples in which this disclosure may be practiced. It should be understood that, unless otherwise specifically indicated, the features and principles described with respect to the various examples may be combined with each other. And in the claims, the designation of certain elements as “first element,” “second element,” “third element,” etc., should not be construed as enumeration. Rather, these designations are used only to refer to different “elements.” That is, for example, the presence of a “third element” does not require the presence of a “first element” and a “second element.” The wire described herein may be a single conductive element or may comprise at least two individual conductive elements connected in series and / or in parallel. The wire may comprise metallic and / or semiconductor materials and may be permanently conductive (i.e., non-switchable). The wire may have a resistivity independent of the direction of the current flowing through it. The semiconductor body described herein may be made of (doped) semiconductor material and may be a semiconductor chip or included in a semiconductor chip. The semiconductor body has electrically connected pads and includes at least one semiconductor element having electrodes. The pads are electrically connected to the electrodes, which includes the pads being electrodes and vice versa.

[0014] refer to Figure 1The diagram schematically shows a cross-sectional view of a semiconductor module device 100. The semiconductor module device 100 includes a housing 7 and a substrate 10. The substrate 10 includes a dielectric insulating layer 11, a (structured) first metallization layer 111 attached to the dielectric insulating layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulating layer 11. The dielectric insulating layer 11 is disposed between the first metallization layer 111 and the second metallization layer 112.

[0015] Each of the first metallization layer 111 and the second metallization layer 112 may be composed of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The substrate 10 may be a ceramic substrate, i.e., the dielectric insulating layer 11 is a ceramic substrate, for example, a thin ceramic layer. The ceramic may be composed of or include one of the following materials: alumina; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may be composed of or include one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 10 may be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal bonding (AMB) substrate. Furthermore, the substrate 10 may be an insulating metal substrate (IMS). The insulating metal substrate typically includes a dielectric insulating layer 11, which may comprise (filled with) a material such as epoxy resin or polyimide. For example, the material of the dielectric insulating layer 11 may be filled with ceramic particles. These particles may include, for example, SiO2, Al2O3, AlN, or BN, and may have a diameter between about 1 μm and about 50 μm. The substrate 10 may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 may consist of or include a curable resin.

[0016] Substrate 10 is disposed within housing 7. Figure 1 In the example shown, substrate 10 is disposed on substrate 12 forming the base surface of housing 7, and housing 7 itself comprises only sidewalls and a cover. However, this is only an example. It is also possible that housing 7 further includes a base surface, and substrate 10 and substrate 12 are disposed within housing 7 and on the base surface of housing 7. In some power semiconductor module devices 100, more than one substrate 10 is disposed on a single substrate 12 or on the base surface of housing 7. According to another example, substrate 12 is omitted, and substrate 10 itself forms the base surface of housing 7.

[0017] One or more semiconductor bodies 20 may be disposed on at least one substrate 10. Each of the semiconductor bodies 20 disposed on at least one substrate 10 may include a diode, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High Electron Mobility Transistor), and / or any other suitable controllable or uncontrollable semiconductor element.

[0018] One or more semiconductor bodies 20 may be formed on the substrate 10 to create a semiconductor device. Figure 1 In the example shown are only two semiconductor bodies 20. Figure 1 The second metallization layer 112 of the substrate 10 is a continuous layer. Figure 1 In the example shown, the first metallization layer 111 is a structured layer. "Structured layer" means that the first metallization layer 111 is not a continuous layer, but rather includes recesses between different portions of the layer. Figure 1 Such a recess is schematically illustrated. In this example, the first metallization layer 111 comprises three distinct portions. However, this is merely an example. Any other number of portions are possible. Different semiconductor bodies 20 may be mounted to the same or different portions of the first metallization layer 111. The different portions of the first metallization layer 111 may not have electrical connections or may be electrically connected to one or more other portions using electrical connection elements 3 (e.g., bonding wires). For example, the electrical connection element 3 may also include a connecting plate or conductor rail, to name just a few. One or more semiconductor bodies 20 may be electrically and mechanically connected to the substrate 10 via a conductive connection layer 30. For example, such a conductive connection layer 30 may be a solder layer, a conductive adhesive layer, or a sintered metal powder layer, such as a sintered silver powder layer. According to other examples, it is also possible that the second metallization layer 112 is also a structured layer. It is also possible to omit the second metallization layer 112 entirely.

[0019] The power semiconductor module device 100 also includes terminal element 4. Figure 1 Only two terminal elements 4 are schematically shown. However, the power semiconductor module device 100 may typically include only one or more terminal elements 4. The terminal elements 4 are electrically connected to the first metallization layer 111 and provide electrical connection between the interior and exterior of the housing 7. The terminal elements 4 may be electrically connected to the first metallization layer 111 via a first end 41, while a second end 42 of each of the terminal elements 4 protrudes outside the housing 7. The terminal elements 4 may be electrically contacted from the outside at their respective second ends 42. A first portion of the terminal element 4 may extend through the interior of the housing 7 in a vertical direction y. The vertical direction y is perpendicular to the top surface of the substrate 10, where the top surface of the substrate 10 is the surface on which at least one semiconductor body 20 is mounted. However, Figure 1The terminal element 4 shown is merely an example. The terminal element 4 can be implemented in any other manner and can be arranged anywhere within the housing 7. For example, one or more terminal elements 4 can be arranged close to or adjacent to the sidewalls of the housing 7. The terminal element 4 can also protrude through the sidewalls of the housing 7 instead of through the cover. For example, the first end 41 of the terminal element 4 can be electrically and mechanically connected to the substrate 10 via a conductive connection layer (for...). Figure 1 Terminal element 4 is not explicitly shown. For example, this conductive connection layer can be a solder layer, a conductive adhesive layer, or a sintered metal powder layer, such as a sintered silver (Ag) powder layer. The first end 41 of terminal element 4 can also be electrically coupled to the substrate 10 via, for example, one or more electrical connection elements 3. For example, the second end 42 of terminal element 4 can optionally be connected to a printed circuit board (…). Figure 1 (Not shown in the image).

[0020] Further reference Figure 1 The semiconductor module device 100 may further include an encapsulation body 5. The encapsulation body 5 may be composed of or comprise silicone gel, for example, or may be, for example, a rigid molding compound. The encapsulation body 5 may at least partially fill the interior of the housing 7, thereby covering components and electrical connections disposed on the substrate 10. Terminal elements 4 may be partially embedded in the encapsulation body 5. However, at least their second ends 42 are not covered by the encapsulation body 5 and protrude from the encapsulation body 5 through the housing 7 to the outside of the housing 7. The encapsulation body 5 is configured to protect the components and electrical connections of the semiconductor module device 100, particularly those disposed on the substrate 10 and inside the housing 7, from certain environmental conditions and mechanical damage.

[0021] As described above, the semiconductor body 20 disposed on the substrate 10 can form a semiconductor device. According to one example, the semiconductor body 20 can form a half-bridge device. Figure 3The circuit diagram of a half-bridge device is schematically shown. A half-bridge device typically includes two controllable semiconductor elements T1, T2 arranged in series between a first terminal and a second terminal. The first terminal may be electrically coupled to a first potential (e.g., a positive potential DC+), and the second terminal may be electrically coupled to a second potential different from the first potential (e.g., a negative potential DC-). A common node between the two controllable semiconductor elements T1, T2 is typically connected to or forms an output node AC. If, as in this example, the first and second controllable semiconductor elements are IGBTs, then a first freewheeling element F1 is coupled in parallel to the first controllable semiconductor element T1, and a second freewheeling element F2 is coupled in parallel to the second controllable semiconductor element T2. If the controllable semiconductor elements are, for example, SiC MOSFETs, then a separate freewheeling element is not required. In the semiconductor module device according to this example, each of the first controllable semiconductor element T1, the second controllable semiconductor element T2, the first freewheeling element F1, and the second freewheeling element F2 can be implemented by two or more semiconductor bodies 20. For example, as... Figure 3 The first controllable semiconductor element T1 shown can be implemented by two or more semiconductor bodies 20, each semiconductor body 20 including a controllable semiconductor element 22x. Two or more controllable semiconductor elements 22x are coupled in parallel to form the first controllable semiconductor element T1. Figure 3 In the half-bridge device shown, the first controllable semiconductor element T1 is typically referred to as the high-side driver / switch, and the second controllable semiconductor element T2 is typically referred to as the low-side driver / switch. Note that... Figure 3 The half-bridge device illustrated is merely an example. Semiconductor elements can typically be arranged similarly in any other type of semiconductor device.

[0022] Now for reference Figure 2 The diagram schematically shows a top view of a semiconductor module device. The semiconductor module device includes a substrate 10, which includes a dielectric insulating layer 11 and a first metallization layer 111 disposed on the surface of the dielectric insulating layer 11. The first metallization layer 111 includes a first portion 1111, a second portion 1112, and a third portion 1113. The semiconductor device also includes two controllable semiconductor elements 221 and 222, each of which includes first contact pads 211 and 221, a second contact pad, and third contact pads 213 and 223. The semiconductor module device also includes two freewheeling elements 231 and 232, each of which includes first contact pads 311 and 321 and a second contact pad. The second contact pads of two controllable semiconductor elements 221, 222 and the second contact pads of two or more freewheeling elements 231, 232 are electrically coupled to the first portion 1111. Figure 2 In the illustrated device, controllable semiconductor elements 221, 222 and freewheeling elements 231, 232 are implemented as so-called vertical devices, and the second contact pads of the two controllable semiconductor elements 221, 222 and the second contact pads of the two or more freewheeling elements 231, 232 are electrically coupled to the first portion 1111 via a conductive interconnect layer, and thus in Figure 2 Not visible in the top view. However, implementing the controllable semiconductor elements 221, 222 and the freewheeling elements 231, 232 as vertical devices is merely an example. Conversely, the devices can also be implemented as so-called lateral devices. In a lateral device, all contact pads are arranged on the surface of the respective device facing away from the respective substrate. If the controllable semiconductor elements 221, 222 and the freewheeling elements 231, 232 are implemented as lateral devices, the second contact pads of the two controllable semiconductor elements 221, 222 and the second contact pads of the two or more freewheeling elements 231, 232 can be electrically coupled to the first portion 1111 via one or more electrical connection elements 3. The first contact pads 211, 221 of each of the two controllable semiconductor elements 221, 222 are electrically coupled to the first contact pads 311, 321 of one of the two freewheeling elements 231, 232 via one or more electrical connection elements 3 and are electrically coupled to the second portion 1112. The third contact pads 213 and 223 of the two controllable semiconductor elements 221 and 222 are electrically coupled to each other via electrical connection element 3. The third contact pad 223 of one of the two controllable semiconductor elements 221 and 222 is further electrically coupled to the third portion 1113 via electrical connection element 3. In addition, the first contact pads 211 and 221 of the two controllable semiconductor elements 221 and 222 can be electrically coupled to each other via electrical connection element 3.

[0023] like Figure 2 The two controllable semiconductor elements 221 and 222 shown can form the first controllable semiconductor element T1, and the two freewheeling elements 231 and 232 can form as shown in the figure. Figure 3The first freewheeling element F1 of the half-bridge device shown, or two controllable semiconductor elements 221, 222, can form a second controllable semiconductor element T2, and two freewheeling elements 231, 232 can, for example, form a second freewheeling element F2. Two or more individual controllable semiconductor elements 22x (semiconductor bodies) can be electrically coupled in parallel to each other to form an element of the semiconductor device, for example, to meet requirements regarding the current capability of the semiconductor device. However, oscillations may occur when the parallel-coupled controllable semiconductor elements are turned on and off. One type of oscillation that may occur is so-called inter-chip oscillation, in which the parasitic capacitance of the controllable semiconductor element oscillates in opposition to the parasitic inductance present between the respective controllable semiconductor elements. Such oscillations can cause EMI (electromagnetic interference) problems, especially if frequencies in the two- to three-digit MHz range are present in the semiconductor device. This high-frequency current flows between the semiconductor bodies electrically coupled in parallel to each other. This can result in electrical rails up to several centimeters in length, which can act as antennas. On the other hand, high peak voltages and high currents may occur inside the controllable semiconductor element 22x, which may ultimately lead to the degradation of the gate oxide of the controllable semiconductor element 22x, or even defects and melting of the structure in the gate network inside the chip.

[0024] Now for reference Figure 4 The diagram schematically illustrates a top view of a semiconductor module device according to an embodiment of the present disclosure. In the semiconductor module device according to an embodiment of the present disclosure, oscillations, particularly inter-chip oscillations, are significantly reduced or even avoided. The semiconductor module device according to an embodiment of the present disclosure includes a first substrate 10, which includes a dielectric insulating layer 11 and a first metallization layer 111 disposed on the surface of the dielectric insulating layer 11, wherein the first metallization layer 111 includes a first portion 1111, a second portion 1112, a third portion 1113, and a fourth portion 1114. The semiconductor module device further includes: two (or more) controllable semiconductor elements 221, 222, each of the two (or more) controllable semiconductor elements 221, 222 including first contact pads 211, 221, second contact pads, and third contact pads 213, 223; and one or more freewheeling elements 231, 232, each of the one or more freewheeling elements 231, 232 including first contact pads 311, 321 and second contact pads. The second contact pads of the two (or more) controllable semiconductor elements 221, 222 and the second contact pads of the one or more freewheeling elements 231, 232 are electrically coupled to the first portion 1111. Figure 4 In the example shown, the second contact pads of the controllable semiconductor elements 221, 222 and the second contact pads of the freewheeling elements 231, 232 are connected by a conductive interconnect layer (in... Figure 4(Not visible in the top view shown) Electrically coupled to the first portion 1111. However, as described above, the second contact pads of the controllable semiconductor elements 221, 222 and the second contact pads of the freewheeling elements 231, 232 may alternatively be electrically coupled to the first portion 1111 via electrical connection element 3 (e.g., if implemented as a lateral device). The first contact pads 211, 221 of each of the two (or more) controllable semiconductor elements 221, 222 are electrically coupled to one or more first contact pads 311, 321 of one or more freewheeling elements 231, 232 via one or more electrical connection elements 3 and are electrically coupled to the second portion 1112. The third contact pads 213, 223 of each of two or more controllable semiconductor elements 221, 222 are electrically coupled to a third portion 1113 via one or more electrical connection elements 3, and the first contact pads 211, 221 of each of two (or more) controllable semiconductor elements 221, 222 are electrically coupled to a fourth portion 1114 via one or more electrical connection elements 3. Figure 4 In the example shown, two freewheeling elements 231 and 232 are illustrated. However, in some applications, a single freewheeling element may suffice. Semiconductor module devices may also include more than two freewheeling elements.

[0025] It can be seen that, Figure 4 The third contact pads 213 and 223 of the controllable semiconductor elements 221 and 222 in the device shown are not directly coupled to each other through electrical connection element 3, as described above. Figure 2 As described. Instead, each of the third contact pads 213, 223 is directly coupled to the third portion 1113 via one or more electrical connection elements 3. Furthermore, the first metallization layer 111 includes an additional fourth portion 1114, which is not present in... Figure 4 In the illustrated device, the fourth portion 1114 serves as an isolation path for direct electrical coupling to each of the first contact pads 211, 221 of two (or more) controllable semiconductor elements 221, 222. The fourth portion 1114 is not directly electrically coupled to any other component of the semiconductor module device, or even to any other component outside the semiconductor module device. For example, the third portion 1113 can be electrically coupled to the outside of the semiconductor module device via one or more terminal elements 40. Figure 4 An exemplary terminal element 40 is shown. No such terminal element is arranged on and electrically coupled to the fourth portion 1114. The fourth portion 1114 only provides an additional path for electrically coupling the first contact pads 211, 221 to each other. This additional path, combined with the emitter path in parallel, results in a very low effective gate loop inductance.

[0026] Similar to the above about Figure 2 Described, Figure 4 The first contact pads 211, 221 of the two (or more) controllable semiconductor elements 221, 222 shown in the diagram can be additionally electrically coupled to each other via one or more electrical connection elements 3. In this way, a second path can be provided to directly electrically couple the first contact pads 211, 221 to each other. This direct connection can further help reduce unwanted oscillations.

[0027] Each of two or more controllable semiconductor elements 22x may include a control electrode and a controllable load path between a first load electrode and a second load electrode. The load paths of the controllable semiconductor elements 22x are coupled in parallel to each other. The control electrode of the controllable semiconductor element 22x may be formed by or coupled to a third contact pad 2x3 of the corresponding controllable semiconductor element 22x, the first load electrode may be formed by or coupled to a first contact pad 2x1 of the corresponding controllable semiconductor element 22x, and the second load electrode may be formed by or coupled to a second contact pad of the corresponding controllable semiconductor element 22x. According to one example, the first contact pad 2x1 of one or more controllable semiconductor elements 22x is an emitter pad, the second contact pad of one or more controllable semiconductor elements 22x is a collector pad, and the third contact pad 2x3 of one or more controllable semiconductor elements 22x is a base (or gate) pad. According to an alternative example, the first contact pad 2x1 of one or more controllable semiconductor elements 22x is a source or drain pad, the second contact pad of one or more controllable semiconductor elements 22x is the other of the drain or source pads, and the third contact pad 2x3 of one or more controllable semiconductor elements 22x is a gate pad.

[0028] Each of one or more freewheeling elements 23x may include a first electrode and a second electrode. The first electrode of the freewheeling element 23x may be formed by or coupled to the first contact pad 3x1 of the corresponding freewheeling element 23x, and the second electrode of the freewheeling element 23x may be formed by or coupled to the second contact pad of the corresponding freewheeling element 23x. For example, the first contact pads 3x1 of two or more freewheeling elements 23x may be anode pads, and the second contact pads of two or more freewheeling elements 23x may be cathode pads, and vice versa.

[0029] Still referencing Figure 4For each of two (or more) controllable semiconductor elements 221, 222, the following can be applied: one or more electrical connection elements 3 electrically coupled to the third contact pad 2x3 to the third portion 1113 are arranged parallel to one or more electrical connection elements 3 electrically coupled to the first contact pad 2x1 to the fourth portion 1114. In this way, the base (or gate) and emitter paths (or source paths) of each controllable semiconductor element 22x electrically coupled to the third portion 1113 and the fourth portion 1114, respectively, can be arranged closely adjacent to each other. This allows for strong inductive coupling between the two corresponding paths (at the substrate level). These two paths will drive the effective emitter / source and gate / base inductances between the different controllable semiconductor elements 22x in the two or more controllable semiconductor elements 22x to a minimum. Simultaneously, with Figure 2 Compared to the device shown, each of the two or more controllable semiconductor elements 22x will exhibit (substantially) the same conduction behavior (dI / dt).

[0030] According to one example, the distance d3 between the third contact pad 2x3 of the controllable semiconductor element 22x electrically coupled to one or more electrical connection elements 3 of the third portion 1113 and the first contact pad 2x1 of the same controllable semiconductor element 22x electrically coupled to one or more electrical connection elements 3 of the fourth portion 1114 can be equal to the minimum required distance to provide sufficient insulation between the one or more electrical connection elements 3 electrically coupled to the third contact pad 2x3 of the third portion 1113 and the one or more electrical connection elements 3 electrically coupled to the first contact pad 2x1 of the fourth portion 1114. The minimum required distance between the respective electrical connection elements 3 can vary for different applications. For example, the minimum required distance depends in particular on the materials used to form the electrical connection elements 3, the manufacturing process used to assemble the device, and the creepage distance. It also depends on the voltage present therein during the use of the device. For example, the minimum required distance can be determined to accommodate voltages up to 40V. The minimum required distance is typically the distance between one or more electrical connection elements 3 that electrically couple the third contact pad 2x3 to the third part 1113 and one or more electrical connection elements 3 that electrically couple the first contact pad 2x1 to the fourth part 1114, at which a short circuit or flashover is unlikely to occur between the corresponding connection elements 3 connected to different potentials.

[0031] In the second horizontal direction z, the fourth portion 1114 can be arranged between the first portion 1111 and the third portion 1113, and the first portion 1111 can be arranged between the fourth portion 1114 and the second portion 1112. That is, the fourth portion 1114 can be arranged closer to the third portion 1113 than the first portion 1111. As the portion closest to the third portion 1113, the fourth portion 1114 further helps to reduce or even avoid so-called inter-chip oscillations between controllable semiconductor elements 22x coupled in parallel with each other. However, arranging the fourth portion 1114 between the first portion 1111 and the third portion 1113 is merely an example. For example, it is also possible that the substrate is a so-called multilayer substrate, i.e., a substrate including a first metallization layer 111 having multiple layers. In a multilayer substrate, the third portion 1113 and the fourth portion 1114 can be arranged in the same horizontal plane or in different horizontal planes (e.g., perpendicularly above each other).

[0032] According to one example, the fourth portion 1114 can be an elongated region. That is, the length of the fourth portion 1114 in the first horizontal direction x can be significantly greater than the width of the fourth portion 1114 in the second horizontal direction z, where the second horizontal direction z is perpendicular to the first horizontal direction x. The fourth portion 1114 can have a substantially rectangular shape. However, any other shape is generally possible. The width of the fourth portion 1114 in the second horizontal direction z can be chosen to be large enough to provide sufficient space to attach one or more electrical connection elements 3 thereto (e.g., to form a reliable engagement connection). The length of the fourth portion 1114 in the first horizontal direction x generally depends on the size of the controllable semiconductor elements 22x and the distance between the controllable semiconductor elements 22x.

[0033] As in Figure 4 and Figure 5 As schematically shown, the fourth portion 1114 can have a meandering shape. That is, some portions of the fourth portion 1114 can be arranged closer to the controllable semiconductor element 22x in the second horizontal direction z than other portions. The length of the electrical connection element 3 connecting the third contact pad 2x3 of each of the two or more controllable semiconductor elements 22x to the third portion 1113 can be selected to be as short as possible. Therefore, the third portion 1113 can have portions arranged as close as possible to the corresponding controllable semiconductor element 22x (e.g., close to the third contact pads 213, 223). However, as in Figure 4 and Figure 5As schematically illustrated, the first portion 1111 can be electrically coupled to a first potential P1 via a first busbar, and the second portion 1112 can be electrically coupled to a second potential P2, different from the first potential P1, via a second busbar. That is, a certain amount of space may need to be provided on the first portion 1111 to allow the first busbar to be connected thereto (e.g., via a conductive interconnect layer). The busbar is typically arranged toward the edge of the substrate 10. Therefore, the first portion 1111 may have a portion further away from the edge of the substrate 10 (where the third portion 1113 is arranged as close as possible to the controllable semiconductor element 22x) and a portion further extending toward the edge of the substrate 10 to provide sufficient space for attaching one or more busbars thereto. This may result in a meandering shape for the fourth portion 1114, as shown. For example, the meandering shape of the fourth portion 1114 may alternatively or additionally be caused by a gap created in the fourth portion 1114. For example, such a gap can be implemented to reduce the effective stray inductance of the device.

[0034] Figure 4 A substrate 10 is schematically shown having two controllable semiconductor elements 22x and two freewheeling elements 23x attached thereto. As mentioned above, it is generally possible for more than two controllable semiconductor elements 22x and / or fewer than two (i.e., only one) or more than two freewheeling elements 23x to be arranged on the substrate 10 to form a first controllable semiconductor element T1 and a first freewheeling element F1, or a second controllable semiconductor element T2 and a second freewheeling element F2 (see, for example, [reference needed]). Figure 3 (half-bridge device).

[0035] It is also possible that two or more of the multiple controllable semiconductor elements 22x are arranged on the first substrate, and two or more of the multiple controllable semiconductor elements 22x are arranged on an additional second substrate 10. The same applies to the freewheeling element 23x. This is in Figure 5 This is illustrated schematically. That is to say, in addition to the above regarding... Figure 4In addition to the first substrate 10 described, the semiconductor module device may further include a second substrate 10, the second substrate 10 including a dielectric insulating layer 11 and a first metallization layer 111 disposed on the surface of the dielectric insulating layer 11, wherein the first metallization layer 111 includes a first portion 1111, a second portion 1112, a third portion 1113, and a fourth portion 1114. The semiconductor module device may further include: two or more additional controllable semiconductor elements 22x, each of the two or more additional controllable semiconductor elements 22x including a first contact pad 2x1, a second contact pad, and a third contact pad 2x3; and one or more additional freewheeling elements 23x, each of the one or more additional freewheeling elements 23x including a first contact pad 3x1 and a second contact pad, wherein the second contact pads of the two or more additional controllable semiconductor elements 22x and the second contact pads of the two or more additional freewheeling elements 23x are electrically coupled to a first portion 1111 of the first metallization layer 111 of the second substrate 10. Each of the two or more additional controllable semiconductor elements 22x has a first contact pad 2x1 electrically coupled to one or more first contact pads 3x1 of one or more additional freewheeling elements 23x via one or more electrical connection elements 3 and electrically coupled to a second portion 1112 of the second substrate 10. Each of the two or more additional controllable semiconductor elements 22x has a third contact pad 2x3 electrically coupled to a third portion 1113 of the second substrate 10 via one or more electrical connection elements 3, and each of the two or more additional controllable semiconductor elements 22x has a first contact pad 2x1 electrically coupled to a fourth portion 1114 of the second substrate 10 via one or more electrical connection elements 3.

[0036] like Figure 5 The first and second substrates 10 shown are each substantially similar to, for example: Figure 4 The substrate 10 is shown. However, in Figure 4 In the example shown, the number of controllable semiconductor elements 22x is equal to the number of freewheeling elements 23x on substrate 10, which is not... Figure 5 The situation is shown in the example. Figure 5 In the example shown, the number of controllable semiconductor elements 22x on each substrate 10 is greater than the number of freewheeling elements 23x on the same substrate 10. Each controllable semiconductor element 22x can be directly electrically coupled to only one of the freewheeling elements 23x on the same substrate 10, or directly electrically coupled to more than one of the freewheeling elements 23x on the same substrate 10, via one or more electrical connection elements 3.

[0037] Still referencing Figure 5The third portion 1113 of the first metallization layer 111 of the first substrate 10 can be electrically coupled to the third portion 1113 of the first metallization layer 111 of the second substrate 10 via one or more electrical connection elements 3. The fourth portion 1114 of the first metallization layer 111 of the first substrate 10 can be electrically coupled to the fourth portion 1114 of the first metallization layer 111 of the second substrate 10 via one or more electrical connection elements 3, and the second portion 1112 of the first metallization layer 10 can be electrically coupled to the second portion 1112 of the first metallization layer 111 of the second substrate 10 via one or more electrical connection elements 3. In this way, the controllable semiconductor element 22x disposed on the first substrate 10 is coupled in parallel with the controllable semiconductor element 22x disposed on the second substrate 10. For example, the controllable semiconductor element 22x disposed on the first substrate 10 and the controllable semiconductor element 22x disposed on the second substrate 10 can together form the first controllable semiconductor element T1, such as... Figure 3 As shown in the diagram. Similarly, the current-carrying element 23x disposed on the first substrate 10 and the current-carrying element 23x disposed on the second substrate 10 can be formed together as shown in the diagram. Figure 3 The first freewheeling element F1 of the half-bridge device shown. For example, it is also possible that the controllable semiconductor element 22x disposed on the first substrate 10 and the controllable semiconductor element 22x disposed on the second substrate 10 together form a second controllable semiconductor element T2, and the freewheeling element 23x disposed on the first substrate 10 and the freewheeling element 23x disposed on the second substrate 10 together form a... Figure 3 The second freewheeling element F2 of the half-bridge device shown.

[0038] Figure 6 The electrical connection element 3 is illustrated in further detail. This electrical connection element 3 electrically couples a fourth portion 1114 of the first metallization layer 111 of the first substrate 10 to a fourth portion 1114 of the first metallization layer 111 of the second substrate 10, and also electrically couples a third portion 1113 of the first metallization layer 111 of the first substrate 10 to a third portion 1113 of the first metallization layer 111 of the second substrate 10, because such a connection is as follows: Figure 5 The busbar shown is not visible behind it.

[0039] Typically, a single (only one / no more than one) electrical connection element 3 coupling a specific portion of the first metallization layer 111 of the first substrate 10 to a corresponding portion of the first metallization layer 111 of the second substrate 10 may be sufficient, as in Figure 5 and Figure 6 This is schematically illustrated. However, the substrate-to-substrate connection can be further improved if more than one electrical connection element 3 is used to form the corresponding substrate-to-substrate connection. This is in Figure 7 It is illustrated schematically. Figure 7 In the example shown, a third portion 1113 of the first metallization layer 111 of the first substrate 10 is electrically coupled to a third portion 1113 of the first metallization layer 111 of the second substrate 10 via more than one (e.g., at least three) electrical connection elements 3 (not visible behind the busbar), a fourth portion 1114 of the first metallization layer 111 of the first substrate 10 is electrically coupled to a fourth portion 1114 of the first metallization layer 111 of the second substrate 10 via more than one (e.g., at least three) electrical connection elements 3 (not visible behind the busbar), and a second portion 1112 of the first metallization layer 111 of the first substrate 10 is electrically coupled to a second portion 1112 of the first metallization layer 111 of the second substrate 10 via more than one (e.g., at least three) electrical connection elements 3. In this way, a very low inductance substrate-to-substrate connection can be achieved, which further reduces unwanted oscillations.

[0040] In addition to or in lieu of the connections provided between the different substrates 10 of the semiconductor module device, connections provided on each of the respective substrates 10 may also be implemented by more than one electrical connection element 3. Still referring to Figure 7 The first contact pad 2x1 of at least one of two or more controllable semiconductor elements 22x can be electrically coupled to the fourth part 1114 by more than one (e.g., at least three) electrical connection elements 3. Figure 7 In the example shown, only one of the two or more controllable semiconductor elements 22x on each substrate 10 is connected by more than one electrical connection element 3. Figure 7 The four electrical connection elements 22x on each substrate 10 are electrically coupled to the fourth portion 1114. The remaining controllable semiconductor elements 22x of two or more controllable semiconductor elements 22x on each substrate 10 are electrically coupled to the fourth portion 1114 of the respective substrate 10 via only one electrical connection element 3. However, this is only an example. It is generally possible that the first contact pads 2x1 of two or more (e.g., all) of the two or more controllable semiconductor elements 22x on each substrate 10 are electrically coupled to the fourth portion 1114 of the respective substrate 10 via more than one electrical connection element 3. Using more than one electrical connection element 3 (e.g., at least two or at least three) can further help reduce unwanted oscillations.

[0041] By individually electrically coupling each controllable semiconductor element 22x to a third portion 1113 of the first metallization layer 111, by providing an additional fourth portion 1114 of the first metallization layer 111, and by further individually electrically coupling each controllable semiconductor element 22x to the fourth portion 1114, low-inductance connections (e.g., emitter or source connections) are provided between different controllable semiconductor elements 22x. Strong inductance coupling between different controllable semiconductor elements 22x can be achieved if the electrical connection elements 3 connecting the controllable semiconductor elements 22x to the third portion 1113 and the electrical connection elements 3 connecting the same controllable semiconductor element 22x to the fourth portion 1114 are arranged in parallel and as close to each other as possible (e.g., distance d3 less than 3 mm or less than 2 mm). Through this measure, the effective source / emitter and gate / base inductances can be driven to a minimum. In this way, inter-chip oscillations can be significantly reduced or even avoided. For example, for the drain-source voltage V... DS Very good results can be achieved for high-frequency pole paths of 200V and low-frequency pole paths for all drain-source voltages.

Claims

1. A semiconductor module arrangement, comprising: a first substrate (10) comprising a dielectric insulating layer (11) and a first metallization layer (111) arranged on a surface of the dielectric insulating layer (11), wherein the first metallization layer (111) comprises a first portion (1111), a second portion (1112), a third portion (1113), and a fourth portion (1114); two or more controllable semiconductor elements (22x), each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) comprising a first contact pad (2xl), a second contact pad, and a third contact pad (2x3); wherein: the second contact pads of the two or more controllable semiconductor elements (22x) are electrically coupled to the first portion (1111), the first contact pads (2xl) of each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) are electrically coupled to the second portion (1112) by one or more electrical connection elements (3), the third contact pads (2x3) of each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) are electrically coupled to the third portion (1113) by one or more electrical connection elements (3), and the first contact pads (2xl) of each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) are electrically coupled to the fourth portion (1114) by one or more electrical connection elements (3).

2. The semiconductor module device according to claim 1, wherein, In a second horizontal direction (z), the fourth portion (1114) is arranged between the first portion (1111) and the third portion (1113), and the first portion (1111) is arranged between the fourth portion (1114) and the second portion (1112).

3. The semiconductor module device according to claim 1 or 2, wherein, The first contact pads (2xl) of the two or more controllable semiconductor elements (22x) are electrically coupled to each other by one or more electrical connection elements (3).

4. The semiconductor module arrangement according to any one of claims 1 to 3, wherein, For each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x), the following applies: the one or more electrical connection elements (3) electrically coupling the third contact pad (2x3) to the third portion (1113) are arranged parallel to the one or more electrical connection elements (3) electrically coupling the first contact pad (2xl) to the fourth portion (1114).

5. The semiconductor module device according to claim 4, wherein, a distance (d3) between the one or more electrical connection elements (3) electrically coupling the third contact pad (2x3) to the third portion (1113) and the one or more electrical connection elements (3) electrically coupling the first contact pad (2x1) to the fourth portion (1114) is equal to a minimum required distance in order to provide sufficient insulation between the one or more electrical connection elements (3) electrically coupling the third contact pad (2x3) to the third portion (1113) and the one or more electrical connection elements (3) electrically coupling the first contact pad (2x1) to the fourth portion (1114).

6. The semiconductor module arrangement according to any of the preceding claims, wherein, The first portion (1111) is electrically coupled to a first potential (P1) by a first busbar and the second portion (1112) is electrically coupled to a second potential (P2) different from the first potential (P1) by a second busbar.

7. The semiconductor module arrangement according to any one of the preceding claims, wherein: The first contact pad (2x1) of the one or more controllable semiconductor elements (22x) is an emitter pad, the second contact pad of the one or more controllable semiconductor elements (22x) is a collector pad, and the third contact pad (2x3) of the one or more controllable semiconductor elements (22x) is a base pad, or The first contact pad (2x1) of the one or more controllable semiconductor elements (22x) is a source or drain pad, the second contact pad of the one or more controllable semiconductor elements (22x) is a respective other one of a drain or source pad, and the third contact pad (2x3) of the one or more controllable semiconductor elements (22x) is a gate pad.

8. The semiconductor module arrangement according to any one of the preceding claims, comprising: one or more freewheeling elements (23x), each of the one or more freewheeling elements (23x) comprising a first contact pad (3x1) and a second contact pad; wherein the second contact pad of the one or more freewheeling elements (23x) is electrically coupled to the first portion (1111); and the first contact pad (2x1) of each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) is electrically coupled to one or more first contact pads (3x1) of the one or more freewheeling elements (23x) and to the second portion (1112).

9. The semiconductor module arrangement according to any one of the preceding claims, further comprising: a second substrate (10) comprising a dielectric insulating layer (11) and a first metallization layer (111) arranged on a surface of the dielectric insulating layer (11), wherein the first metallization layer (111) comprises a first portion (1111), a second portion (1112), a third portion (1113), and a fourth portion (1114); two or more controllable semiconductor elements (22x), each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) comprising a first contact pad (2xl), a second contact pad, and a third contact pad (2x3); wherein: the second contact pad of the two or more controllable semiconductor elements (22x) is electrically coupled to the first portion (1111), the first contact pad (2xl) of each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) is electrically coupled to one or more first contact pads (3xl) of the one or more freewheeling elements (23x) and to the second portion (1112) by one or more electrical connection elements (3), the third contact pad (2x3) of each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) is electrically coupled to the third portion (1113) by one or more electrical connection elements (3), and the first contact pad (2xl) of each controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) is electrically coupled to the fourth portion (1114) by one or more electrical connection elements (3).

10. The semiconductor module arrangement according to claim 9, wherein: the third portion (1113) of the first metallization layer (111) of the first substrate (10) is electrically coupled to the third portion (1113) of the first metallization layer (111) of the second substrate (10) by one or more electrical connection elements (3), the fourth portion (1114) of the first metallization layer (111) of the first substrate (10) is electrically coupled to the fourth portion (1114) of the first metallization layer (111) of the second substrate (10) by one or more electrical connection elements (3), and the second portion (1112) of the first metallization layer (111) of the first substrate (10) is electrically coupled to the second portion (1112) of the first metallization layer (111) of the second substrate (10) by one or more electrical connection elements (3).

11. The semiconductor module device of claim 10, wherein, at least one of the following is met: the third portion (1113) of the first metallization layer (111) of the first substrate (10) is electrically coupled to the third portion (1113) of the first metallization layer (111) of the second substrate (10) by more than one electrical connection element (3), the fourth portion (1114) of the first metallization layer (111) of the first substrate (10) is electrically coupled to the fourth portion (1114) of the first metallization layer (111) of the second substrate (10) by more than one electrical connection element (3), and the second portion (1112) of the first metallization layer (111) of the first substrate (10) is electrically coupled to the second portion (1112) of the first metallization layer (111) of the second substrate (10) by more than one electrical connection element (3). The second portion (1112) of the first metallization layer (111) of the first substrate (10) is electrically coupled to the second portion (1112) of the first metallization layer (111) of the second substrate (10) by more than one electrical connection element (3).

12. The semiconductor module arrangement according to any of the preceding claims, wherein, The first contact pad (2x1) of at least one controllable semiconductor element (22x) of the two or more controllable semiconductor elements (22x) is electrically coupled to the fourth portion (1114) by more than one electrical connection element (3).

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