Pixel circuit and driving method thereof, display panel and display device

Abstract

The invention provides a pixel circuit and a driving method thereof, a display panel and a display device, and belongs to the technical field of display. The pixel circuit comprises a plurality of control circuits and a driving circuit. Wherein the plurality of control circuits can be matched with each other to control the potential of the first node and the potential of the second node, so that the driving circuit can transmit a driving signal to the light-emitting element based on the potential of the first node and the potential of the second node so as to drive the light-emitting element to emit light. Wherein the potential difference of initial signals transmitted by the control circuit to the first node and the second node is large. Therefore, the bias voltage of the driving transistor in the driving circuit can be increased as much as possible, so that the light-emitting element can be reliably driven to emit light after the temperature rises, the temperature drift phenomenon of the display panel is solved, and the display effect of the display panel can be better.

Description

Pixel circuit and driving method thereof, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display panels are widely used in various display products due to their advantages such as self-luminescence, high contrast, wide color gamut and wide operating temperature range.

[0003] Currently, OLED display panels generally include multiple pixels. Each pixel includes a pixel circuit and a light-emitting element (i.e., an OLED). The pixel circuit is coupled to the light-emitting element, and the pixel circuit includes at least a drive transistor. The drive transistor is capable of transmitting a drive current to the light-emitting element to drive the light-emitting element to emit light.

[0004] However, due to the characteristic drift of the driving transistor, the pixel circuit in the related art cannot reliably drive the light-emitting element to emit light, resulting in the display panel being prone to temperature drift, in which abnormal brightness increases with temperature.

[0005] Summary of the Invention

[0006] The present disclosure provides a pixel circuit and a driving method thereof, a display panel, and a display device. The technical solution is as follows:

[0007] In one aspect, a pixel circuit is provided for driving a light-emitting element to emit light in multiple frame periods at a target refresh frequency, each frame period including a refresh frame and at least one hold frame; the pixel circuit comprises:

[0008] a first control circuit, coupled to the first gate control terminal, the second gate control terminal, the data terminal, the first node, the second node, and the third node, respectively, and configured to control the connection and disconnection between the first node and the third node in response to a first gate control signal provided by the first gate control terminal, and to control the connection and disconnection between the data terminal and the second node in response to a second gate control signal provided by the second gate control terminal;

[0009] a second control circuit coupled to the first reset terminal, the second reset terminal, the first initial terminal, the second initial terminal, the third initial terminal, the second node, the third node, and the fourth node, respectively, and configured to control the connection and disconnection between the first initial terminal and the third node in response to a first reset signal provided by the first reset terminal, and to control the connection and disconnection between the second initial terminal and the fourth node in response to a second reset signal provided by the second reset terminal, and to control the connection and disconnection between the third initial terminal and the second node;

[0010] a third control circuit, coupled to the light-emitting control terminal, the driving power supply terminal, the second node, the third node, and the fourth node, respectively, and configured to control the connection and disconnection between the driving power supply terminal and the second node, and the connection and disconnection between the third node and the fourth node in response to a light-emitting control signal provided by the light-emitting control terminal, wherein the fourth node is coupled to the light-emitting element;

[0011] a driving circuit, coupled to the first node, the second node, and the third node, respectively, and configured to transmit a driving signal to the third node based on the potentials of the first node and the second node;

[0012] Among them, in the refresh frame, the first initial end and the third initial end are controlled in turn to be connected to the first node and the second node respectively, so that the first initial end and the third initial end transmit the first initial signal and the third initial signal to the first node and the second node respectively in turn, and the potential difference between the transmitted first initial signal and the third initial signal is greater than or equal to the potential difference threshold.

[0013] Optionally, the potential difference threshold is -9V.

[0014] Optionally, the first control circuit includes: a first transistor and a second transistor; the second control circuit includes: a third transistor, a fourth transistor and a fifth transistor; the third control circuit includes: a sixth transistor and a seventh transistor; the driving circuit includes: an eighth transistor;

[0015] The gate of the first transistor is coupled to the first gate control terminal, the first electrode of the first transistor is coupled to the third node, and the second electrode of the first transistor is coupled to the first node;

[0016] The gate of the second transistor is coupled to the second gate control terminal, the first electrode of the second transistor is coupled to the data terminal, and the second electrode of the second transistor is coupled to the second node;

[0017] The gate of the third transistor is coupled to the first reset terminal, the first electrode of the third transistor is coupled to the first initial terminal, and the second electrode of the third transistor is coupled to the third node;

[0018] The gate of the fourth transistor is coupled to the second reset terminal, the first electrode of the fourth transistor is coupled to the second initial terminal, and the second electrode of the fourth transistor is coupled to the fourth node;

[0019] The gate of the fifth transistor is coupled to the second reset terminal, the first electrode of the fifth transistor is coupled to the third initial terminal, and the second electrode of the fifth transistor is coupled to the second node;

[0020] The gate of the sixth transistor is coupled to the light emitting control terminal, the first electrode of the sixth transistor is coupled to the driving power supply terminal, and the second electrode of the sixth transistor is coupled to the second node;

[0021] The gate of the seventh transistor is coupled to the light emitting control terminal, the first electrode of the seventh transistor is coupled to the third node, and the second electrode of the seventh transistor is coupled to the fourth node;

[0022] The gate of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the third node;

[0023] The pixel circuit further includes a storage capacitor connected in series between the driving power supply terminal and the first node.

[0024] Optionally, the first transistor is an N-type transistor; the second transistor to the eighth transistor are all P-type transistors;

[0025] Furthermore, the material of the N-type transistor includes an oxide material; and the material of the P-type transistor includes a low-temperature polysilicon material.

[0026] In another aspect, a method for driving a pixel circuit is provided, for driving the pixel circuit according to the above aspect; the method comprising: sequentially executing a refresh frame and at least one hold frame in each frame period of a multi-frame period of a target refresh frequency;

[0027] In a refresh frame: providing a light emitting control signal of an effective potential and an ineffective potential in sequence to the light emitting control terminal; providing a first gate control signal of an effective potential and an ineffective potential in sequence to the first gate control terminal within at least one cycle, and the first gate control signal of an effective potential is within a time period when the light emitting control signal is at an ineffective potential; providing a first reset signal of an effective potential and a second gate control signal of an effective potential in sequence to the first reset terminal and the second gate control terminal within a time period when the first gate control signal is at an effective potential, and providing a second reset signal of an ineffective potential to the second reset terminal; providing a first reset signal of an ineffective potential and a second gate control signal of an ineffective potential to the first reset terminal and the second gate control terminal, respectively, within a time period when the first gate control signal is at an ineffective potential, and providing a second reset signal of an effective potential to the second reset terminal;

[0028] In the hold frame: providing light emitting control signals of valid potential and invalid potential to the light emitting control terminal in sequence;

[0029] Among them, for any signal among the light-emitting control signal, the first gate control signal, the second gate control signal, the first reset signal and the second reset signal, the signal of the effective potential is used to control the conduction of the coupled parts; the signal of the invalid potential is used to control the disconnection of the coupled parts.

[0030] Optionally, the providing the first gate control signal of the effective potential and the invalid potential to the first gate control terminal in sequence within at least one cycle includes: providing the first gate control signal of the effective potential and the invalid potential to the first gate control terminal in sequence within two cycles;

[0031] The step of providing the second gate control signal with an effective potential to the second gate control terminal during the time period when the first gate control signal is at an effective potential includes:

[0032] In a second period of the two periods, and within a time period when the first gate control signal is at an effective potential, providing a second gate control signal at an effective potential to the second gate control terminal;

[0033] The method further comprises:

[0034] In the refresh frame, before the first cycle of the two cycles, a light-emitting control signal with an invalid potential is provided to the light-emitting control terminal, a first gate control signal with an invalid potential is provided to the first gate control terminal, a first reset signal with an invalid potential is provided to the first reset terminal, a second gate control signal with an invalid potential is provided to the second gate control terminal, and a second reset signal with an invalid potential is provided to the second reset terminal.

[0035] Optionally, the duration during which the first reset signal is at the effective potential in the second period is greater than or equal to the duration during which the first reset signal is at the effective potential in the second period.

[0036] Optionally, the overlapping time length of the first gate control signal of the invalid potential and the second reset signal of the valid potential in the first cycle is less than or equal to the overlapping time length of the first gate control signal of the invalid potential and the second reset signal of the valid potential in the second cycle.

[0037] Optionally, the providing the first gate control signal of the effective potential and the invalid potential in sequence to the first gate control terminal in at least one cycle includes: providing the first gate control signal of the effective potential and the invalid potential in sequence to the first gate control terminal in one cycle;

[0038] The method further comprises:

[0039] In a refresh frame, before the one period, a light emitting control signal with an invalid potential is provided to the light emitting control terminal, a first gate control signal with an invalid potential is provided to the first gate control terminal, a first reset signal with an invalid potential is provided to the first reset terminal, a second gate control signal with an invalid potential is provided to the second gate control terminal, and a second reset signal with an effective potential is provided to the second reset terminal;

[0040] Furthermore, the duration during which the second reset signal is at the effective potential before the one cycle is longer than the duration during which the second reset signal is at the effective potential during the one cycle.

[0041] Optionally, the duration during which the second reset signal is at the effective potential before the one cycle is equal to the duration during which the first gate control signal is at the effective potential during the one cycle.

[0042] Optionally, the method further includes:

[0043] In the holding frame, a first gate control signal of an invalid potential is provided to the first gate control terminal, a first reset signal of an invalid potential is provided to the first reset terminal, a second gate control signal of an invalid potential is provided to the second gate control terminal, and within at least one cycle, a second reset signal of an effective potential and an invalid potential is sequentially provided to the second reset terminal, and the second reset signal of the effective potential is within the time duration when the light-emitting control signal is at an invalid potential.

[0044] Optionally, the target refresh frequency includes: 120 Hz; the method includes: executing a refresh frame and two hold frames in sequence in each frame period.

[0045] In yet another aspect, a display panel is provided, comprising: a substrate, and a plurality of pixels located on the substrate;

[0046] The pixel includes: a light-emitting element, and the pixel circuit as described in the above aspect; the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

[0047] Optionally, the display panel further includes: a plurality of array substrate row driving GOA circuits corresponding one-to-one to the first gate control terminal, the second gate control terminal, the first reset terminal, the second reset terminal and the light emitting control terminal coupled to the pixel circuit;

[0048] Each group of GOA circuits is respectively coupled to the start signal terminal, the clock signal terminal and the corresponding signal terminal, and is used to transmit a signal to the corresponding signal terminal based on the start signal provided by the start signal terminal and the clock signal provided by the clock signal terminal according to the driving method according to any one of claims 6 to 12.

[0049] In another aspect, a display device is provided, comprising: a power supply component, and the display panel as described in the above-mentioned further aspect;

[0050] The power supply component is coupled to the display panel and is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0052] FIG1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0053] FIG2 is a circuit structure diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0054] FIG3 is a flow chart of a driving method of a pixel circuit provided by an embodiment of the present disclosure;

[0055] FIG4 is a timing diagram of a signal terminal coupled to a pixel circuit provided by an embodiment of the present disclosure;

[0056] FIG5 is a timing diagram of signal terminals coupled to another pixel circuit provided by an embodiment of the present disclosure;

[0057] FIG6 is a timing diagram of a signal terminal coupled to another pixel circuit provided by an embodiment of the present disclosure;

[0058] FIG7 is a timing diagram of a signal terminal coupled to another pixel circuit provided by an embodiment of the present disclosure;

[0059] FIG8 is a schematic diagram of a frequency conversion provided by an embodiment of the present disclosure;

[0060] FIG9 is a schematic diagram of an x-color coordinate decrease amplitude provided by an embodiment of the present disclosure;

[0061] FIG10 is a schematic diagram of a y color coordinate drop amplitude provided by an embodiment of the present disclosure;

[0062] FIG11 is a schematic diagram of a brightness reduction range provided by an embodiment of the present disclosure;

[0063] FIG12 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0064] 13 is a signal timing diagram of a GOA circuit corresponding to a first gate control terminal provided by an embodiment of the present disclosure;

[0065] FIG14 is a signal timing diagram of a GOA circuit corresponding to a second gate control terminal provided by an embodiment of the present disclosure;

[0066] FIG15 is a signal timing diagram of a GOA circuit corresponding to a first reset terminal provided by an embodiment of the present disclosure;

[0067] FIG16 is a signal timing diagram of a GOA circuit corresponding to a second reset terminal provided by an embodiment of the present disclosure;

[0068] FIG17 is a signal timing diagram of a GOA circuit corresponding to a light emitting control terminal provided in an embodiment of the present disclosure;

[0069] FIG18 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0071] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. The source is referred to as the first electrode and the drain as the second electrode, or the drain is referred to as the first electrode and the source as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end as the source, and the signal output end as the drain. Furthermore, the switching transistors used in the embodiments of the present disclosure may include either a P-type transistor or an N-type transistor, or a combination thereof. A P-type transistor is turned on when the gate voltage is low and turned off when the gate voltage is high, while an N-type transistor is turned on when the gate voltage is high and turned off when the gate voltage is low. Furthermore, multiple signals in each embodiment correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two different states and do not represent that the first potential or the second potential has a specific value.

[0072] Temperature drift is explained below, in conjunction with the background technology and Table 1 below: Temperature drift refers to the difference in brightness and chromaticity of a display product (e.g., a mobile phone) after the screen temperature rises from room temperature (e.g., 25°C) to, for example, 50°C. The greater the difference, the worse the display quality and the more detrimental it is to the display product. Examples of temperature rise include charging or gaming.

[0073] Table 1

[0074] In Table 1, Temp refers to temperature; Band refers to the display brightness level, which is shown as 2 nits; Pattern refers to the display image, which is shown as a white (W) image at 32 grayscales; x and y refer to the x and y color coordinates, respectively; Lv also refers to brightness, with units of candela / square meter (cd / m 2 ) represents the change in the x-color coordinate after a temperature rise from room temperature to 50°C; ΔWx and Wx% represent the change in the x-color coordinate after a temperature rise from room temperature to 50°C and the rate of change; ΔWy and ΔWy% represent the change in the y-color coordinate after a temperature rise from room temperature to 50°C and the rate of change; ΔLW and ΔLW% represent the change in brightness after a temperature rise from room temperature to 50°C and the rate of change. As shown in Table 1, the current brightness difference due to temperature drift is approximately 50% to 70%. As the temperature rises, screen brightness often decreases rapidly, for example, the display quickly shifts from white to blue, resulting in poor display quality.

[0075] Based on this, an embodiment of the present disclosure provides a pixel circuit and a driving method thereof to improve the temperature drift problem and ensure a better display effect. Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure. The pixel circuit can be used to drive a light-emitting element to emit light under multiple frame periods of a target refresh frequency, each frame period including a refresh frame and at least one hold frame. As shown in Figure 1, the pixel circuit includes: a first control circuit 01, a second control circuit 02, a third control circuit 03, and a driving circuit 04.

[0076] The first control circuit 01 is coupled to the first gate control terminal Gate_N(n), the second gate control terminal Gate_P(n), the data terminal Data(n), the first node N1, the second node N2, and the third node N3, respectively. The first control circuit 01 is configured to control the connection between the first node N1 and the third node N3 in response to a first gate control signal provided by the first gate control terminal Gate_N(n), and to control the connection between the data terminal Data(n) and the second node N2 in response to a second gate control signal provided by the second gate control terminal Gate_P(n).

[0077] For example, the first control circuit 01 can control the first node N1 and the third node N3 to be conductive when the potential of the first gate control signal provided by the first gate control terminal Gate_N(n) is a valid potential, so that the signal transmitted to the third node N3 can be further transmitted to the first node N1. The first control circuit 01 can control the first node N1 to be decoupled from the third node N3 when the potential of the first gate control signal provided by the first gate control terminal Gate_N(n) is a deactivated potential.

[0078] Similarly, when the potential of the second gate control signal provided by the second gate control terminal Gate_P(n) is a valid potential, the first control circuit 01 can control the data terminal Data(n) to be conductively connected to the second node N2, so that the data signal provided by the data terminal Data(n) can be transmitted to the second node N2. When the potential of the second gate control signal provided by the second gate control terminal Gate_P(n) is a de-active potential, the first control circuit 01 can control the data terminal Data(n) to be decoupled from the second node N2.

[0079] Optionally, for a P-type transistor included in the circuit, the effective potential may be a low potential relative to the invalid potential; for an N-type transistor included in the circuit, the effective potential may be a high potential relative to the invalid potential.

[0080] Continuing with FIG1 , it can be seen that the second control circuit 02 is coupled to the first reset terminal Reset_P(n), the second reset terminal Reset_H(n), the first initial terminal Vinit1, the second initial terminal Vinit2, the third initial terminal Vinit3, the second node N2, the third node N3, and the fourth node N4, respectively. The second control circuit 02 is configured to control the connection between the first initial terminal Vinit1 and the third node N3 in response to a first reset signal provided by the first reset terminal Reset_P(n), and to control the connection between the second initial terminal Vinit2 and the fourth node N4, and to control the connection between the third initial terminal Vinit3 and the second node N2 in response to a second reset signal provided by the second reset terminal Reset_H(n).

[0081] For example, when the potential of the first reset signal provided by the first reset terminal Reset_P(n) is a valid potential, the second control circuit 02 can control the first initial terminal Vinit1 to be conductive with the third node N3, so that the first initial signal provided by the first initial terminal Vinit1 can be transmitted to the third node N3. On this basis, when the first control circuit 01 simultaneously controls the first node N1 and the third node N3 to be conductive, the first initial signal transmitted to the third node N3 can be further transmitted to the first node N1, that is, the first initial signal is written to the first node N1. The second control circuit 02 can control the first initial terminal Vinit1 to be decoupled from the third node N3 when the potential of the first reset signal provided by the first reset terminal Reset_P(n) is an invalid potential.

[0082] Similarly, when the potential of the second reset signal provided by the second reset terminal Reset_H(n) is a valid potential, the second control circuit 02 can control the second initial terminal Vinit2 to be conductively connected to the fourth node N4, and control the third initial terminal Vinit3 to be conductively connected to the second node N2, so that the second initial signal provided by the second initial terminal Vinit2 can be transmitted to the fourth node N4, and the third initial signal provided by the third initial terminal Vinit3 can be transmitted to the second node N2. When the potential of the second reset signal provided by the second reset terminal Reset_H(n) is a deactivated potential, the second control circuit 02 can control the second initial terminal Vinit2 to be decoupled from the fourth node N4, and control the third initial terminal Vinit3 to be decoupled from the second node N2.

[0083] Optionally, the fourth node N4 can be coupled to the light-emitting element L1. Furthermore, referring to FIG1 , the light-emitting element L1 can be an OLED having a first electrode and a second electrode, one of which can be an anode and the other a cathode. As shown in FIG1 , the fourth node N4 can be coupled to the anode of the light-emitting element L1. The cathode of the light-emitting element L1 can also be coupled to the pull-down power supply terminal VSS.

[0084] Continuing with FIG1 , it can be seen that the third control circuit 03 is coupled to the light-emitting control terminal EM(n), the driving power supply terminal VDD, the second node N2, the third node N3, and the fourth node N4, respectively. The third control circuit 03 is configured to control the connection between the driving power supply terminal VDD and the second node N2, and the connection between the third node N3 and the fourth node N4, in response to a light-emitting control signal provided by the light-emitting control terminal EM(n).

[0085] For example, when the potential of the light-emitting control signal provided by the light-emitting control terminal EM(n) is at a valid potential, the third control circuit 03 can control the driving power supply terminal VDD to be electrically connected to the second node N2, and the third node N3 to be electrically connected to the fourth node N4, so that the driving power supply signal provided by the driving power supply terminal VDD can be transmitted to the second node N2, and the signal transmitted to the third node N3 can be further transmitted to the fourth node N4. In other words, a path can be formed between the driving power supply terminal VDD and the pull-down power supply terminal VSS, thereby allowing the light-emitting element L1 to reliably emit light under the action of the signal voltage difference received by its anode and cathode. When the potential of the light-emitting control signal provided by the light-emitting control terminal EM(n) is at an inactive potential, the third control circuit 03 can control the driving power supply terminal VDD to be decoupled from the second node N2, and the third node N3 to be decoupled from the fourth node N4.

[0086] Continuing with FIG. 1 , it can be seen that the drive circuit 04 is coupled to the first node N1, the second node N2, and the third node N3, respectively. The drive circuit 04 is configured to transmit a drive signal (e.g., a drive current) to the third node N3 based on the potentials of the first node N1 and the second node N2. On this basis, when the third control circuit 03 controls the third node N3 to be conductive with the fourth node N4, the drive signal transmitted to the third node N3 can be further transmitted to the fourth node N4, i.e., to the anode of the light-emitting element L1. At this point, the light-emitting element L1 can emit light due to the voltage difference between the drive signal and the pull-down power signal provided by the pull-down power supply terminal VSS.

[0087] During a refresh frame, the first initial terminal Vinit1 and the third initial terminal Vinit3 can be sequentially controlled to be conductive with the first node N1 and the second node N2, respectively, so that the first initial terminal Vinit1 and the third initial terminal Vinit3 can transmit the first initial signal and the third initial signal to the first node N1 and the second node N2, respectively. Furthermore, the potential difference between the transmitted first initial signal and the third initial signal can be greater than or equal to a potential difference threshold, i.e., the difference between the two can be large. This can increase the voltage difference between the first node N1 and the second node N2, thereby increasing the bias voltage stress of the driver transistor in the driver circuit 04. The greater the stress, the less affected the operation of the driver circuit 04 is by characteristic drift, enabling reliable transmission of the drive signal to the light-emitting element L1, avoiding a significant difference in brightness between the light-emitting element L1 before and after a temperature rise, thereby addressing the temperature drift issue.

[0088] It should be noted that in the embodiments of the present disclosure, a pixel circuit and a light-emitting element coupled to each other may be referred to as a pixel. The display panel may include a plurality of pixels arranged in an array, and the above xx(n) may refer to the xx signal terminal coupled to the pixel circuit in the nth row of pixels. For example, the first gate control terminal Gate_N(n) may refer to the first gate control terminal Gate_N coupled to the pixel circuit in the nth row of pixels.

[0089] In summary, an embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes multiple control circuits and a drive circuit. The multiple control circuits can cooperate with each other to control the potential of the first node and the potential of the second node, so that the drive circuit can transmit a drive signal to the light-emitting element based on the potential of the first node and the potential of the second node to drive the light-emitting element to emit light. The potential difference of the initial signal transmitted by the control circuit to the first node and the second node is large. In this way, the bias voltage of the driving transistor in the driving circuit can be increased as much as possible, thereby ensuring that it can still reliably drive the light-emitting element to emit light after the temperature rises, thereby solving the temperature drift phenomenon of the display panel and ensuring that the display effect of the display panel can be better.

[0090] Optionally, in some embodiments, the potential difference threshold may be -9 volts (V). That is, the potential difference between the first initial signal and the third initial signal may be greater than or equal to -9V.

[0091] For example, the potential Vinit10 of the first initial power signal may be greater than or equal to -6V and less than or equal to -1V; the potential Vinit20 of the second initial power signal may be greater than or equal to 3V and less than or equal to 7V.

[0092] Optionally, based on the structure shown in FIG1 , FIG2 shows a circuit structure diagram of a pixel circuit. As shown in FIG2 , the first control circuit 01 may include a first transistor T1 and a second transistor T2. The second control circuit 02 may include a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The third control circuit 03 may include a sixth transistor T6 and a seventh transistor T7. The drive circuit 04 may include an eighth transistor T8.

[0093] The gate of the first transistor T1 may be coupled to the first gate control terminal Gate_N(n), the first electrode of the first transistor T1 may be coupled to the third node N3, and the second electrode of the first transistor T1 may be coupled to the first node N1.

[0094] A gate of the second transistor T2 may be coupled to the second gate control terminal Gate_P(n), a first electrode of the second transistor T2 may be coupled to the data terminal Data(n), and a second electrode of the second transistor T2 may be coupled to the second node N2.

[0095] A gate of the third transistor T3 may be coupled to the first reset terminal Reset_P(n), a first electrode of the third transistor T3 may be coupled to the first initial terminal Vinit1 , and a second electrode of the third transistor T3 may be coupled to the third node N3 .

[0096] A gate of the fourth transistor T4 may be coupled to the second reset terminal Reset_H(n), a first electrode of the fourth transistor T4 may be coupled to the second initial terminal Vinit2 , and a second electrode of the fourth transistor T4 may be coupled to the fourth node N4 .

[0097] A gate of the fifth transistor T5 may be coupled to the second reset terminal Reset_H(n), a first electrode of the fifth transistor T5 may be coupled to the third initial terminal Vinit3 , and a second electrode of the fifth transistor T5 may be coupled to the second node N2 .

[0098] A gate of the sixth transistor T6 may be coupled to the light emitting control terminal EM(n), a first electrode of the sixth transistor T6 may be coupled to the driving power supply terminal VDD, and a second electrode of the sixth transistor T6 may be coupled to the second node N2.

[0099] A gate of the seventh transistor T7 may be coupled to the light emitting control terminal EM(n), a first electrode of the seventh transistor T7 may be coupled to the third node N3, and a second electrode of the seventh transistor T7 may be coupled to the fourth node N4.

[0100] A gate of the eighth transistor T8 may be coupled to the first node N1 , a first electrode of the eighth transistor T8 may be coupled to the second node N2 , and a second electrode of the eighth transistor T8 may be coupled to the third node N3 .

[0101] Furthermore, the pixel circuit may further include: a storage capacitor Cst connected in series between the driving power supply terminal VDD and the first node N1.

[0102] Optionally, referring to FIG. 2 , it can be seen that the first transistor T1 can be an N-type transistor, and the second transistor T2 to the eighth transistor T8 can all be P-type transistors.

[0103] Moreover, the material of the N-type transistor may include an oxide material. The material of the P-type transistor may include a low-temperature polysilicon (LTPS) material. It should be noted that the transistor materials here refer to the materials of the active layer included in the transistor. Transistors made of low-temperature polysilicon have the advantages of high mobility and fast charging, while transistors made of oxide materials have the advantages of low leakage current. Integrating the two on a display panel, namely the LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and thus improve display quality.

[0104] Optionally, the pixel circuit shown in FIG2 can be regarded as a circuit with an 8T1C (i.e., 8 transistors and 1 capacitor) structure; in some other embodiments, the pixel circuit can also be other structures, such as 7T1C, which is not limited in the embodiments of the present disclosure.

[0105] As can be seen from the pixel circuit shown in Figure 2, the eighth transistor T8 is a driving transistor. The potential difference (Vinit10-Vinit20) between the potential of the first initial power signal Vinit10 transmitted to the first node N1 and the potential of the second initial power signal Vinit20 transmitted to the second node N2 can be referred to as the gate-source voltage difference Vgs of the driving transistor. That is, Vgs = Vinit10-Vinit20 ≈ -9V. This increases the stress of the driving transistor and addresses the issue of poor display quality caused by temperature drift.

[0106] In summary, an embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes multiple control circuits and a drive circuit. The multiple control circuits can cooperate with each other to control the potential of the first node and the potential of the second node, so that the drive circuit can transmit a drive signal to the light-emitting element based on the potential of the first node and the potential of the second node to drive the light-emitting element to emit light. The potential difference of the initial signal transmitted by the control circuit to the first node and the second node is large. In this way, the bias voltage of the driving transistor in the driving circuit can be increased as much as possible, thereby ensuring that it can still reliably drive the light-emitting element to emit light after the temperature rises, thereby solving the temperature drift phenomenon of the display panel and ensuring that the display effect of the display panel can be better.

[0107] Based on the structure of the above pixel circuit, an embodiment of the present disclosure provides a driving method of a pixel circuit to drive the pixel circuit described in the above embodiment to achieve the purpose of increasing the stress of the driving transistor.

[0108] FIG3 is a flow chart of a driving method provided by an embodiment of the present disclosure. The method comprises: sequentially executing a refresh frame and at least one hold frame in each frame period of a multi-frame period of a target refresh frequency.

[0109] Step 301, in a refresh frame: sequentially providing a light-emitting control signal with a valid potential and an invalid potential to the light-emitting control terminal; sequentially providing a first gate control signal with a valid potential and an invalid potential to the first gate control terminal within at least one cycle, and the first gate control signal with a valid potential is within the duration when the light-emitting control signal is at an invalid potential; sequentially providing a first reset signal with a valid potential and a second gate control signal with a valid potential to the first reset terminal and the second gate control terminal within the duration when the first gate control signal is at a valid potential, and providing a second reset signal with an invalid potential to the second reset terminal; providing a first reset signal with an invalid potential and a second gate control signal with an invalid potential to the first reset terminal and the second gate control terminal respectively within the duration when the first gate control signal is at an invalid potential, and providing a second reset signal with a valid potential to the second reset terminal.

[0110] Step 302: In the hold frame, provide light-emitting control signals of valid potential and invalid potential to the light-emitting control terminal in sequence.

[0111] As can be seen from the above embodiments, for any of the light-emitting control signal, the first gate control signal, the second gate control signal, the first reset signal, and the second reset signal, a signal with an effective potential is used to control the conduction of the coupled components; a signal with an ineffective potential is used to control the disconnection of the coupled components. For example, in conjunction with FIG1 , a first gate control signal with an effective potential can cause the first control circuit 01 to control the conduction of the coupled first node N1 and the third node N3; a first gate control signal with an ineffective potential can cause the first control circuit 01 to control the disconnection of the coupled first node N1 and the third node N3.

[0112] Optionally, based on the above driving method, the following embodiments provide multiple timing design examples.

[0113] As an optional implementation:

[0114] As can be seen from a timing diagram shown in FIG4 , in step 301 , providing the first gate control signal of the effective potential and the invalid potential to the first gate control terminal Gate_N(n) in sequence within at least one cycle may include:

[0115] The first gate control signal of valid potential and invalid potential is sequentially provided to the first gate control terminal Gate_N(n) in two cycles. That is, the operation of sequentially providing the first gate control signal of valid potential and invalid potential to the first gate control terminal Gate_N(n) is performed twice.

[0116] On this basis, referring to FIG4 , it can be seen that in step 301 , during the time period when the first gate control signal is at the effective potential, providing the second gate control signal with an effective potential to the second gate control terminal Gate_P(n) may include:

[0117] In the second period of the two periods, and within the time period when the first gate control signal is at the effective potential, the second gate control signal at the effective potential is provided to the second gate control terminal Gate_P(n).

[0118] And, the driving method may further include:

[0119] In the refresh frame, before the first cycle of the two cycles, a light-emitting control signal of an invalid potential is provided to the light-emitting control terminal EM(n), a first gate control signal of an invalid potential is provided to the first gate control terminal Gate_N(n), a first reset signal of an invalid potential is provided to the first reset terminal Reset_P(n), a second gate control signal of an invalid potential is provided to the second gate control terminal Gate_P(n), and a second reset signal of an invalid potential is provided to the second reset terminal Reset_H(n).

[0120] Optionally, as shown in FIG4 , the duration during which the first reset signal is at the effective potential in the second cycle may be greater than the duration during which the first reset signal is at the effective potential in the second cycle.

[0121] Alternatively, as shown in the derived timing sequence 1 in FIG5 , the duration during which the first reset signal is at the valid potential in the second cycle may be equal to the duration during which the first reset signal is at the valid potential in the second cycle. Of course, in some other embodiments, the duration during which the first reset signal is at the valid potential in the second cycle may also be less than the duration during which the first reset signal is at the valid potential in the second cycle.

[0122] The derived timing sequence 1 shown in FIG5 can be considered as shortening the duration of the first reset signal being at the effective potential in the second cycle based on FIG4 , which is also referred to as “duration shortening” as shown in FIG5 .

[0123] Optionally, as shown in Figure 4, the overlapping time length of the first gate control signal of the invalid potential and the second reset signal of the valid potential in the first cycle can be equal to the overlapping time length of the first gate control signal of the invalid potential and the second reset signal of the valid potential in the second cycle.

[0124] Alternatively, as shown in the derived timing sequence 2 in FIG6 , the overlap duration of the first gate control signal at the inactive potential and the second reset signal at the active potential in the first cycle may be shorter than the overlap duration of the first gate control signal at the inactive potential and the second reset signal at the active potential in the second cycle. Of course, in some other embodiments, the overlap duration of the first gate control signal at the inactive potential and the second reset signal at the active potential in the first cycle may also be longer than the overlap duration of the first gate control signal at the inactive potential and the second reset signal at the active potential in the second cycle.

[0125] The derived timing 2 shown in FIG6 can be considered as shortening the overlapping time of the first gate control signal of the invalid potential and the second reset signal of the valid potential in the first cycle based on FIG4, that is, the "time shortening" shown in FIG6.

[0126] As another optional implementation:

[0127] As can be seen from another timing diagram shown in FIG7 , in step 301, sequentially providing the first gate control signal with a valid potential and an invalid potential to the first gate control terminal Gate_N(n) within at least one cycle may include sequentially providing the first gate control signal with a valid potential and an invalid potential to the first gate control terminal Gate_N(n) within one cycle. In other words, the operation of sequentially providing the first gate control signal with a valid potential and an invalid potential to the first gate control terminal Gate_N(n) is performed only once.

[0128] On this basis, referring to FIG7 , it can be seen that the driving method further includes:

[0129] In the refresh frame, before one cycle, a light emitting control signal of an invalid potential is provided to the light emitting control terminal EM(n), a first gate control signal of an invalid potential is provided to the first gate control terminal Gate_N(n), a first reset signal of an invalid potential is provided to the first reset terminal Reset_P(n), a second gate control signal of an invalid potential is provided to the second gate control terminal Gate_P(n), and a second reset signal of a valid potential is provided to the second reset terminal Reset_H(n).

[0130] Furthermore, the duration that the second reset signal is at an effective potential before a cycle can be longer than the duration that the second reset signal is at an effective potential during a cycle. In other words, the duration that the second reset signal is at an effective potential for the first time can be extended as much as possible, as shown in the "Extended Duration" label in FIG7 .

[0131] Alternatively, with continued reference to FIG7 , in some embodiments, the duration that the second reset signal is at an effective potential before a cycle may be equal to the duration that the first gate control signal is at an effective potential during a cycle. For example, both durations are 18 hours. Furthermore, FIG7 schematically illustrates the durations of other signals provided.

[0132] Optionally, referring to FIG. 4 to FIG. 7 , it can be seen that the driving method may further include:

[0133] In the hold frame, a first gate control signal of an invalid potential is provided to the first gate control terminal Gate_N(n), a first reset signal of an invalid potential is provided to the first reset terminal Reset_P(n), a second gate control signal of an invalid potential is provided to the second gate control terminal Gate_P(n), and within at least one cycle, a second reset signal of a valid potential and an invalid potential is sequentially provided to the second reset terminal Reset_H(n), and the second reset signal of the valid potential is within the time period when the light-emitting control signal is at an invalid potential.

[0134] For example, in the timing sequences shown in FIG. 4 to FIG. 7 , the second reset signal of the valid potential and the invalid potential is sequentially provided to the second reset terminal Reset_H(n) within one period of the hold frame.

[0135] Optionally, taking the structure shown in FIG2 and the timing shown in FIG4 as an example, the working principle of the pixel circuit is described as follows:

[0136] At time t01, a first gate control signal with an effective potential (i.e., a high potential) can be provided to the first gate control terminal Gate_N(n), and a first reset signal with an effective potential (i.e., a low potential) can be provided to the first reset terminal Reset_P(n). On this basis, both the first transistor T1 and the third transistor T3 can be turned on. Furthermore, the first initial signal provided by the first initial terminal Vinit1 can first be transmitted to the third node N3 via the turned-on third transistor T3, and then transmitted to the first node N1 via the turned-on first transistor T1. In other words, the first initial signal can be written to the gate of the driving transistor "eighth transistor T8."

[0137] At time t02, a first gate control signal of an invalid potential (ie, a low potential) may be provided to the first gate control terminal Gate_N(n), thereby turning off the first transistor T1.

[0138] At time t03, a second reset signal of an effective potential (i.e., a low potential) can be provided to the second reset terminal Reset_H(n). On this basis, the fourth transistor T4 and the fifth transistor T5 can both be turned on. Furthermore, the second initial signal provided by the second initial terminal Vinit2 can be transmitted to the fourth node N4 via the turned-on fourth transistor T4, that is, transmitted to the anode of the light-emitting element L1, to reset the light-emitting element L1. Moreover, the third initial signal provided by the third initial terminal Vinit3 can be transmitted to the second node N2 via the turned-on fifth transistor T5. That is, the third initial signal can be written to the source of the driving transistor "eighth transistor T8". At this time, the gate-source voltage difference Vgs of the driving transistor can satisfy: Vgs=Vinit10-Vinit30. As described in the above embodiment, in the implementation of the present disclosure, Vgs=Vinit10-Vinit30≈-9V. In this way, the stress of the driving transistor can be made larger.

[0139] At time t04, the first gate control signal of an effective potential can be provided to the first gate control terminal Gate_N(n) again, and the first reset signal of an effective potential can be provided to the first reset terminal Reset_P(n), so that the first transistor T1 and the third transistor T3 are turned on again, and the first initial signal is written to the gate of the driving transistor "eighth transistor T8" again to reset the storage capacitor Cst.

[0140] It should be noted that in the timing sequence shown in Figure 4, the duration of the effective potential of the first reset signal provided at time t04 is relatively longer than that at time t01. For example, time t01 can be 6 hours, while time t04 can be extended to 14 hours. In the derived timing sequence 1 shown in Figure 5, the duration of the effective potential of the first reset signal provided at time t04 can be shortened, thereby improving brightness differences caused by temperature changes.

[0141] At time t05, the first gate control signal with an effective potential can continue to be provided to the first gate control terminal Gate_N(n), and the second gate control signal with an effective potential (i.e., a low potential) can be provided to the second gate control terminal Gate_P(n) at the same time. On this basis, the first transistor T1 can remain turned on, and the second transistor T2 can be turned on. Furthermore, the data signal provided by the data terminal Data(n) can be transmitted to the second node N2 via the turned-on second transistor T2. Because the first initial signal is written to the first node N1 at time t04, the eighth transistor T8 can be turned on. Furthermore, at time t05, the data signal transmitted to the second node N2 can first be transmitted to the third node N3 via the turned-on eighth transistor T8, and then transmitted to the first node N1 via the turned-on first transistor T1. That is, the data signal can be written to the gate of the driving transistor "eighth transistor T8", facilitating subsequent compensation of the threshold voltage Vth of the driving transistor.

[0142] At time t06, a first gate control signal with an inactive potential can be provided to the first gate control terminal Gate_N(n), and a second reset signal with an active potential can be provided to the second reset terminal Reset_H(n). On this basis, the first transistor T1 can be turned off, and the fourth transistor T4 and the fifth transistor T5 can be turned on again. Furthermore, the second initial signal provided by the second initial terminal Vinit2 can be transmitted to the fourth node N4 via the turned-on fourth transistor T4, i.e., to the anode of the light-emitting element L1, thereby resetting the light-emitting element L1. Furthermore, the third initial signal provided by the third initial terminal Vinit3 can be transmitted to the second node N2 via the turned-on fifth transistor T5. Because the eighth transistor T8 is turned on at time t05, it can remain on at time t06 under the maintenance effect of the storage capacitor Cst. Furthermore, the third initial signal transmitted to the second node N2 can be further transmitted to the third node N3 via the turned-on eighth transistor T8. That is, at time t06, the third initial signal can be written to the second node N2 and the third node N3, and the second initial signal can be written to the light-emitting element L1. This can improve the flicker problem and can also be characterized by a variable refresh rate (VRR), that is, improve the VRR.

[0143] At time t07, a light-emission control signal with an effective potential (i.e., a low potential) can be provided to the light-emission control terminal EM(n). This turns on the sixth transistor T6 and the seventh transistor T7. Furthermore, a path is formed between the driving power supply terminal VDD and the pull-down power supply terminal VSS, driving the light-emitting element L1 to reliably emit light.

[0144] At time t08, a light-emission control signal with an inactive potential (i.e., a high potential) can be provided to the light-emission control terminal EM(n), and a second reset signal with an active potential can be provided to the second reset terminal Reset_H(n). Consequently, the sixth transistor T6 and the seventh transistor T7 can be turned off, and the fourth transistor T4 and the fifth transistor T5 can be turned on. Furthermore, the third initial signal is written to the second node N2 and the third node N3, and the second initial signal is written to the light-emitting element L1. This improves VRR / Flicker issues. Time t09 remains consistent with time t08.

[0145] It should be noted that, comparing the derived timing sequence 2 shown in FIG4 and FIG6 , the time at t03 is relatively shortened, which can facilitate Flicker optimization. Furthermore, comparing the derived timing sequence 3 shown in FIG4 and FIG7 , the effective duration of the first provided second reset signal is lengthened, which can also facilitate Flicker optimization.

[0146] In Figure 4, time t01 to time t03 can be considered as the first cycle of the first gate control signal, which sequentially provides an effective potential and an ineffective potential to the first gate control terminal Gate_N(n); time t04 to time t07 can be considered as the second cycle of the first gate control signal, which sequentially provides an effective potential and an ineffective potential to the first gate control terminal Gate_N(n). Time t01 to time t07 is within the refresh frame; time t08 and time t09 are within two hold frames, respectively. In other words, the driving method provided by the embodiments of the present disclosure may include: a refresh frame and two hold frames, which are sequentially executed in each frame period.

[0147] It can also be seen that in the hold frame, only the effective potential signal can be provided to the light-emitting control terminal EM(n) and the second reset terminal Reset_H(n), that is, only the fourth transistor T4 to the seventh transistor T7 are selected to be turned on. The target refresh frequency can be 120 Hz. In addition, the second reset terminal Reset_H(n) can adopt a 3-pulse design, which is mainly based on high-precision frequency conversion. That is, as shown in the timing of Figures 4 to 7, a frame can be divided into a refresh frame and two hold frames described in the above embodiment. Assuming that the length of a frame is 8.33 milliseconds (ms), the length of each frame in a refresh frame and two hold frames can be 2.78ms. On this basis, the second reset terminal Reset_H(n) under 3 pulses is 360Hz. In this way, higher-precision frequency conversion can be achieved by increasing the number of hold frames in each frame period.

[0148] For example, referring to Figure 8, with 360Hz as the benchmark, the 3pulse design of the timing shown in Figures 4 to 7 may include: one refresh frame and two hold frames, thereby achieving a refresh frequency of 120Hz. Similarly, when including one refresh frame and three hold frames, that is, adding one hold frame, a refresh frequency of 90Hz can be achieved; when including one refresh frame and four hold frames, that is, adding two hold frames, a refresh frequency of 72Hz can be achieved; when including one refresh frame and five hold frames, that is, adding three hold frames, a refresh frequency of 60Hz can be achieved. The rest is similar and will not be repeated one by one. It can be seen from this that the driving method provided in the embodiment of the present disclosure can achieve the purpose of frequency conversion.

[0149] Alternatively, in some other embodiments, the second reset terminal Reset_H(n) may be designed as a 2-pulse or 4-pulse device. Alternatively, during the hold frame, the second reset signal with a valid potential may not be provided to the second reset terminal Reset_H(n). Alternatively, during the hold frame, the first reset signal with a valid potential may be provided to the first reset terminal Reset_P(n) to turn on the third transistor T3.

[0150] Based on the different timing designs shown in FIG. 4 to FIG. 7 , the following Table 2 shows the corresponding temperature drift improvement data.

[0151] Table 2

[0152] In Table 2, "Item" refers to the timing solution; "Ave.ΔL" refers to the average brightness change before and after temperature changes; and "90nitL16Flicker" refers to the flicker parameter when displaying a 16-grayscale image at 90nit brightness, expressed in decibels (dB). Comparing Tables 1 and 2, it can be seen that improving the timing can reduce brightness differences with temperature changes and simultaneously improve flickering.

[0153] Optionally, Figures 9 to 11 also respectively show the comparison data of the x color coordinate, the comparison data of the y color coordinate, and the comparison data of the brightness L under different grayscales when displaying a 2nit brightness picture, after the temperature is increased from normal temperature 25°C to 50°C in the timing sequence shown in Figure 4 and the related technology. Among them, the horizontal axis refers to the grayscale; the vertical axis refers to the change amplitude, specifically the decrease amplitude / %. With reference to Figures 9 to 11, it can be seen that after adopting the timing provided by the embodiment of the present disclosure, the decrease amplitude can be reduced, that is, the difference before and after the temperature rises is smaller, which can make the display effect better. It should be noted that the embodiment of the present disclosure can improve the brightness of the first frame of the display screen.

[0154] Since the driving method can have basically the same implementation manner and technical effects as the pixel circuit described in the previous embodiment, for the purpose of brevity, the implementation manner and technical effects of the driving method will not be repeatedly described here.

[0155] Fig. 12 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As shown in Fig. 12, the display panel includes: a substrate 10 and a plurality of pixels P1 located on the substrate.

[0156] 1 , the pixel P1 may include: a light emitting element L1 and a pixel circuit. The pixel circuit is coupled to the light emitting element L1 and is used to drive the light emitting element L1 to emit light.

[0157] Optionally, in the embodiment of the present disclosure, the display panel may further include: a plurality of groups of array substrate row driving (gate driver on array, GOA) circuits corresponding one to one to the first gate control terminal Gate_N(n), the second gate control terminal Gate_P(n), the first reset terminal Reset_P(n), the second reset terminal Reset_H(n) and the light emitting control terminal EM(n) coupled to the pixel circuit.

[0158] Each set of GOA circuits can be coupled to the start signal terminal STV, the clock signal terminal CK / CB, and the corresponding signal terminal, and is configured to transmit a signal to the corresponding signal terminal according to the driving method described in the above embodiment based on the start signal provided by the start signal terminal and the clock signal provided by the clock signal terminal. That is, the output signal satisfies the timing sequence shown in any one of Figures 4 to 7.

[0159] For example, referring to the signal timing diagram of the GOA circuit corresponding to the first gate control terminal provided in Figure 13, it can be seen that the GOA circuit corresponding to the first gate control terminal Gate_N(n) can be coupled to the start signal terminal NSTV and the clock signal terminal NCK / NCB respectively, and can be coupled to the first gate control terminal Gate_N(n) through the output terminal Nout to output a signal as shown in any one of Figures 4 to 7 to the first gate control terminal Gate_N(n).

[0160] Referring to the signal timing diagram of the GOA circuit corresponding to the second gate control terminal provided in Figure 14, it can be seen that the GOA circuit corresponding to the second gate control terminal Gate_P(n) can be coupled to the start signal terminal GSTV and the clock signal terminal GCK / GCB respectively, and can be coupled to the second gate control terminal Gate_P(n) through the output terminal Gout to output any signal shown in Figures 4 to 7 to the second gate control terminal Gate_P(n).

[0161] Referring to the signal timing diagram of the GOA circuit corresponding to the first reset terminal provided in Figure 15, it can be seen that the GOA circuit corresponding to the first reset terminal Reset_P(n) can be coupled to the start signal terminal PSTV and the clock signal terminal PCK / PCB respectively, and can be coupled to the first reset terminal Reset_P(n) through the output terminal Pout to output a signal as shown in any one of Figures 4 to 7 to the first reset terminal Reset_P(n).

[0162] Referring to the signal timing diagram of the GOA circuit corresponding to the second reset terminal provided in Figure 16, it can be seen that the GOA circuit corresponding to the second reset terminal Reset_H(n) can be coupled to the start signal terminal HSTV and the clock signal terminal HCK / HCB respectively, and can be coupled to the second reset terminal Reset_H(n) through the output terminal Hout to output a signal as shown in any one of Figures 4 to 7 to the second reset terminal Reset_H(n).

[0163] Referring to the signal timing diagram of the GOA circuit corresponding to the light-emitting control terminal provided in Figure 17, it can be seen that the GOA circuit corresponding to the light-emitting control terminal EM(n) can be coupled to the start signal terminal ESTV and the clock signal terminal ECK / ECB respectively, and can be coupled to the light-emitting control terminal EM(n) through the output terminal Eout to output any signal shown in Figures 4 to 7 to the light-emitting control terminal EM(n).

[0164] Moreover, taking the timing shown in FIG4 as an example, combined with FIG13 , it can be seen that in order to provide the first gate control terminal Gate_N(n) with a valid potential (i.e., a high potential) and an invalid potential (i.e., a low potential) of the first gate control signal in two cycles, in the refresh frame, the start signal terminal NSTV coupled to the corresponding GOA circuit can output a high potential start signal twice.

[0165] Similarly, in combination with Figure 14, it can be seen that in the refresh frame, the low-voltage start signal output by the start signal terminal GSTV coupled to the GOA circuit corresponding to the second gate control terminal Gate_P(n) can cover the low voltage of the clock signal provided by the 1-row clock signal terminal GCK, so that a second gate control signal with a valid voltage (i.e., a low voltage) is output to the second gate control terminal Gate_P(n) through the output terminal GOUT.

[0166] In combination with Figure 15, it can be seen that in the refresh frame, the start signal terminal PSTV coupled to the GOA circuit corresponding to the first reset terminal Reset_P(n) can output a low-voltage start signal twice, so that the first reset signal with a valid potential (i.e., a low potential) is output twice to the first reset terminal Reset_P through the output terminal Pout.

[0167] In conjunction with Figure 16, it can be seen that in the refresh frame, the start signal terminal HSTV coupled to the GOA circuit corresponding to the second reset terminal Reset_H(n) can output a low-voltage start signal twice, so that the second reset signal with a valid voltage (i.e., a low voltage) is output twice to the second reset terminal Reset_H(n) through the output terminal Hout.

[0168] In addition, it can be seen from Figure 17 that in the refresh frame, the start signal terminal ESTV coupled to the GOA circuit corresponding to the light-emitting control terminal EM(n) can output a high-voltage start signal once, so that an invalid potential (i.e., high potential) light-emitting control signal is output to the light-emitting control terminal EM(n) through the output terminal Eout.

[0169] Here, the GOA circuit is mostly disposed on the substrate 10 included in the display panel and is a part of the display panel. Of course, in some other embodiments, the GOA circuit can also be independent of the display panel.

[0170] Since the display panel can have basically the same implementation manner and technical effects as the pixel circuit and its driving method described in the previous embodiment, for the purpose of brevity, the implementation manner and technical effects of the display panel will not be repeated here.

[0171] FIG18 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG18 , the display device includes: a power supply component J1 and a display panel 100 as shown in FIG12 .

[0172] The power supply component J1 is coupled to the display panel 100 and is used to supply power to the display panel 100 .

[0173] Optionally, the display device may be an OLED display device or an active-matrix organic light-emitting diode (AMOLED) display device, etc. OLED display technology has been widely recognized by the market due to its advantages such as high resolution and high contrast.

[0174] Optionally, the display device may also include: any product or component with a display function, such as a mobile phone, a tablet computer, a flexible display device, a television, and a monitor.

[0175] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0176] It should be understood that the terms used in the examples of this disclosure are only used to explain the examples and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this disclosure should have the same ordinary meaning as those understood by persons of ordinary skill in the art to which this disclosure belongs.

[0177] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0178] When we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may be present. In addition, "connected" or "coupled" as used herein may include wireless connection or wireless coupling.

[0179] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0180] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0181] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0182] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A pixel circuit for driving a light-emitting element to emit light in a multi-frame period at a target refresh frequency, each frame period including a refresh frame and at least one hold frame ； The pixel circuit includes: A first control circuit, respectively coupled to a first gate control terminal, a second gate control terminal, a data terminal, a first node, a second node, and a third node, and configured to control the connection and disconnection between the first node and the third node in response to a first gate control signal provided by the first gate control terminal, and control the connection and disconnection between the data terminal and the second node in response to a second gate control signal provided by the second gate control terminal; A second control circuit, respectively coupled to a first reset terminal, a second reset terminal, a first initial terminal, a second initial terminal, a third initial terminal, the second node, the third node, and a fourth node, and configured to control the connection and disconnection between the first initial terminal and the third node in response to a first reset signal provided by the first reset terminal, control the connection and disconnection between the second initial terminal and the fourth node in response to a second reset signal provided by the second reset terminal, and control the connection and disconnection between the third initial terminal and the second node; A third control circuit, respectively coupled to a light-emitting control terminal, a driving power terminal, the second node, the third node, and the fourth node, and configured to control the connection and disconnection between the driving power terminal and the second node in response to a light-emitting control signal provided by the light-emitting control terminal, and control the connection and disconnection between the third node and the fourth node, the fourth node being coupled to the light-emitting element; A driving circuit, respectively coupled to the first node, the second node, and the third node, and configured to transmit a driving signal to the third node based on the potentials of the first node and the second node; Wherein, in the refresh frame, the first initial terminal and the third initial terminal are sequentially controlled to be conducted with the first node and the second node respectively, so that the first initial terminal and the third initial terminal sequentially transmit a first initial signal and a third initial signal to the first node and the second node respectively, and the potential difference between the transmitted first initial signal and the third initial signal is greater than or equal to a potential difference threshold.

2. The pixel circuit according to claim 1, Wherein, The potential difference threshold is -9V.

3. The pixel circuit according to claim 1 or 2, Wherein, The first control circuit includes: a first transistor and a second transistor; the second control circuit includes: a third transistor, a fourth transistor, and a fifth transistor; the third control circuit includes: a sixth transistor and a seventh transistor; the driving circuit includes: an eighth transistor; Wherein, the gate of the first transistor is coupled to the first gate control terminal, the first pole of the first transistor is coupled to the third node, and the second pole of the first transistor is coupled to the first node; The gate of the second transistor is coupled to the second gate control terminal, the first pole of the second transistor is coupled to the data terminal, and the second pole of the second transistor is coupled to the second node; The gate of the third transistor is coupled to the first reset terminal, the first pole of the third transistor is coupled to the first initial terminal, and the second pole of the third transistor is coupled to the third node; The gate of the fourth transistor is coupled to the second reset terminal, the first pole of the fourth transistor is coupled to the second initial terminal, and the second pole of the fourth transistor is coupled to the fourth node; The gate of the fifth transistor is coupled to the second reset terminal, the first pole of the fifth transistor is coupled to the third initial terminal, and the second pole of the fifth transistor is coupled to the second node; The gate of the sixth transistor is coupled to the light emission control terminal, the first pole of the sixth transistor is coupled to the driving power supply terminal, and the second pole of the sixth transistor is coupled to the second node; The gate of the seventh transistor is coupled to the light emission control terminal, the first pole of the seventh transistor is coupled to the third node, and the second pole of the seventh transistor is coupled to the fourth node; The gate of the eighth transistor is coupled to the first node, the first pole of the eighth transistor is coupled to the second node, and the second pole of the eighth transistor is coupled to the third node; The pixel circuit further includes: a storage capacitor connected in series between the driving power supply terminal and the first node.

4. The pixel circuit according to claim 3, wherein, the first transistor is an N-type transistor; the second transistor to the eighth transistor are all P-type transistors; and, the material of the N-type transistor includes an oxide material; the material of the P-type transistor includes a low-temperature polycrystalline silicon material.

5. A driving method for a pixel circuit, used to drive the pixel circuit according to any one of claims 1 to 4; the method includes: successively executing a refresh frame and at least one holding frame in each frame period of a multi-frame period with a target refresh frequency; in the refresh frame: successively providing a light emission control signal with an effective potential and an ineffective potential to the light emission control terminal; successively providing a first gate control signal with an effective potential and an ineffective potential to the first gate control terminal within at least one period, and the first gate control signal with the effective potential is located within the time duration when the light emission control signal is at the ineffective potential; within the time duration when the first gate control signal is at the effective potential, successively providing a first reset signal with an effective potential and a second gate control signal with an effective potential to the first reset terminal and the second gate control terminal, and providing a second reset signal with an ineffective potential to the second reset terminal; within the time duration when the first gate control signal is at the ineffective potential, respectively providing a first reset signal with an ineffective potential and a second gate control signal with an ineffective potential to the first reset terminal and the second gate control terminal, and providing a second reset signal with an effective potential to the second reset terminal; in the holding frame: successively providing a light emission control signal with an effective potential and an ineffective potential to the light emission control terminal; wherein, for any one of the light emission control signal, the first gate control signal, the second gate control signal, the first reset signal, and the second reset signal, the signal with the effective potential is used to control the conduction of each part coupled thereto; the signal with the ineffective potential is used to control the disconnection of each part coupled thereto.

6. The method according to claim 5, Among them, the first gate control signal that sequentially provides an effective potential and an ineffective potential to the first gate control terminal within at least one period includes: a first gate control signal that sequentially provides an effective potential and an ineffective potential to the first gate control terminal within two periods; the second gate control signal that provides an effective potential to the second gate control terminal during the duration when the first gate control signal is at the effective potential includes: a second gate control signal that provides an effective potential to the second gate control terminal during the second period of the two periods and during the duration when the first gate control signal is at the effective potential; the method further includes: in the refresh frame, before the first period of the two periods, a light emission control signal with an ineffective potential is provided to the light emission control terminal, a first gate control signal with an ineffective potential is provided to the first gate control terminal, a first reset signal with an ineffective potential is provided to the first reset terminal, a second gate control signal with an ineffective potential is provided to the second gate control terminal, and a second reset signal with an ineffective potential is provided to the second reset terminal.

7. The method according to claim 6, wherein, the duration when the first reset signal is at the effective potential in the second period is greater than or equal to the duration when the first reset signal is at the effective potential in the second period.

8. The method according to claim 6, wherein, the overlapping duration between the first gate control signal with an ineffective potential and the second reset signal with an effective potential in the first period is less than or equal to the overlapping duration between the first gate control signal with an ineffective potential and the second reset signal with an effective potential in the second period.

9. The method according to claim 5, wherein, the first gate control signal that sequentially provides an effective potential and an ineffective potential to the first gate control terminal within at least one period includes: a first gate control signal that sequentially provides an effective potential and an ineffective potential to the first gate control terminal within one period; the method further includes: in the refresh frame, before the one period, a light emission control signal with an ineffective potential is provided to the light emission control terminal, a first gate control signal with an ineffective potential is provided to the first gate control terminal, a first reset signal with an ineffective potential is provided to the first reset terminal, a second gate control signal with an ineffective potential is provided to the second gate control terminal, and a second reset signal with an effective potential is provided to the second reset terminal; and, the duration when the second reset signal is at the effective potential before the one period is greater than the duration when the second reset signal is at the effective potential during the one period.

10. The method according to claim 9, wherein, the duration when the second reset signal is at the effective potential before the one period is equal to the duration when the first gate control signal is at the effective potential during the one period.

11. The method according to any one of claims 5 to 10, wherein, the method further includes: in the hold frame, a first gate control signal with an ineffective potential is provided to the first gate control terminal, a first reset signal with an ineffective potential is provided to the first reset terminal, a second gate control signal with an ineffective potential is provided to the second gate control terminal, a second reset signal that sequentially provides an effective potential and an ineffective potential is provided to the second reset terminal within at least one period, and the second reset signal with an effective potential is located within the duration when the light emission control signal is at the ineffective potential.

12. The method according to any one of claims 5 to 11, wherein, the target refresh rate includes: 120 Hz; the method includes: a refresh frame and two hold frames sequentially executed in each frame period.

13. A display panel, the display panel comprising: a substrate, and a plurality of pixels located on the substrate; wherein, the pixel includes: a light-emitting element, and a pixel circuit according to any one of claims 1 to 4; the pixel circuit is coupled to the light-emitting element and is configured to drive the light-emitting element to emit light.

14. The display panel according to claim 13, wherein, the display panel further includes: a plurality of groups of array substrate row driving GOA circuits corresponding to a first gate control terminal, a second gate control terminal, a first reset terminal, a second reset terminal, and a light-emitting control terminal coupled to the pixel circuit one by one; wherein, each group of GOA circuits is respectively coupled to an enable signal terminal, a clock signal terminal, and a corresponding signal terminal, and is configured to transmit signals to the corresponding signal terminal according to the driving method according to any one of claims 6 to 12 based on the enable signal provided by the enable signal terminal and the clock signal provided by the clock signal terminal.

15. A display device, the display device comprising: a power supply component, and a display panel according to claim 13 or 14; wherein, the power supply component is coupled to the display panel and is configured to supply power to the display panel.

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