Clock gating device and method, chip, computer equipment and storage medium

Abstract

The invention relates to a clock gating device and method, a chip, computer equipment and a storage medium. The device comprises a voltage monitoring module which is configured to output a clock frequency regulation and control signal based on the internal voltage of a monitored unit; the clock frequency regulation and control signal is used for indicating a clock frequency regulation and control strategy; and the clock gating module is configured to respond to a clock gating enable signal, determine the on-off state of the clock signal of the monitored unit, and gradually adjust the frequency of the clock signal to the frequency indicated by the on-off state based on the clock frequency regulation and control strategy. The method can reduce the power consumption of the chip.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a clock gating device, method, chip, computer device, and storage medium. Background Technology

[0002] With the rise and widespread adoption of technologies such as large AI models, higher demands are being placed on the performance indicators of single chips, including computing power, storage, and on-chip and off-chip communication. However, as we enter the deep submicron era, Moore's Law is gradually slowing down, and the power consumption reduction brought about by process advancements is far from enough to offset the power consumption overhead brought about by performance increases. Power optimization from the front-end design has become a consensus. Clock gating technology, as one of the mainstream low-power design methods, can effectively reduce unnecessary power consumption overhead in clock networks and is widely used in chip design.

[0003] In current clock gating technologies, the clock gating signal is simply controlled based on clock demand. A clock signal is output directly when needed and turned off when not. This method causes a significant instantaneous change in the clock network load when the clock signal is turned on or off, resulting in substantial current fluctuations in the power supply. To cope with these current fluctuations, a higher voltage than the normal operating voltage needs to be supplied to the chip, leading to increased chip power consumption. Summary of the Invention

[0004] Therefore, it is necessary to provide a clock gating device, method, chip, computer device, and storage medium to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a clock gating device. The device includes:

[0006] The voltage monitoring module is configured to output a clock frequency control signal based on the voltage inside the monitored unit; the clock frequency control signal is used to indicate the clock frequency control strategy.

[0007] The clock gating module is configured to, in response to a clock gating enable signal, determine the on / off state of the clock signal of the monitored unit, and, based on the clock frequency control strategy, gradually adjust the frequency of the clock signal to the frequency indicated by the on / off state.

[0008] In one embodiment, the clock gating module is further configured to gradually adjust the frequency of the clock signal to the input clock frequency according to the clock frequency control strategy when the switch is in the on state, or to gradually adjust the frequency of the clock signal to 0 according to the clock frequency control strategy when the switch is in the off state.

[0009] In one embodiment, the voltage monitoring module includes one or more, and the voltage monitoring module is disposed on a target path in the monitored unit. The target path satisfies at least one of the following: the voltage drop is greater than a preset voltage threshold, the current is greater than a preset current threshold, and the load of the logic unit connected to the target path is greater than a preset load threshold.

[0010] In one embodiment, each of the voltage monitoring modules and the clock gating module are sequentially connected via a dedicated bus, and the voltage monitoring module includes a management unit;

[0011] The management unit, connected to the dedicated bus, is configured to determine a first clock frequency control strategy based on the voltage inside the monitored unit.

[0012] The management unit is further configured to receive a clock frequency control signal output by the first module, compare the second clock frequency control strategy indicated by the clock frequency control signal with the first clock frequency control strategy, determine a target clock frequency control strategy based on the comparison result, and output a clock frequency control signal indicating the target clock frequency control strategy to the second module; wherein, the first module is the module arranged on the dedicated bus before the voltage monitoring module where the management unit is located, and the second module is the module arranged on the dedicated bus after the voltage monitoring module where the management unit is located.

[0013] In one embodiment, the voltage monitoring module further includes a counting unit, which includes a counter and an oscillation loop;

[0014] The counter is configured to record the number of oscillations of the oscillating ring within a preset time period;

[0015] The management unit is also configured to determine the voltage based on the number of oscillations, and to determine the clock frequency control strategy based on the voltage.

[0016] In one embodiment, the counting unit includes at least two units, and the oscillation frequency of the oscillation ring is affected by temperature to different degrees in different counting units.

[0017] In one embodiment, the clock gating module includes a clock divider unit and a control unit;

[0018] The control unit is configured to, in response to a clock gating enable signal, determine the number of adjustment cycles based on the clock frequency control strategy, and determine the output clock frequency corresponding to each adjustment cycle; wherein, the adjustment cycle is the period required to gradually adjust the frequency of the clock signal to the frequency indicated by the switch state.

[0019] The control unit is further configured to calculate the division ratio based on the output clock frequency, and send the division ratio corresponding to the adjustment period to the clock division unit at the beginning of each adjustment period;

[0020] The clock division unit is configured to divide the input clock signal based on the division ratio in each adjustment period and output the divided input clock signal to the monitored unit.

[0021] In one embodiment, the clock gating module further includes a counting unit;

[0022] The counting unit is configured to count based on a fixed-frequency clock signal and send a trigger signal to the control unit when the count reaches a preset value;

[0023] The control unit is further configured to send the division ratio corresponding to the adjustment period to the clock division unit when the trigger signal is received.

[0024] Secondly, this application also provides a clock gating method. The method includes:

[0025] Based on the voltage inside the monitored unit, determine the clock frequency control strategy;

[0026] In response to the clock gating enable signal, the on / off state of the clock signal of the monitored unit is determined, and based on the clock frequency control strategy, the frequency of the clock signal is gradually adjusted to the frequency indicated by the on / off state.

[0027] In one embodiment, the step of gradually adjusting the frequency of the clock signal to the frequency indicated by the switch state based on the clock frequency control strategy includes:

[0028] When the switch is in the ON state, the frequency of the clock signal is gradually adjusted to the input clock frequency according to the clock frequency control strategy; or when the switch is in the OFF state, the frequency of the clock signal is gradually adjusted to 0 according to the clock frequency control strategy.

[0029] In one embodiment, determining the clock frequency modulation strategy based on the voltage inside the monitored unit includes:

[0030] Based on the voltage at different locations within the monitored unit, a first clock frequency control strategy is determined for each of the locations.

[0031] The clock frequency control strategies at each of the aforementioned locations are compared, and the clock frequency control strategy is determined based on the comparison results.

[0032] In one embodiment, the step of gradually adjusting the frequency of the clock signal to the frequency indicated by the switch state based on the clock frequency control strategy further includes:

[0033] The number of adjustment periods is determined based on the clock frequency control strategy, and the output clock frequency corresponding to each adjustment period is determined; wherein, the adjustment period is the period required to gradually adjust the frequency of the clock signal to the frequency indicated by the switch state.

[0034] The division ratio is calculated based on the output clock frequency, and the input clock signal is divided based on the division ratio in each adjustment period.

[0035] Thirdly, this application also provides a chip that includes a clock gating device as described in any of the foregoing embodiments.

[0036] Fourthly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement any of the methods described above.

[0037] Fifthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements any of the above methods.

[0038] Sixthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements any of the above methods.

[0039] The aforementioned clock gating device, method, chip, computer equipment, and storage medium, based on the voltage-generated clock frequency control strategy within the monitored unit, gradually adjust the frequency of the monitored unit's clock signal to the required frequency according to the clock frequency control strategy when it is necessary to turn the clock on or off. This allows the frequency change of the clock signal to match the power supply voltage of the monitored unit, avoiding large fluctuations in the monitored unit's current caused by instantaneous large changes in the clock network load. Therefore, it can reduce the requirements for the power supply voltage of the power supply network, thereby reducing chip power consumption. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of a clock network in one embodiment;

[0041] Figure 2 This is a schematic diagram of clock gating in one embodiment;

[0042] Figure 3 This is a schematic diagram illustrating the voltage relationships between the various power supply networks of a chip in one embodiment;

[0043] Figure 4 This is a schematic diagram of a clock gating device in one embodiment;

[0044] Figure 5 This is a schematic diagram of a clock gating device in another embodiment;

[0045] Figure 6 This is a schematic diagram of a voltage monitoring module in one embodiment;

[0046] Figure 7 This is a schematic diagram of a clock gating module in one embodiment;

[0047] Figure 8 This is a schematic diagram illustrating the adjustment of the output clock frequency in one embodiment;

[0048] Figure 9 This is a flowchart illustrating a clock gating method in one embodiment;

[0049] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] It should be noted that the terms "first," "second," etc., used in this application may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more.

[0052] To facilitate understanding, the technical background involved in this application will be explained first. For example... Figure 1 As shown, a clock network typically transmits data unidirectionally from a root node (clock source) to leaf nodes (flip-flop clock pins), and the network structure is usually a tree structure or a mesh structure. The clock signal flips twice in each clock cycle, so the entire clock network flips rapidly with the clock source.

[0053] To prevent invalid flips in the clock network, clock gating devices can be added to the clock network, such as... Figure 2 As shown, clock gating devices can determine whether to propagate clock signals backward based on the enable signal. By properly controlling the enable signal, invalid flips in the clock network can be significantly reduced, thereby saving power consumption in the clock network.

[0054] However, in related technologies, clock gating devices typically control the clock gating signal simply based on clock demand. When a clock signal is needed, it outputs the clock directly; when not, it shuts it off. This control method causes a sudden and significant change in the clock network load when the clock signal is turned on or off, resulting in large current fluctuations in the power supply and consequently, a dynamic voltage drop.

[0055] like Figure 3 As shown, the power supply chip provides power to the various devices on the chip, requiring it to pass through the motherboard power supply network, the substrate power supply network, and the chip's power supply network. Due to the influence of the resistance, capacitance, and inductance of each stage of the power supply network, each stage causes a drop in supply voltage and power consumption, resulting in issues such as… Figure 3 The diagram shows the power chip output voltage 1 > motherboard power supply network output voltage 2 > substrate power supply network output voltage 3 > chip power supply network output voltage 4.

[0056] The chip power supply network output voltage 4 represents the supply voltage that the device can obtain. To ensure the device functions properly, the chip power supply network output voltage 4 must be greater than or equal to the device's minimum operating voltage. Considering the dynamic voltage drop caused by the clock gating switch, the chip power supply network output voltage 4 needs to be even higher, which further necessitates increasing the power chip output voltage 1, leading to increased chip power consumption.

[0057] To address at least one technical problem existing in related technologies, this application provides a clock gating device. See also... Figure 4 The diagram shown is a schematic of the clock gating device provided in this application. The clock gating device includes a voltage monitoring module and a clock gating module. The voltage monitoring module is configured to output a clock frequency adjustment signal based on the voltage inside the monitored unit; the clock frequency adjustment signal is used to indicate a clock frequency adjustment strategy. The clock gating module is configured to, in response to a clock gating enable signal, determine the on / off state of the clock signal of the monitored unit, and, based on the clock frequency adjustment strategy, gradually adjust the frequency of the clock signal to the frequency indicated by the on / off state.

[0058] Those skilled in the art can set multiple monitored units on the chip according to actual needs. For example, a clock domain can be set as a monitored unit, an area in the chip with a high clock frequency and therefore a large dynamic voltage drop when switching clock signals can be set as a monitored unit, a design unit can be set as a monitored unit, etc. The embodiments of this application do not limit this.

[0059] The voltage monitoring module needs to be connected to a path capable of sensing the voltage inside the monitored unit. Due to the influence of the resistance, capacitance, and inductance of the power supply network to the monitored unit, the voltage received by each component inside the monitored unit may differ. Therefore, multiple voltage monitoring modules can be installed, each placed on a path where different voltages may occur.

[0060] In one embodiment, the voltage monitoring module is positioned on a target path within the monitored unit. The target path satisfies at least one of the following: voltage drop greater than a preset voltage threshold, current greater than a preset current threshold, or the load of the logic unit connected to the target path greater than a preset load threshold. The voltage drop and current along the path can be obtained through pre-silicon simulation or post-silicon testing. The load of the logic unit can be determined based on the unit type (e.g., logic units within a processor or field-programmable gate array are considered high-load logic units), the maximum power consumption of the logic unit, or the required input current. The preset voltage threshold, preset current threshold, and preset load threshold can all be set according to the needs of those skilled in the art.

[0061] The clock gating module is connected to the voltage monitoring module and the input path of the clock gating enable signal. It needs to be connected to the output of the clock source input to the monitored unit so that the clock gating module can control the switching of the clock signal on and off in the monitored unit. If the monitored unit has multiple clock sources, the clock gating module can be configured with multiple sources accordingly.

[0062] The voltage monitoring module can employ any design capable of detecting the internal voltage of the chip. For example, it can use a voltage divider resistor to detect the voltage, or a ring oscillator to detect the voltage. The voltage monitoring module can be used to detect specific voltage values, or it can simply be used to detect the approximate difference between the current voltage and a certain reference voltage. If the latter approach is adopted, the reference voltage can be set to a voltage that allows all components within the monitored unit to operate normally.

[0063] The voltage monitoring module outputs a clock frequency control signal based on the voltage it detects. This clock frequency control signal indicates the clock frequency control strategy. The clock frequency control strategy may include at least one of the following: the adjustment frequency of the clock signal frequency, the number of adjustments to the clock signal frequency, and the adjustment interval of the clock signal frequency. Those skilled in the art can also set other clock frequency control strategies according to actual needs, and this application embodiment does not specifically limit them.

[0064] The adjustment frequency refers to the upper limit of the clock signal frequency change per unit time. The unit time can be set to 1 millisecond, a fixed number of fixed-frequency clock cycles, or any value set according to actual needs. For example, if the clock signal needs to be activated and the required frequency is 1 GHz, and the adjustment frequency is 100 MHz / ms, then the clock gating module will adjust the clock signal frequency to 100 MHz in the 1st millisecond, to 200 MHz in the 2nd millisecond, and so on, until it adjusts the clock signal frequency to 1 GHz in the 10th millisecond.

[0065] The number of adjustments refers to the number of times the clock signal frequency needs to be adjusted to the required frequency. For example, if the clock signal needs to be turned on and the required frequency is 1GHz, and the number of adjustments is 2, then the clock gating module will adjust the clock signal frequency to 500MHz the first time it adjusts the clock signal frequency, and adjust the clock signal frequency to 1GHz the second time it adjusts the clock signal frequency.

[0066] The adjustment interval refers to the time interval between two adjustments to the frequency of the clock signal. For example, if the clock signal needs to be turned on and the required frequency is 1GHz, the number of adjustments is 2, and the adjustment interval is 1ms, then the clock gating module will adjust the frequency of the clock signal to 500MHz in the first millisecond and adjust the frequency of the clock signal to 1GHz in the second millisecond.

[0067] The correspondence between different voltages and different clock frequency control strategies can be set by those skilled in the art according to actual needs. Generally speaking, the lower the voltage, the smaller the load on the clock network caused by the selected clock frequency control strategy, in order to avoid situations where excessive instantaneous load causes some devices to receive voltages lower than their normal operating voltage. The voltage monitoring module can internally set registers to store the correspondence between different voltages and different clock frequency control strategies. After acquiring the voltage inside the monitored unit, the voltage monitoring module outputs the corresponding clock frequency control strategy through a clock frequency control signal.

[0068] The voltage monitoring module can continuously monitor the voltage and output a clock frequency adjustment signal. Alternatively, the clock gating module can output a trigger signal to the voltage monitoring module when the clock gating enable signal changes (i.e., when the switching state of the clock signal needs to be changed), causing the voltage monitoring module to output a clock frequency adjustment signal in response to the trigger signal. Alternatively, other upstream logic units or management units can simultaneously send clock gating enable signals to the voltage monitoring module, so that the voltage monitoring module outputs a clock frequency adjustment signal when the state of the clock gating enable signal changes. This application does not specifically limit this approach.

[0069] When the clock gating enable signal transitions, the clock gating module determines the on / off state of the clock signal currently indicated by the clock gating enable signal. If the clock gating enable signal is currently valid (valid can be 1 or 0, and similarly invalid can be 0 or 1, depending on the chip design), the clock gating module needs to enable the clock signal. If the clock gating enable signal is currently invalid, the clock gating module needs to disable the clock signal.

[0070] The clock gating module further follows the clock frequency control strategy to gradually turn the clock signal on or off to the required frequency indicated by the switch state.

[0071] In one embodiment, when the switch is on, the clock gating module gradually adjusts the frequency of the clock signal to the input clock frequency according to the clock frequency control strategy; or when the switch is off, it gradually adjusts the frequency of the clock signal to 0 according to the clock frequency control strategy.

[0072] In another embodiment, the frequency of the on state indicator can be set by those skilled in the art according to actual needs, for example, it can be the input clock frequency, N times the input clock frequency, or a fraction of N times the input clock frequency. The frequency of the off state indicator can also be set according to actual needs, generally to 0, but can also be set to a lower value. In this case, registers can be set inside the clock gating module to store the frequencies of the on and off state indicators separately.

[0073] The clock gating device provided in this application embodiment is based on the voltage-generated clock frequency adjustment strategy inside the monitored unit. When it is necessary to turn the clock on or off, the frequency of the clock signal of the monitored unit is gradually adjusted to the required frequency according to the clock frequency adjustment strategy. Therefore, the frequency change of the clock signal can be matched with the power supply voltage of the monitored unit, avoiding the situation where the current of the monitored unit fluctuates greatly due to the instantaneous large change of the clock network load. Thus, the requirements of the power supply network voltage can be reduced, thereby reducing the chip power consumption.

[0074] When multiple voltage monitoring modules are set up, the voltages monitored by different modules may differ, and therefore the output clock frequency control strategies may also differ. However, the clock gating module can only adjust the clock frequency according to one clock frequency control strategy.

[0075] In order to determine the clock frequency control strategy that a clock gating module should ultimately execute under such circumstances, the voltage monitoring module can compare its own clock frequency control strategy with the clock frequency control strategy generated by another voltage monitoring module, and select the better one to output to the next voltage monitoring module. The clock frequency control strategy output by the last voltage monitoring module to the clock gating module is the final clock frequency control strategy.

[0076] In one embodiment, see Figure 5 As shown, each voltage monitoring module and clock gating module is connected sequentially via a dedicated bus, and the voltage monitoring module includes a management unit;

[0077] The management unit is connected to a dedicated bus and is configured to determine a first clock frequency regulation strategy based on the voltage inside the monitored unit.

[0078] The management unit is also configured to receive the clock frequency control signal output by the first module, compare the second clock frequency control strategy indicated by the clock frequency control signal with the first clock frequency control strategy, determine the target clock frequency control strategy based on the comparison result, and output a clock frequency control signal indicating the target clock frequency control strategy to the second module; wherein, the first module is a module arranged on the dedicated bus before the voltage monitoring module where the management unit is located, and the second module is a module arranged on the dedicated bus after the voltage monitoring module where the management unit is located.

[0079] In this embodiment, each voltage monitoring module is sequentially connected in series on a dedicated bus, and the clock gating module is connected to the end of the dedicated bus, located after each voltage monitoring module.

[0080] A management unit is set up in the voltage monitoring module. The management unit can determine the clock frequency control strategy according to the method in the aforementioned embodiments. The clock frequency control strategy determined by the management unit is called the first clock frequency control strategy. The management unit also receives the clock frequency control signal output by the module located one position before its own voltage monitoring module from the dedicated bus. The clock frequency control strategy indicated by the clock frequency control signal is called the second clock frequency control strategy.

[0081] The management unit then compares the first clock frequency control strategy with the second clock frequency control strategy to determine which is superior. "Superior" means causing less change in the clock network load. Taking the aforementioned clock frequency control strategies, including the adjustment frequency, the number of adjustments, and the adjustment interval of the clock signal frequency, as an example, a superior clock frequency control strategy could refer to a strategy with a lower adjustment frequency, more adjustments, or a longer adjustment interval.

[0082] The management unit selects a better clock frequency control strategy as the target clock frequency control strategy to be output, and sends a clock frequency control signal indicating the target clock frequency control strategy to the next module on the dedicated bus.

[0083] If the next module is a voltage monitoring module, the management unit in the next module will use the target clock frequency control strategy as the second clock frequency control strategy, perform the aforementioned process of comparing the first clock frequency control strategy and the second clock frequency control strategy, and output the better target clock frequency control strategy.

[0084] If the next module is a clock gating module, then the clock gating module will gradually adjust the frequency of the clock signal to the frequency indicated by the switch state based on the target clock frequency control strategy.

[0085] The clock gating device provided in this application provides a method for setting multiple voltage monitoring modules. When multiple voltage monitoring modules are set, the voltage monitoring module compares its own clock frequency control strategy with the clock frequency control strategy generated by another voltage monitoring module, and selects the better one to output to the next voltage monitoring module. The clock frequency control strategy output by the last voltage monitoring module to the clock gating module is the final clock frequency control strategy. This allows the clock gating module to select the optimal one from the clock frequency control strategies output by multiple voltage monitoring modules for execution.

[0086] In one embodiment, the voltage monitoring module further includes a counting unit, which includes a counter and an oscillation ring;

[0087] The counter is configured to record the number of oscillations of the oscillating loop within a preset time period;

[0088] The management unit is also configured to determine the voltage based on the number of oscillations, and to determine the clock frequency control strategy based on the voltage.

[0089] In this embodiment, the oscillation loop consists of a set of delay devices, and its oscillation frequency is affected by the voltage. Therefore, the oscillation loop can be used to estimate the voltage inside the monitored unit.

[0090] The voltage monitoring module internally includes a counter, which is connected to an oscillation loop and a management module. The counter records the number of oscillations of the oscillation loop within one clock cycle indicated by a fixed-frequency clock signal and outputs this number to the management module. The relationship between the counter's output value and the voltage can be obtained through pre-silicon simulation or post-silicon testing, and this relationship is converted into a counter-voltmeter and stored in the voltage monitoring module's register.

[0091] After receiving the number of oscillations, the management module can query the voltage inside the monitored unit based on the counter-voltmeter, and further determine the clock frequency control strategy based on the relationship between the voltage recorded in the register and the clock frequency control strategy.

[0092] Since the oscillation frequency of the oscillating ring is affected not only by voltage but also by temperature, multiple counting units can be set up to further improve the accuracy of voltage measurement. In one embodiment, the counting units include at least two, and the degree to which the oscillation frequency of the oscillating ring is affected by temperature varies in different counting units.

[0093] See Figure 6 As shown, each voltage monitoring module contains at least two oscillation rings. The delay of the two delay devices in the same oscillation ring changes with temperature at the same rate, while the delay of the delay devices in different oscillation rings changes with temperature at different rates, so that the oscillation frequency of the oscillation rings in different counting units is affected by temperature to different degrees.

[0094] By using pre-silicon simulation or post-silicon testing, the output values ​​of the counters in each counting unit at different voltages and temperatures can be obtained. Based on these values, a formula for calculating the voltage in each counting unit, using the counter's output value and temperature, can be derived. Furthermore, by combining the formulas corresponding to different counting units, elimination can be performed to obtain a formula for calculating the voltage based on the output values ​​of each counter. This formula is then converted into a counter-voltmeter and stored in the register of the voltage monitoring module.

[0095] After receiving the number of oscillations output by different counting units, the management module can query the voltage inside the monitored unit based on the counter-voltmeter, and further determine the clock frequency control strategy based on the relationship between the voltage recorded in the register and the clock frequency control strategy.

[0096] The clock gating device provided in this application embodiment sets up multiple oscillation rings with different oscillation frequencies affected by temperature. By calculating the voltage through the oscillation counts of different oscillation rings, the influence of temperature on voltage calculation can be reduced, thereby improving the accuracy of the clock frequency control strategy.

[0097] In one embodiment, the clock gating module includes a clock divider unit and a control unit;

[0098] The control unit is configured to, in response to a clock gating enable signal, determine the number of adjustment cycles based on a clock frequency control strategy, and determine the output clock frequency corresponding to each adjustment cycle; wherein, the adjustment cycle is the period required to gradually adjust the frequency of the clock signal to the frequency indicated by the switch state.

[0099] The control unit is also configured to calculate the division ratio based on the output clock frequency and send the division ratio corresponding to the adjustment period to the clock division unit at the beginning of each adjustment period.

[0100] The clock divider unit is configured to divide the input clock signal based on the division ratio in each adjustment cycle and output the divided input clock signal to the monitored unit.

[0101] In the embodiments of this application, such as Figure 7 As shown, the clock gating unit includes a control unit and a clock divider unit. The control unit is connected to the voltage monitoring module or the dedicated bus as described in the previous embodiments. The clock divider unit is connected to the input clock source and the clock network of the monitored unit. The clock divider unit can employ any design capable of dividing the input clock signal, such as a digital divider circuit or an analog divider circuit.

[0102] After receiving the clock frequency control strategy, the control unit calculates the adjustment period required to adjust the clock signal frequency according to the strategy, and also calculates the frequency of the clock signal output by the clock gating module to the clock network of the monitored unit in each adjustment period. For example, if the clock signal needs to be turned off, the input clock frequency is 1GHz, and the adjustment frequency of the clock signal indicated by the clock frequency control strategy is 500MHz / ms, then the required adjustment period is 2, and the frequencies of the clock signals output by the clock gating module to the clock network of the monitored unit in each adjustment period are 500MHz and 1GHz, respectively.

[0103] The control unit then calculates the division ratio for each adjustment cycle based on the ratio of the input clock frequency to the output clock frequency. Since the output clock frequency in this embodiment is always less than or equal to the input clock frequency, the output clock signal is always obtained by dividing the input clock signal. For example, in the aforementioned example, the division ratios calculated for each adjustment cycle are 2 and 1 (1 being no division). It should be noted that the division ratio here can be either an integer or a non-integer division.

[0104] The control unit can calculate the adjustment period based on the input clock signal or other fixed-frequency clock signals. At the beginning of each adjustment period, the control unit sends the frequency division ratio corresponding to the period to the clock frequency division unit. The clock frequency division unit divides the input clock signal according to the frequency division ratio and outputs the divided signal as the output clock signal to the clock network of the monitored unit.

[0105] In one embodiment, see Figure 7 As shown, the clock gating module also includes a counting unit;

[0106] The counting unit is configured to count based on a fixed-frequency clock signal and send a trigger signal to the control unit when the count reaches a preset value.

[0107] The control unit is also configured to send the division ratio corresponding to the adjustment period to the clock division unit when a trigger signal is received.

[0108] In this embodiment, a counting unit is provided in the clock gating module. The counting unit is connected to a fixed-frequency clock source and counts based on the fixed-frequency clock signal. When the count reaches a preset value, it is considered that an adjustment cycle has elapsed, and the counting unit can send a trigger signal to the control unit. After receiving the trigger signal, the control unit considers the adjustment cycle to have started and sends the frequency division ratio corresponding to the adjustment cycle to the clock frequency division unit.

[0109] If the length of the adjustment period is fixed, the preset value can be pre-configured. For example, if the length of the adjustment period is fixed at 1ms, the count value of the counting unit in 1ms can be determined through pre-silicon simulation or post-silicon testing, and this value can be used as the preset value. If the length of the adjustment period is indicated by the clock frequency control strategy, a relationship table between the preset value and the length of the adjustment period can be stored in the control unit, and the control unit can send the corresponding preset value to the counting unit after receiving the clock frequency control strategy.

[0110] See Figure 8 The diagram shows the change in the output clock frequency of the clock gating unit during the clock shutdown and clock startup processes. The corresponding configuration is as follows: the adjustment period is 1ms, the input clock frequency is 1GHz, and the frequency change rate of the output clock signal does not exceed 500MHz / ms.

[0111] In the clock shutdown process, at time 0ms, the output clock frequency is clock frequency 1, which is equal to the input clock frequency of 1GHz. At time 1ms, the output clock frequency drops to clock frequency 2, which is 500MHz. At time 2ms, the output clock frequency drops to clock frequency 3, which is 250MHz. At time 3ms, the clock is turned off.

[0112] During the clock startup process, the clock signal is off at time 0ms. At time 1ms, the output clock frequency is increased to clock frequency 3, which is 250MHz. At time 2ms, the output clock frequency is increased to clock frequency 2, which is 500MHz. At time 3ms, the output clock frequency is increased to clock frequency 1, which is 1GHz, which is the expected input clock frequency.

[0113] In one embodiment, such as Figure 9 As shown, a clock gating method is provided. This embodiment describes the application of this method to the clock gating device of any of the foregoing embodiments, including the following steps:

[0114] Step 902: Determine the clock frequency control strategy based on the voltage inside the monitored unit;

[0115] Step 904: In response to the clock gating enable signal, determine the on / off state of the clock signal of the monitored unit, and gradually adjust the frequency of the clock signal to the frequency indicated by the on / off state based on the clock frequency adjustment strategy.

[0116] In one embodiment, the step of gradually adjusting the frequency of the clock signal to the frequency indicated by the switch state based on the clock frequency adjustment strategy includes:

[0117] When the switch is in the ON state, the frequency of the clock signal is gradually adjusted to the input clock frequency according to the clock frequency control strategy; or when the switch is in the OFF state, the frequency of the clock signal is gradually adjusted to 0 according to the clock frequency control strategy.

[0118] In one embodiment, determining the clock frequency regulation strategy based on the voltage inside the monitored unit includes:

[0119] Based on the voltage at different locations within the monitored unit, a first clock frequency control strategy is determined for each of the locations.

[0120] The clock frequency control strategies at each of the aforementioned locations are compared, and the clock frequency control strategy is determined based on the comparison results.

[0121] In one embodiment, based on the clock frequency adjustment strategy, gradually adjusting the frequency of the clock signal to the frequency indicated by the switch state further includes:

[0122] The number of adjustment periods is determined based on the clock frequency control strategy, and the output clock frequency corresponding to each adjustment period is determined; wherein, the adjustment period is the period required to gradually adjust the frequency of the clock signal to the frequency indicated by the switch state.

[0123] The division ratio is calculated based on the output clock frequency, and the input clock signal is divided based on the division ratio in each adjustment period.

[0124] The execution method of the above steps can be found in the relevant description of the clock gating device in the foregoing embodiments, and will not be repeated here.

[0125] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0126] In one embodiment, a chip is provided that includes a clock gating device as described in any of the foregoing embodiments, wherein a voltage monitoring module in the clock gating device is connected to the chip's power supply network, and the clock gating module is connected to the chip's clock network.

[0127] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 10 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a clock gating method.

[0128] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0129] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0130] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0131] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0132] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0133] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0134] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A clock gating device, characterized by The device comprises: a voltage monitoring module configured to output a clock frequency regulation signal based on the voltage inside the monitored unit; the clock frequency regulation signal is used to indicate a clock frequency regulation strategy; a clock gating module configured to determine the on-off state of the clock signal of the monitored unit in response to a clock gating enable signal, and gradually adjust the frequency of the clock signal to the frequency indicated by the on-off state based on the clock frequency regulation strategy.

2. The apparatus of claim 1, wherein, The clock gating module is further configured to gradually adjust the frequency of the clock signal to the input clock frequency according to the clock frequency regulation strategy when the on-off state is on, or gradually adjust the frequency of the clock signal to 0 according to the clock frequency regulation strategy when the on-off state is off.

3. The apparatus of claim 1, wherein, The voltage monitoring module comprises one or more, and the voltage monitoring module is arranged on a target path in the monitored unit, and the target path satisfies at least one of the following conditions: the voltage drop is greater than a preset voltage threshold, the current is greater than a preset current threshold, and the load of a logic unit connected to the target path is greater than a preset load threshold.

4. The apparatus of claim 2, wherein, Each of the voltage monitoring module and the clock gating module is sequentially connected through a dedicated bus, and the voltage monitoring module comprises a management unit; The management unit is connected with the dedicated bus and is configured to determine a first clock frequency regulation strategy based on the voltage inside the monitored unit; The management unit is further configured to receive a clock frequency regulation signal output by a first module, compare a second clock frequency regulation strategy indicated by the clock frequency regulation signal with the first clock frequency regulation strategy, determine a target clock frequency regulation strategy based on the comparison result, and output a clock frequency regulation signal indicating the target clock frequency regulation strategy to a second module; wherein the first module is a module arranged in front of the voltage monitoring module where the management unit is located on the dedicated bus, and the second module is a module arranged behind the voltage monitoring module where the management unit is located on the dedicated bus.

5. The apparatus of claim 4, wherein, The voltage monitoring module further comprises a counting unit, and the counting unit comprises a counter and an oscillation ring; The counter is configured to record the number of oscillations of the oscillation ring within a preset time length; The management unit is further configured to determine the voltage based on the number of oscillations, and determine the clock frequency regulation strategy according to the voltage.

6. The apparatus of claim 5, wherein, The counting unit comprises at least two, and the degree to which the oscillation frequency of the oscillation ring is affected by temperature is different in different counting units.

7. The apparatus of claim 1, wherein, The clock gating module comprises a clock frequency division unit and a control unit; The control unit is configured to determine the number of adjustment periods based on the clock frequency regulation strategy and determine the output clock frequency corresponding to each adjustment period in response to a clock gating enable signal; wherein the adjustment period is the period required for gradually adjusting the frequency of the clock signal to the frequency indicated by the on-off state. The control unit is further configured to calculate a frequency division ratio according to the output clock frequency, and send the frequency division ratio corresponding to the adjustment period to the clock frequency division unit at the beginning of each adjustment period. The clock frequency division unit is configured to divide the input clock signal based on the frequency division ratio in each adjustment period, and output the divided input clock signal to the monitored unit.

8. The apparatus of claim 7, wherein, The clock gating module further comprises a counting unit. The counting unit is configured to count based on a constant frequency clock signal, and send a trigger signal to the control unit when the count reaches a preset value. The control unit is further configured to send the frequency division ratio corresponding to the adjustment period to the clock frequency division unit when the trigger signal is received.

9. A clock gating method, comprising: The method comprises: determining a clock frequency regulation strategy based on the voltage inside the monitored unit; in response to a clock gating enable signal, determining the switching state of the clock signal of the monitored unit, and gradually adjusting the frequency of the clock signal to the frequency indicated by the switching state based on the clock frequency regulation strategy.

10. The method of claim 9, wherein, The gradually adjusting the frequency of the clock signal to the frequency indicated by the switching state based on the clock frequency regulation strategy comprises: when the switching state is on, gradually adjusting the frequency of the clock signal to the input clock frequency according to the clock frequency regulation strategy, or when the switching state is off, gradually adjusting the frequency of the clock signal to 0 according to the clock frequency regulation strategy.

11. The method of claim 9, wherein, The determining a clock frequency regulation strategy based on the voltage inside the monitored unit comprises: determining a first clock frequency regulation strategy for each position based on the voltage at different positions inside the monitored unit; comparing the clock frequency regulation strategies for each position, and determining the clock frequency regulation strategy based on the comparison result.

12. The method of claim 9, wherein, The gradually adjusting the frequency of the clock signal to the frequency indicated by the switching state based on the clock frequency regulation strategy further comprises: determining the number of adjustment periods based on the clock frequency regulation strategy, and determining the output clock frequency corresponding to each adjustment period; wherein the adjustment period is the period required to gradually adjust the frequency of the clock signal to the frequency indicated by the switching state; calculating a frequency division ratio according to the output clock frequency, and dividing the input clock signal based on the frequency division ratio in each adjustment period.

13. A chip, characterized by The clock gating device comprises any one of claims 1-8.

14. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to realize the steps of the method of claims 9-12.

15. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize the steps of the method of claims 9-12.

16. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to realize the steps of the method of claims 9-12.

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