Nonvolatile multi-bit ferroelectric memory cell, ferroelectric memory, reading circuit and writing method

Abstract

The invention discloses a read-write method and circuit of a multi-bit ferroelectric storage unit based on multistability. The read circuit of the special ferroelectric memory comprises a bit line, a plate line, a word line and a read amplifier chain, the sense amplifier chain comprises at least two stages of cascade structures which are used for distinguishing high-order data and low-order data respectively; the first-stage sense amplifier is used for judging a high-order logic state, and the second-stage sense amplifier is used for judging a low-order logic state in a capacitive coupling mode (or charging and discharging duration). According to the writing method of the ferroelectric storage unit, writing of four polarization states is achieved by controlling the polarity, the amplitude and the time sequence of writing pulses; the states' 00 'and' 11 'are written in through a single saturated polarization pulse; the states' 01 'and' 10 'are written in through two polarization pulses, including writing in a saturation state and then applying part of depolarization pulses to form a metastable state. The amplitude of the partially depolarized pulses is 1 / 2 of the amplitude of the saturated pulses, and the polarities of the partially depolarized pulses are opposite.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of microelectronic devices and novel storage material, in particular to a non-volatile multi-bit ferroelectric storage unit, a non-volatile multi-bit dynamic random ferroelectric memory, and a reading circuit and a writing method thereof. BACKGROUND

[0002] High bandwidth HBM dynamic random access memory is the focus of current storage technology development. However, limited by the current mainstream 1T1C storage unit structure, the storage density is still the bottleneck restricting the further development of DRAM. At the same time, data transfer and dynamic refresh operation to compensate for capacitor leakage account for more than 80% of the total energy consumption of current computing systems. Therefore, improving data density and reducing storage power consumption is of great significance to improve the overall computing energy efficiency of the system.

[0003] Ferroelectric memory (FeRAM) as a non-volatile storage technology has the advantages of high speed reading and writing, low operating voltage, high integration and low power consumption, and is considered as one of the effective technical paths to realize non-volatile dynamic random ferroelectric memory (NVDRAM). Compared with traditional capacitors, ferroelectric capacitors are more likely to realize multiple stable metastable states, thereby supporting reliable multi-bit storage, which helps to significantly improve storage density and has broad development prospects in AI computing applications. However, the key technologies for multi-bit NVDRAM storage units, especially the read-write logic timing and read-write circuit design, are still under research. SUMMARY

[0004] One aspect of the present disclosure is a non-volatile multi-bit ferroelectric storage unit, comprising:

[0005] a first electrode, a second electrode, and a ferroelectric layer sandwiched between the first electrode and the second electrode;

[0006] The ferroelectric layer is a hafnium-zirconium-oxygen solid solution film, and ferroelectric O-phase and anti-ferroelectric T-phase exist simultaneously in the same film layer. The O-phase and the T-phase have a coercive field difference of flip-flop in sequence under an applied electric field, so that the ferroelectric layer presents four stable and distinguishable remanent polarization states under zero external electric field, for directly representing at least two bits of data.

[0007] The four remanent polarization states are non-volatilely maintained by the interface charge pinning effect of the O-phase, without the need for refresh operation. The polarization state can be non-volatilely maintained under zero external electric field; and the ferroelectric layer material is a hafnium-zirconium-oxygen solid solution.

[0008] One aspect of the present disclosure is a multi-bit writing method of the storage unit, comprising:

[0009] Two opposite saturated polarization states are directly written by a single saturated polarization pulse to correspond to "00" and "11" logic states;

[0010] Two metastable polarization states are formed by a two-step pulse sequence of "first saturated polarization and then applied reverse partial depolarization pulse" to selectively partially flip T-phase while keeping O-phase pinned to correspond to "01" and "10" logic states;

[0011] The amplitude of the partial depolarization pulse is 1 / 2 of the saturated pulse amplitude and the polarity is opposite, thereby completing four-state writing in the same ferroelectric capacitor.

[0012] One aspect of the present disclosure, a multi-bit ferroelectric memory reading circuit compatible with DRAM process, for performing four-state reading and automatic write-back on the array, comprising:

[0013] Bit line, plate line, word line and at least two levels of readout amplifier chain;

[0014] The first level readout amplifier is used to directly distinguish high bit according to polarity;

[0015] The second level readout amplifier introduces offset voltage or offset charge controlled by the first level output through capacitive coupling or charge and discharge time window method to distinguish between metastable state and saturated state, thereby distinguishing low bit;

[0016] The offset is set to 1 / 6 to 1 / 3 of the saturated state voltage difference to ensure four-state reading window separation;

[0017] The circuit automatically writes back to the storage unit according to the original discrimination result after completing the reading, realizing non-destructive reading.

[0018] Among them, the readout amplifier chain includes at least two levels of cascade structure for distinguishing high and low data respectively; the first level readout amplifier is used to judge high bit logic state, and the second level readout amplifier judges low bit logic state through capacitive coupling method;

[0019] The word line, bit line and plate line timing of the memory is fully compatible with the existing DRAM specification, and the four-state data can be non-volatile without refresh operation, thereby realizing at least twice the storage density of traditional DRAM on the same chip area.

[0020] One aspect of the present disclosure, a non-volatile dynamic random ferroelectric memory, comprising:

[0021] The array composed of the storage units;

[0022] The reading circuit is used for multi-bit data reading of the storage units in the array;

[0023] The read timing of the memory is compatible with existing DRAM technology, supports synchronous control of word lines, bit lines, and board lines, and has a planar or three-dimensional integrated structure compatible with DRAM process.

[0024] Therefore, this disclosure proposes a read / write method and circuit for a multi-bit ferroelectric memory cell based on multistable states. The read circuit of this ferroelectric memory includes bit lines, board lines, word lines, and a read amplifier chain; the read amplifier chain includes at least two cascaded stages for distinguishing high-order and low-order data respectively; the first-stage read amplifier is used to determine the high-order logic state, and the second-stage read amplifier determines the low-order logic state through capacitive coupling (or charge / discharge duration). The write method of this ferroelectric memory cell achieves the writing of four polarization states by controlling the polarity, amplitude, and timing of the write pulse; states "00" and "11" are written using a single saturation polarization pulse; states "01" and "10" are written using two polarization pulses, including first writing a saturation state and then applying a partial depolarization pulse to form a metastable state. The amplitude of the partial depolarization pulse is half the amplitude of the saturation pulse, and the polarity is opposite. Therefore, the present disclosure of a high-density, low-power non-volatile dynamic random access memory and its implementation scheme solves the problems of storage density bottleneck, high refresh energy consumption and data volatility caused by the "1T1C" structure of DRAM in the prior art. Attached Figure Description

[0025] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein:

[0026] Figure 1 A schematic structural diagram of a ferroelectric storage capacitor according to one embodiment of the present invention.

[0027] Figure 2 A schematic diagram of the current stable polarization multistate according to one embodiment of the present invention.

[0028] Figure 3 A schematic diagram of the steady-state and metastable polarization retention mechanism according to one embodiment of the present invention.

[0029] Figure 4 A schematic diagram of a DRAM-compatible multi-bit read / write circuit and read / write process according to one embodiment of the present invention.

[0030] Figure 5 An example of a multi-bit read / write result according to one embodiment of the present invention.

[0031] Figure 6 A schematic diagram of another multi-bit determination method according to one embodiment of the present invention.

[0032] Figure 7 A schematic diagram of the pulse duration required for a charge / discharge determination method according to one embodiment of the present invention.

[0033] Figure 8 yes Figure 4 middle Figure 4 The circuit diagram for c.

[0034] Wherein, 1 is the first electrode, 2 is the second electrode, and 3 is the multi-state ferroelectric layer. Detailed Implementation

[0035] Ferroelectric capacitor (FeRAM) memory solutions utilize ferroelectric thin films to replace the dielectric material in traditional DRAM and employ crystal phase modulation techniques to achieve multiple stable states (such as "00", "01", "10", and "11") based on different polarization directions and intensities of the ferroelectric material. By extending the storage states from the traditional two-state to multi-state, FeRAM can simultaneously combine the high-speed read / write performance of DRAM with the high storage density advantages of NAND Flash.

[0036] Currently, multi-state ferroelectric memory capacitors have been widely validated in numerous studies, but related explorations are still mainly focused on the memory capacitor cell level, and complete functional memory integration has not yet been achieved. Due to the insufficient stability of multi-state memory cells under actual operating conditions, coupled with the immature design of peripheral circuits to match multi-bit read / write operations, fully integrated ferroelectric dynamic random access memory capable of stably achieving multi-bit read / write functionality remains a technological gap. Therefore, optimizing the crystal phase and grain of ferroelectric thin films to construct multiple controllable metastable states is the technological foundation for realizing non-volatile multi-bit memory. On the other hand, developing peripheral read / write circuits compatible with existing DRAM processes is key to fabricating high-density non-volatile dynamic random access memory (NVDRAM) based on ferroelectric devices and promoting its commercial application.

[0037] According to one or more embodiments, such as Figure 1As shown, the ferroelectric storage device provided in this application embodiment includes a sandwich structure formed by a first electrode 1, a multi-state ferroelectric layer 3, and a second electrode 2, with the multi-state ferroelectric layer 3 sandwiched between the first electrode 1 and the second electrode 2. This sandwich structure can take several forms. One form is where the first electrode is a flat cylinder, the multi-state ferroelectric layer is a fan-shaped ring cylinder that semi-encloses the flat cylinder of the first electrode, and the second electrode is a fan-shaped ring cylinder that semi-encloses the fan-shaped ring cylinder of the multi-state ferroelectric layer, thus forming a quasi-cylindrical structure. Another form is where the first electrode, as a cylinder, is surrounded by the ring cylinder of the multi-state ferroelectric layer, and the ferroelectric layer is surrounded by the ring cylinder of the second electrode, thus forming a quasi-cylindrical structure. Yet another form is where the first electrode, the ferroelectric layer, and the second electrode are stacked sequentially to form a hamburger-like sandwich structure. From the perspective of the materials used, this can be a metal electrode-ferroelectric thin film-metal electrode (MFM) structure, but is not limited to this. In some embodiments, the first electrode 1 and the second electrode 2 may also be made of materials other than metals, such as metal oxide semiconductors. In the ferroelectric device of this disclosure, the first electrode 1 and the second electrode 2 are two electrodes arranged opposite each other, referring to the materials used to introduce the electric field and to which the ferroelectric layer is attached. This disclosure does not limit the shape of the electrodes.

[0038] Furthermore, in this embodiment, the ferroelectric material of the ferroelectric layer is a solid solution of hafnium oxide (HfO2) and zirconium oxide (ZrO2) doped with single or multiple elements, thereby ensuring the compatibility and scalability of ferroelectric devices with CMOS processes. This disclosure provides an in-depth analysis of the technical problems and mechanisms of hafnium oxide-based ferroelectric materials in multi-state memory applications. Although multi-state memory plays a positive role in reducing memory power consumption and improving integration density, existing hafnium oxide-based ferroelectric materials still face a series of reliability challenges caused by physical mechanisms in practical applications. Specifically, when an electric field exceeding the coercive field is applied, the remanent polarization intensity of this type of material increases approximately linearly with the increase of the electric field. This characteristic can theoretically be used to realize continuous multi-state polarization memory. However, during the preparation of the bottom electrode and subsequent annealing processes, the metal electrode can extract oxygen from the ferroelectric film, triggering an "oxygen extraction" effect, thereby forming oxygen vacancies at the metal-ferroelectric layer interface. These oxygen vacancies generate a built-in electric field, pinning some ferroelectric dipoles in the initial stage and even causing opposite polarization directions. Because oxygen vacancies are unstable and mobile under the influence of an electric field, and also play a role in stabilizing the ferroelectric phase, as they gradually diffuse and migrate to the bulk phase of the ferroelectric thin film, they can induce some non-ferroelectric phases to transform into ferroelectric phases, thereby further increasing the remanent polarization. However, with the increase in the number of electric field cycles, the ferroelectric thin film continuously loses oxygen, and the electrode interfaces are continuously oxidized, leading to the formation of more defects and oxygen vacancies. These defect interfaces divide the applied external electric field, reducing the actual electric field experienced by the ferroelectric layer. Simultaneously, the charges trapped by defects and the migrating vacancies continue to pin the ferroelectric dipoles, hindering their flipping, ultimately leading to a decrease in remanent polarization, i.e., "fatigue." Therefore, if multi-state storage relies solely on linear incomplete polarization behavior, the aforementioned mechanism will cause multi-state logic ambiguity during cycling, severely affecting the device's data retention capability and read / write stability. Therefore, this disclosure subsequently proposes corresponding material and structural optimization solutions to address this issue.

[0039] This disclosure provides a ferroelectric device, such as... Figure 1 As shown, the crystal phase ratio is precisely controlled by adding one or more doping elements, superlattice stress modulation, and oxygen flux modulation to the non-fixed proportion hafnium zirconium oxide solid solution in the ferroelectric layer 3. After annealing, a microstructure with a uniform mixture of ferroelectric phase (O-phase) and antiferroelectric phase (T-phase) can be formed in the ferroelectric layer 3. The annealed and optimized ferroelectric layer 3 forms a uniformly mixed structure of O phase and T phase with a specific ratio. This composite phase structure exhibits electrical behavior different from the O-phase-dominated system during polarization reversal: its polarization response exhibits non-single peak characteristics, specifically manifested by multiple stable polarization current peaks appearing in the positive and negative polarization regions (see...). Figure 2a). This multi-peak characteristic provides a physical basis for achieving controllable multi-state storage. The stable multi-bit storage mechanism achieved by this structure is based on the cooperative polarization behavior of the O phase and T phase in the stack: such as Figure 2 As shown in Figure a, when the applied electric field reaches the coercive field of phase O, the first polarization current peak is induced, forming a half-polarized state with a low polarization voltage. As the electric field further increases to the coercive field of phase T, the second polarization current peak appears, at which point the ferroelectric layer 3 reaches the fully polarized state. By recording the half-polarized and fully polarized states in the positive and negative electric field directions respectively, four stable polarization states can be formed in the memory, thereby realizing the multi-bit (2-bit) storage function.

[0040] It is important to note that the difference in the magnitude of these two polarization electric fields is caused by the polarization electric field strength required by the O / T-phase itself. Therefore, the O / T-phase hybrid ferroelectric layer 3 will naturally split into two polarization states with different electric field phases. Those skilled in the art should understand that a single antiferroelectric material cannot maintain its polarization state after the applied electric field is removed; therefore, a simple antiferroelectric layer cannot be directly used for non-volatile storage.

[0041] like Figure 3 As shown in this embodiment, after the full polarization process is completed, the semi-polarized state generated by the O phase will form a charge pinning effect at the electrode interface. Even after the applied electric field is removed, this effect can still maintain a portion of the residual electric field generated by the polarization of the O phase inside the capacitor. When the intensity of this residual electric field exceeds the depolarization field of the T phase, the polarization charge formed in the full polarization state can be maintained under zero external electric field conditions, thereby realizing two stable storage states in the positive and negative polarization directions respectively.

[0042] Therefore, unlike the bimodal phenomenon caused by material defect pinning in traditional methods, the device described in this disclosure utilizes the inherent polarization differences between the O and T phases in the ferroelectric layer to achieve multi-state storage through the coordinated control of their polarization charges. This method is based on the intrinsic phase structure stability of the material, thereby enabling each polarization state to exhibit excellent operational reliability and state retention capability during long-term cyclic flipping.

[0043] On the other hand, electrode-induced stress effects have a significant impact on the phase composition ratio of the ferroelectric layer and the device durability. Therefore, the structural parameters of the ferroelectric layer 3 in this disclosure—including the phase ratios, film thickness, and stacking order—can be optimized according to the stress characteristics of the lower electrode material to achieve precise control of the phase composition and stable improvement of device performance. According to embodiments of this disclosure, even when the ferroelectric layer thickness is reduced to 5 nm, it can still maintain a high remanent polarization intensity and a low operating voltage, thus possessing the combined advantages of high integration and low power consumption. Simultaneously, the durability of this configuration can reach 1E11, approaching the durability specifications of current DRAMs. Furthermore, the device uniformity of this configuration meets the requirements of arrays.

[0044] According to the physical mechanism of polymorphic storage in embodiments of this disclosure, Figure 4 When performing multi-bit (2-bit) state operations, the 1T1C core memory cell selected in C must strictly follow the timing specifications and voltage conditions defined in Table 1 during its read and write processes. Specifically, state 1 (00) and state 4 (11) correspond to two saturation polarization states in opposite directions. When writing to these two states, only one saturation write pulse of the corresponding polarity needs to be applied, for example, by setting the bit line voltage VBL to VDD to write state "11", or by setting the board line voltage VPL to VDD to write state "00". On the other hand, state 2 (01) and state 3 (10) are two metastable states in opposite directions, and two polarization pulse operations are required when writing to these two states. Among them, writing "01" requires first setting the state to "00" and then by applying a saturation write pulse to the bit line voltage VBL to VDD. BL Apply 1 / 2V DD By removing the antiferroelectric polarization, a small amount of AFE-polarized charge can be obtained when a read pulse is applied to the PL line to read 0 or 1. Similarly, when writing "10", a V pulse needs to be applied to the BL line. DD Write "11" and then add 1 / 2 VDD to the PL line to remove part of the antiferroelectric polarization, so that when reading the "10" state on the PL line, only the charge of the reverse FE can be obtained.

[0045] Table 1. Write operation voltage and timing table for each memory state.

[0046]

[0047] According to one or more embodiments, in addition to the aforementioned steady-state multi-bit memory cell structure, this disclosure provides a read circuit compatible with existing DRAM processes. This circuit provides a hardware foundation for realizing a high-efficiency, high-density non-volatile memory computing architecture. For example... Figure 4As shown, the solution in this embodiment is effectively applicable to data reading in high-density three-dimensional storage structures. In the read path design, the peripheral circuit retains the read amplifier compatible with traditional DRAM, but to adapt to the multi-bit storage characteristics, an innovative two-stage (or higher) cascaded read amplifier structure is introduced, which is used for the discrimination and recovery of high-order and low-order data respectively.

[0048] In the data reading process, the read circuit of this embodiment applies a saturation polarization voltage pulse with an amplitude of VDD and a pulse width of tens of nanoseconds through the board line. This pulse width is determined by the saturation polarization response time of the ferroelectric device. When the pulse polarity is opposite to the current polarization state of the read cell, it induces a polarization reversal of the ferroelectric domains, resulting in a change in polarization charge on the ferroelectric capacitor related to the stored state. This charge change is coupled through a series capacitor and converted into a graded voltage signal corresponding to the stored logic state, thereby enabling the discrimination of multi-bit data.

[0049] In this embodiment, the logic state voltage signal generated by the multi-bit storage unit can be according to... Figure 4 The timing sequence of the read circuit shown in diagram d is followed, and the data is ultimately sent to the sense amplifier for logic state determination. Specifically, during the word line enable period, a read voltage pulse is applied to the board line, and simultaneously, switch SW is closed, guiding the node voltage representing the storage state to the subsequent multi-stage sense amplifier chain to complete the parallel or sequential determination of high and low bit data. For example... Figure 4 As shown in e, the data read operation in this embodiment includes four stages in sequence: pre-charge stage, polarization state read stage, logic state judgment stage, and data write-back stage. The specific judgment mechanism is as follows:

[0050] The high-order data is directly determined by the first-stage sense amplifier, which compares the logic state voltage with a set reference voltage. The low-order data is determined by the second-stage (sub-stage) sense amplifier. During this process, a coupling capacitor is used to create a cross-coupling structure between the preceding and following stage bit lines. The final state is determined by detecting the voltage difference at this coupling node. After cross-coupling, the input voltage of the second-stage sense amplifier will shift according to the output state of the preceding stage: if the preceding stage bit line output is logic "0", the voltage rises after coupling; if the output is logic "1", the voltage falls after coupling. This voltage adjustment is determined by the capacitance of the coupling capacitor and the voltage at the preceding node.

[0051] In this embodiment, the coupling adjustment voltage is set between 1 / 6 and 1 / 3 of the saturation voltage difference, i.e., ΔV. couple ∈ [1 / 6(V 11 - V 00 ), 1 / 3(V 11 - V 00This design ensures that the bit line output remains in the correct "11" or "00" state when reading from the saturated state; while when reading from the metastable state, the coupling effect can cause the low-order output to undergo a logic inversion, thereby achieving reliable differentiation and identification of the four memory states.

[0052] The actual measurement results of this embodiment are as follows: Figure 5 As shown, after the board line read pulse is applied and before the coupling enable signal takes effect, the bit line output states of the preceding and following stages remain consistent. When the coupling enable signal is effective, the bit line output corresponding to the metastable state undergoes the expected flip, while the saturated state output remains unchanged. This result is in complete agreement with the design expectation, verifying the feasibility and operational stability of this scheme in multi-state identification.

[0053] This embodiment features an automatic write-back function, triggered by the logic judgment circuit after completing data reading and status determination. The voltage conditions and timing specifications used in the write-back operation are consistent with the write timing defined in Table 1.

[0054] It should be noted that although the discrimination of low-order data in this embodiment is achieved using the capacitive coupling method described above, in practical applications, the technical path for implementing this function is not limited to this. Therefore, this disclosure also provides another low-order logic discrimination scheme based on the charging and discharging principle, which can be used as an alternative or optimized implementation method to achieve the same function. For example... Figure 6 As shown, this embodiment provides an alternative implementation of the capacitive coupling scheme, namely, replacing the coupling capacitor with a charge / discharge logic judgment circuit. In this circuit, the selector's control terminal is driven by the high-order output signal: when the high-order output is high, the selector connects the input terminal of the low-order readout amplifier to ground, performing a discharge operation; conversely, when the high-order output is low, the selector connects the input terminal to VDD, performing a charging operation. In this method, the duration of the charge / discharge process is a key parameter for low-order logic judgment, and its specific duration can be precisely set according to the RC charge / discharge curve. Figure 7 As shown, the charging operation time should be controlled within t. 00 To t 01 Between (t) ref (Based on t); correspondingly, the duration of the discharge operation should be between t and t. 11 To t 10 Between (t) ref (Based on).

[0055] It should be noted that, Figure 7The timing values ​​shown are merely illustrative examples illustrating the principle of this method. In actual circuit design, specific device parameters and operating times need to be adjusted and optimized according to the selected process node and device characteristics. Furthermore, the discrimination of polymorphic logic voltages can also be achieved by using an analog-to-digital converter to read the node voltage in real time and quantify its state. This approach can serve as an effective supplement and alternative to the aforementioned capacitive coupling and charge / discharge discrimination methods.

[0056] According to one or more embodiments, such as Figure 6 The circuit described includes a charge / discharge type low-order byte discrimination circuit, comprising a memory array, a high-order byte discrimination path (MSB), and a low-order byte discrimination path (LSB). The memory array includes a 1T1C cell, where the gate of transistor T1 is connected to the word line WL, the source is connected to the bit line BL, and the drain is connected to a ferroelectric capacitor C. fe The lower electrode is connected to the plate line PL. In the high-order discrimination path (MSB), the bit line BL is connected to the input switch SW1 and also to the differential input terminal of SA1. The output of SA1 is connected to the selector of the MSB node. The low-order discrimination path (LSB) SA2 is connected in parallel to the bit line BL and the complementary bit line BLB through switches SW1 and SW2 respectively. The read pulse control PL is driven by PL_DRV, generating a pulse with a VDD amplitude and a pulse width of tens of nanoseconds.

[0057] Figure 8 The circuit described is a two-stage cascaded sense amplifier chain, corresponding to Figure 4c. This circuit includes a memory cell 1T1C, a first-stage sense amplifier SA1 (MSB), and a second-stage sense amplifier SA2 (LSB). The gate of memory cell 1T1C is connected to WL, the source is connected to BL, and the drain is connected to C. fe The upper plate is connected to the PL line. The complementary bit line BLB forms a differential pair with BL through a dummy cell or a reference cell. The first-stage sense amplifier SA1 (MSB) is connected to the bit line BL and the switch S. wa and switch S wb The second-stage sense amplifier SA2 (LSB) is connected to the SA1 cross input terminal through capacitor Cc.

[0058] Through the above connections, the circuit in Figure 6 achieves LSB discrimination using "charge / discharge + selector", and the circuit in Figure 8 achieves the same function using "two-stage SA + capacitive coupling". Both are fully compatible with DRAM technology.

[0059] Therefore, for the multi-bit ferroelectric memory cell of this embodiment, a 2-bit writing method is adopted, wherein when "00 / 11" is written, a single saturation pulse (±V) is achieved. DDThe process involves writing "01 / 10" (with a width of approximately tens of ns), followed by writing the saturated state "00 / 11" and then applying a reverse ½VDD "partial depolarization" pulse to partially depolarize the T-phase, forming a metastable state. The read circuit for this multi-bit ferroelectric memory cell is suitable for 1T1C arrays, using the WL / BL / PL three-dimensional wiring of DRAM, and can be directly embedded in DRAM technology. The read circuit includes at least two cascaded sense amplifiers SA1 (MSB) + SA2 (LSB). The read pulse is a VDD pulse applied by PL with a width of tens of ns. Ferroelectric domain inversion charges are injected through BL, generating four voltage levels corresponding to the four states. After the read operation, the judgment result drives the write circuit to rewrite the original state back to the cell according to the timing in Table 1, realizing the NVDRAM function.

[0060] This disclosure proposes a ferroelectric memory architecture whose memory array is arranged in DRAM topology using the aforementioned 2-bit 1T1C cells, which can be planar or 3D stacked. The word lines, bit lines, and board line control signals in the peripheral timing are fully compatible with existing DRAM controllers. The dielectric layer is replaced with a mixed-phase HfZrO2 and loaded with a two-stage SA chain. In terms of density, it improves upon 1T1C DRAM by ≥2× (2 bits per cell) for the same area. Regarding power consumption, it eliminates refresh energy consumption, providing a high-bandwidth, low-power "non-volatile dynamic random access memory (NVDRAM)" for AI and HPC. The material can utilize 5 nm ultrathin HfZrO2 while maintaining high Pr, ensuring compatibility with CMOS back-ends. Furthermore, oxygen vacancy migration is suppressed through O / T phase ratio optimization, solving fatigue / imprinting issues. The same principle can be extended to 3-bit (8 states) or more by simply increasing the number of SA stages and coupling / quantization stages.

[0061] In summary, the improvements made to the prior art by this disclosure include at least the following:

[0062] (1) Improve the structure of the storage cell by using a ferroelectric thin film instead of the linear dielectric material in the traditional DRAM as the storage medium. By optimizing and controlling the crystal phase and grain of the ferroelectric thin film, multiple controllable and stable metastable states (such as polarization states corresponding to "00", "01", "10" and "11") are constructed, thereby realizing multi-bit data storage of a single storage cell and significantly improving storage density.

[0063] (2) A new peripheral read / write circuit compatible with existing DRAM manufacturing processes is provided. This circuit is designed for multi-bit operation and can accurately identify and write different metastable states of ferroelectric capacitors. It solves the stability and signal reading problems of multi-state cells in actual operation and realizes complete functional memory integration.

[0064] The beneficial effects of this disclosure lie in combining the high-speed read / write, low operating voltage, and non-volatile characteristics of ferroelectric memory with the high integration advantages of DRAM. The resulting non-volatile dynamic random access memory (NVDRAM) combines the high-speed performance of DRAM with the high-density characteristics of NAND Flash, while fundamentally eliminating refresh energy consumption, thus significantly improving the overall energy efficiency of computing systems. The NVDRAM of this disclosure is particularly suitable for fields such as artificial intelligence and high-performance computing, which have stringent requirements for memory bandwidth and energy efficiency, and has broad industrialization prospects.

[0065] It should be understood that in the embodiments of the present invention, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.

[0066] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0067] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A non-volatile multi-bit ferroelectric memory cell, characterized in that, Comprising: a first electrode, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode; wherein the ferroelectric layer comprises a crystal phase structure mixed with ferroelectric phase (O-phase) and anti-ferroelectric phase (T-phase), and the ferroelectric layer has at least four stable and distinguishable polarization states under the action of an applied electric field, for representing at least two bits of data; wherein the polarization states can be non-volatilely maintained under zero external electric field; the ferroelectric layer material is hafnium-zirconium-oxygen solid solution.

2. The memory cell of claim 1, wherein, the thickness of the ferroelectric layer is ≤5 nm, and the precise control of the O-phase and T-phase ratio is achieved by one or more of the following ways: doping elements, superlattice stress control, or oxygen flux control.

3. The memory cell of claim 1 or 2, wherein, The four polarization states correspond to data "00", "01", "10", and "11", respectively, wherein "00" and "11" are saturated polarization states, and "01" and "10" are metastable states.

4. A method of writing to a nonvolatile multi-bit ferroelectric memory cell, comprising: Comprising: for the memory cell as claimed in any one of claims 1 to 3, the writing of the four polarization states is achieved by controlling the polarity, amplitude and timing of the writing pulse; wherein the states "00" and "11" are written by a single saturated polarization pulse; the states "01" and "10" are written by two polarization pulses, including first writing a saturated state, and then applying a partial depolarization pulse to form a metastable state.

5. The write method of claim 4, wherein, The amplitude of the partial depolarization pulse is 1 / 2 of the amplitude of the saturated pulse, and the polarity is opposite.

6. A read circuit for a non-volatile multi-bit ferroelectric memory, characterized in that, Comprising: bit lines, plate lines, word lines, and a readout amplifier chain; wherein the readout amplifier chain comprises at least two levels of cascaded structure for respectively judging high-bit and low-bit data; wherein the first level readout amplifier is used to judge the high-bit logic state, and the second level readout amplifier judges the low-bit logic state by capacitive coupling; Wherein, the voltage offset ΔV introduced by the capacitive coupling couple Satisfies: ΔV couple ∈ [1 / 6(V 11 – V 00 ), 1 / 3(V 11 – V 00 )], where V 11 and V 00 are the read voltages corresponding to the states "11" and "00", respectively.

7. The read circuit of claim 6, wherein, further comprising an automatic write-back module for writing data back to the original memory cell according to the judgment result after reading is completed.

8. The read circuit according to claim 6 or 7, characterized in that, The input end of the second level readout amplifier is cross-coupled with the previous stage bit line through a coupling capacitor, to realize the logic inversion of the metastable state.

9. A non-volatile dynamic random ferroelectric memory, characterized by, Comprising: an array composed of a plurality of memory cells as claimed in any one of claims 1 to 3; the readout circuit as claimed in any one of claims 6 to 8, for performing multi-bit data reading on the memory cells in the array; wherein the memory supports non-volatile storage of at least four stable polarization states, and does not require refresh operation.

10. The memory of claim 9, wherein, The read timing of the memory is compatible with existing DRAM processes, supports the synchronous control of word lines, bit lines, and plate lines, and has a planar or three-dimensional integrated structure compatible with DRAM processes.

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