Dynamic performance collaborative optimization control method for multi-phase multi-level converter

Abstract

The invention provides a dynamic performance collaborative optimization control method for a multi-phase multi-level converter, the converter comprises a plurality of power phase units connected in parallel, each phase comprises at least one flying capacitor and a multi-level switch bridge arm, the output ends of the phases are jointly connected to an energy storage load, and the method is executed by a digital controller. The method comprises the following steps: S1, configuring each phase of PWM driving signal to have fixed phase deviation, and synchronizing the duty ratio updating operation of each phase to the reference moment of the corresponding carrier period of each phase; in a physical switching period, N times of independent duty ratio calculation and loading are executed according to a phase sequence in a time-sharing manner; a multi-phase parallel three-level topological structure is adopted, each phase of PWM carrier is subjected to uniform phase dislocation in a time domain, and each phase of modulation signal is updated in a single physical switching period in a time-sharing manner, so that the effective control frequency of a current loop is improved to integral multiples of the physical switching frequency, the output current ripple is remarkably suppressed, and the dynamic response capability is enhanced.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion control technology, and more specifically, to a dynamic performance collaborative optimization control method for multiphase multilevel converters. Background Technology

[0002] With the widespread application of high-voltage, high-power power electronic systems in new energy power generation, electric vehicles, rail transit, and industrial power supplies, higher requirements are placed on the power density, efficiency, and dynamic performance of converters. Against this backdrop, the combination of multiphase parallel technology and the flying capacitor (FC) three-level topology has become a research hotspot due to its unique advantages: on the one hand, multiphase phase-shifting control can significantly improve the system's equivalent switching frequency, effectively suppress output current ripple, and reduce the size of passive components; on the other hand, the flying capacitor three-level structure, by introducing a midpoint potential, can reduce the voltage stress on power devices under the same bus voltage, thereby improving system reliability and efficiency.

[0003] However, in practical engineering applications, this composite topology still faces two major dynamic performance challenges, which severely restrict its high-performance operation across the entire operating range: First, there is an inherent contradiction between dynamic response speed and sampling accuracy. To achieve ripple cancellation and equivalent switching frequency doubling, a multi-phase 120° phase-shift control strategy is typically employed, shortening the system control cycle to 1 / N of the original switching cycle (where N is the number of phases). However, high-precision current sampling devices (such as high-resolution ADCs) are limited by their conversion rate, making it difficult to match the high-frequency control requirements after frequency doubling. During dynamic processes such as load step changes and sudden input voltage fluctuations, sampling delays cause feedback information to lag, preventing the controller from adjusting the duty cycle in time. This leads to significant output voltage overshoot / drop or inductor current oscillations, weakening the theoretical frequency doubling advantage.

[0004] Secondly, significant nonlinear phenomena exist under low-current conditions. When operating under light load or within a specific duty cycle range, the natural equilibrium point of the flying capacitor voltage in a three-level topology may become unstable, or even experience polarity reversal. This nonlinear behavior alters the transfer function relationship between the duty cycle and the inductor current, leading to control model mismatch. Especially during current rise or switching phases, unexpected current "drops," oscillations, or response hysteresis are prone to occur, severely impacting the system's stability and current smoothness in low-load regions.

[0005] While traditional frequency multiplication control schemes can improve the equivalent switching frequency, they do not optimize the control loop bandwidth and sampling system in a coordinated manner, and neglect the need for real-time feedback during dynamic processes. Although the dynamic sampling switching strategy attempts to compromise between high speed and high precision, its switching logic relies on threshold judgment, which is prone to introducing additional disturbances. Furthermore, it does not take into account the nonlinear characteristics unique to flying capacitor topologies and is powerless to deal with abnormal phenomena under light load. While low-current control methods (such as burst mode or frequency conversion control) can improve efficiency under light loads, they often sacrifice dynamic response capabilities and lack active compensation methods for the voltage imbalance mechanism of flying capacitors.

[0006] Currently, existing technical solutions mostly focus on single-dimensional optimization and lack systematic and collaborative design solutions. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a dynamic performance collaborative optimization control method for multiphase multilevel converters that addresses the shortcomings of the above-mentioned technical solutions and solves the problem of the coexistence of high dynamic and light load conditions in flying capacitor three-level converters.

[0008] This invention provides a dynamic performance collaborative optimization control method for a multiphase multilevel converter. The converter includes multiple parallel power phase units, each phase containing at least one flying capacitor and a multilevel switching bridge arm. The output terminals of each phase are commonly connected to an energy storage load. The method is executed by a digital controller and includes the following steps: S1, configure each phase PWM drive signal to have a fixed phase offset, and synchronize the duty cycle update operation of each phase with the reference time of the corresponding carrier cycle; within a physical switching cycle, perform N independent duty cycle calculations and loadings in phase sequence, so that the effective update frequency of the control loop reaches N times the physical switching frequency, where N is the number of phases, thereby achieving an equivalent switching frequency multiplication, improving dynamic response capability and suppressing output current ripple; S2, dynamically switching control modes based on system operating status: In the dynamic adjustment phase, the coprocessor responds to high-frequency interrupts, reads the current sampling values ​​collected by the low-precision and high-speed analog-to-digital conversion channels, executes the closed-loop control algorithm, and updates the PWM duty cycle; in the steady-state operation phase, the main processor responds to low-frequency interrupts and performs closed-loop adjustment based on the current sampling values; wherein, the high-frequency interrupt and the low-frequency interrupt are synchronously generated by the same hardware timer source, and automatic linear calibration and manual linear calibration strategies are respectively adopted for the high-speed and low-speed analog-to-digital conversion channels to ensure that the feedback signal is continuous and without step jumps during the control mode switching process; S3. Monitor the output current of the energy storage load in real time. When the output current is lower than the preset light load threshold, activate the interphase circulating current compensation mechanism, generate a filtered asymmetric duty cycle compensation amount Δd, and inject the duty cycle command of each phase upper tube according to the distribution method that satisfies the conservation of the three-phase average duty cycle, so as to establish a controllable circulating current between phases, stabilize the polarity of the flying capacitor voltage, and suppress the current drop or oscillation caused by the inherent nonlinearity of the topology. When the output current recovers to the non-light load region, the compensation amount is automatically cleared.

[0009] In the dynamic performance collaborative optimization control method for multiphase multilevel converters described in this invention; in step S1, the number of phases N is 3, and the PWM drive signals of each phase are out of phase by 120°; within one physical switching cycle T, the current loop PI calculation and corresponding duty cycle loading are performed sequentially for phases A, B, and C, so that the control loop is updated three times in each physical switching cycle, making the update frequency of the control loop three times the physical switching frequency f, thus achieving equivalent triple frequency control.

[0010] In the dynamic performance collaborative optimization control method for multiphase multilevel converters described in this invention, in step S1, each phase multilevel switch bridge arm is a flying capacitor three-level structure, including four switching transistors and one flying capacitor; wherein, the drive signals of the upper and lower transistors in the same bridge arm are complementary and have a phase difference of 180°.

[0011] In the dynamic performance collaborative optimization control method for multiphase multilevel converters described in this invention, the frequency of the high-frequency interrupt in step S2 is 72 kHz, the frequency of the low-frequency interrupt is 24 kHz, the ratio of the two is 3:1, and it matches the number of phases N to meet the closed-loop update requirements under equivalent N-fold frequency control.

[0012] In the dynamic performance collaborative optimization control method for multiphase multilevel converters described in this invention, in step S2, the sampling rate of the low-precision, high-speed analog-to-digital conversion channel is not less than 50 kSPS and the resolution is not higher than 12 bits; the resolution of the high-precision, low-speed analog-to-digital conversion channel is not less than 16 bits and the sampling rate is not higher than 30 kSPS.

[0013] In the dynamic performance collaborative optimization control method for multiphase multilevel converters described in this invention, the preset light load threshold in step S3 is 10 A; when the output current is lower than this threshold for several consecutive control cycles, the system is determined to enter a light load state, and the interphase circulating current compensation mechanism is activated.

[0014] In the dynamic performance collaborative optimization control method for multiphase multilevel converters described in this invention; in step S3, the filtering process employs a first-order low-pass filter, and the compensation amount... Updated according to the recursive formula: , in These are the filter coefficients, and their values ​​range from [value range missing]. , For proportional gain, This refers to the physical switching cycle.

[0015] In the dynamic performance collaborative optimization control method for multiphase multilevel converters described in this invention, the allocation method that satisfies the conservation of the three-phase average duty cycle in step S3 is specifically as follows: , , , To keep the sum of the three-phase duty cycles constant and avoid introducing DC bias, among which... For phase A duty cycle, For phase B duty cycle, For the C phase duty cycle, This represents the average duty cycle.

[0016] In the dynamic performance collaborative optimization control method for multiphase multilevel converters described in this invention, the energy storage load in step S3 is a lithium-ion battery, a lithium iron phosphate battery, or a supercapacitor, and the control method is applicable to constant current, constant voltage, constant current and constant voltage, and constant power charging and discharging steps.

[0017] In the dynamic performance collaborative optimization control method for multiphase multilevel converters described in this invention, the coprocessor in step S2 is one of a control law accelerator, a floating-point coprocessor, or a dedicated hardware acceleration unit.

[0018] The dynamic performance collaborative optimization control method for multiphase multilevel converters of this invention adopts a multiphase parallel three-level topology. By uniformly shifting the phase of each phase's PWM carrier in the time domain and updating the modulation signals of each phase in a time-division multiple manner within a single physical switching cycle, the effective control frequency of the current loop is increased to an integer multiple of the physical switching frequency, significantly suppressing output current ripple and enhancing dynamic response capability. The control system is based on a digital signal processing platform with multi-core processing capabilities, realizing dual-core collaborative operation in dynamic and steady-state modes: in the dynamic adjustment phase, a high-speed coprocessor unit combined with an on-chip fast sampling channel is activated to perform high-frequency closed-loop control; in the steady-state maintenance phase, the main processing unit is switched to cooperate with an external high-precision sampling module to implement low-frequency high-precision adjustment. Both modes are synchronously triggered by a unified hardware timing reference, and a sampling channel calibration mechanism ensures a continuous and smooth switching process without data jumps. To address the problem of unstable midpoint potential or flying capacitor voltage caused by weak energy flow under light load conditions, this invention further introduces an interphase circulating current active compensation strategy based on state recognition. This strategy uses an automatic start-stop compensation mechanism based on the load current level to generate dynamic compensation through low-pass filtering, and distributes it to each phase modulation signal in a way that keeps the average output voltage constant, thereby inducing a controllable circulating current to stabilize the charging and discharging direction of the energy storage element.

[0019] This invention achieves excellent current control performance across the entire load range: it effectively suppresses voltage oscillations and abnormal drop in output current under light load, significantly accelerates response speed during dynamic processes, and ensures high-precision regulation during steady-state operation. It is particularly suitable for advanced battery management systems with stringent requirements for power quality and system stability. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating an embodiment of the dynamic performance collaborative optimization control method for multiphase multilevel converters according to the present invention; Figure 2 This is a control flowchart of an embodiment of the dynamic performance collaborative optimization control method for multiphase multilevel converters of the present invention; Figure 3 This is a working waveform diagram of the dynamic performance collaborative optimization control method for multiphase multilevel converters in this invention; Figure 4 This is a graph showing the rate of change of duty cycle and output current in the dynamic performance collaborative optimization control method for multiphase multilevel converters according to the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] like Figure 1-3 The diagram shown is a flowchart illustrating an embodiment of a dynamic performance collaborative optimization control method for a multiphase multilevel converter according to the present invention. The method provides a dynamic performance collaborative optimization control method for a multiphase multilevel converter, wherein the converter includes multiple parallel power phase units, each phase comprising at least one flying capacitor and a multilevel switching bridge arm, and the output terminals of each phase are commonly connected to an energy storage load. The method is characterized by being executed by a digital controller and includes the following steps: S1, configure each phase PWM drive signal to have a fixed phase offset, and synchronize the duty cycle update operation of each phase with the reference time of the corresponding carrier cycle; within a physical switching cycle, perform N independent duty cycle calculations and loadings in phase sequence, so that the effective update frequency of the control loop reaches N times the physical switching frequency, where N is the number of phases, thereby achieving an equivalent switching frequency multiplication, improving dynamic response capability and suppressing output current ripple; S2, dynamically switching control modes based on system operating status: In the dynamic adjustment phase, the coprocessor responds to high-frequency interrupts, reads the current sampling values ​​collected by the low-precision and high-speed analog-to-digital conversion channels, executes the closed-loop control algorithm, and updates the PWM duty cycle; in the steady-state operation phase, the main processor responds to low-frequency interrupts and performs closed-loop adjustment based on the current sampling values; wherein, the high-frequency interrupt and the low-frequency interrupt are synchronously generated by the same hardware timer source, and automatic linear calibration and manual linear calibration strategies are respectively adopted for the high-speed and low-speed analog-to-digital conversion channels to ensure that the feedback signal is continuous and without step jumps during the control mode switching process; S3. Monitor the output current of the energy storage load in real time. When the output current is lower than the preset light load threshold, activate the interphase circulating current compensation mechanism, generate a filtered asymmetric duty cycle compensation amount Δd, and inject the duty cycle command of each phase upper tube according to the distribution method that satisfies the conservation of the three-phase average duty cycle, so as to establish a controllable circulating current between phases, stabilize the polarity of the flying capacitor voltage, and suppress the current drop or oscillation caused by the inherent nonlinearity of the topology. When the output current recovers to the non-light load region, the compensation amount is automatically cleared.

[0024] In one embodiment, the number of phases N in step S1 is 3, and the PWM drive signals of each phase are out of phase by 120°. Within one physical switching cycle T, the current loop PI calculation and corresponding duty cycle loading are performed sequentially for phases A, B and C, so that the control loop is updated three times in each physical switching cycle, and the update frequency of the control loop reaches three times the physical switching frequency f, thereby achieving equivalent triple frequency control.

[0025] In one embodiment, in step S1, each phase of the multi-level switching bridge arm is a flying capacitor three-level structure, including four switching transistors and one flying capacitor; wherein, the drive signals of the upper and lower transistors in the same bridge arm are complementary and are 180° out of phase.

[0026] In one embodiment, the frequency of the high-frequency interrupt in step S2 is 72 kHz, the frequency of the low-frequency interrupt is 24 kHz, the ratio of the two is 3:1, and it matches the number of phases N to meet the closed-loop update requirements under equivalent N-fold frequency control.

[0027] In one embodiment, in step S2, the sampling rate of the low-precision, high-speed analog-to-digital conversion channel is not less than 50 kSPS and the resolution is not more than 12 bits; the resolution of the high-precision, low-speed analog-to-digital conversion channel is not less than 16 bits and the sampling rate is not more than 30 kSPS.

[0028] In one embodiment, the preset light load threshold in step S3 is 10 A; when the output current is lower than this threshold for multiple consecutive control cycles, the system is determined to enter a light load state and the phase-to-phase circulating current compensation mechanism is activated.

[0029] In one embodiment, the filtering process in step S3 employs a first-order low-pass filter, and the compensation amount Updated according to the recursive formula: , in These are the filter coefficients, and their values ​​range from [value range missing]. , For proportional gain, This refers to the physical switching cycle.

[0030] In one embodiment, the allocation method that satisfies the conservation of the three-phase average duty cycle in step S3 is specifically as follows: , , , To keep the sum of the three-phase duty cycles constant and avoid introducing DC bias, among which... For phase A duty cycle, For phase B duty cycle, For the C phase duty cycle, This represents the average duty cycle.

[0031] In one embodiment, the energy storage load in step S3 is a lithium-ion battery, a lithium iron phosphate battery, or a supercapacitor, and the control method is applicable to constant current, constant voltage, constant current and constant voltage, and constant power charging and discharging steps.

[0032] In one embodiment, the coprocessor in step S2 is one of a control law accelerator, a floating-point coprocessor, or a dedicated hardware acceleration unit.

[0033] This embodiment uses a three-phase parallel flying capacitor three-level converter as the main power circuit. Each phase includes four power switching devices (such as IGBTs or MOSFETs, labeled S1 to S4) and one flying capacitor. This forms a flying capacitor type three-level structure. Each phase output is filtered by an inductor. , , Connect to the common output terminal, and through the output capacitor Power energy storage loads such as lithium-ion batteries.

[0034] The system uses a digital signal processor (DSP), such as the TI TMS320F28379D, as the main control platform. This DSP integrates a main CPU core, a control law accelerator (CLA), a multi-channel enhanced PWM module (ePWM), an internal high-speed ADC, and an external high-precision ADC interface such as the ADS131E08.

[0035] The multi-channel enhanced PWM module ePWM is configured with independent sub-modules for phases A, B, and C, with a carrier frequency set to f=24kHz, corresponding to a physical switching period T=1 / f≈41.67μs. The initial phases of the three carrier counters are sequentially offset by 120°, i.e., the time interval is T / 3. The update of each phase duty cycle register (CMPA) is strictly synchronized with the moment when its corresponding carrier counter CNT=0, achieving hard-aligned loading.

[0036] Within a physical switching cycle T, the control loop performs three independent updates according to the following timing sequence: At time t=0, i.e., when CNT=0 for phase A, the first PI calculation is performed to update the duty cycle of phase A. ; At time t=T / 3, i.e., when CNT=0 for phase B, the second PI calculation is performed to update the duty cycle of phase B. ; At time t=2T / 3, i.e., when C-phase CNT=0, the third PI calculation is performed to update the C-phase duty cycle. .

[0037] Since each update is based on the latest output current feedback, the total output current... The frequency is then dynamically adjusted, thereby increasing the effective control frequency of the current loop to 3f = 72kHz. This equivalent third-harmonic control mechanism significantly improves the dynamic response speed of the system and increases the output current ripple frequency to 72kHz, while reducing the ripple amplitude to about 1 / 3 of that of a single-phase structure.

[0038] The system automatically switches control modes based on the status of each step, balancing dynamic performance and steady-state accuracy. During the dynamic adjustment phase (e.g., current step rise): a 72 kHz high-speed interrupt is triggered, the CLA coprocessor reads the internal high-speed DSP_ADC sampling value, executes a lightweight PI algorithm to calculate the duty cycle, and completes the PWM update within 5μs. The CLA coprocessor runs independently of the main CPU, avoiding task scheduling delays and ensuring fast response.

[0039] During steady-state operation (e.g., constant current maintenance): switch to 24 kHz low-speed interrupt, the main CPU reads external high-precision ADC data such as ADS131E08, performs high-precision PI adjustment, and ensures that the steady-state error is less than ±0.1%.

[0040] Both interrupts are generated synchronously by the periodic events of the same multi-channel enhanced PWM module (ePWM), ensuring strict timing alignment. Simultaneously: On-chip automatic linear calibration is enabled for the internal DSP_ADC; manual gain / offset calibration is performed on the external high-precision ADC during system initialization; thus ensuring continuous sampling values ​​without step transitions at the high-speed / low-speed mode switching points. This design achieves synergistic optimization of high-speed response and high-precision steady-state performance, balancing dynamic performance and control accuracy under resource-constrained conditions.

[0041] Under light load conditions, such as output current In certain situations, flying capacitors are prone to voltage oscillations due to the uncertain charging and discharging direction, leading to a drop in output current. To address this, the present invention introduces an interphase circulating current compensation mechanism, the specific process of which is as follows: Real-time monitoring of output current If the A value is below 10 A for three consecutive control cycles, the system is determined to be in a light load state; when the system exits the light load state, such as... After three consecutive cycles, the software will automatically clear the compensation amount. Resetting to zero is equivalent to deintegrating or disabling additional compensation terms in current loop control, causing the system to return to the standard three-phase symmetrical control mode.

[0042] Compensation amount calculation: The recursive formula for activating the first-order low-pass compensator is: , among which The proportional gain is experimentally tuned, with a typical value of k, This filter structure effectively suppresses high-frequency noise and ensures smooth changes in compensation.

[0043] The compensation amount is distributed to the duty cycle of the three-phase upper tube as follows: , , This allocation satisfies This does not change the average output voltage and avoids introducing DC bias. At the same time, the inductor currents of phases A and B are slightly greater than those of phase C, forming a controllable interphase circulating current, which forces the flying capacitors of each phase to stabilize in a single charging and discharging direction.

[0044] This compensation strategy artificially introduces a controllable and stable interphase circulating current, causing the flying capacitor voltage to deviate from its unstable equilibrium point near zero current. This fundamentally avoids the capacitor repeatedly switching between "charging" and "discharging" modes, completely eliminating the nonlinear "drop-off" phenomenon of output current under light load conditions, and significantly improving the smoothness and controllability of the dynamic process. Under normal load conditions, the system automatically exits compensation without affecting conventional high-precision control performance.

[0045] like Figure 4 As shown in the figure (comparison with and without interphase circulating current: duty cycle versus output current rate of change curve, with the horizontal axis representing output current and the vertical axis representing duty cycle), in the low current region, the duty cycle-current characteristic exhibits significant nonlinear distortion without compensation; however, after introducing interphase circulating current compensation, this nonlinearity is effectively suppressed, and the system demonstrates good linearity and stability across the entire load range. This strategy has been experimentally verified and has practical engineering value.

[0046] This invention employs a three-phase interleaved PWM modulation strategy, sequentially shifting the phases of the A, B, and C phase carriers by 120°. Within a 24 kHz physical switching cycle, the three-phase duty cycle is updated in a time-division manner, increasing the effective control frequency of the current loop to 72 kHz. This significantly reduces output current ripple and accelerates dynamic response. The system utilizes a DSP main control platform for dual-core collaborative control: during dynamic adjustment, the CLA coprocessor performs 72 kHz interrupt control based on its internal high-speed ADC; during steady-state operation, the main CPU switches to utilize an external high-precision ADC for 24 kHz high-precision adjustment, and a unified timing source and ADC calibration mechanism ensure smooth mode switching without jumps. To address the current drop caused by the flying capacitor voltage oscillation under light load conditions, an interphase circulating current compensation mechanism is introduced. This mechanism generates compensation through a first-order low-pass recursion and injects it into the three-phase duty cycle in a specific ratio, stabilizing the capacitor charging and discharging direction without altering the average output voltage. Experiments show that this invention can reduce the voltage fluctuation of the flying capacitor under light load by more than 80%, reduce the output current ripple amplitude to 1 / 3 of that of a single-phase structure, and achieve a steady-state error of less than ±0.1%. It combines excellent dynamic performance, steady-state accuracy, and stability across the entire load range, making it suitable for high-reliability lithium-ion battery charging and discharging systems.

[0047] In summary, this invention significantly improves the dynamic performance, steady-state accuracy, and operational stability of the flying capacitor three-level converter over a wide load range through three core technologies: three-phase interleaved modulation, dual-core collaborative control, and light-load circulating current compensation.

[0048] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0049] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0050] Therefore, the above description is only a preferred embodiment of the present invention, and the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dynamic performance co-optimization control method for a multi-phase multi-level converter, the converter comprising a plurality of parallel connected power phase units, each phase containing at least one flying capacitor and a multi-level switching bridge arm, the output terminals of each phase being commonly connected to an energy storage load, characterized in that, The method is executed by a digital controller, and the method comprises the following steps: S1, configuring each phase PWM drive signal with a fixed phase offset, and synchronizing the duty cycle updating operation of each phase with the reference time of the corresponding carrier period; in one physical switching cycle, N times of independent duty cycle calculation and loading are performed in time according to the phase sequence, so that the effective update frequency of the control loop reaches N times of the physical switching frequency, wherein N is the number of phases, thereby realizing equivalent switching frequency multiplication, improving dynamic response capability and suppressing output current ripple; S2, dynamically switching the control mode based on the system running state: in the dynamic adjustment stage, the high-frequency interrupt is responded by the coprocessor, the current sample value collected by the low-precision high-speed analog-to-digital conversion channel is read, the closed-loop control algorithm is executed and the PWM duty cycle is updated; in the steady-state running stage, the low-frequency interrupt is responded by the main processor, and the closed-loop adjustment is performed based on the current sample value; wherein the high-frequency interrupt and the low-frequency interrupt are generated synchronously by the same hardware timer source, and automatic linear calibration and manual linear calibration strategies are adopted for high-speed and low-speed analog-to-digital conversion channels respectively, so as to ensure that the feedback signal is continuous and there is no step jump during the control mode switching process; S3, real-time monitoring of the output current of the energy storage load, when the output current is lower than the preset light load threshold, the inter-phase circulating current compensation mechanism is activated, a filtered asymmetric duty cycle compensation quantity Δd is generated, and the compensation quantity Δd is injected into the upper tube duty cycle instruction of each phase according to a distribution mode that meets the conservation of three-phase average duty cycle, so as to establish a controllable circulating current among the phases, stabilize the flying capacitor voltage polarity, and suppress the current drop or oscillation caused by the inherent nonlinearity of the topology; when the output current returns to the non-light load area, the compensation quantity is automatically cleared.

2. The dynamic performance co-optimization control method for a multi-phase multi-level converter according to claim 1, characterized in that, In the step S1, the number of phases N is 3, and the phase PWM drive signals are mutually out of phase by 120°; in one physical switching cycle T, the current loop PI calculation and the corresponding duty cycle loading are performed once for the A phase, the B phase and the C phase in turn, so that the control loop is updated three times in each physical switching cycle, the update frequency of the control loop reaches three times of the physical switching frequency f, and equivalent three times frequency control is realized.

3. The dynamic performance co-optimization control method for a multi-phase multi-level converter according to claim 2, characterized in that, In the step S1, the multi-level switching bridge arm of each phase is a flying capacitor three-level structure, which comprises four switching tubes and one flying capacitor; wherein the upper tube and the lower tube drive signals in the same bridge arm are complementary and have a phase difference of 180°.

4. The dynamic performance co-optimization control method for a multi-phase multi-level converter of claim 1, wherein, In the step S2, the frequency of the high-frequency interrupt is 72 kHz, the frequency of the low-frequency interrupt is 24 kHz, the ratio of the two is 3:1, and they are matched with the number of phases N to meet the closed-loop update requirement under the equivalent N times frequency control.

5. The dynamic performance co-optimization control method for a multi-phase multi-level converter according to claim 3, wherein, In the step S2, the sampling rate of the low-precision high-speed analog-to-digital conversion channel is not less than 50 kSPS and the resolution is not higher than 12 bits; the resolution of the high-precision low-speed analog-to-digital conversion channel is not less than 16 bits and the sampling rate is not higher than 30 kSPS.

6. The dynamic performance co-optimization control method for a multi-phase multi-level converter according to claim 5, wherein, In the step S3, the preset light load threshold is 10 A; when the output current is lower than the threshold for a plurality of control periods, it is determined that the system enters the light load state, and the inter-phase circulating current compensation mechanism is enabled.

7. The dynamic performance co-optimization control method for a multi-phase multi-level converter of claim 1, wherein, In the step S3 the filter processing employs a first order low pass filter, the compensation quantity is updated according to the recurrence formula: ， wherein is a filter coefficient, with a value range of , is a proportional gain, is a physical switching period.

8. The dynamic performance co-optimization control method for a multi-phase multi-level converter of claim 1, wherein, The allocation mode satisfying the three-phase average duty cycle conservation in the step S3 is specifically: ， ， , such that the sum of the three phase duty cycles remains constant, avoiding the introduction of a DC bias, where is the A phase duty cycle, is the B phase duty cycle, is the C phase duty cycle, is the average duty cycle.

9. The dynamic performance co-optimization control method for a multi-phase multi-level converter according to claim 8, wherein, In the step S3, the energy storage load is a lithium ion battery, a lithium iron phosphate battery or a super capacitor, and the control method is suitable for constant current, constant voltage, constant current and constant voltage and constant power charging and discharging steps.

10. The dynamic performance co-optimization control method for a multi-phase multi-level converter of claim 5, wherein, In the step S2, the coprocessor is one of a control law accelerator, a floating point coprocessor or a dedicated hardware acceleration unit.

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