A ZVT-boost type PFC circuit with active saturated inductance

Abstract

This application relates to the field of power electronic conversion technology and discloses an active ZVT-Boost type PFC circuit with a saturated inductor. The active ZVT auxiliary branch of this power stage circuit is connected in parallel across the main switch, and a saturated inductor and a blocking diode are connected in series. The digital control system includes modules for fast-scale timing calculation, steady-state gating discrimination, energy efficiency adaptive correction, and drive signal generation. The digital control system calculates the basic lead-on time based on a piecewise linearized model of the saturated inductor to achieve fast-scale feedforward control; it locks the steady-state operating condition through steady-state gating discrimination, uses the voltage loop adjustment as the basis for loss observation, and employs an extreme value search algorithm to update the timing correction coefficients online to achieve slow-scale closed-loop optimization. This invention solves the soft-switching timing deviation problem caused by the thermal drift of the saturated inductor, ensuring zero-voltage turn-on across the entire load range without additional sensors, thus improving system energy efficiency and robustness.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion technology, specifically to an active ZVT-Boost type PFC circuit with saturated inductor. Background Technology

[0002] Boost-type power factor correction (PFC) converters are the core front-end circuits in AC-DC power systems. To improve power density, switching frequencies are constantly increasing, leading to a significant increase in switching losses of the main switching devices. Active zero-voltage switching (ZVT) technology creates zero-voltage turn-on conditions by briefly operating an auxiliary branch before the main switch operates, which is an effective means of reducing losses. Among these, using a saturated inductor as the key component of the auxiliary branch, leveraging its magnetic saturation characteristics under high current to limit the diode reverse recovery current and reduce the circulating energy of the auxiliary branch, is a superior topology.

[0003] However, the physical characteristics of a saturated inductor are highly nonlinear and extremely sensitive to temperature changes. In actual operation, as the operating time increases and the load intensifies, the core temperature rises, leading to a decrease in its saturation magnetic flux density, which in turn causes a drift in the inductor's saturation point. Simultaneously, the inductor current in a PFC circuit exhibits a large sinusoidal variation within the power frequency cycle, meaning that the optimal lead time required for the auxiliary branch to achieve soft switching is constantly changing dynamically. Most existing control schemes employ fixed timing control or simple feedforward control based solely on ideal models, making it difficult to simultaneously address the dual challenges of large current fluctuations and thermal drift of component parameters. This mismatch between timing and actual operating conditions often results in the main switch failing to achieve complete zero-voltage turn-on, or additional circulating current losses due to excessively long auxiliary switch conduction times. While compensation can be achieved by adding temperature sensors or high-frequency current detection circuits, this undoubtedly increases hardware costs and system complexity.

[0004] Therefore, this invention proposes an active ZVT-Boost type PFC circuit with saturated inductor to overcome the shortcomings of the prior art. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an active ZVT-Boost PFC circuit with saturated inductor, which solves the problem that existing active ZVT-Boost PFC circuits with saturated inductor suffer from soft-switching timing mismatch due to thermal drift of component parameters and dynamic changes in input current, thus failing to maintain zero-voltage turn-on and optimal energy efficiency across the entire load range.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution: an active ZVT-Boost type PFC circuit with saturated inductor, including a power stage circuit and a digital control system;

[0007] The power stage circuit includes a main power circuit and an active ZVT auxiliary branch; the main power circuit is configured as a Boost topology; the active ZVT auxiliary branch is coupled in parallel to the main switching device of the main power circuit, and the active ZVT auxiliary branch includes a saturated inductor, a blocking diode, and an auxiliary switching device connected in series; the blocking diode is configured to allow current to flow only from the saturated inductor to the auxiliary switching device;

[0008] The digital control system includes a signal acquisition module, a fast-scale timing calculation module, a steady-state gating discrimination module, an energy efficiency adaptive correction module, and a drive signal generation module;

[0009] The fast-scale timing calculation module is configured to calculate the basic lead-on time based on the piecewise linearization model of the saturated inductor.

[0010] The steady-state gating discrimination module is configured to identify the load steady-state operating condition of the PFC circuit and generate an optimized enable signal;

[0011] The energy efficiency adaptive correction module is configured to adjust the timing correction coefficient by using the voltage loop adjustment as the basis for loss observation in response to the optimization enable signal.

[0012] The drive signal generation module is configured to synthesize the actual lead time based on the basic lead time and the timing correction coefficient, and output a drive signal to control the auxiliary switching device to turn on before the main switching device.

[0013] Preferably, the main power circuit includes a boost inductor, the main switching device, a boost diode, and an output capacitor;

[0014] The positive terminal of the input voltage source is connected to one end of the boost inductor, and the other end of the boost inductor is connected to the drain of the main switching device and the anode of the boost diode; the cathode of the boost diode is connected to the positive terminal of the output capacitor.

[0015] Preferably, the active ZVT auxiliary branch further includes a resonant capacitor and a clamping diode;

[0016] The resonant capacitor is connected in parallel between the drain of the main switching device and the source of the main switching device.

[0017] One end of the saturated inductor is connected to the common connection point of the boost inductor and the main switching device, and the other end of the saturated inductor is connected to the anode of the blocking diode; the cathode of the blocking diode is connected to the drain of the auxiliary switching device.

[0018] The anode of the clamping diode is connected to the common node of the cathode of the blocking diode and the drain of the auxiliary switching device, and the cathode of the clamping diode is connected to the positive terminal of the output capacitor.

[0019] Preferably, the magnetic core of the saturated inductor has piecewise nonlinear impedance characteristics;

[0020] The saturated inductor is configured to have the following characteristics: when the absolute value of the current flowing through the saturated inductor is less than the saturation current threshold, the saturated inductor exhibits a linear region inductance value; when the absolute value of the current flowing through the saturated inductor is greater than the saturation current threshold, the saturated inductor exhibits a saturation region inductance value; and the linear region inductance value is greater than the saturation region inductance value.

[0021] Preferably, the fast-scale timing calculation module has a pre-set lookup table, which stores the corresponding relationships calculated based on the piecewise linearization model of the saturated inductance;

[0022] The fast-scale timing calculation module is configured to obtain the corresponding basic lead-on time from the lookup table based on the real-time sampled main input current; the piecewise linearization model is a model established based on the linear region inductance value, the saturation region inductance value, and the saturation current threshold.

[0023] Preferably, the steady-state gating discrimination module is configured to receive the output voltage and the voltage loop adjustment, calculate the statistical feature quantity within a set window, and compare the statistical feature quantity with a preset threshold to identify whether the PFC circuit is in the load steady-state condition.

[0024] The steady-state gating discrimination module is configured to send the optimization enable signal to the energy efficiency adaptive correction module to allow the timing correction coefficient to be updated when the PFC circuit is identified as being in the steady-state load condition.

[0025] Preferably, the statistical characteristics include the average value of the output voltage error and the fluctuation range of the voltage loop regulation.

[0026] The steady-state gating discrimination module is configured to determine that the PFC circuit is in the load steady-state condition only when the average value of the output voltage error is less than the allowable threshold for voltage error and the fluctuation amplitude of the voltage loop regulation is less than the allowable threshold for control fluctuation.

[0027] Preferably, the energy efficiency adaptive correction module is configured to update the time-series correction coefficients using an extreme value search algorithm;

[0028] The energy efficiency adaptive correction module is configured to construct a cost function with the average value of the voltage loop regulation as the objective, and to superimpose a disturbance on the current timing correction coefficient. Based on the gradient of the change of the cost function, the timing correction coefficient for the next control cycle is calculated to drive the voltage loop regulation to converge toward the minimum value.

[0029] Preferably, the energy efficiency adaptive correction module is configured to employ an asymmetric search strategy;

[0030] The energy efficiency adaptive correction module is configured to set the initial value of the timing correction coefficient in the overcompensated region, where the overcompensated region is defined as the time interval during which the conduction time of the auxiliary switching device is greater than the ideal resonant period; the energy efficiency adaptive correction module is configured to control the timing correction coefficient to search and update from the overcompensated region to the undercompensated region.

[0031] Preferably, the drive signal generation module is configured to perform parameter synthesis calculation, multiplying the basic lead conduction time by the timing correction coefficient to obtain the actual lead conduction time;

[0032] The drive signal generation module is further configured to map the actual lead-on time to the count value of a digital counter, and generate a main drive signal and an auxiliary drive signal with interlocking logic.

[0033] This invention provides an active ZVT-Boost PFC circuit with a saturated inductor. It has the following advantages:

[0034] 1. This invention establishes a piecewise linearized model of the saturated inductor through a fast-scale timing calculation module. Based on the real-time acquired main input current, it distinguishes the different physical characteristics of the inductor in the linear and saturated regions, and accurately calculates the basic lead-on time to match the current operating conditions. This mechanism solves the problem that traditional fixed-sequence control cannot adapt to large fluctuations in AC input current, ensuring that the auxiliary switch provides accurate resonant energy in each switching cycle. This achieves zero-voltage turn-on of the main switching device throughout the entire power frequency cycle, reducing switching losses.

[0035] 2. To address the issue of saturated inductor core parameters drifting with increasing temperature or aging, this invention utilizes an energy efficiency adaptive correction module. It uses the existing voltage loop regulation within the control system as an observational basis for characterizing the total system loss, and corrects timing parameters online through an extreme value search algorithm. This method eliminates the need for additional current transformers or temperature sensors, automatically compensating for ZVT timing deviations caused by component thermal drift. This ensures the circuit always operates at its optimal energy efficiency point, reducing hardware costs and improving the long-term reliability of the system.

[0036] 3. This invention introduces a steady-state gating discrimination module and an asymmetric search strategy. Logically, it only allows the system to perform parameter optimization under steady-state conditions, effectively isolating the interference of transient load changes on energy efficiency optimization and preventing control parameter divergence. In terms of hardware, it utilizes the unidirectional blocking characteristic of the blocking diodes in the auxiliary branch, combined with a search strategy that approaches the undercompensated region from the overcompensated region, to construct a unidirectional safety domain at the physical level. This ensures that even if timing excess occurs during the optimization process, it will not cause reverse current backflow or additional hard-turn-off losses, guaranteeing the safe operation of the system. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the ZVT-Boost type PFC circuit architecture of the present invention;

[0038] Figure 2 This is a schematic diagram of the overall architecture of the ZVT-Boost type PFC circuit system of the present invention;

[0039] Figure 3 This is a schematic diagram of the method flow of the present invention;

[0040] Figure 4 This is a schematic diagram of the key node driving timing and soft switching waveforms of the present invention;

[0041] Figure 5 This is a schematic diagram illustrating the characteristics of the piecewise linearized saturated inductor model of the present invention;

[0042] Figure 6 This is a schematic diagram of the convergence curve of the energy efficiency adaptive correction process of the present invention;

[0043] Figure 7 This is a schematic diagram illustrating the characteristics of the loss cost function of the present invention.

[0044] Among them, 100 is the signal acquisition module; 200 is the fast-scale time series calculation module; 300 is the steady-state gating discrimination module; 400 is the energy efficiency adaptive correction module; and 500 is the drive signal generation module. Detailed Implementation

[0045] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] See attached document Figures 1-2The active ZVT-Boost PFC circuit with saturated inductor provided by this invention mainly includes a power stage circuit and a digital control system. The power stage circuit performs power conversion of electrical energy, and the digital control system samples the status signal of the power stage circuit and outputs a drive control signal.

[0047] The power stage circuit includes a main power circuit and an active ZVT auxiliary branch. The main power circuit is configured with a boost topology to convert input AC or DC power into stable DC output power. The active ZVT auxiliary branch is coupled in parallel across the main switching device in the main power circuit to establish zero-voltage switching conditions before the main switching device is turned on. The active ZVT auxiliary branch includes an inductor with magnetic saturation characteristics and a diode with unidirectional blocking characteristics.

[0048] The digital control system is connected to the power stage circuit via a signal sampling link and controls the switching devices in the power stage circuit via a drive signal link. The digital control system's logical architecture includes:

[0049] The signal acquisition module 100 acquires the operating status parameters of the power stage circuit in real time. The input terminals of the signal acquisition module 100 are connected to the voltage and current sensors of the power stage circuit, and the output terminals are connected to the fast-scale timing calculation module 200, the steady-state gating discrimination module 300, and the energy efficiency adaptive correction module 400, respectively. The data output by the signal acquisition module 100 includes the main input current, input voltage, output voltage, and voltage loop regulation.

[0050] The fast-scale timing calculation module 200 performs feedforward control calculations based on a physical model of a saturated inductor. The fast-scale timing calculation module 200 receives main input current data from the signal acquisition module 100 and calculates the basic lead-on time of the auxiliary switch using a preset piecewise linearized inductor model. The output of the fast-scale timing calculation module 200 is connected to the drive signal generation module 500.

[0051] The steady-state gating discrimination module 300 identifies the steady-state operating condition of the system load. The steady-state gating discrimination module 300 receives output voltage and voltage loop regulation data from the signal acquisition module 100, calculates the statistical characteristics of the variables and compares them with preset thresholds, and generates an optimization enable flag. The output of the steady-state gating discrimination module 300 is connected to the energy efficiency adaptive correction module 400 to control the operating state of the energy efficiency adaptive correction module 400.

[0052] The energy efficiency adaptive correction module 400 performs closed-loop optimization to address the thermal drift characteristics of a saturated inductor. The energy efficiency adaptive correction module 400 is controlled by the steady-state gating discrimination module 300. When the system is in steady state, the energy efficiency adaptive correction module 400 uses the voltage loop adjustment input from the signal acquisition module 100 as the basis for loss observation and updates the timing correction coefficients using an extreme value search algorithm. The output of the energy efficiency adaptive correction module 400 is connected to the drive signal generation module 500.

[0053] The drive signal generation module 500 synthesizes the final switching timing. The drive signal generation module 500 receives the basic lead time from the fast-scale timing calculation module 200 and the timing correction coefficient from the energy efficiency adaptive correction module 400, and synthesizes the two to obtain the actual lead time. The output of the drive signal generation module 500 is connected to the control gates of the main switching device and the auxiliary switching device in the power stage circuit.

[0054] See attached document Figure 3 This invention provides a control method for an active ZVT-Boost type PFC circuit with a saturated inductor, comprising the following steps:

[0055] S100, perform state sampling, and obtain the voltage and current information of the current switching cycle through the signal acquisition module 100, including the main input current, input voltage, output voltage and voltage loop regulation;

[0056] S200, the fast-scale timing calculation module 200 calculates the basic lead-on time of the auxiliary switch based on the main input current and the preset piecewise linearized inductor model;

[0057] S300, the steady-state gating discrimination module 300 calculates the statistical characteristics of the output voltage and voltage loop regulation to determine whether the PFC circuit is in a steady-state condition.

[0058] S400, if the PFC circuit is in an unsteady state, the energy efficiency adaptive correction module 400 keeps the current timing correction coefficient unchanged;

[0059] S500, if the PFC circuit is in steady-state operation, the energy efficiency adaptive correction module 400 updates the timing correction coefficients according to the changing trend of the voltage loop regulation using an extreme value search algorithm.

[0060] S600, the drive signal generation module 500 multiplies and synthesizes the basic lead conduction time and timing correction coefficient to obtain the actual lead conduction time;

[0061] S700, the drive signal generation module 500 generates a PWM drive waveform based on the actual lead time, controlling the auxiliary switch in the power stage circuit to turn on before the main switch.

[0062] To further clarify the implementation of each technical aspect of the present invention, the following will provide a detailed description of the implementation of each functional module involved above and its internal processing flow.

[0063] See attached document Figure 2 The power stage circuit mainly consists of the main power circuit and the active ZVT auxiliary branch.

[0064] The main power circuit employs a boost converter topology for power factor correction and voltage conversion. The main power circuit includes a boost inductor L, a main switch T, a boost diode D, and an output capacitor. The positive terminal of the input voltage source Vin is connected to one end of the boost inductor L, and the other end of the boost inductor L is connected to the drain of the main switch T and the anode of the boost diode D. The source of the main switch T is grounded (or connected to a current sampling resistor). The cathode of the boost diode D is connected to the positive terminal of the output capacitor and one end of the load Vo, while the negative terminal of the output capacitor and the other end of the load Vo are grounded. During the conduction period of the main switch T, the boost inductor L stores energy; during the turn-off period of the main switch T, the boost inductor L releases energy to the output terminal through the boost diode D.

[0065] An active ZVT auxiliary branch is coupled in parallel across the main switch T to provide a discharge path for the resonant capacitor Cr during the short period before the main switch T turns on, achieving zero-voltage turn-on of the main switch T. The active ZVT auxiliary branch includes the resonant capacitor Cr, a saturated inductor Lr, a blocking diode D2, an auxiliary switch T1, and a clamping diode D1. The resonant capacitor Cr is connected in parallel between the drain and source of the main switch T (or utilizing the parasitic output capacitance of the main switch T). One end of the saturated inductor Lr is connected to the common connection point between the boost inductor L and the main switch T, and the other end is connected to the anode of the blocking diode D2. The cathode of the blocking diode D2 is connected to the drain of the auxiliary switch T1. The source of the auxiliary switch T1 is grounded. The anode of the clamping diode D1 is connected to the common node between the cathode of the blocking diode D2 and the drain of the auxiliary switch T1, and the cathode of the clamping diode D1 is connected to the positive terminal of the output voltage Vo.

[0066] As a key magnetic component, the saturated inductor Lr possesses a core material with high permeability and a rectangular hysteresis loop, exhibiting piecewise nonlinear impedance characteristics that vary with current. When the current flowing through the saturated inductor Lr is less than the saturation threshold... When the current flows through the saturated inductor Lr, it is in the linear region and exhibits high impedance characteristics, limiting the rate of current rise in the auxiliary branch; when the current flowing through the saturated inductor Lr exceeds the saturation threshold... When the saturated inductor Lr enters the saturation region, the core permeability drops sharply, exhibiting low impedance characteristics, allowing the current to rise rapidly and resonate at high frequency with the resonant capacitor Cr. The physical characteristics of the saturated inductor Lr include thermal sensitivity, and its saturation threshold... The saturation threshold is negatively correlated with the core temperature; as the core temperature increases, the saturation threshold decreases. The decrease leads to an earlier entry into the saturation region.

[0067] The blocking diode D2, as a key unidirectional control device, is connected in series in the auxiliary resonant circuit. Utilizing the unidirectional conductivity of the PN junction, the blocking diode D2 allows current to flow only from the saturated inductor Lr to the auxiliary switch T1, thus allowing the discharge current of the resonant capacitor Cr to pass through. When the resonance process ends and the resonant current attempts to flow in the reverse direction (from the auxiliary switch T1 to the saturated inductor Lr), the blocking diode D2 enters the reverse cutoff state, physically cutting off the current path. This characteristic constructs a unidirectional blocking safety domain in the circuit. Even if the on-time of the drive signal of the auxiliary switch T1 exceeds the ideal resonant period, the blocking diode D2 can prevent reverse current from flowing through the body diode of the auxiliary switch T1, avoiding parasitic oscillations and additional hard-turn-off losses, and providing hardware safety assurance for the control system to perform a wide-range timing search. The clamping diode D1 is used to provide a freewheeling path for the remaining energy in the saturated inductor Lr to be fed back to the output terminal at the moment the auxiliary switch T1 is turned off, suppressing voltage spikes.

[0068] See attached document Figure 2 In this embodiment, the signal acquisition module 100 is configured as the physical interface between the digital control system and the power stage circuit. It is responsible for converting the analog voltage and current signals of the power stage circuit into a discrete state sequence that the digital controller can process, providing a high-precision real-time data foundation for subsequent fast-scale feedforward control and slow-scale energy efficiency adaptive correction. The signal acquisition module 100 specifically includes:

[0069] S110, Perform synchronous sampling and preprocessing of physical quantities. In this embodiment, the analog-to-digital converter (ADC) within the digital controller is configured to be sampled by a PWM time base unit. To avoid the impact of switching noise on sampling accuracy, an RC low-pass filter is configured at the hardware input port. The sampling trigger time is configured at the midpoint of the rising edge or falling edge of the boost inductor current, at which point the sampled value is approximately equal to the average current value of that switching cycle. The signal acquisition module 100 acquires the instantaneous input voltage through a resistor divider network. and instantaneous output voltage The main input current is acquired by a current sensor (such as a low-inductance sampling resistor) connected in series in the rectifier bridge output circuit, boost inductor circuit, or main switch source. .in, This indicates the index of the current discrete control cycle.

[0070] S120 extracts the voltage loop regulation and its physical state mapping. Voltage loop regulation. It is the output value of the proportional-integral (PI) controller in the voltage loop within the digital control system. In the PFC average current control logic, Multiplying the input voltage feedforward signal with the input voltage signal, the given reference amplitude of the inner current loop is determined. Under the premise of constant output load, changes in system efficiency will directly reflect changes in the input current amplitude required to maintain output power, and thus linearly map to... The magnitude of the change. Therefore, this variable can serve as an observed proxy variable characterizing the total loss of the system under steady state.

[0071] In this embodiment, the value is read directly from the controller's internal calculation unit. Voltage loop regulation amount The calculation expression is:

[0072] ;

[0073] In the formula, This is the voltage loop proportional gain coefficient. These are the voltage loop integral gain coefficients. The values ​​of these two coefficients are designed based on the target bandwidth of the voltage loop, which is typically set between 10Hz and 20Hz to effectively suppress the twice-power-frequency ripple component in the output voltage and ensure... In steady state, it is a stationary quantity that approximates DC. This represents the signed voltage error value; This is the variable for the integral accumulation.

[0074] S130, calculate the absolute value of the output voltage error. Based on the sampled instantaneous output voltage. With the system's preset reference voltage Calculate the absolute value of the output voltage error used for steady-state discrimination. The calculation logic is as follows:

[0075] ;

[0076] In the formula, The target output voltage constant is stored in the controller's non-volatile memory, and its value is set according to the rated voltage requirement of the downstream load. The calculated value is... It will be transmitted to the subsequent steady-state gating discrimination module for evaluating the load regulation status of the system.

[0077] See attached document Figure 2In this embodiment, the fast-scale timing calculation module 200 is configured to perform microsecond-level feedforward control based on the physical characteristic model of a saturated inductor. This fast-scale timing calculation module 200 aims to solve the problem of inconsistent auxiliary branch commutation time caused by large dynamic changes in the boost inductor current within the power frequency cycle, ensuring accurate timing matching the current state in each switching cycle. Its basic physical principle is as follows: before the main switch is turned on, the main current flowing through the boost diode is completely transferred to the auxiliary branch, and further, the low impedance characteristic of the saturated inductor resonates with the resonant capacitor to pull the voltage across the main switch down to zero. The fast-scale timing calculation module 200 specifically includes:

[0078] S210, Establish a piecewise linearized model and calibrate the parameters of the saturated inductor. This embodiment uses a piecewise linearization method to numerically model the nonlinear magnetization curve of the saturated inductor. The saturation magnetic flux density is determined by performing BH curve tests on the selected core material or by consulting a magnetic material property handbook. And the corresponding magnetic field strength, and then calculate the saturation current threshold. The physical characteristics of a saturated inductor are simplified to two discrete inductance value states:

[0079] When the absolute value of the current flowing through the saturated inductor Lr is less than or equal to the saturation current threshold When an inductor exhibits high impedance characteristics, its inductance value is defined as the inductance value in the linear region. The larger inductance value is mainly used to limit the rate of current change during the turn-off process of the clamping diode D1. To suppress reverse recovery loss;

[0080] When the absolute value of the current flowing through the saturated inductor Lr is greater than the saturation current threshold When the magnetic core becomes magnetically saturated, the inductance drops sharply. The inductance value is defined as the inductance value in the saturation region. .

[0081] See attached document Figure 5 This section details the piecewise linearized model of the saturated inductor that the fast-scale timing calculation module 200 relies on. The horizontal axis represents the absolute value of the current flowing through the saturated inductor, and the vertical axis represents the inductance value. For example... Figure 5 As shown, the model uses a saturation current threshold. (The example in the figure is approximately 4A) serves as a boundary, simplifying the complex hysteresis curve into two discrete states: when the current is less than... At that time, the inductance value remains in the higher linear region. (The example in the diagram is 50uH); when the current exceeds When the inductance value drops stepwise to the saturation region inductance value (The example in the figure is 2uH). This invention is based on this stepped model, calculating the rise time of the current in two different slope intervals, thereby achieving advance conduction time of the foundation. The precise feedforward calculation significantly reduces the computational burden on the digital controller. Among these, The value is usually designed as 10 to 50 times the value.

[0082] S220, calculate the basic lead time. Basic lead time. It consists of two physical processes: one is the current rise time. That is, the auxiliary branch current rises from zero to the current boost inductor current. The time required to complete the current transfer; and the resonant discharge time. That is, the time required for the voltage of the resonant capacitor Cr to discharge to zero after the auxiliary branch current exceeds the boost inductor current.

[0083] Regarding current rise time The calculation, based on the volt-second balance principle and the aforementioned piecewise linearization model, is handled under two operating conditions:

[0084] Operating Condition 1: When the main circuit input current Less than or equal to the saturation current threshold When the auxiliary branch current operates entirely in the linear region, the current rise time is only related to the inductance value in the linear region.

[0085] Operating Condition 2: When the main circuit input current greater than the saturation current threshold At that time, the auxiliary branch current first rises through the linear region to It then continued to rise in the saturation region. .

[0086] Based on the above physical processes, the fundamental lead time The calculation formula is as follows:

[0087] when hour:

[0088] ;

[0089] when hour:

[0090] ;

[0091] In the formula, This represents the inductance value of the saturated inductor in the linear region. This represents the inductance value of the saturated inductor in the saturation region. This is the preset saturation current threshold; This is the current sampled main input current; The rated output voltage of the system is used in this embodiment as... The steady-state approximation is used in the feedforward calculation; This is the total capacitance of the resonant capacitor, which includes the external physical capacitance and the parasitic capacitance between the drain and source of the main switching device. The sum of capacitance values.

[0092] S230, execute the engineering implementation based on lookup table. Considering that executing the above formula containing division and square root operations in each switching cycle would consume too much CPU computing power, this embodiment uses a one-dimensional lookup table (LUT) to implement the above algorithm.

[0093] During system initialization or offline compilation, based on the above formula and the system's rated output voltage... A series of fundamental lead-on time values ​​corresponding to discrete current points are pre-calculated and stored in the controller's non-volatile program memory. During real-time operation, the fast-scale timing calculation module 200 uses real-time sampled data... The underlying lead time is obtained either directly from the lookup table or through linear interpolation, serving as the index address. This method eliminates the latency of real-time floating-point operations, ensuring the instantaneous response capability of control timing on a microsecond timescale.

[0094] See attached document Figure 2 In this embodiment, the steady-state gating discrimination module 300 is configured as a condition identification unit in the digital control system. Its core function is to construct a "steady-state window" that only opens when the system is in a steady state by analyzing the statistical characteristics of key system variables. Its basic control principle lies in the fact that the energy efficiency adaptive correction module 400 relies on loss proxy variables... Simultaneously affected by changes in load power and energy efficiency, with the magnitude of load changes being far greater than the small changes caused by energy efficiency optimization, it is essential to ensure the system operates under steady-state conditions with constant load and input, eliminating interference from macroscopic dynamic processes to guarantee the optimal values ​​observed by subsequent extreme value search algorithms. The change stems solely from the energy efficiency alteration resulting from timing adjustments. The steady-state gating discrimination module 300 specifically includes:

[0095] S310 constructs a sliding statistical window and data cache. The steady-state gating discrimination module 300 is internally configured with a length of... A first-in-first-out (FIFO) circular buffer queue is used to store the most recently used data in real time. Output voltage error within each control cycle and voltage loop regulation The data sequence. Window length. The value of must be strictly designed to be an integer multiple of the second harmonic ripple period of the output voltage. For 50Hz or 60Hz AC input systems, the PFC output voltage exhibits a low-frequency ripple of 100Hz or 120Hz. This embodiment will... The number of switching cycles is set to correspond to half a power frequency cycle (i.e., 10ms or 8.33ms). This design ensures that the sliding window always covers the complete ripple cycle, allowing the average value calculation within the window to automatically cancel out the periodic ripple component, thereby obtaining an accurate DC component.

[0096] S320 calculates steady-state discrimination statistical features. After updating the buffer queue in each control cycle, the steady-state gating discrimination module 300 calculates two key statistical features: the average value of the output voltage error. and the fluctuation range of voltage loop regulation .

[0097] Average output voltage error The formula used to characterize whether the output voltage converges to the target value is:

[0098] ;

[0099] In the formula, The length of the sliding window. This is the historical voltage error data stored in the buffer queue.

[0100] Fluctuation amplitude of voltage loop regulation The stability of the system's internal energy balance is characterized by the range of data within a calculation window, and the calculation formula is as follows:

[0101] ;

[0102] In the formula, and These represent the maximum and minimum values ​​extracted from the data within the window, respectively. This indicator can promptly reflect the control quantity adjustment process caused by load fluctuations.

[0103] S330 performs dual threshold discrimination and status flag generation. The calculated statistical features are compared with preset thresholds to generate an optimized enable flag. The judgment logic is as follows:

[0104] Set voltage error allowable threshold This threshold is determined based on the system's static voltage regulation rate, and is typically set to the rated output voltage. 1% to 2%.

[0105] Set the allowable threshold for control quantity fluctuations The specific calibration method for this threshold is as follows: The system is operated in open-loop or closed-loop steady-state mode under rated load, and the values ​​under this state are measured. The natural peak-to-peak noise within the sliding window period will The value is set to 1.2 to 1.5 times the measured noise level. This setting ensures that background noise in steady state will not trigger transient misjudgments, while also being able to identify the smallest load step change whose amplitude exceeds the background noise.

[0106] If and only if satisfying and When both conditions are met, the system determines that it is currently in a steady-state condition and will optimize the enable flag. Set to 1; otherwise, determine that the system is in a transient condition and optimize the enable flag. Set to 0.

[0107] S340, execute the state freeze and protection mechanism. This step defines the control permissions of the steady-state gating discrimination module 300 over subsequent modules. When At this time, the subsequent energy efficiency adaptive correction module is allowed to update the control parameters based on real-time data. At this time, the state freeze mechanism is triggered, forcing the subsequent energy efficiency adaptive correction module to stop iterative updates, and the output timing correction coefficients are changed. Reset and hold to 1.0 (i.e., using only the theoretical model value) or hold to the converged value from the previous steady-state time. This mechanism physically prevents voltage loop regulation during load dynamic response. The large fluctuations were misjudged as changes in energy efficiency, thus avoiding the risk of system instability caused by the divergence of control parameters.

[0108] See attached document Figure 2 In this embodiment, the energy efficiency adaptive correction module 400 is configured as an optimized controller operating on a slow timescale (update cycle set to 100ms to 500ms). Its design aims to address the thermal drift problem of power magnetic components: when the PFC converter operates under high load for extended periods, the increased temperature of the saturated inductor core leads to a decrease in its permeability, thereby reducing the actual inductance value. The deviation from the initial calibration value will cause the auxiliary branch to fail to complete the charge transfer required for zero-voltage turn-on (ZVS) within the predetermined time if the fixed parameters are still used. Therefore, the core function of the energy efficiency adaptive correction module 400 is to use the extreme value search algorithm (ESC) to correct the timing correction coefficients online within the steady-state window determined by the aforementioned steady-state gating discrimination module. By utilizing the asymmetric loss characteristics formed by the unidirectional blocking mechanism of the blocking diode in the hardware circuit, the system is always maintained at the optimal operating point where soft-switching losses are minimized. The energy efficiency adaptive correction module 400 specifically includes:

[0109] S410, construct the loss cost function based on the voltage loop regulation. Since the digital control system in this embodiment adopts a dual-loop control architecture, under the steady-state condition locked by the steady-state gate discrimination module, the output voltage... Clamped to the reference value, output power Constant. At this point, the input power... With total system losses They exhibit a linear positive correlation. The given reference value for the input current is regulated by the voltage loop. Decision, therefore The value directly reflects the amount of input energy required to maintain that output power.

[0110] The energy efficiency adaptive correction module 400 constructs a cost function for extreme value search. It is defined as the current search period. The average value of the voltage loop regulation within the circuit is calculated using the following formula:

[0111] ;

[0112] In the formula, This is the index of the iteration steps of the extreme value search algorithm; The number of switching cycle samples included within a single search step must be selected to cover at least one half-power frequency cycle of the AC input (i.e., 10ms or 8.33ms) to completely filter out... The inherent second harmonic ripple is prevented from interfering with gradient calculation. For the first The voltage loop regulation amount of the next sample. This cost function. It exhibits a positive monotonically correlated relationship with system losses and serves as the objective function for optimizing system energy efficiency.

[0113] S420 utilizes the unidirectional characteristics of hardware to establish an asymmetric search strategy. To address the risk of reverse current backflow and oscillation caused by parameter disturbances in traditional ZVT control, this embodiment utilizes the unidirectional conduction characteristic of the blocking diode D2 connected in series in the auxiliary branch to construct a parameter-optimized asymmetric protection mechanism.

[0114] The physical mechanism is as follows: Loss Cost Function Relative to lead time It exhibits asymmetric convex function characteristics.

[0115] when If the time is too short (undercompensated region), the main switch cannot achieve zero-voltage turn-on, resulting in a huge capacitor turn-on loss (0.5CV). 2 ),lead to Follow It decreases and then rises sharply, with a maximum gradient.

[0116] when When the time is too long (beyond the compensation region), the auxiliary branch current attempts to flow in the reverse direction after resonance is achieved, but it is blocked by diode D2, and the current remains zero until the main switch is turned on. At this time, only a small amount of auxiliary switch conduction loss is added. Follow It increases slowly, with a very small and gentle gradient.

[0117] See attached document Figure 7 The figure reveals the physical basis of the asymmetric search strategy employed in this invention, namely the system loss cost function. Relative to lead time The nonlinear relationship.

[0118] like Figure 7 As shown, the curve exhibits a significant asymmetry. The left side of the curve represents the "undercompensated region," where insufficient time leads to hard switching, causing losses to increase exponentially. The lowest point of the curve corresponds to the "optimal energy efficiency operating point." The right side of the curve represents the "overcompensated region," where the invention incorporates a blocking diode D2 in series to cut off the reverse recovery current, resulting in losses increasing only linearly and very slowly over time (adding only a small amount of auxiliary conduction loss).

[0119] Based on this characteristic, the energy efficiency adaptive correction module 400 of the present invention sets the initial search point in the overcompensated region on the right side of the curve and searches to the left along the gradient descent direction. This strategy utilizes the gentle "safe region" on the right side, effectively preventing the algorithm from accidentally entering the high-risk "hard switching region" on the left side during the iteration process.

[0120] Based on this asymmetric characteristic, the algorithm will adjust the timing correction coefficients. The initial value is set in the overcompensation region (usually set to 1.1 to 1.3) to ensure that the search process always approaches the "optimal energy efficiency point" from the side where "loss increases slightly due to excessive conduction time", avoiding the high stress risk of directly triggering hard switching due to initialization in the undercompensation region.

[0121] S430 performs perturbation injection and gradient estimation. In the... In the next iteration cycle, the module uses the current baseline timing correction coefficient. On top of that, add a small perturbation. Outputs the actual test coefficients used to drive the generation. .

[0122] Disturbance The value range is set to 0.01 to 0.05 (i.e., an adjustment range of 1% to 5%). The selection principle for this range is: it should be sufficient to cause an observable change in system losses (i.e., reflected in...). The change in the input current must be greater than the system's detection noise floor, but also small enough to avoid causing significant input current distortion.

[0123] Subsequently, the energy efficiency adaptive correction module 400 reads the cost function value under the action of the test coefficient. The loss gradient is then calculated by combining the state from the previous cycle. The calculation formula is:

[0124] ;

[0125] In the formula, and These are the cost function values ​​for the current period and the previous period, respectively; and These are the corresponding test coefficients.

[0126] S440, iteratively update the timing correction coefficients. Based on the calculated loss gradient, the timing correction coefficients are updated using gradient descent to drive the system operating point towards the loss minimum. The update iteration law is as follows:

[0127] ;

[0128] In the formula, This serves as the reference timing correction factor for the next cycle; This is the gain coefficient for the iteration step size. The value is usually set between 0.01 and 0.1, and its specific value needs to be related to the cost function. The dimensions are matched. In this embodiment, for Normalization or piecewise assignment is used: when the gradient When it is large, decrease Values ​​to prevent overshoot oscillations; when gradient When smaller, maintain the rated The value is used to maintain the convergence rate.

[0129] At the same time, Set hard upper and lower limit saturation constraints (set range is [0.8, 1.5]) to prevent parameters from diverging beyond the allowable range of the physical model due to external transient disturbances, and ensure that the controller output is always within the effective operating range.

[0130] See attached document Figure 6This figure demonstrates the actual operating performance of the energy efficiency adaptive correction module 400 under steady-state conditions. The left vertical axis of the figure represents the timing correction coefficient. The right vertical axis represents the voltage loop regulation, which characterizes system losses. .

[0131] like Figure 6 As shown, in the early stage of iteration (n<20), the timing correction coefficients are... Starting with an initial conservative value (approximately 1.3), the value is gradually reduced under the drive of an extremum search algorithm. Simultaneously, the voltage loop regulation... The synchronous downward trend indicates that the input energy required to maintain the same output power is decreasing, meaning that the total system loss is decreasing.

[0132] After approximately 30 iterations, the system automatically searches for and locks onto the optimal energy efficiency point (as shown in the figure). Approximately 1.05, (Reaching the minimum value). This result strongly demonstrates that the present invention can compensate for component parameter drift in real time without relying on additional sensors, ensuring that the circuit always operates in an optimal energy-efficiency state.

[0133] Through the above steps, the energy efficiency adaptive correction module 400 can automatically compensate for aging, temperature drift and batch differences of power stage components without the need for any additional current / temperature sensors, relying only on software logic and existing voltage loop data.

[0134] See attached document Figure 2 In this embodiment, the drive signal generation module 500 is configured as the final execution unit of the digital control system. It is responsible for converting the digital timing parameters calculated upstream into physical PWM (pulse width modulation) level signals to drive the power switching devices. The drive signal generation module 500 coordinates the action sequence of the main switch T and the auxiliary switch T1 through high-precision timing synthesis logic, ensuring that the voltage across the main switch T has resonated to zero or close to zero at the moment the main switch is turned on, thereby achieving zero voltage transition (ZVT).

[0135] See attached document Figure 4 The figure illustrates the key waveform timing of this invention during a complete soft-switching cycle. From top to bottom, the figures show the auxiliary switch drive signals. Auxiliary branch current Main switch drain-source voltage and main switch drive signal .

[0136] like Figure 4 As shown, around time t=10ns, the auxiliary switch drive signal First, the circuit is set to high, and auxiliary switch T1 is turned on. At this time, the auxiliary branch current... The current begins to rise, exhibiting a clear "gradual then steep" waveform, corresponding to the physical process of the saturated inductor transitioning from the linear region (high impedance) to the saturation region (low impedance). As the current surges, the resonant process is triggered, and the drain-source voltage of the main switch... It decreases in a cosine pattern.

[0137] It is worth noting that around time t=50ns, which is marked as the "ZVS time" in the figure, The voltage has resonated and dropped to zero potential. At this point, the drive signal generation module 500 outputs the main switch drive signal. The high level ensures that the main switch T is turned on under zero-voltage conditions, thus completely eliminating turn-on losses. (See diagram) and The time difference between rising edges is the actual lead time. The drive signal generation module 500 specifically includes:

[0138] S510 synthesizes the actual lead time parameters. The drive signal generation module 500 receives the basic lead time from the fast-scale timing calculation module 200. And timing correction coefficients from the energy efficiency adaptive correction module .because It is an ideal value calculated based on a theoretical model, while Including correction information for actual circuit parameter drift, the drive signal generation module 500 first performs parameter synthesis calculation to obtain the actual lead time required for the current switching cycle. The calculation formula is:

[0139] ;

[0140] In the formula, This is the lead-on time control quantity that is ultimately applied to the hardware timing logic; These are the base time values ​​calculated based on the piecewise linearization model; This refers to the dimensionless correction coefficients updated based on the extreme value search algorithm. This multiplication operation achieves the decoupling and fusion of feedforward control and feedback optimization.

[0141] To generate accurate timing waveforms in the digital microcontroller, this embodiment converts time quantities into digital counter count values. The high-frequency PWM clock period of the microcontroller is set to... The corresponding maximum count value of the counter (i.e., the switching cycle) is The on-time of the main PWM signal is determined by the duty cycle calculated from the main voltage loop, and the corresponding counter comparison value is... .

[0142] Based on this, the drive signal generation module 500 calculates the counter comparison value of the opening time of the auxiliary switch T1. and the comparison value of the turn-off time counter The mapping logic for when the auxiliary function is activated is as follows:

[0143] ;

[0144] If the above calculation results This indicates that the auxiliary switch is activated at the end of the previous switching cycle. In this case, the embodiment performs cycle loop processing, and the calculation formula is as follows:

[0145] ;

[0146] The mapping logic for the auxiliary shutdown time is as follows:

[0147] ;

[0148] In the formula, The preset main and auxiliary switch overlap conduction time; This is the clock resolution for the PWM peripheral.

[0149] S530 generates the interlock timing and physical drive waveforms. Based on the comparison value calculated above, the drive signal generation module 500 controls the output level of the PWM generator to flip, generating the main drive signal. With auxiliary drive signal The specific waveform logic control is divided into the following three physical stages:

[0150] First stage (resonance establishment stage): When the counter reaches... At this time, set the auxiliary drive signal high. Auxiliary switch T1 is turned on. At this time, the inductor current quickly transfers to the auxiliary branch and resonates with the resonant capacitor, forcing the drain-source voltage across the main switch to increase. It has begun to descend.

[0151] Second stage (zero voltage conduction stage): When the counter reaches... When, set the main drive signal high. The main switch T is turned on. At this time, after the aforementioned... During the long resonance process, the voltage across the main switch drops to zero, achieving zero-voltage turn-on and eliminating turn-on losses.

[0152] Phase 3 (Auxiliary Shutdown and Reset Phase): When the counter reaches... At that time, pull down the auxiliary drive signal. Auxiliary switch T1 is turned off. In this embodiment, the overlap time... The parameter is typically set to 50ns to 100ns. The physical meaning of this parameter setting is that, considering the turn-on delay of power devices and the transmission delay of drive signals, the auxiliary switch T1 can only be turned off after the main switch T has fully established a conduction channel at the physical level, thereby preventing the auxiliary branch from being disconnected prematurely due to signal jitter, which would cause current discontinuity and voltage spikes.

[0153] Finally, the generated logic level signal is amplified by the power drive circuit and then drives the gates of the main switch T and the auxiliary switch T1 respectively, completing a complete soft-switching control cycle.

[0154] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An active ZVT-Boost PFC circuit with saturated inductor, characterized in that, Includes power stage circuitry and digital control systems; The power stage circuit includes a main power circuit and an active ZVT auxiliary branch; the main power circuit is configured as a Boost topology; the active ZVT auxiliary branch is coupled in parallel to the main switching device of the main power circuit, and the active ZVT auxiliary branch includes a saturated inductor, a blocking diode, and an auxiliary switching device connected in series; the blocking diode is configured to allow current to flow only from the saturated inductor to the auxiliary switching device; The digital control system includes a signal acquisition module, a fast-scale timing calculation module, a steady-state gating discrimination module, an energy efficiency adaptive correction module, and a drive signal generation module; The fast-scale timing calculation module is configured to calculate the basic lead-on time based on a piecewise linearized model of the saturated inductor. The saturated inductor's core has piecewise nonlinear impedance characteristics. The saturated inductor is configured to have the following characteristics: when the absolute value of the current flowing through the saturated inductor is less than the saturation current threshold, the saturated inductor exhibits a linear region inductance value; when the absolute value of the current flowing through the saturated inductor is greater than the saturation current threshold, the saturated inductor exhibits a saturation region inductance value; the linear region inductance value is greater than the saturation region inductance value. The fast-scale timing calculation module has a pre-built lookup table storing the corresponding relationships calculated based on the piecewise linearized model of the saturated inductor. The fast-scale timing calculation module is configured to obtain the corresponding basic lead-on time from the lookup table based on the real-time sampled main input current. The piecewise linearized model is a model established based on the linear region inductance value, the saturation region inductance value, and the saturation current threshold. The steady-state gating discrimination module is configured to identify the load steady-state operating condition of the PFC circuit and generate an optimized enable signal; The energy efficiency adaptive correction module is configured to adjust the timing correction coefficient by using the voltage loop adjustment as the basis for loss observation in response to the optimization enable signal. The drive signal generation module is configured to synthesize the actual lead time based on the basic lead time and the timing correction coefficient, and output a drive signal to control the auxiliary switching device to turn on before the main switching device.

2. The ZVT-Boost type PFC circuit with active saturated inductor according to claim 1, characterized in that, The main power circuit includes a boost inductor, the main switching device, a boost diode, and an output capacitor; The positive terminal of the input voltage source is connected to one end of the boost inductor, and the other end of the boost inductor is connected to the drain of the main switching device and the anode of the boost diode; the cathode of the boost diode is connected to the positive terminal of the output capacitor.

3. The ZVT-Boost type PFC circuit with active saturated inductor according to claim 2, characterized in that, The active ZVT auxiliary branch also includes a resonant capacitor and a clamping diode; The resonant capacitor is connected in parallel between the drain of the main switching device and the source of the main switching device. One end of the saturated inductor is connected to the common connection point of the boost inductor and the main switching device, and the other end of the saturated inductor is connected to the anode of the blocking diode; the cathode of the blocking diode is connected to the drain of the auxiliary switching device. The anode of the clamping diode is connected to the common node of the cathode of the blocking diode and the drain of the auxiliary switching device, and the cathode of the clamping diode is connected to the positive terminal of the output capacitor.

4. The ZVT-Boost type PFC circuit with active saturated inductor according to claim 1, characterized in that, The steady-state gating discrimination module is configured to receive the output voltage and the voltage loop adjustment, calculate the statistical feature quantity within the set window, and compare the statistical feature quantity with the preset threshold to identify whether the PFC circuit is in the load steady-state condition. The steady-state gating discrimination module is configured to send the optimization enable signal to the energy efficiency adaptive correction module to allow the timing correction coefficient to be updated when the PFC circuit is identified as being in the steady-state load condition.

5. The ZVT-Boost type PFC circuit with active saturated inductor according to claim 4, characterized in that, The statistical characteristics include the average output voltage error and the fluctuation range of the voltage loop regulation. The steady-state gating discrimination module is configured to determine that the PFC circuit is in the load steady-state condition only when the average value of the output voltage error is less than the allowable threshold for voltage error and the fluctuation amplitude of the voltage loop regulation is less than the allowable threshold for control fluctuation.

6. The ZVT-Boost type PFC circuit with active saturated inductor according to claim 1, characterized in that, The energy efficiency adaptive correction module is configured to update the time-series correction coefficients using an extreme value search algorithm; The energy efficiency adaptive correction module is configured to construct a cost function with the average value of the voltage loop regulation as the objective, and to superimpose a disturbance on the current timing correction coefficient. Based on the gradient of the change of the cost function, the timing correction coefficient for the next control cycle is calculated to drive the voltage loop regulation to converge toward the minimum value.

7. The ZVT-Boost type PFC circuit with active saturated inductor according to claim 6, characterized in that, The energy efficiency adaptive correction module is configured to use an asymmetric search strategy; The energy efficiency adaptive correction module is configured to set the initial value of the timing correction coefficient in the overcompensated region, where the overcompensated region is defined as the time interval during which the conduction time of the auxiliary switching device is greater than the ideal resonant period; the energy efficiency adaptive correction module is configured to control the timing correction coefficient to search and update from the overcompensated region to the undercompensated region.

8. The ZVT-Boost type PFC circuit with active saturated inductor according to claim 1, characterized in that, The drive signal generation module is configured to perform parameter synthesis calculation, multiplying the basic lead conduction time by the timing correction coefficient to obtain the actual lead conduction time; The drive signal generation module is further configured to map the actual lead-on time to the count value of a digital counter, and generate a main drive signal and an auxiliary drive signal with interlocking logic.

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