Parallel three-level boost circuit device

Abstract

The three-level boost circuit module comprises a first boost circuit and a second boost circuit which are connected in parallel, and each of the first boost circuit and the second boost circuit comprises an output control module and an energy storage module which are connected in series; the output control module comprises an output switch sub-module and an output capacitor sub-module which are connected in parallel, the output switch sub-module comprises a positive half switch unit and a negative half switch unit which are sequentially connected in series, and the output capacitor sub-module comprises a positive half diode, a positive half output capacitor, a negative half output capacitor and a negative half diode which are sequentially connected in series; the energy storage module comprises a positive half energy storage inductor and a negative half energy storage inductor, the positive half energy storage inductor is connected with the output control module and the positive electrode of the direct-current power supply, the negative half energy storage inductor is connected with the output control module and the negative electrode of the direct-current power supply, and the output end of the positive half switch unit of the second booster circuit is connected with the negative electrode of the positive half output capacitor of the second booster circuit. The problem that the output bus voltage of an existing single three-level booster circuit is unstable can be solved.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a parallel three-level boost circuit device. Background Technology

[0002] Traditional parallel connection of multiple three-level boost circuit modules (such as Figure 1 As shown in the diagram, due to the unequal duty cycles or loads of the two power switches within a single three-level boost circuit module (R1≠R2), the currents of the two input inductors within each module become unequal (i.e., I1≠I2, I3≠I4), or even deviate significantly, causing current runaway. This, in turn, leads to unequal voltages between the positive and negative output bus capacitors (i.e., U...). C1 ≠U C2 This reduces the stability of the output bus voltage of the three-level boost circuit module. Summary of the Invention

[0003] This application provides a parallel three-level boost circuit device, which can solve the problem that the positive half-bus capacitor voltage and the negative half-bus capacitor voltage output by the existing three-level boost circuit device are not equal (i.e., U... C1 ≠U C2 This reduces the stability of the output bus voltage of the three-level boost circuit module.

[0004] In a first aspect, this application provides a parallel three-level boost circuit device, comprising: A first boost circuit and a second boost circuit are connected in parallel, and both the first boost circuit and the second boost circuit include an output control module and an energy storage module connected in series. The output control module includes an output switch submodule and an output capacitor submodule connected in parallel. The output switch submodule includes a positive half switch unit and a negative half switch unit connected in series. The output capacitor submodule includes a positive half diode, a positive half output capacitor, a negative half output capacitor, and a negative half diode connected in series. The energy storage module includes a positive half-energy storage inductor and a negative half-energy storage inductor. The positive half-energy storage inductor is connected to the positive terminal of the output control module and the DC power supply, and the negative half-energy storage inductor is connected to the negative terminal of the output control module and the DC power supply. The output terminal of the positive half-switching unit of the second boost circuit is connected to the negative terminal of the positive half-output capacitor of the second boost circuit. The boost control drive module is connected to the first boost circuit and the second boost circuit, and is used to adjust the duty cycle of the positive half-switching unit and the negative half-switching unit.

[0005] In some embodiments, the output control module further includes an input capacitor, the two ends of which are connected to the positive and negative terminals of the DC power supply, respectively.

[0006] In some embodiments, the boost control drive module includes: The conditioning circuit has its input terminal connected to the first boost circuit and the second boost circuit, and is used to collect the positive half energy storage inductor current of the first boost circuit, the positive half energy storage inductor current of the second boost circuit, the positive half output capacitor voltage of the first boost circuit, and the negative half output capacitor voltage of the first boost circuit. The control submodule is connected to the output of the conditioning circuit and is used to receive and calculate and output the voltage regulation duty cycle signal and the current sharing duty cycle signal based on the first positive half-inductor current sampling value, the second positive half-inductor current sampling value, the first positive half-capacitor voltage sampling value and the first negative half-capacitor voltage sampling value output by the conditioning circuit. The drive submodule, connected to the control submodule and the positive half-switch unit and the negative half-switch unit, is used to receive and generate the voltage regulation drive signal and the current sharing drive signal based on the voltage regulation duty cycle signal and the current sharing duty cycle signal; The voltage regulation drive signal is used to control the on / off state of the positive half-switching unit and the negative half-switching unit in the first boost circuit, and the current sharing drive signal is used to control the on / off state of the positive half-switching unit in the second boost circuit.

[0007] In some embodiments, the control submodule includes: A voltage and current dual closed-loop controller is connected to the output terminal of the conditioning circuit. It is used to receive, calculate and output the voltage regulation duty cycle signal based on the sampled value of the first positive half-inductor current, the sampled value of the first positive half-capacitor voltage and the sampled value of the first negative half-capacitor voltage. An input current sharing controller is connected to the output terminal of the conditioning circuit and is used to receive, calculate and output the original current sharing duty cycle signal based on the first positive half-inductor current sampling value and the second positive half-inductor current sampling value. An external current sharing adder is connected to the output terminals of the voltage and current dual closed-loop controller and the input current sharing controller. It is used to add the voltage regulation duty cycle signal to the original current sharing duty cycle signal to obtain the current sharing duty cycle signal.

[0008] In some embodiments, the voltage and current dual closed-loop controller includes: The first voltage regulator adder is used to receive and add the sampled value of the first positive half-capacitor voltage to the sampled value of the first negative half-capacitor voltage to obtain the bus voltage sampled value. The first voltage regulator subtractor, connected to the first voltage regulator adder, is used to receive and subtract the bus voltage reference value from the bus voltage sample value to obtain the bus voltage error signal. The first voltage-stabilized PI regulator, connected to the first voltage-stabilized subtractor, is used to receive and output a given current reference value based on the bus voltage error signal; The second voltage regulator subtractor, connected to the first voltage regulator PI controller, is used to receive and subtract the given current reference value from the sampled value of the first positive half-inductor current to obtain the given current error signal. The second voltage-regulating PI regulator, connected to the voltage-regulating subtractor, is used to receive and output the voltage-regulating duty cycle signal based on the given current error signal.

[0009] In some embodiments, the input current sharing controller includes: An internal current sharing subtractor is used to receive and subtract the sampled value of the first positive half-inductor current from the sampled value of the second positive half-inductor current to obtain a current difference signal. A current sharing PI regulator, connected to the internal current sharing subtractor, is used to receive and output the original current sharing duty cycle signal based on the current difference signal.

[0010] In some embodiments, the control submodule further includes: A midpoint voltage balance controller, connected to the output of the conditioning circuit, is used to receive and calculate and output the original voltage balance duty cycle signal based on the first positive half-capacitor voltage sample value and the first negative half-capacitor voltage sample value. A voltage balancing adder, connected to the output of the external current sharing adder and the midpoint voltage balancing controller, is used to add the current sharing duty cycle signal to the original voltage balancing duty cycle signal to obtain a voltage balancing duty cycle signal.

[0011] In some embodiments, the midpoint voltage balance controller includes: The first voltage balance subtractor is used to receive and subtract the sampled value of the first positive half-capacitor voltage from the sampled value of the first negative half-capacitor voltage to obtain the positive and negative voltage error signal. The second voltage balance subtractor is connected to the first voltage balance subtractor and is used to receive and subtract the positive and negative voltage error reference value signal from the positive and negative voltage error signal to obtain the midpoint balance error signal. A voltage balance PI regulator, connected to the first voltage balance subtractor, is used to receive and output the original voltage balance duty cycle signal based on the midpoint balance error signal.

[0012] In some embodiments, the driver submodule includes: The PWM generator is connected to the output terminals of the voltage and current dual closed-loop controller, the external current sharing adder, and the voltage balance adder. It is used to receive and generate voltage regulation pulse control signal, current sharing pulse control signal, and voltage balance pulse control signal based on the voltage regulation duty cycle signal, the current sharing duty cycle signal, and the voltage balance duty cycle signal. The driving circuit is connected at one end to the PWM generator and at the other end to the positive half-switching unit and the negative half-switching unit. It is used to receive and generate the voltage regulation driving signal, the current sharing driving signal and the voltage balance driving signal based on the voltage regulation pulse control signal, the current sharing pulse control signal and the voltage balance pulse control signal. The voltage balance drive signal is used to control the on / off state of the negative half-switch unit in the second boost circuit.

[0013] In some embodiments, the positive half-switching unit and the negative half-switching unit each include a switching transistor and an anti-parallel diode connected in reverse parallel with the switching transistor.

[0014] The technical solutions provided in this application have the following advantages compared with the prior art: The three-level boost circuit module provided in this application includes a first boost circuit and a second boost circuit connected in parallel. Both the first and second boost circuits include an output control module and an energy storage module connected in series. The output control module includes an output switch submodule and an output capacitor submodule connected in parallel. The output switch submodule includes a positive half-switch unit and a negative half-switch unit connected in series. The output capacitor submodule includes a positive half-diode, a positive half-output capacitor, a negative half-output capacitor, and a negative half-diode connected in series. The energy storage module includes a positive half-energy storage inductor and a negative half-energy storage inductor. The positive half-energy storage inductor is connected to the output control module and the positive terminal of the DC power supply, and the negative half-energy storage inductor is connected to the output control module and the positive terminal of the DC power supply. The module is connected to the negative terminal of the DC power supply. The output terminal of the positive half-switching unit of the second boost circuit is connected to the negative terminal of the positive half-output capacitor of the second boost circuit. That is, the output terminal of the positive half-switching unit of the first boost circuit is not connected to the negative terminal of the positive half-output capacitor of the first boost circuit. This allows for simultaneous control of the positive and negative half-switching units of the first boost circuit. This solves the problem that in existing single three-level boost circuit modules, the duty cycles or loads of the two power switches are unequal, causing unequal currents in the two input inductors within each module, resulting in current runaway. Consequently, the output positive half-bus capacitor voltage and the negative half-bus capacitor voltage are unequal, reducing the stability of the output bus voltage of the three-level boost circuit module. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 A diagram of an existing parallel three-level boost circuit is provided for one embodiment of this application; Figure 2 A parallel three-level boost circuit diagram provided in one embodiment of this application; Figure 3 This is a schematic diagram of a conditioning circuit provided in one embodiment of this application; Figure 4 A schematic diagram of a three-level boost circuit control strategy (boost control drive module) provided in an embodiment of this application; Figure 5 This is a schematic diagram of a three-level boost circuit device provided in an embodiment of this application; Figure 6 This is a schematic diagram of a PWM generator provided in one embodiment of this application; Figure 7 DC power supply voltage U provided in an embodiment of this application BAT The waveform is at 120V. Figure 8 DC power supply voltage U provided in one embodiment of this application BAT Waveform at 150V; Figure 9 DC power supply voltage U provided in an embodiment of this application BAT The waveform is at 180V. Figure 10 DC power supply voltage U provided in one embodiment of this application BAT Waveform diagram when the voltage is 150V and the load changes; Attached image description: 10. Conditioning circuit; 20. Control Submodule; 210. Voltage and current dual closed-loop controller; 2101. First voltage regulator adder; 2102. First voltage regulator subtractor; 2103. First voltage regulator PI regulator; 2104. Second voltage regulator subtractor; 2105. Second voltage regulator PI regulator; 220. Input current sharing controller; 2201. Internal current sharing subtractor; 2202. Current sharing PI regulator; 230. Midpoint voltage balance controller; 2301. First voltage balance subtractor; 2302. Second voltage balance subtractor; 2303. Voltage balance PI regulator; 240. External current equalization adder; 250. Voltage Balance Adder 30. Driver submodule; 310. PWM generator; 320. Driver circuit Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0021] For ease of description, spatial relative terms may be used in the text to describe the relative position or movement of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "front," "back," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure undergoes a positional flip, orientation change, or change of motion, these directional indications will change accordingly. For instance, an element described as "below other elements or features" or "below other elements or features" will subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0022] Three-level boost circuits are often connected to the battery side of a power converter system (PCS) to boost the battery voltage. Their output serves as the input of the subsequent inverter. As the power of the PCS increases, the demand for three-level boost circuit systems with parallel input and output sides powered by the same set of batteries is growing.

[0023] In a device consisting of multiple three-level boost circuit modules connected in parallel, such as Figure 1 As shown, because the duty cycles of the two power switches in a single three-level boost circuit module are not equal or the loads are not equal (R1≠R2), the input inductor currents between modules will be unequal (i.e., I1≠I3) and the two input inductor currents within each module will be unequal (i.e., I1≠I2, I3≠I4), even with large deviations, causing current runaway. Simultaneously, this leads to unequal voltages between the positive and negative output bus capacitors (i.e., U...). C1 ≠U C2 This will reduce the stability and reliability of the system, and thus affect the output of the subsequent inverter circuit.

[0024] Therefore, it is necessary to propose a new type of parallel three-level boost circuit based on the traditional parallel three-level boost circuit. This new circuit retains the advantages of the traditional parallel three-level boost circuit and solves the problems of unequal input inductor currents between modules due to unequal duty cycles or loads of the two power switches in a single three-level boost circuit module, unequal input inductor currents within each module, and unbalanced voltages of the positive and negative output bus capacitors.

[0025] Firstly, such as Figure 1-10 As shown, to address the aforementioned technical problems, this application provides a parallel three-level boost circuit device, comprising: The first boost circuit and the second boost circuit are connected in parallel. Both the first boost circuit and the second boost circuit include an output control module and an energy storage module connected in series. The output control module includes an output switch submodule and an output capacitor submodule connected in parallel. The output switch submodule includes a positive half switch unit and a negative half switch unit connected in series. The output capacitor submodule includes a positive half diode, a positive half output capacitor, a negative half output capacitor, and a negative half diode connected in series. The energy storage module includes a positive half-energy storage inductor and a negative half-energy storage inductor. The positive half-energy storage inductor is connected to the positive terminal of the output control module and the DC power supply, and the negative half-energy storage inductor is connected to the negative terminal of the output control module and the DC power supply. The output terminal of the positive half-switching unit of the second boost circuit is connected to the negative terminal of the positive half-output capacitor of the second boost circuit. The boost control drive module is connected to the first boost circuit and the second boost circuit, and is used to adjust the duty cycle of the positive half-switching unit and the negative half-switching unit.

[0026] It should be noted that, as Figure 2 As shown, the first boost circuit is Boost circuit 1, the second boost circuit is Boost circuit 2, the positive half switching unit of the first boost circuit is the first switching unit S1, the negative half switching unit of the first boost circuit is the second switching unit S2, the positive half diode of the first boost circuit is the fifth diode D5, the negative half diode of the first boost circuit is the sixth diode D6, the positive half output capacitor of the first boost circuit is the third output capacitor C3, the negative half output capacitor of the first boost circuit is the fourth output capacitor C4, the positive half energy storage inductor of the first boost circuit is the first energy storage inductor L1, the negative half energy storage inductor of the first boost circuit is the second energy storage inductor L2; the positive half switching unit of the second boost circuit is the third switching unit S2. Unit S3, the negative half switch unit of the second boost circuit is the fourth switch unit S4, the positive half diode of the second boost circuit is the seventh diode D7, the negative half diode of the second boost circuit is the eighth diode D8, the positive half output capacitor of the second boost circuit is the fifth output capacitor C5, the negative half output capacitor of the second boost circuit is the sixth output capacitor C6, the positive half energy storage inductor of the second boost circuit is the third energy storage inductor L3, and the negative half energy storage inductor of the second boost circuit is the fourth energy storage inductor L4. Among them, the first energy storage inductor L1 = the second energy storage inductor L2 = the third energy storage inductor L3 = the fourth energy storage inductor L4, the third output capacitor C3 = the fourth output capacitor C4 = the fifth output capacitor C5 = the sixth output capacitor C6.

[0027] It should be noted that in the first boost circuit (i.e., Boost circuit 1), the DC power supply U BAT The positive terminal of the first energy storage inductor L1 is connected to the left end, and the right end of the first energy storage inductor L1 is connected to the drain of the first switching unit S1 and the anode of the fifth diode D5; the source of the first switching unit S1 is connected to the drain of the second switching unit S2, the source of the second switching unit S2 is connected to the right end of the second energy storage inductor L2, and the left end of the second energy storage inductor L2 is connected to the DC power supply U. BAT The negative terminal of the fifth diode D5 is connected to the upper end of the third output capacitor C3, the lower end of the third output capacitor C3 is connected to the upper end of the fourth output capacitor C4, the lower end of the fourth output capacitor C4 is connected to the anode of the sixth diode D6, the cathode of the sixth diode D6 is connected to the right end of the second energy storage inductor L2, and the cathode of the sixth diode D6 is connected to the source of the second switching unit S2.

[0028] It should be noted that in the second boost circuit (i.e., Boost circuit 2), the DC power supply U BAT The positive terminal of the third energy storage inductor L3 is connected to the left end of the third energy storage inductor L3, and the right end of the third energy storage inductor L3 is connected to the drain of the third switching unit S3 and the anode of the seventh diode D7; the source of the third switching unit S3 is connected to the drain of the fourth switching unit S4, the source of the fourth switching unit S4 is connected to the right end of the fourth energy storage inductor L4, and the left end of the fourth energy storage inductor L4 is connected to the DC power supply U. BAT The negative terminal of the seventh diode D7 is connected to the upper end of the fifth output capacitor C5, the lower end of the fifth output capacitor C5 is connected to the upper end of the sixth output capacitor C6, the lower end of the sixth output capacitor C6 is connected to the anode of the eighth diode D8, the cathode of the eighth diode D8 is connected to the right end of the fourth energy storage inductor L4, and the cathode of the eighth diode D8 is connected to the source of the fourth switching unit S4.

[0029] It should be noted that the cathode of the fifth diode D5 in Boost circuit 1, the upper end of the third output capacitor C3, and the upper end of the load R1 are connected to the cathode of the seventh diode D7 and the upper end of the fifth output capacitor C5 in Boost circuit 2, which constitutes the output voltage U. BUS The positive terminal; the anode of the sixth diode D6 in Boost circuit 1, the lower end of the fourth output capacitor C4, and the lower end of the load R2 are connected to the anode of the eighth diode D8 in Boost circuit 2 and the lower end of the sixth output capacitor C6, which is the output bus voltage U. BUS The negative terminal; the lower end of the third output capacitor C3, the upper end of the fourth output capacitor C4, the lower end of the load R1, the upper end of the load R2 in Boost circuit 1, the lower end of the fifth output capacitor C5, the upper end of the sixth output capacitor C6 in Boost circuit 2, the source of the third switching unit S3, and the drain of the fourth switching unit S4 are connected.

[0030] In some embodiments, the output control module further includes an input capacitor, the two ends of which are connected to the positive and negative terminals of the DC power supply, respectively.

[0031] It should be noted that, as Figure 2 As shown, the input capacitor in Boost circuit 1 is the first input capacitor C1, and the DC power supply U... BAT The positive terminal is connected to the upper end of the first input capacitor C1, and the DC power supply U... BAT The negative terminal is connected to the lower end of the first input capacitor C1; the input capacitor in Boost circuit 2 is the second input capacitor C2, and the DC power supply U... BAT The positive terminal is connected to the upper end of the second input capacitor C2, and the DC power supply U... BAT The negative terminal is connected to the lower end of the second input capacitor C2. By setting the first input capacitor C1 and the second input capacitor C2, the current ripple on the input side is filtered out, and the current and voltage on the input side are stabilized.

[0032] In some embodiments, the boost control drive module includes: The conditioning circuit 10 has its input terminal connected to the first boost circuit and the second boost circuit, and is used to collect the positive half energy storage inductor current of the first boost circuit, the positive half energy storage inductor current of the second boost circuit, the positive half output capacitor voltage of the first boost circuit, and the negative half output capacitor voltage of the first boost circuit. The control submodule 20 is connected to the output terminal of the conditioning circuit 10. It is used to receive and calculate and output the voltage regulation duty cycle signal and the current sharing duty cycle signal based on the first positive half-inductor current sampling value, the second positive half-inductor current sampling value, the first positive half-capacitor voltage sampling value and the first negative half-capacitor voltage sampling value output by the conditioning circuit 10. The drive submodule 30 is connected to the control submodule 20 and the positive half-switching unit and the negative half-switching unit. It is used to receive and generate the voltage regulation drive signal and the current sharing drive signal based on the voltage regulation duty cycle signal and the current sharing duty cycle signal. The voltage regulation drive signal is used to control the on / off state of the positive half-switching unit and the negative half-switching unit in the first boost circuit, and the current sharing drive signal is used to control the on / off state of the positive half-switching unit in the second boost circuit.

[0033] It should be noted that, as Figure 3 As shown, the positive half-storage inductor current of the first boost circuit is the first storage inductor current I1, the positive half-storage inductor current of the second boost circuit is the third storage inductor current I3, and the positive half-output capacitor voltage of the first boost circuit is the third output capacitor voltage U. C1 The negative half-output capacitor voltage of the first boost circuit is the fourth output capacitor voltage U. C2The conditioning circuit 10 can process the first energy storage inductor current I1, the third energy storage inductor current I3, and the third output capacitor voltage U. C1 and the fourth output capacitor voltage U C2 Preprocessing is performed (such as signal amplification, level conversion, filtering and noise reduction), and the first positive half-inductor current sample value (i.e., the first energy storage inductor current sample value I) is output. L1 The second positive half-inductor current sampling value (which is also the third energy storage inductor current sampling value I) L3 The first positive half capacitor voltage sample value (i.e., the third output capacitor voltage sample value U1) and the first negative half capacitor voltage sample value (i.e., the fourth output capacitor voltage sample value U2).

[0034] In some embodiments, the control submodule 20 includes: The voltage and current dual closed-loop controller 210 is connected to the output terminal of the conditioning circuit 10. It is used to receive and calculate and output the voltage regulation duty cycle signal based on the sampled values ​​of the first positive half-inductor current, the first positive half-capacitor voltage, and the first negative half-capacitor voltage. The input current sharing controller 220 is connected to the output terminal of the conditioning circuit 10. It is used to receive and calculate and output the original current sharing duty cycle signal based on the first positive half-inductor current sampling value and the second positive half-inductor current sampling value. The external current sharing adder 240 is connected to the output terminals of the voltage and current dual closed-loop controller 210 and the input current sharing controller 220. It is used to add the regulated duty cycle signal to the original current sharing duty cycle signal to obtain the current sharing duty cycle signal.

[0035] In some embodiments, the voltage and current dual closed-loop controller 210 includes: The first voltage regulator adder 2101 is used to receive and add the sampled value of the first positive half capacitor voltage to the sampled value of the first negative half capacitor voltage to obtain the bus voltage sampled value. The first voltage regulator subtractor 2102 is connected to the first voltage regulator adder 2101 and is used to receive and subtract the bus voltage reference value from the bus voltage sample value to obtain the bus voltage error signal. The first voltage-stabilized PI regulator 2103 is connected to the first voltage-stabilized subtractor 2102 and is used to receive and output a given current reference value based on the bus voltage error signal. The second voltage regulator subtractor 2104 is connected to the first voltage regulator PI regulator 2103 and is used to receive and subtract the given current reference value from the first positive half-inductor current sample value to obtain the given current error signal. The second voltage-regulating PI regulator 2105, connected to the voltage-regulating subtractor, is used to receive and output a voltage-regulating duty cycle signal based on a given current error signal.

[0036] It should be noted that adding the sampled value of the first positive half-capacitor voltage to the sampled value of the first negative half-capacitor voltage gives the sampled value of the third output capacitor voltage U1 + the sampled value of the fourth output capacitor voltage U2 = the sampled value of the bus voltage U. bus By using the bus voltage reference value U ref With bus voltage sampling value U bus The bus voltage error signal ΔU is obtained by subtraction. bus The deviation of the current output voltage can be obtained by using the given current reference value I. ref Compared with the first positive half-inductor current sampling value (i.e., the first energy storage inductor current sampling value I) L1 Subtracting the given current error signal from the given current error signal, and generating the voltage regulation duty cycle D1 (or D) based on the given current error signal. S1 The output voltage of Boost circuit 1 can be stabilized by adjusting the duty cycle of the first switching unit S1 and the second switching unit S2.

[0037] In some embodiments, the input current sharing controller 220 includes: The internal current sharing subtractor 2201 is used to receive and subtract the sampled value of the first positive half-inductor current from the sampled value of the second positive half-inductor current to obtain the current difference signal. The current sharing PI regulator 2202 is connected to the internal current sharing subtractor 2201 and is used to receive and output the original current sharing duty cycle signal based on the current difference signal.

[0038] It should be noted that by sampling the first positive half-inductor current value (i.e., the first energy storage inductor current value I), L1 ) and the second positive half-inductor current sampling value (the third energy storage inductor current sampling value I) L3 Subtracting the two currents yields the current difference between the two Boost circuits (i.e., the current difference signal). By inputting the current difference signal into the current sharing PI regulator 2202, the switching on and off of the third switching unit S3 can be controlled based on the original current sharing duty cycle signal D2, so that the current of the first energy storage inductor I1 equals the current of the third energy storage inductor I3. Furthermore, the voltage regulation duty cycle signal D1 is added to the original current sharing duty cycle signal D2 by the external current sharing adder 240 to obtain the current sharing duty cycle signal D. S3 This allows for voltage regulation while ensuring that the current I1 of the first energy storage inductor equals the current I3 of the third energy storage inductor.

[0039] In some embodiments, the control submodule 20 further includes: The midpoint voltage balance controller 230 is connected to the output terminal of the conditioning circuit 10 and is used to receive, calculate and output the original voltage balance duty cycle signal based on the first positive half capacitor voltage sample value and the first negative half capacitor voltage sample value. The voltage balancing adder 250 is connected to the output terminals of the external current sharing adder 240 and the midpoint voltage balancing controller 230. It is used to add the current sharing duty cycle signal to the original voltage balancing duty cycle signal to obtain the voltage balancing duty cycle signal.

[0040] In some embodiments, the midpoint voltage balance controller 230 includes: The first voltage balance subtractor 2301 is used to receive and subtract the sampled value of the first positive half capacitor voltage from the sampled value of the first negative half capacitor voltage to obtain the positive and negative voltage error signal. The second voltage balance subtractor 2302 is connected to the first voltage balance subtractor 2301. It is used to receive and subtract the positive and negative voltage error reference value signal from the positive and negative voltage error signal to obtain the midpoint balance error signal. The voltage balance PI regulator 2303 is connected to the first voltage balance subtractor 2301 and is used to receive and output the original voltage balance duty cycle signal based on the midpoint balance error signal.

[0041] It should be noted that subtracting the first positive half-capacitor voltage sample value from the first negative half-capacitor voltage sample value gives the third output capacitor voltage sample value U1 - the fourth output capacitor voltage sample value U2 = positive and negative voltage error signal ΔU. The positive and negative voltage error reference signal ΔU... ref Subtracting the positive and negative voltage error signals ΔU yields the deviation of the midpoint voltage balance (i.e., the midpoint balance error signal). By outputting the original voltage balance duty cycle signal based on the midpoint balance error signal, the on / off state of the fourth switching unit S4 can be controlled based on the original voltage balance duty cycle signal D3, so as to control the voltage U of the third output capacitor. C1 Equal to (or approximately equal to) the voltage U of the fourth output capacitor C2 Furthermore, the current-sharing duty cycle signal D is converted by the voltage balancing adder 250. S3 Adding this to the original voltage balance duty cycle signal D3 yields the voltage balance duty cycle signal D. S4 It can achieve voltage regulation and current sharing while simultaneously reducing the voltage U of the third output capacitor. C1 Equal to (or approximately equal to) the voltage U of the fourth output capacitor C2 .

[0042] In some embodiments, the driver submodule 30 includes: The PWM generator 310 is connected to the output terminals of the voltage and current dual closed-loop controller 210, the external current sharing adder 240, and the voltage balance adder 250. It is used to receive and generate voltage regulation pulse control signals, current sharing pulse control signals, and voltage balance pulse control signals based on the voltage regulation duty cycle signal, the current sharing duty cycle signal, and the voltage balance duty cycle signal. The drive circuit 320 is connected at one end to the PWM generator 310 and at the other end to the positive half-switching unit and the negative half-switching unit. It is used to receive and generate the voltage regulation drive signal, the current sharing drive signal and the voltage balance drive signal based on the voltage regulation pulse control signal, the current sharing pulse control signal and the voltage balance pulse control signal. The voltage balance drive signal is used to control the on / off state of the negative half-switch unit in the second boost circuit.

[0043] It should be noted that, as Figure 4 , 5 As shown in Figure 6, the regulated duty cycle signal D S1 Current sharing duty cycle signal D S3 and voltage balance duty cycle signal D S4 The PWM generator 310 generates a voltage regulation pulse control signal PWM1A, a current sharing pulse control signal PWM2A, and a voltage balance pulse control signal PWM3A. The PWM generator 310 consists of three comparators and can be configured by the CPU via a program. The voltage regulation duty cycle signal D... S1 The carrier wave vca1 is compared with a comparator to form a regulated pulse control signal PWM1A, and the current sharing duty cycle signal D is also included. S3 The carrier wave vca1 is compared with a comparator to form a current sharing pulse control signal PWM2A, and a voltage balancing duty cycle signal D. S4 The carrier wave vca1 is compared with a comparator to form a voltage balance pulse control signal PWM3A.

[0044] It should be noted that the input terminal of the drive circuit 320 is connected to the PWM generator 310, and the output terminal of the drive circuit 320 is connected to the first switching unit S1, the second switching unit S2, the third switching unit S3, and the fourth switching unit S4. The voltage regulation pulse control signal PWM1A, the current sharing pulse control signal PWM2A, and the voltage balance pulse control signal PWM3A are generated into a voltage regulation drive signal V after passing through the drive circuit 320. gs 1A, Current sharing drive signal V gs 2A and voltage balance drive signal V gs 3A, where the regulated drive signal V gs 1A is used to control the on / off state of the first switching unit S1 and the second switching unit S2, and the current sharing drive signal V gs 2A is used to control the on / off state of the third switching unit S3, and the voltage balance drive signal V gs 3A is used to control the on / off state of the fourth switching unit S4.

[0045] In some embodiments, both the positive half-switching unit and the negative half-switching unit include a switching transistor and an anti-parallel diode connected in reverse parallel with the switching transistor.

[0046] It should be noted that controlling the on / off state of the first switch unit S1, the second switch unit S2, the third switch unit S3, and the fourth switch unit S4 is equivalent to controlling the on / off state of the switching transistors within the first switch unit S1, the second switch unit S2, the third switch unit S3, and the fourth switch unit S4.

[0047] It should be noted that when the bus voltage reference value U ref Greater than the bus voltage sampling value U bus At this time, it is necessary to increase the voltage regulation duty cycle D1, that is, increase the voltage regulation drive signal V of the first switching unit S1 and the second switching unit S2. gs 1A, increasing the voltage regulator duty cycle D1 alone will cause the bus voltage sampling value U bus The first energy storage inductor current I1 of Boost circuit 1 is larger than the third energy storage inductor current I3 of Boost circuit 2, resulting in unequal input inductor currents between modules. To achieve input inductor current balance between modules, it is necessary to increase the original current sharing duty cycle signal D2, i.e., increase the current sharing drive signal V of the third switching unit S3. gs 2A, an increase in the original current sharing duty cycle signal D2 will increase the third energy storage inductor current I3 and the third output capacitor voltage U of Boost circuit 2. C1 Greater than the fourth output capacitor voltage U C2 To achieve voltage balance between the positive and negative output buses, it is necessary to increase the original voltage balance duty cycle signal D3, which means increasing the voltage balance drive signal V of the fourth switching unit S4. gs 3A, thereby realizing DC bus voltage control, input current sharing control, and bus midpoint balance control.

[0048] It should be noted that the structure of Boost circuit 1 prevents the parallel three-level boost circuit device from having unequal input inductor currents within each three-level boost circuit module; the voltage and current dual closed-loop controller 210 enables stable control of the bus voltage; the input current sharing controller 220 enables input current sharing between the two Boost circuits; and the bus midpoint balance controller (or midpoint voltage balance controller 230) ensures voltage balance between the two capacitors on the DC bus of the parallel three-level Boost converter, which contributes to the stable and reliable operation of the inverter after PCS, thereby ensuring the stable and reliable operation of the entire PCS system.

[0049] It should be noted that, for example, such as Figure 6 As shown, the three-level boost circuit device provided by this invention is applied to a front-end DC-DC circuit system that supplies power to a multi-PCS system using the same group of batteries. Its structure consists of the following components: DC power supply U BATThe device consists of load 1, load 2, parallel three-level boost circuit (including Boost circuit 1 and Boost circuit 2), conditioning circuit 10, drive circuit 320, and a CPU based on TMS320F28335 controller. The CPU implements the control strategy of the parallel three-level boost circuit device (i.e., control sub-module 20) and PWM generator 310. The parallel three-level boost circuit has four switching units (i.e., first switching unit S1, second switching unit S2, third switching unit S3, and fourth switching unit S4).

[0050] It should be noted that the parallel three-level boost circuit is used in a pre-amplifier DC-DC circuit system that supplies power to a multi-PCS system using the same battery pack. The power is 1.2kW. Load 1 and Load 2 are both purely resistive loads, with Load 1 being 80.7Ω and Load 2 being 53.8Ω. The input inductance (i.e., the energy storage inductance) is L1=L2=L3=L4=1.5mH, the input capacitance is C1=C2=470uF, and the output capacitance is C3=C4=C5=C6=470uF. The parameter of the first voltage-regulating PI regulator 2103 in the voltage and current dual closed-loop controller 210 is K. P1 =0.28, K I1 =0.005, the parameter K of the second voltage regulator PI controller 2105 is 0.005. P2 =0.02, K I2 =0.0005; the parameter of the current sharing PI regulator 2202 in the input current sharing controller 220 is K. P3 =0.022, K I3 =0.002; the voltage balance PI regulator 2303 in the midpoint voltage balance controller 230 (or bus midpoint balance controller) has a parameter of K. P4 =0.15, K I4 =0; The input DC power supply voltage U in the simulation experiment is... BAT =120-180V, bus voltage U BUS =400V, switching frequency f=20kHz, such as Figure 2 The switching units (S1, S2, S3, S4) in the circuit are Infineon's K50EH5, the operational amplifier in the conditioning circuit 10 is TI's TL074CN, and the digital control chip is TI's TM320F28335.

[0051] It should be noted that the voltage U across the positive half bus capacitor (or positive half output capacitor, third output capacitor) C3 of the Boost circuit 1 in the parallel three-level boost circuit is... C1 The voltage U across the negative half bus capacitor (or negative half output capacitor, fourth output capacitor) C4 C2The current I1 flowing through the first energy storage inductor L1 in Boost circuit 1 and the current I3 flowing through the third energy storage inductor L3 in Boost circuit 2 are processed by conditioning circuit 10 to obtain the corresponding positive half bus voltage capacitor voltage sample value U1 (first positive half capacitor voltage sample value, third output capacitor voltage sample value) and negative half bus voltage capacitor voltage sample value U2 (first negative half capacitor voltage sample value, fourth output capacitor voltage sample value U2). The current sample value I of the first energy storage inductor L1 in Boost circuit 1 is also processed. L1 and the current sampling value I flowing through the third energy storage inductor L3 in Boost circuit 2 L3 The duty cycle signal (D) is obtained through the control strategy of the parallel three-level boost circuit device in the DSPTM320F28335. S1 D S3 D S4 ), duty cycle signal (D S1 D S3 D S4 The PWM generator 310 generates pulse control signals (PWM1A, PWM2A, PWM3A), which, after passing through the drive circuit 320, control the on / off state of the switching units (S1, S2, S3, S4).

[0052] It should be noted that the DC power supply U BAT Discharge through Boost circuit 1 Figure 7 DC power supply voltage U BAT It is 120V. Figure 7 The waveforms on the left, from top to bottom, represent the current I1 (1A / div) flowing through the first energy storage inductor L1 in Boost circuit 1, the current I2 (1A / div) flowing through the second energy storage inductor L2 in Boost circuit 1, the current I3 (1A / div) flowing through the third energy storage inductor L3 in Boost circuit 2, and the current I4 (1A / div) flowing through the fourth energy storage inductor L4 in Boost circuit 2. Figure 7 The waveforms on the right, from top to bottom, represent the DC power supply voltage U. BAT (50V / div), positive half bus capacitor voltage U C1 (50V / div), negative half bus capacitor voltage U C2 (50V / div), current I1 is 5.17A, current I2 is 5.17A, current I3 is 5.163A, current I4 is 5.163A, DC power supply voltage U BAT The voltage U of the positive half-bus capacitor is 120V. C1 The voltage U of the negative half-bus capacitor is 200V. C2As shown above, the parallel three-level boost circuit device will not produce unequal input inductor currents within each three-level boost circuit module or between modules. It can achieve equal input inductor currents within each three-level boost circuit module and equal input inductor currents between modules, thus achieving positive and negative bus voltage balance.

[0053] It should be noted that, Figure 8 DC power supply voltage U BAT It is 150V. Figure 8 The waveforms on the left, from top to bottom, represent the current I1 (1A / div) flowing through the first energy storage inductor L1 in Boost circuit 1, the current I2 (1A / div) flowing through the second energy storage inductor L2 in Boost circuit 1, the current I3 (1A / div) flowing through the third energy storage inductor L3 in Boost circuit 2, and the current I4 (1A / div) flowing through the fourth energy storage inductor L4 in Boost circuit 2. Figure 8 The waveforms on the right, from top to bottom, represent the DC power supply voltage U. BAT (50V / div), positive half bus capacitor voltage U C1 (50V / div), negative half bus capacitor voltage U C2 (50V / div), current I1 is 4.184A, current I2 is 4.184A, current I3 is 4.171A, current I4 is 4.171A, DC power supply voltage U BAT The voltage U of the positive half-bus capacitor is 150V. C1 The voltage U of the negative half-bus capacitor is 200V. C2 As shown above, the parallel three-level boost circuit device will not produce unequal input inductor currents within each three-level boost circuit module or between modules. It can achieve equal input inductor currents within each three-level boost circuit module and equal input inductor currents between modules, thus achieving positive and negative bus voltage balance.

[0054] It should be noted that, Figure 9 DC power supply voltage U BAT It is 180V. Figure 9 The waveforms on the left, from top to bottom, represent the current I1 (1A / div) flowing through the first energy storage inductor L1 in Boost circuit 1, the current I2 (1A / div) flowing through the second energy storage inductor L2 in Boost circuit 1, the current I3 (1A / div) flowing through the third energy storage inductor L3 in Boost circuit 2, and the current I4 (1A / div) flowing through the fourth energy storage inductor L4 in Boost circuit 2. Figure 9 The waveforms on the right, from top to bottom, represent the DC power supply voltage U. BAT (50V / div), positive half bus capacitor voltage UC1 (50V / div), negative half bus capacitor voltage U C2 (50V / div), current I1 is 3.514A, current I2 is 3.514A, current I3 is 3.494A, current I4 is 3.494A, DC power supply voltage U BAT The voltage U of the positive half-bus capacitor is 180V. C1 The voltage U of the negative half-bus capacitor is 200V. C2 As shown above, the parallel three-level boost circuit device will not produce unequal input inductor currents within each three-level boost circuit module or between modules. It can achieve equal input inductor currents within each three-level boost circuit module and equal input inductor currents between modules, thus achieving positive and negative bus voltage balance.

[0055] It should be noted that, as shown in the above experiments, when the DC power supply voltage is within the range of 120-180V, the DC bus voltage of the parallel three-level boost circuit device can be stably output. There will be no unequal input inductor currents within each three-level boost circuit module or between modules. It can achieve equal input inductor currents within each three-level boost circuit module and equal input inductor currents between modules, thereby achieving positive and negative bus voltage balance and enabling the system to operate reliably and stably.

[0056] It should be noted that, Figure 10 DC power supply voltage U BAT It is 150V. Figure 10 The waveforms on the left, from top to bottom, represent the current I1 (1A / div) flowing through the first energy storage inductor L1 in Boost circuit 1, the current I2 (1A / div) flowing through the second energy storage inductor L2 in Boost circuit 1, the current I3 (1A / div) flowing through the third energy storage inductor L3 in Boost circuit 2, and the current I4 (1A / div) flowing through the fourth energy storage inductor L4 in Boost circuit 2. Figure 10 The waveforms on the right, from top to bottom, represent the DC power supply voltage U. BAT (50V / div), positive half bus capacitor voltage U C1 (50V / div), negative half bus capacitor voltage U C2 (50V / div), initial load 1 is 80.7Ω, load 2 is 53.8Ω. At time 0.6, load 1 is reduced to 53.8Ω. Initial currents I1, I2, I3, and I4 are 4.178A and 4.185A respectively. DC power supply voltage U... BAT The voltage U of the positive half-bus capacitor is 150V. C1 The voltage U of the negative half-bus capacitor is 200V. C2With a voltage of 200V, after the load 1 is reduced to 53.8Ω, the currents I1, I2, I3, and I4 are 5.233A and 5.233A respectively. The DC power supply voltage U... BAT The voltage U of the positive half-bus capacitor is 150V. C1 The voltage U of the negative half-bus capacitor is 200V. C2 With a voltage of 200V, the above test data shows that when the load changes, the parallel three-level boost circuit device will not produce unequal input inductor currents within each three-level boost circuit module or between modules. It can achieve equal input inductor currents within each three-level boost circuit module and equal input inductor currents between modules, thus achieving positive and negative bus voltage balance.

[0057] It should be noted that, compared with existing level boost circuits, the present invention has the following advantages: 1) As a front-end DC-DC circuit for powering a multi-PCS system with the same group of batteries, the parallel three-level boost circuit addresses the problems of unequal input inductor currents between modules, unequal input inductor currents within each module, and unbalanced positive and negative output bus voltages caused by unequal duty cycles or loads of the two power switches within a single three-level boost circuit module in traditional parallel three-level boost circuits. The parallel three-level boost circuit proposed in this invention achieves equal input inductor currents within each three-level boost circuit by changing the hardware structure of the modules; 2) The parallel three-level boost circuit device provided by this invention can achieve stable bus voltage, current sharing of input currents in different modules, and balanced bus midpoint voltage.

[0058] Secondly, embodiments of this application provide a control method for a parallel three-level boost circuit device, including: 1) real-time acquisition of the positive half-bus capacitor voltage U of the parallel three-level boost circuit. C1 Negative half bus capacitor voltage U C2 1) The current I1 flowing through the first energy storage inductor L1 in Boost circuit 1 and the current I3 flowing through the third energy storage inductor L3 in Boost circuit 2; 2) The voltage U of the positive half bus capacitor. C1 Negative half bus capacitor voltage U C2 The current I1 flowing through the first energy storage inductor L1 in Boost circuit 1 and the current I3 flowing through the third energy storage inductor L3 in Boost circuit 2 are input to the conditioning circuit 10, and the corresponding sampled values ​​of the positive half-bus capacitor voltage U1, negative half-bus capacitor voltage U2, and current I3 flowing through the first energy storage inductor L1 in Boost circuit 1 are obtained. L1 and the current sampling value I flowing through the third energy storage inductor L3 in Boost circuit 2 L33) Add the positive half-bus capacitor voltage sample value U1 and the negative half-bus capacitor voltage sample value U2 to obtain the bus voltage sample value U. bus 4) Sample the bus voltage value U bus The sampled value I of the current flowing through the first energy storage inductor L1 in Boost circuit 1 L1 Input voltage and current dual closed-loop controller 210, output duty cycle signal D1 based on voltage and current dual closed-loop control; 5) Sample the current value I flowing through the first energy storage inductor L1 in the Boost circuit 1. L1 The sampled value I of the current flowing through the third energy storage inductor L3 in Boost circuit 2 L3 The input current sharing controller 220 is sent to the bus midpoint balance controller (midpoint voltage balance controller 230), which outputs a duty cycle signal D2 based on the input current sharing control; 6) The positive half-bus capacitor voltage sampling value U1 and the negative half-bus capacitor voltage sampling value U2 are sent to the bus midpoint balance controller (midpoint voltage balance controller 230), which outputs a duty cycle signal D3 based on the bus midpoint balance control; 7) The duty cycle signal D1 based on voltage and current dual closed-loop control, the duty cycle signal D2 based on input current sharing control, and the duty cycle signal D3 based on bus midpoint balance control are processed to obtain the duty cycle signal D of the switching transistor (switching unit). S1 D S3 D S4 8) Set the duty cycle D of the switching transistor (switching unit) to... S1 D S3 D S4 All inputs are fed into the PWM generator 310, which generates a pulse control signal for the switching transistor (switching unit). The pulse control signal for the switching transistor (switching unit) is then processed by the drive circuit 320 to generate a drive signal for the switching transistor (switching unit). The drive signal for the switching transistor is used to control the switching unit (switching transistor) in the parallel three-level boost circuit to turn on and off.

[0059] It should be noted that, as a preferred control scheme for the parallel three-level boost circuit device control method described in this invention, the specific method for the voltage and current dual closed-loop controller 210 to output the duty cycle signal D1 based on voltage and current dual closed-loop control is as follows: In the voltage and current dual closed-loop controller 210, the bus voltage sample value U... bus With bus voltage reference value U ref The signal is sent to the subtractor to make the bus voltage reference value U... ref Subtract the bus voltage sampling value U bus The output value obtained from the subtractor is sent to the PI regulator, which then outputs a dual closed-loop control of the voltage and current, controlling the reference value of the given current I. ref Given current reference value I ref The sampled value I of the current flowing through the first energy storage inductor L1 in Boost circuit 1 L1The current is fed into another subtractor, given the reference current value I. ref Subtract the sampled current I flowing through the first energy storage inductor L1 in Boost circuit 1 L1 The output value obtained from another subtractor is sent to the PI regulator, which then outputs the duty cycle signal D1 based on voltage and current dual closed-loop control.

[0060] It should be noted that, as a preferred control scheme for the parallel three-level boost circuit device control method described in this invention, the specific method for the input current sharing controller 220 to output the duty cycle signal D2 based on the input current sharing control is as follows: In the input current sharing controller 220, the current sampling value I flowing through the first energy storage inductor L1 in the Boost circuit 1 is... L1 The sampled value I of the current flowing through the third energy storage inductor L3 in Boost circuit 2 L3 The sampled current I flowing through the first energy storage inductor L1 in the Boost circuit 1 is sent to the subtractor. L1 Subtract the sampled current I flowing through the third energy storage inductor L3 in Boost circuit 2 L3 The output value obtained by the subtractor is sent to the PI regulator, which then outputs a duty cycle signal D2 based on the input current sharing control.

[0061] It should be noted that, as a preferred control scheme for the parallel three-level boost circuit device control method described in this invention, the bus midpoint balancing controller (or midpoint voltage balancing controller 230) outputs the duty cycle signal D3 based on the bus midpoint balancing control. Specifically, in the bus midpoint balancing controller, the sampled values ​​U1 and U2 of the positive half-bus capacitor voltage are sent to a subtractor, causing the negative half-bus capacitor voltage sampled value U2 to be subtracted from the positive half-bus capacitor voltage sampled value U1. The output value of the subtractor, the positive and negative bus capacitor voltage error signal ΔU, is then compared with the reference value ΔU of the positive and negative bus capacitor voltage error signal. ref The reference value ΔU of the positive and negative bus capacitor voltage error signal is sent to another subtractor. ref Subtract the positive and negative bus capacitor voltage error signals ΔU, and send the output value obtained from another subtractor to the PI regulator to output the duty cycle signal D3 based on the bus midpoint balance control.

[0062] It should be noted that the duty cycle signal D1 of the voltage and current dual closed-loop control, the duty cycle signal D2 of the input current current sharing control, and the duty cycle signal D3 of the bus midpoint balance control are processed to obtain the duty cycle signal D of the switching transistor (or switching unit). S1 D S3 D S4 The specific method is as follows: the duty cycle D of the switching transistor S1The duty cycle signal D1 is directly obtained from the voltage and current dual closed-loop control; the duty cycle signal D of the switching transistor is... S3 The duty cycle signal D1, controlled by a dual closed-loop voltage and current system, and the duty cycle signal D2, controlled by current sharing of the input current, are added together by an adder. The output value of the adder is the duty cycle signal D of the switching transistor. S3 ; Duty cycle signal D of the switching transistor S4 The duty cycle signal D of the switching transistor S3 The duty cycle signal D3 of the bus midpoint balance control is added to the signal through an adder. The output value of the adder is the duty cycle signal D of the switching transistor. S4 .

[0063] It should be noted that, compared with the prior art, the beneficial effects of the present invention are as follows: The parallel three-level boost circuit device of the present invention can achieve stable control of the output DC bus voltage through the duty cycle signal controlled by the voltage and current dual closed loop, can achieve input current sharing of the two Boost circuits through the duty cycle signal controlled by the input current sharing, and can ensure the voltage balance of the two capacitors of the DC bus of the parallel three-level boost circuit through the duty cycle signal controlled by the bus midpoint balance. The present invention solves the problems of unequal input inductor current between modules, unequal input inductor current within each module, and unbalanced positive and negative output bus voltage of the device caused by the unequal duty cycles of the two power switches or unequal loads in the traditional parallel three-level boost circuit, thus improving the reliability and stability of the system.

[0064] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0065] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0066] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A parallel three-level boost circuit device, characterized in that, include: A first boost circuit and a second boost circuit are connected in parallel, and both the first boost circuit and the second boost circuit include an output control module and an energy storage module connected in series. The output control module includes an output switch submodule and an output capacitor submodule connected in parallel. The output switch submodule includes a positive half switch unit and a negative half switch unit connected in series. The output capacitor submodule includes a positive half diode, a positive half output capacitor, a negative half output capacitor, and a negative half diode connected in series. The energy storage module includes a positive half-energy storage inductor and a negative half-energy storage inductor. The positive half-energy storage inductor is connected to the positive terminal of the output control module and the DC power supply, and the negative half-energy storage inductor is connected to the negative terminal of the output control module and the DC power supply. The output terminal of the positive half-switching unit of the second boost circuit is connected to the negative terminal of the positive half-output capacitor of the second boost circuit. The boost control drive module is connected to the first boost circuit and the second boost circuit, and is used to adjust the duty cycle of the positive half-switching unit and the negative half-switching unit.

2. The parallel three-level boost circuit device according to claim 1, characterized in that, The output control module also includes an input capacitor, the two ends of which are connected to the positive and negative terminals of the DC power supply, respectively.

3. The parallel three-level boost circuit device according to claim 1, characterized in that, The boost control drive module includes: The conditioning circuit has its input terminal connected to the first boost circuit and the second boost circuit, and is used to collect the positive half energy storage inductor current of the first boost circuit, the positive half energy storage inductor current of the second boost circuit, the positive half output capacitor voltage of the first boost circuit, and the negative half output capacitor voltage of the first boost circuit. The control submodule is connected to the output of the conditioning circuit and is used to receive and calculate and output the voltage regulation duty cycle signal and the current sharing duty cycle signal based on the first positive half-inductor current sampling value, the second positive half-inductor current sampling value, the first positive half-capacitor voltage sampling value and the first negative half-capacitor voltage sampling value output by the conditioning circuit. The drive submodule, connected to the control submodule and the positive half-switch unit and the negative half-switch unit, is used to receive and generate the voltage regulation drive signal and the current sharing drive signal based on the voltage regulation duty cycle signal and the current sharing duty cycle signal; The voltage regulation drive signal is used to control the on / off state of the positive half-switching unit and the negative half-switching unit in the first boost circuit, and the current sharing drive signal is used to control the on / off state of the positive half-switching unit in the second boost circuit.

4. The parallel three-level boost circuit device according to claim 3, characterized in that, The control submodule includes: A voltage and current dual closed-loop controller is connected to the output terminal of the conditioning circuit. It is used to receive, calculate and output the voltage regulation duty cycle signal based on the sampled value of the first positive half-inductor current, the sampled value of the first positive half-capacitor voltage and the sampled value of the first negative half-capacitor voltage. An input current sharing controller is connected to the output terminal of the conditioning circuit and is used to receive, calculate and output the original current sharing duty cycle signal based on the first positive half-inductor current sampling value and the second positive half-inductor current sampling value. An external current sharing adder is connected to the output terminals of the voltage and current dual closed-loop controller and the input current sharing controller. It is used to add the voltage regulation duty cycle signal to the original current sharing duty cycle signal to obtain the current sharing duty cycle signal.

5. The parallel three-level boost circuit device according to claim 4, characterized in that, The voltage and current dual closed-loop controller includes: The first voltage regulator adder is used to receive and add the sampled value of the first positive half-capacitor voltage to the sampled value of the first negative half-capacitor voltage to obtain the bus voltage sampled value. The first voltage regulator subtractor, connected to the first voltage regulator adder, is used to receive and subtract the bus voltage reference value from the bus voltage sample value to obtain the bus voltage error signal. The first voltage-stabilized PI regulator, connected to the first voltage-stabilized subtractor, is used to receive and output a given current reference value based on the bus voltage error signal; The second voltage regulator subtractor, connected to the first voltage regulator PI controller, is used to receive and subtract the given current reference value from the sampled value of the first positive half-inductor current to obtain the given current error signal. The second voltage-regulating PI regulator, connected to the voltage-regulating subtractor, is used to receive and output the voltage-regulating duty cycle signal based on the given current error signal.

6. The parallel three-level boost circuit device according to claim 4, characterized in that, The input current sharing controller includes: An internal current sharing subtractor is used to receive and subtract the sampled value of the first positive half-inductor current from the sampled value of the second positive half-inductor current to obtain a current difference signal. A current sharing PI regulator, connected to the internal current sharing subtractor, is used to receive and output the original current sharing duty cycle signal based on the current difference signal.

7. The parallel three-level boost circuit device according to claim 4, characterized in that, The control submodule further includes: A midpoint voltage balance controller, connected to the output of the conditioning circuit, is used to receive and calculate and output the original voltage balance duty cycle signal based on the first positive half-capacitor voltage sample value and the first negative half-capacitor voltage sample value. A voltage balancing adder, connected to the output of the external current sharing adder and the midpoint voltage balancing controller, is used to add the current sharing duty cycle signal to the original voltage balancing duty cycle signal to obtain a voltage balancing duty cycle signal.

8. The parallel three-level boost circuit device according to claim 7, characterized in that, The midpoint voltage balance controller includes: The first voltage balance subtractor is used to receive and subtract the sampled value of the first positive half-capacitor voltage from the sampled value of the first negative half-capacitor voltage to obtain the positive and negative voltage error signal. The second voltage balance subtractor is connected to the first voltage balance subtractor and is used to receive and subtract the positive and negative voltage error reference value signal from the positive and negative voltage error signal to obtain the midpoint balance error signal. A voltage balance PI regulator, connected to the first voltage balance subtractor, is used to receive and output the original voltage balance duty cycle signal based on the midpoint balance error signal.

9. The parallel three-level boost circuit device according to any one of claims 7 or 8, characterized in that, The driver submodule includes: The PWM generator is connected to the output terminals of the voltage and current dual closed-loop controller, the external current sharing adder, and the voltage balance adder. It is used to receive and generate voltage regulation pulse control signal, current sharing pulse control signal, and voltage balance pulse control signal based on the voltage regulation duty cycle signal, the current sharing duty cycle signal, and the voltage balance duty cycle signal. The driving circuit is connected at one end to the PWM generator and at the other end to the positive half-switching unit and the negative half-switching unit. It is used to receive and generate the voltage regulation driving signal, the current sharing driving signal and the voltage balance driving signal based on the voltage regulation pulse control signal, the current sharing pulse control signal and the voltage balance pulse control signal. The voltage balance drive signal is used to control the on / off state of the negative half-switch unit in the second boost circuit.

10. The parallel three-level boost circuit device according to any one of claims 1-7, characterized in that, Both the positive half-switching unit and the negative half-switching unit include a switching transistor and an anti-parallel diode connected in reverse parallel with the switching transistor.

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