A high-isolation radio frequency switch circuit based on parasitic parameter compensation

Abstract

The application discloses a high-isolation radio frequency switch circuit based on parasitic parameter compensation and belongs to the technical field of radio frequency switch circuits. The circuit comprises an input end, a first output end, a second output end, two impedance conversion sections, two output transmission lines and two parallel branches. The input end is connected to one end of the two impedance conversion sections through a common node, and the other end of the impedance conversion section is connected to a T-shaped junction node. Each T-shaped junction node is connected to the first output end and the second output end through the output transmission line. One end of the parallel branch is connected to the T-shaped junction node. The parallel branch comprises a compensation stub and a PIN diode connected in series. The microstrip line structure at the T-shaped junction node is configured to introduce a parallel capacitor to form parallel resonance with the parallel branch in a conducting state.

Description

Technical Field

[0001] This invention relates to the field of radio frequency switch circuit technology, and specifically to a high isolation radio frequency switch circuit based on parasitic parameter compensation. Background Technology

[0002] Traditional high-performance PIN diodes and MEMS switches, while having small parasitic parameters, are expensive and complex to drive, making them unsuitable for large-scale array applications.

[0003] The existing technology that uses printed interdigital capacitors for parasitic compensation is extremely sensitive to PCB etching precision. Processing errors can easily lead to performance failure, and the operating bandwidth is relatively narrow.

[0004] Switching technology based on phase change materials requires special thin-film processes, which are incompatible with standard low-cost PCB processes, making mass production difficult.

[0005] Low-cost commercial PIN diodes are significantly affected by parasitic parameters at high frequencies. The lack of effective impedance coordination design can lead to severe signal leakage (low isolation) and high insertion loss. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention proposes a high-isolation radio frequency switch circuit based on parasitic parameter compensation.

[0007] The objective of this invention can be achieved through the following technical solutions:

[0008] A first aspect of the present invention relates to a radio frequency switching circuit based on parasitic parameter compensation, comprising: an input terminal, a first output terminal, a second output terminal, two impedance transformation sections, two output transmission lines, and two parallel branches;

[0009] The input terminal is connected to one end of each of the two impedance transformation segments via a common node, and the other end of each impedance transformation segment is connected to a T-junction node; each of the T-junction nodes is connected to the first output terminal and the second output terminal via the output transmission line.

[0010] One end of the parallel branch is connected to the T-junction node, and the other end is grounded;

[0011] The parallel branch includes a compensation stub and a PIN diode connected in series; one end of the compensation stub is connected to the connection between the impedance transformation section and the output transmission line to form the T-junction node, and the other end is connected to the positive or negative terminal of the PIN diode; the end of the PIN diode not connected to the compensation stub is connected to the ground plane.

[0012] The microstrip line structure at the T-junction node is configured to introduce a parallel capacitor to form a parallel resonance with the parallel branch in the conducting state.

[0013] Optionally, the angle formed by the compensation stub, the impedance transformation section, and the output transmission line is a right angle, and no chamfer structure is provided on the inner side of the right angle.

[0014] Optionally, the impedance transformation section or the output transmission line has a stepped impedance structure in the region adjacent to the T-junction node, and the linewidth at the stepped impedance structure is greater than the linewidth of the rest of the impedance transformation section or the output transmission line, so as to introduce a stepped capacitance.

[0015] Optionally, the length of the impedance transformation section is one-quarter of the guided wave wavelength corresponding to the operating frequency.

[0016] Optionally, the PIN diodes in the two parallel branches are arranged in reverse; the positive terminal of the PIN diode in one parallel branch is connected to the compensation stub and the negative terminal is connected to the metal via; the negative terminal of the PIN diode in the other parallel branch is connected to the compensation stub and the positive terminal is connected to the metal via.

[0017] Optionally, it also includes a DC bias line, one end of which is connected to the connection point between the compensation stub and the PIN diode, and the other end is connected to a DC control voltage source; the DC bias line includes a high-impedance line and an RF choke connected in series.

[0018] Optionally, the radio frequency switch circuit is disposed on the top layer of the dielectric substrate, the ground plane is disposed on the bottom layer of the dielectric substrate, and the distance between the circuit and the ground plane is determined by the thickness of the dielectric substrate; the metal via penetrates the dielectric substrate.

[0019] A second aspect of the present invention relates to a design method for a radio frequency switching circuit based on parasitic parameter compensation as described above, comprising the following steps:

[0020] Step 1: Obtain the parasitic capacitance value of the PIN diode in the off state, the parasitic inductance value of the package, and the parasitic inductance value of the metal via; calculate the characteristic impedance and electrical length of the compensation stub based on the parasitic capacitance value, the parasitic inductance value of the package, and the parasitic inductance value of the metal via, so that the inductive reactance provided by the compensation stub and the total impedance of the PIN diode and the metal via form a series resonance at the T-junction node;

[0021] Step 2: Under the condition that the characteristic impedance and electrical length of the compensation stub are fixed, obtain the conduction inductance value of the PIN diode in the conducting state; calculate the total equivalent inductance of the parallel branch including the compensation stub, the PIN diode in the conducting state, and the metal via.

[0022] Step 3: Adjust the geometric parameters of the T-junction node and introduce an equivalent parallel capacitor so that the equivalent parallel capacitor and the total equivalent inductance of the parallel branch form a parallel resonance.

[0023] Optionally, in step one, the characteristic impedance of the compensation stub is... and electrical length The following relationship must be satisfied:

[0024]

[0025] in, The operating angular frequency, This refers to the parasitic capacitance of a PIN diode in the cutoff state. Parasitic inductance for PIN diode cut-off state package, Parasitic inductance of a metal through-hole To compensate for the characteristic impedance of the stub, To compensate for the electrical length of the stub;

[0026] In step three, the parallel resonance satisfies the following relationship:

[0027]

[0028] in, The total equivalent inductance of the parallel branches in the on state is given. The equivalent parallel capacitance introduced to adjust the geometric parameters of the T-junction.

[0029] Optionally, in step three, adjusting the geometric parameters of the T-junction includes:

[0030] To introduce the first part of the capacitance by maintaining the right-angle structure at the T-junction node without chamfering, and to increase the linewidth of the transmission line at the T-junction node to introduce the second part of the capacitance;

[0031] The sum of the first portion of the capacitor and the second portion of the capacitor is equal to the capacitance value required for parallel resonance with the total equivalent inductance of the parallel branch.

[0032] The beneficial effects of this invention are:

[0033] This invention achieves a step-by-step collaborative design through cutoff-state series resonance, λ / 4 impedance transformation, and conduction-state structural compensation, addressing the performance limitations of low-cost PIN diodes in the X-band and achieving high-performance switching levels in key RF indicators. The circuit was modeled and simulated in the commercial electromagnetic simulation software CST MICROWAVE STUDIO, as shown in the specific circuit model below. Figure 6 As shown, the simulation results and performance comparisons are as follows: Figure 7 , Figure 8 As shown in the above results, we can conclude that:

[0034] 1. High isolation: Near the operating frequency, the proposed solution has a significant improvement in isolation compared to the other two solutions. A single-stage switch can achieve an isolation of up to 61.9 dB, effectively blocking signal leakage and meeting the low crosstalk requirements of radar and phased array antennas.

[0035] 2. Low insertion loss: Near the operating frequency, the proposed scheme has lower insertion loss than the other two schemes, with the lowest insertion loss being approximately 0.07 dB, effectively reducing signal energy loss;

[0036] 3. Ideal impedance matching characteristics: Near the operating frequency, the proposed scheme has lower return loss compared to the other two schemes. Under all operating conditions, the return loss at the input and output ports is as low as -50.7 dB, avoiding signal reflection caused by impedance mismatch. Attached Figure Description

[0037] The invention will now be further described with reference to the accompanying drawings.

[0038] Figure 1 This is the circuit topology of this application;

[0039] Figure 2 The RF switch circuit model used in this application adopts MADP-000907-14020x;

[0040] Figure 3 The figure shows the performance of the RF switching circuit using MADP-000907-14020x in this application. In the figure, at 9 GHz, S11 is -15.3 dB, corresponding to return loss; S21 is -0.8 dB, corresponding to insertion loss of 0.8 dB; and S31 is -12.3 dB, corresponding to isolation of 12.3 dB.

[0041] Figure 4 This application presents a radio frequency switch circuit model using SMP1320-079LF;

[0042] Figure 5 The figure shows the performance of the RF switching circuit using SMP1320-079LF in this application. In the figure, at 9 GHz, S11 is -15.1 dB, corresponding to return loss; S21 is -1.7 dB, corresponding to insertion loss of 1.7 dB; and S31 is -5.6 dB, corresponding to isolation of 5.6 dB.

[0043] Figure 6 This is the optimized RF switch circuit model for this application.

[0044] Figure 7 The figure shows the optimized RF switch circuit performance of this application; S11 achieves a minimum value of -50.7 dB at 8.99 GHz, corresponding to return loss; S21 achieves a maximum value of -0.07 dB at 9 GHz, corresponding to insertion loss of 0.07 dB; S31 achieves a minimum value of -61.9 dB at 9 GHz, corresponding to isolation of 61.9 dB.

[0045] Figure 8 As shown in the figure, near the operating frequency, the optimized scheme outperforms the other two schemes in terms of insertion loss, isolation and return loss, achieving better performance at a lower cost. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] In some embodiments of this invention, the performance of RF switching circuits constructed based on PIN diodes of different models and costs was compared and analyzed. Through simulation verification of high-cost MADP series PIN diodes and low-cost SMP series PIN diodes at 9 GHz, the impact of device parasitic parameters on the isolation and insertion loss of the switching circuit was quantitatively evaluated. The comparative results aim to reveal the performance degradation problem caused by directly replacing low-cost devices, thereby illustrating the urgency of developing a novel low-cost, high-isolation switching circuit.

[0048] The PIN diode used here is specifically model MADP-000907-14020x. At 9GHz, when conducting, it is equivalent to a series circuit including a resistor and an inductor, with a resistance of 7.8Ω and an inductance of 30pF; when cut off, it is equivalent to a series circuit including an inductor and a capacitor, with an inductance of 30pF and a capacitance of 0.025pF. The circuit was modeled and simulated in the commercial electromagnetic simulation software CST MICROWAVESTUDIO. The corresponding RF switch circuit model is as follows: Figure 2 As shown, the circuit effect can be equivalent to a single-pole double-throw switch, and the simulation results are as follows. Figure 3 As shown. By Figure 3 It can be seen that at a frequency of 9 GHz, the return loss is -15.3 dB, the isolation is 12.3 dB, and the insertion loss is 0.8 dB. In practical applications, the return loss needs to be lower than -10 dB; the isolation needs to be higher than 10 dB; and the insertion loss should be as close to 0 dB as possible.

[0049] In summary, the RF switch circuit using this PIN diode can achieve good switching performance, but the cost of this PIN diode is relatively high. If 1000 of this type of PIN diode are purchased, the price of a single PIN diode is about 25 yuan. When applied to large-scale scenarios, the overall cost is high.

[0050] To address the high cost of high-performance PIN diodes (such as MADP-000907-14020x), some embodiments of this invention attempt to replace these PIN diodes with low-cost PIN diodes, specifically the SMP1320-079LF model. If 1000 of these PIN diodes are purchased, the price per diode is approximately 1 yuan. The circuit is modeled and simulated in the commercial electromagnetic simulation software CSTMICROWAVE STUDIO, and the corresponding RF switching circuit model is as follows: Figure 4 As shown, the simulation results are as follows: Figure 5 As shown. By Figure 5 It can be seen that at a frequency of 9 GHz, the return loss is -15.1 dB, the isolation is 5.6 dB, and the insertion loss is 1.7 dB. Considering the standard parameters, the isolation of the switching circuit is too low and the insertion loss is too high, which cannot achieve the ideal switching effect.

[0051] In summary, using PIN diodes with good switching selectivity generally results in higher costs; while using low-cost PIN diodes leads to unsatisfactory switching performance. Therefore, a new method is needed to achieve a low-cost, high-isolation RF switching circuit.

[0052] Based on this, the present invention proposes a low-cost, high-isolation RF switch circuit based on parasitic parameter compensation. It is developed through three dimensions: circuit topology construction, performance quantification comparison, and collaborative matching design. The aim is to solve the key technical problems of poor isolation and high insertion loss of low-cost PIN diodes in X-band applications.

[0053] like Figure 1 As shown, this invention provides a low-cost, high-isolation RF switch circuit design method based on parasitic parameter compensation. The circuit is implemented using microstrip line technology and mainly includes: an input terminal, output terminal 1, output terminal 2, a main transmission line, a T-junction, a compensation stub, a PIN diode, and a DC bias line. The circuit is 0.2mm away from the ground plane and filled with Rogers RO4003C dielectric with a dielectric constant of 3.55.

[0054] The input terminal serves as the feed point for radio frequency signals, and its characteristic impedance is designed to be a standard 50 Ω to match the external system.

[0055] The output terminals are located at the ends of the two branch circuits, serving as RF signal output points, and also maintaining a characteristic impedance of 50Ω.

[0056] The main transmission line connects the RF input port and the RF output port. The section between the input port and the T-junction is called the impedance transformation section, and the length of the impedance transformation section is... ( (Wheelwidth is the wavelength corresponding to the operating frequency).

[0057] In the circuit structure described above, the T-junction serves as the orthogonal bifurcation point between the main transmission line and the compensation stub. It adopts a right-angle, non-cut-corner design and utilizes the edge field effect generated by its discontinuity to introduce an equivalent grounding capacitance.

[0058] One end of the compensation stub is vertically connected to the T-junction, and the other end is connected to the PIN diode. Its characteristic impedance and electrical length are precisely calculated to provide specific inductive reactance to tune the circuit's resonant frequency.

[0059] One end of the PIN diode is connected to the ground plane through a metal via, and the other end is connected to a compensation stub. The two PIN diodes are placed in opposite directions. In some embodiments of the present invention, the PIN diode used is specifically model SMP1320-079LF. At a frequency of 9 GHz, when cut off, it is equivalent to a series circuit including an inductor and a capacitor, with an inductance value of 0.5nH and a capacitance value of 0.24 pF; when turned on, it is equivalent to a series circuit including a resistor and an inductor, with a resistance value of 0.5 Ω and an inductance value of 0.7 nH.

[0060] The DC bias line includes a high-impedance line and an RF choke, which is connected to one end of the PIN diode to apply a DC control voltage to switch the state of the PIN diode, while preventing RF signals from leaking to the power supply.

[0061] In some embodiments of the present invention, a design method for a high-isolation radio frequency switch circuit based on parasitic parameter compensation is disclosed, including the following process.

[0062] The RF switch circuit is divided into two branches, left and right. The PIN diodes on the two branches have opposite states. When the branch switch changes state, the state of the PIN diodes also changes accordingly. In the explanation of the principle, unless otherwise specified, the left branch will be used as an example. In addition, each branch contains a parallel branch, which includes a compensation stub, a PIN diode, and a grounding metal via.

[0063] In some embodiments of the present invention, the RF switching circuit is logically equivalent to a single-pole double-throw switch. The core issue is solving the selective ambiguity of circuit on / off states caused by complex parasitic parameters of low-cost PIN diodes in high-frequency RF environments. Unlike traditional designs that only focus on single-state matching, this embodiment provides a step-by-step collaborative design method that prioritizes the determination of the cutoff state and compensates for the structure in the on-state. This method comprises two closely related design stages: First, for the cutoff state, a series resonant circuit is constructed using a compensation stub, the parasitic parameters of the PIN diode, and the parasitic inductance of the metal via. High isolation of the signal is achieved in the branch through RF short circuits and impedance transformation. Then, given that the physical dimensions of the compensation stub are fixed, the inductance of the parallel branch in the on-state is addressed.

[0064] The load is utilized to construct a parallel resonant circuit using the geometric distribution parameters of the T-junction and the step impedance line, transforming the parallel branch into a virtual open circuit, thereby eliminating signal shunting and achieving low insertion loss. Through the aforementioned step-by-step cooperative logic, the harmful parasitic parameters of the PIN diode can be transformed into part of the matching network, achieving optimal performance under all operating conditions. The design principles of the PIN diode in both the cutoff and conduction states will be introduced next.

[0065] In some embodiments of the present invention, the following design method is specifically considered for the aforementioned cutoff state. When the branch switch is in the open state, the PIN diode is in the cutoff state. The core objective is to obtain extremely high impedance for the corresponding branch to maximize the blocking of signal transmission from the input port to the output port. Traditional designs often ignore the parasitic parameters of the PIN diode or only perform simple compensation, resulting in deterioration of isolation at high frequencies. The present invention proposes a design method based on parasitic parameter compensation.

[0066] When a PIN diode is in reverse-biased cutoff state, it is not an ideal open circuit. At high frequencies, the PIN diode chip exhibits junction capacitance. With package parasitic inductance The series structure. At this time, the impedance of the PIN diode... for:

[0067]

[0068] in The corresponding angular frequency is 9 GHz, where j is the imaginary unit. Substituting the parameters of the PIN diode, we can obtain the impedance at this point. for:

[0069]

[0070] In an ideal parallel RF switch design, the cutoff state requires the parallel branch impedance to ground to be close to 0 Ω, and the impedance to be infinite is achieved through impedance transformation to force total reflection of the RF signal, thus achieving a high isolation design. However, the above results show that, due to the dominant effect of parasitic capacitance, the uncompensated PIN diode exhibits a capacitive impedance of 45.41 Ω at 9 GHz, which is close to the system characteristic impedance (50 Ω), failing to form an effective RF short circuit. This means that a large amount of RF signal will not be cut off but will leak directly through this branch to the output, resulting in a severe deterioration in switch isolation and failing to meet high-performance requirements. Therefore, an external compensation network must be introduced to offset this residual impedance.

[0071] In some embodiments of the present invention, to eliminate the aforementioned residual impedance, a compensating stub is introduced at the T-junction bifurcation point (node ​​A and node B) to terminate the PIN diode. The characteristic impedance of this compensating stub is... The electric length is Its input impedance for:

[0072]

[0073] Meanwhile, considering that in engineering implementation, one end of the PIN diode needs to be connected to the ground plane through a metal via, the metal via introduces a non-negligible parasitic inductance at high frequencies. Its impedance .

[0074] This invention treats the compensation stub, the cut-off PIN diode, and the grounding metal via as a single parallel branch to ground. Looking from node A of the T-junction to ground, the total input impedance of this branch is... The sum of the impedances of each part:

[0075]

[0076]

[0077] To allow the signal to enter the ground wire and thus interrupt transmission, a radio frequency short circuit must be formed between this branch and ground. Since the imaginary part is zero, the key design formula of this invention can be derived:

[0078]

[0079] This formula shows that by carefully designing the parameters of the compensation stub ( and This allows the inductive reactance provided by the PIN diode to cancel out the net capacitive reactance and the inductive reactance of the metal via, thus creating a series resonance at node A. At this point, the impedance of node A to ground approaches zero (short-circuit state).

[0080] In some embodiments of the present invention, furthermore, in order to prevent the short-circuit state of node A from affecting the matching of the preceding circuit, the length of the main transmission line between the input port and the T-junction is strictly designed to be one-quarter of the waveguide wavelength. According to the principle of microwave transmission line impedance transformation:

[0081]

[0082] in The impedance of the main transmission line is 50 Ω. When the load impedance... When the value is 0, the equivalent impedance seen at the input port The signal tends towards infinity (open circuit). Therefore, the radio frequency signal undergoes total reflection when entering the left branch, preventing it from entering the next stage of the circuit, thus achieving ideal isolation at the physical level.

[0083] In some embodiments of the present invention, a collaborative design method for the conduction state is provided, mainly including the following ideas. When the RF switch is in the closed state, the PIN diode is in the conduction state. The core design objective is to obtain extremely high impedance for the corresponding parallel branch, so as to block the signal transmission from the input port to the parallel branch to the greatest extent, thereby allowing the signal to flow to the output as much as possible. After the parameters of the cutoff state are determined, the physical dimensions of the compensation stub are fixed. Under this condition, the equivalent circuit of the parallel branch is a small resistor in series with a parasitic inductor. Since the resistance value is very small, it can be ignored. However, the parasitic inductance in the parallel branch will form a large parallel inductive load on the main transmission line, resulting in impedance mismatch. The solution of the present invention is to introduce a parallel capacitor through structural design, which forms a parallel resonance with the above-mentioned parallel inductor, achieving infinite impedance, preventing current from flowing into the parallel branch, thereby restoring ideal matching.

[0084] When a PIN diode is forward-biased, its equivalent model becomes on-resistance. With conducting inductor The series connection. At this point, the total impedance of the parallel branches... It becomes:

[0085]

[0086] Since the compensation stub has been determined to be inductive in the first step of the design, and and All are based on emotion, ignoring the minute details. The total inductance of the entire branch circuit for:

[0087]

[0088] At this point, the parallel branch exhibits strong inductive properties. This is equivalent to an inductive load connected in parallel with the main transmission line, which will break the 50Ω matching and cause impedance mismatch.

[0089] To eliminate the influence of the aforementioned inductive load, this invention utilizes the distributed parameter characteristics of the circuit structure to introduce a parallel capacitor for cancellation. Specifically, the following two measures are taken:

[0090] T-junction edge effect: Employing a right-angled T-junction design without cut corners, the edge electric field generated by the discontinuity in the metal area at the microstrip line intersection is used to construct an equivalent parallel capacitance to ground. .

[0091] Specifically, the line widths of the transverse main line and the longitudinal compensation stub at the T-junction depend on the specific circumstances. In this embodiment, the width of the transverse main line is 0.465mm, and the width of the longitudinal compensation stub is 0.45mm. The size of the introduced capacitance is directly related to the overlap area of ​​the transverse main line and the longitudinal compensation stub.

[0092] Step Impedance Main Line: The main transmission line width near node A is locally widened to form a low-impedance step segment, introducing an additional parallel step capacitance. Therefore, the total equivalent compensation capacitance introduced at node A is: Its corresponding capacitive impedance is:

[0093]

[0094] Specifically, such as Figure 6 As shown, the local widening can be achieved by adding a metal patch below the T-junction. This metal patch effectively increases the linewidth of the main transmission line at the corresponding location, thereby introducing a parallel step capacitor. In this embodiment, the metal patch has a lateral width of 0.59 mm and a longitudinal width of 0.56 mm, which is equivalent to a main transmission line with a length of 0.59 mm and a width of 1.025 mm at the T-junction. The size of the introduced capacitance is directly related to the area of ​​the metal patch. It should be noted that if the capacitance introduced by the T-junction edge effect already satisfies the parallel resonance condition, there is no need to introduce a step impedance structure.

[0095] At node A, the aforementioned inductive branch and capacitive structure form a parallel connection. According to circuit principles, the total input impedance of the parallel branch at this point is... for:

[0096]

[0097] Will and Substituting the expression into the above equation, we can derive:

[0098]

[0099] Observe the denominator of the above equation This invention designs the geometric parameters and linewidth of the T-junction to satisfy the parallel resonance condition at the operating frequency:

[0100]

[0101] At this point, the denominator approaches zero, thus making the total impedance to ground at node A approach infinity:

[0102]

[0103] Through the synergistic design of this invention, the parallel branch, which originally exhibited low impedance inductance, is transformed into a high impedance open circuit at the resonant frequency. For the RF signal on the main transmission line, this parallel branch is equivalent to an open circuit; therefore, RF energy cannot be shunted into this branch and is transmitted to the output port along the main transmission line with almost no loss. Simultaneously, due to the elimination of the parallel shunting effect, the impedance of the input port is maintained at 50Ω, thereby achieving ideal return loss and reducing insertion loss.

[0104] In summary, the technical effects of the circuit and its design method described above in this invention can be summarized as follows:

[0105] 1. Full-condition step-by-step collaborative matching design

[0106] Unlike existing technologies that only focus on the isolation of PIN diodes in the cutoff state, this invention proposes a step-by-step collaborative logic of prioritizing cutoff state design and secondary compensation in the on-state: based on the parasitic parameters of the PIN diode in the cutoff state, the characteristic impedance and electrical length of the compensation stub are accurately calculated to ensure that the cutoff state achieves series resonance and impedance transformation, satisfying high isolation; given that the size of the compensation stub is fixed, the T-junction structure parameters are designed in reverse to address the inductive load mismatch caused by the parasitic inductance of the parallel branch in the on-state and the inductance of the metal via, and a compensation capacitor is introduced to offset the inductive impedance.

[0107] Therefore, this invention achieves a balance between high isolation in the cutoff state and good matching in the on state with low insertion loss under all operating conditions through step-by-step collaborative logic, avoiding the trade-offs caused by single-state optimization and covering the core performance requirements of RF switches.

[0108] 2. Structurally integrated capacitor compensation

[0109] Instead of relying on additional components such as surface-mount capacitors and interdigital capacitors in existing technologies, this method utilizes the distributed parameter characteristics of the circuit's own geometry to construct a precise compensation capacitor.

[0110] A right-angle, uncut T-junction design is adopted: the edge electric field discontinuity at the intersection of microstrip lines is utilized to generate an equivalent capacitance to ground;

[0111] Locally widen the main transmission line width: Design a step impedance segment near the T-junction node and introduce an additional step capacitance;

[0112] The inductance of the parallel branch is offset by the introduced compensation capacitor.

[0113] In practical applications, the above design method can bring the following benefits:

[0114] No additional components: Simplifies circuit structure and reduces PCB area footprint;

[0115] High process compatibility: Based on standard microstrip line etching, it eliminates the need for high-precision post-processing, reducing costs;

[0116] Parasitic parameters are controllable: The integrated capacitor structure has no welding parasites, avoiding the additional losses introduced by discrete components.

[0117] 3. Incorporate the parasitic inductance of the metal via into the model.

[0118] When calculating the total impedance in the cutoff state and the total inductance in the on state, the parasitic inductance of the metal via is taken into account, and the parameters of the stub and the capacitance parameters of the T-junction are corrected in reverse. This achieves a high degree of consistency between theoretical design and actual production, meets the requirements for performance stability, and reduces the trial and error costs of R&D and production.

[0119] 4. Achieving high-frequency applications of low-cost PIN diodes

[0120] The circuit design proposed in this invention can compensate for the high parasitic parameters of low-cost PIN diodes: addressing the parasitic parameters of low-cost PIN diodes at high frequencies by compensating for stub length, T-junction capacitance, and... The combined design of impedance transformation adapts low-cost devices that were originally only applicable to low frequencies to high-frequency scenarios in the X-band.

[0121] In large-scale phased array antenna scenarios, it can reduce the cost of RF front-end switching modules while meeting the high-performance indicators of the X-band, achieving a balance between low-cost mass production and high-frequency performance.

[0122] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0123] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A radio frequency switching circuit based on parasitic parameter compensation, characterized in that, include: Input terminal, first output terminal, second output terminal, two impedance transformation sections, two output transmission lines, and two parallel branches; The input terminal is connected to one end of each of the two impedance transformation segments via a common node, and the other end of each impedance transformation segment is connected to a T-junction node; each of the T-junction nodes is connected to the first output terminal and the second output terminal via the output transmission line. One end of the parallel branch is connected to the T-junction node, and the other end is grounded; The parallel branch includes a compensation stub and a PIN diode connected in series; one end of the compensation stub is connected to the connection between the impedance transformation section and the output transmission line to form the T-junction node, and the other end is connected to the positive or negative terminal of the PIN diode; the end of the PIN diode not connected to the compensation stub is connected to the ground plane. The microstrip line structure at the T-junction node is configured to introduce a parallel capacitor to form a parallel resonance with the parallel branch in the conducting state; The angle formed by the compensation stub, the impedance transformation section, and the output transmission line is a right angle. No chamfering structure is provided on the inner side of the right angle. An equivalent parallel capacitance to ground is constructed using the edge electric field generated by the discontinuity of the metal area at the microstrip line intersection. ; A metal patch is placed at the main transmission line of the T-junction node to locally widen it, forming a low-impedance step segment, and an additional parallel step capacitor is introduced. .

2. The radio frequency switching circuit based on parasitic parameter compensation according to claim 1, characterized in that, The length of the impedance transformation section is one-quarter of the wavelength of the guided wave corresponding to the operating frequency.

3. The radio frequency switching circuit based on parasitic parameter compensation according to claim 1, characterized in that, The PIN diodes in the two parallel branches are arranged in opposite directions; the positive terminal of the PIN diode in one parallel branch is connected to the compensation stub and the negative terminal is connected to the metal via; the negative terminal of the PIN diode in the other parallel branch is connected to the compensation stub and the positive terminal is connected to the metal via.

4. The radio frequency switching circuit based on parasitic parameter compensation according to claim 1, characterized in that, It also includes a DC bias line, one end of which is connected to the connection point between the compensation stub and the PIN diode, and the other end is connected to a DC control voltage source; the DC bias line includes a high-impedance line and an RF choke connected in series.

5. The radio frequency switching circuit based on parasitic parameter compensation according to claim 3, characterized in that, The radio frequency switch circuit is disposed on the top layer of the dielectric substrate, and the ground plane is disposed on the bottom layer of the dielectric substrate. The distance between the circuit and the ground plane is determined by the thickness of the dielectric substrate. The metal via penetrates the dielectric substrate.

6. A design method for a radio frequency switching circuit based on parasitic parameter compensation as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Step 1: Obtain the parasitic capacitance, package parasitic inductance, and metal via values ​​of the PIN diode in the off state; The characteristic impedance and electrical length of the compensation stub are calculated based on the parasitic capacitance, package parasitic inductance, and metal via parasitic inductance, so that the inductive reactance provided by the compensation stub and the total impedance of the PIN diode and metal via form a series resonance at the T-junction node. Step 2: Under the condition that the characteristic impedance and electrical length of the compensation stub are fixed, obtain the conduction inductance value of the PIN diode in the conducting state; calculate the total equivalent inductance of the parallel branch including the compensation stub, the PIN diode in the conducting state, and the metal via. Step 3: Adjust the geometric parameters of the T-junction node and introduce an equivalent parallel capacitor so that the equivalent parallel capacitor and the total equivalent inductance of the parallel branch form a parallel resonance; The method for introducing the equivalent parallel capacitance includes: The angle formed by the compensation stub, the impedance transformation section, and the output transmission line is a right angle. No chamfering structure is provided on the inner side of the right angle. An equivalent parallel capacitance to ground is constructed using the edge electric field generated by the discontinuity of the metal area at the microstrip line intersection. ;as well as A metal patch is placed at the main transmission line of the T-junction node to locally widen it, forming a low-impedance step segment, and an additional parallel step capacitor is introduced. .

7. The design method for a radio frequency switching circuit based on parasitic parameter compensation according to claim 6, characterized in that, In step one, the characteristic impedance of the compensation stub is... and electrical length The following relationship must be satisfied: in, The operating angular frequency, This refers to the parasitic capacitance of a PIN diode in the cutoff state. Parasitic inductance for PIN diode cut-off state package, Parasitic inductance of a metal through-hole To compensate for the characteristic impedance of the stub, To compensate for the electrical length of the stub; In step three, the parallel resonance satisfies the following relationship: in, The total equivalent inductance of the parallel branches in the on state is given. The equivalent parallel capacitance introduced to adjust the geometric parameters of the T-junction.

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