Analog-to-digital converter circuit with grouping calibration
By grouping and calibrating the capacitor array of the analog-to-digital converter (ADC), and using multiple group capacitor array circuits to quantize and calibrate the capacitors, the problem of error accumulation caused by capacitor mismatch is solved, thereby improving the accuracy and effective number of bits of the ADC.
Patent Information
- Application Number
- CN202511645511.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-11
- Publication Date
- 2026-02-17
AI Technical Summary
In high-precision analog-to-digital converters (ADCs), the accumulation of calibration errors caused by capacitor mismatch limits the improvement of accuracy, especially in ADCs with more than 12 bits. Traditional bottom-up calibration methods cannot effectively reduce the impact of low-bit capacitor errors.
A group calibration method is adopted to calibrate the capacitor array of the analog-to-digital converter in groups. The capacitors are quantized and calibrated by multiple groups of group capacitor array circuits, which reduces error accumulation and improves calibration accuracy.
By using a group calibration method, the calibration error of the capacitor is effectively reduced, the accuracy of the analog-to-digital converter is improved, and a higher effective number of bits is achieved, which improves the accuracy by 0.5 bits compared with the traditional method.
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Figure CN121547047A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of analog-to-digital converter, in particular to an analog-to-digital converter circuit with grouped calibration. BACKGROUND
[0002] In the design and implementation of high-precision analog-to-digital converters, the precision reduction caused by capacitor mismatch is unavoidable. Therefore, in high-precision design, especially for analog-to-digital converters of more than 12 bits, capacitor calibration technology is an indispensable step to achieve high precision. The traditional capacitor technology is a bottom-up calibration technology, that is, assuming that small capacitors are ideal capacitors, using "ideal" small capacitors to calibrate large capacitors. However, in actual production and manufacturing, the small capacitors used in the calibration technology also have capacitor mismatch, and the mismatch error of the capacitors is cumulative, and the high-order capacitors will exponentially increase the mismatch error of the capacitors. The main reason is that the low-order capacitors themselves have errors, so the errors of the low-order capacitors will be brought into the measured capacitance value of the high-order capacitors. Unlike random noise, the calibration error caused by low-order capacitor mismatch cannot be eliminated by averaging, and the calibration error of the low-order capacitors also accumulates exponentially with the calibration process, thereby limiting the calibration accuracy. SUMMARY
[0003] The present application relates to the technical field of analog-to-digital converter, in particular to an analog-to-digital converter circuit with grouped calibration.
[0004] Technical scheme: In order to achieve the above-mentioned purpose, the present application provides an analog-to-digital converter circuit with grouped calibration, which comprises a capacitor array circuit, a comparator, a P-end LSB segment capacitor array circuit and an N-end LSB segment capacitor array circuit. The lower plates of a plurality of capacitors in the capacitor array circuit are electrically connected to the output terminals of the reference voltage and common mode voltage generation circuit through a switch circuit, the upper plates of the plurality of capacitors in the capacitor array circuit are connected to the VCM signal through a control switch, and the upper plates of the plurality of capacitors in the capacitor array circuit are respectively electrically connected to the positive input terminal and the negative input terminal of the comparator through the control switch. The output terminals of the P-end LSB segment capacitor array circuit and the N-end LSB segment capacitor array circuit are respectively electrically connected to the positive input terminal and the negative input terminal of the comparator through control switches, the input terminals of the P-end LSB segment capacitor array circuit and the N-end LSB segment capacitor array circuit are respectively connected to the VCM signal through control switches, and the positive input terminal and the negative input terminal of the comparator are respectively connected to the VCM signal through control switches. The upper plates of the capacitor array circuit are respectively connected to the P-end LSB segment capacitor array circuit and the N-end LSB segment capacitor array circuit, and the plurality of capacitors in the capacitor array circuit are sequentially calibrated in groups.
[0005] Further, the capacitor array circuit includes a P-end capacitor array circuit and an N-end capacitor array circuit; the lower plates of a plurality of capacitors in the P-end capacitor array circuit are electrically connected to the output end of the first reference voltage and common mode voltage generating circuit through a switch circuit, and the lower plates of a plurality of capacitors in the N-end capacitor array circuit are electrically connected to the output end of the second reference voltage and common mode voltage generating circuit through a switch circuit; the upper plates of a plurality of capacitors in the P-end capacitor array circuit are connected to the VCM signal through an ST1 control switch, and the upper plates of a plurality of capacitors in the N-end capacitor array circuit are connected to the VCM signal through an ST3 control switch; the upper plates of a plurality of capacitors in the P-end capacitor array circuit are electrically connected to the positive input end of the comparator through an ST2 control switch, and the upper plates of a plurality of capacitors in the N-end capacitor array circuit are respectively connected to the negative input end of the comparator through an ST4 control switch.
[0006] Further, the P-end LSB section capacitor array circuit includes a Group1 capacitor array circuit, a Group2 capacitor array circuit, a Group3 capacitor array circuit, and a Group4 capacitor array circuit; the output ends of the Group1 capacitor array circuit, the Group2 capacitor array circuit, the Group3 capacitor array circuit, and the Group4 capacitor array circuit are electrically connected to the positive input end of the comparator through an S1 control switch, an S2 control switch, an S3 control switch, and an S4 control switch, respectively; and the input ends of the Group1 capacitor array circuit, the Group2 capacitor array circuit, the Group3 capacitor array circuit, and the Group4 capacitor array circuit are connected to the VCM signal through a control switch as the input end of the P-end LSB section capacitor array circuit.
[0007] Further, the N-end LSB section capacitor array circuit includes a Group5 capacitor array circuit, a Group6 capacitor array circuit, a Group7 capacitor array circuit, and a Group8 capacitor array circuit; the output ends of the Group5 capacitor array circuit, the Group6 capacitor array circuit, the Group7 capacitor array circuit, and the Group8 capacitor array circuit are electrically connected to the negative input end of the comparator through an S5 control switch, an S6 control switch, an S7 control switch, and an S8 control switch, respectively; and the input ends of the Group5 capacitor array circuit, the Group6 capacitor array circuit, the Group7 capacitor array circuit, and the Group8 capacitor array circuit are connected to the VCM signal through a control switch as the input end of the N-end LSB section capacitor array circuit.
[0008] Further, the positive input end of the comparator is connected to the VCM signal through an S9 control switch, and the negative input end of the comparator is connected to the VCM signal through an S10 control switch.
[0009] Further, the output end of the first reference voltage and common mode voltage generating circuit and the output end of the second reference voltage and common mode voltage generating circuit both output VREFN signal, VREFP signal and VCM signal.
[0010] Further, when quantitatively calibrating the capacitors in the P-end capacitor array circuit, ST1 control switch is closed, ST2 control switch is closed, S10 control switch is closed, and the rest of the control switches are opened; at this time, the lower plate of the capacitor to be calibrated in the P-end capacitor array circuit is connected to VREFP signal or VREFN signal, and the lower plate of the rest of the capacitors in the P-end capacitor array circuit is connected to VREFN signal.
[0011] At this time, S1 control switch is closed, the lower plate of the capacitors in Group1 capacitor array circuit is connected to VCM signal, and Group1 capacitor array circuit is used to quantitatively calibrate the capacitor to be calibrated; then S1 control switch is opened, S2 control switch is closed, the lower plate of the capacitors in Group2 capacitor array circuit is connected to VCM signal, and Group2 capacitor array circuit is used to quantitatively calibrate the capacitor to be calibrated; then S2 control switch is opened, S3 control switch is closed, the lower plate of the capacitors in Group3 capacitor array circuit is connected to VCM signal, and Group3 capacitor array circuit is used to quantitatively calibrate the capacitor to be calibrated; then S3 control switch is opened, S4 control switch is closed, the lower plate of the capacitors in Group4 capacitor array circuit is connected to VCM signal, and Group4 capacitor array circuit is used to quantitatively calibrate the capacitor to be calibrated; Group1 capacitor array circuit, Group2 capacitor array circuit, Group3 capacitor array circuit and Group4 capacitor array circuit are used to quantitatively calibrate the capacitor to be calibrated in turn.
[0012] Further, when quantitatively calibrating the capacitors in the P-end capacitor array circuit, ST1 control switch is closed, ST2 control switch is closed, S10 control switch is closed, and the rest of the control switches are opened; at this time, the lower plate of the capacitor to be calibrated in the P-end capacitor array circuit is connected to VREFP signal or VREFN signal, and the lower plate of the rest of the capacitors in the P-end capacitor array circuit is connected to VREFN signal.
[0013] At this time, the S5 control switch is closed, the lower plate of several capacitors in the Group 5 capacitor array circuit is connected to the VCM signal, the Group 5 capacitor array circuit is used to quantitatively calibrate the capacitors to be calibrated; then the S5 control switch is opened, the S6 control switch is closed, the lower plate of several capacitors in the Group 6 capacitor array circuit is connected to the VCM signal, the Group 6 capacitor array circuit is used to quantitatively calibrate the capacitors to be calibrated; then the S6 control switch is opened, the S7 control switch is closed, the lower plate of several capacitors in the Group 7 capacitor array circuit is connected to the VCM signal, the Group 7 capacitor array circuit is used to quantitatively calibrate the capacitors to be calibrated; then the S7 control switch is opened, the S8 control switch is closed, the lower plate of several capacitors in the Group 8 capacitor array circuit is connected to the VCM signal, the Group 8 capacitor array circuit is used to quantitatively calibrate the capacitors to be calibrated; the Group 5 capacitor array circuit, the Group 6 capacitor array circuit, the Group 7 capacitor array circuit and the Group 8 capacitor array circuit are used to quantitatively calibrate the capacitors to be calibrated in turn.
[0014] Beneficial effects: the analog-to-digital converter circuit with grouping calibration provided by the application can calibrate capacitors in groups through several Group capacitor array circuits, average the errors of small capacitors, reduce the error accumulation effect, and solve the problem of error accumulation in the traditional bottom-up calibration method; all capacitors in the P terminal capacitor array circuit and the N terminal capacitor array circuit can be quantitatively calibrated by controlling the control switches in the circuit, each capacitor can be quantitatively calibrated in groups, the calibration accuracy of each capacitor is improved, and all capacitors in the capacitor array can be calibrated in groups in all aspects. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 It is a circuit diagram of the analog-to-digital converter circuit with grouping calibration.
[0016] Figure 2 It is a simplified diagram of the switch circuit.
[0017] Figure 3 It is a comparison diagram of the bottom-up calibration method and the Group grouping calibration method for capacitor calibration. DETAILED DESCRIPTION
[0018] The application will be further described below with reference to the accompanying drawings.
[0019] As Figure 1As shown, an analog-to-digital converter circuit with grouping calibration includes a capacitor array circuit, a comparator 5, a P-end LSB segment capacitor array circuit and an N-end LSB segment capacitor array circuit; the lower plates of a plurality of capacitors in the capacitor array circuit are electrically connected to the output terminals of a reference voltage and a common-mode voltage generation circuit through a switch circuit, the upper plates of the plurality of capacitors in the capacitor array circuit are connected to a VCM signal through a control switch, and the upper plates of the plurality of capacitors in the capacitor array circuit are respectively electrically connected to the positive input terminal and the negative input terminal of the comparator 5 through control switches; the output terminals of the P-end LSB segment capacitor array circuit and the N-end LSB segment capacitor array circuit are respectively electrically connected to the positive input terminal and the negative input terminal of the comparator 5 through control switches, the output terminal of the comparator 5 is connected to a subsequent circuit and outputs a signal after comparison; the input terminals of the P-end LSB segment capacitor array circuit and the N-end LSB segment capacitor array circuit are respectively connected to the VCM signal through control switches, and the positive input terminal and the negative input terminal of the comparator 5 are respectively connected to the VCM signal through control switches; the upper plates of the capacitor array circuit are respectively connected to the P-end LSB segment capacitor array circuit and the N-end LSB segment capacitor array circuit, and a plurality of capacitors in the capacitor array circuit are sequentially grouped and quantitatively calibrated; after the capacitors in the analog-to-digital converter are grouped and quantitatively calibrated, the analog-to-digital converter can perform subsequent analog-to-digital conversion work.
[0020] The capacitor array circuit includes a P-end capacitor array circuit 1 and an N-end capacitor array circuit 3; the lower plates of a plurality of capacitors in the P-end capacitor array circuit 1 are electrically connected to the output terminals of a first reference voltage and a common-mode voltage generation circuit 2 through a switch circuit, and the lower plates of a plurality of capacitors in the N-end capacitor array circuit 3 are electrically connected to the output terminals of a second reference voltage and a common-mode voltage generation circuit 4 through a switch circuit; the upper plates of a plurality of capacitors in the P-end capacitor array circuit 1 are connected to a VCM signal through an ST1 control switch, and the upper plates of a plurality of capacitors in the N-end capacitor array circuit 3 are connected to the VCM signal through an ST3 control switch; the upper plates of a plurality of capacitors in the P-end capacitor array circuit 1 are electrically connected to the positive input terminal of the comparator 5 through an ST2 control switch, and the upper plates of a plurality of capacitors in the N-end capacitor array circuit 3 are respectively connected to the negative input terminal of the comparator 5 through an ST4 control switch.
[0021] The P-terminal capacitor array circuit 1 includes capacitors C1 to CN; the N-terminal capacitor array circuit 3 includes capacitors C11 to C1N; the lower plates of capacitors C1 to CN are electrically connected to the output terminals of the first reference voltage and common-mode voltage generation circuit 2 via a switching circuit, and the lower plates of capacitors C11 to C1N are electrically connected to the output terminals of the second reference voltage and common-mode voltage generation circuit 3 via a switching circuit; the upper plates of capacitors C1 to CN are electrically connected to the positive input terminal of comparator 5 via a control switch ST2, and the upper plates of capacitors C11 to C1N are electrically connected to the negative input terminal of comparator 5 via a control switch ST4. The switching circuit includes three control switches: SS1 control switch, SS2 control switch, and SS3 control switch; for example... Figure 2 As shown, the lower plate of the capacitor is electrically connected to the reference voltage and the VCM signal output terminal, VREFP signal output terminal, and VREFN signal output terminal of the common-mode voltage generation circuit through SS1 control switch, SS2 control switch, and SS3 control switch, respectively; that is, the lower plate of each of the capacitors C1 to CN and C11 to C1N is connected to the VCM signal, VREFP signal, and VREFN signal through SS1 control switch, SS2 control switch, and SS3 control switch, respectively.
[0022] The P-terminal LSB segment capacitor array circuit includes Group1 capacitor array circuit 11, Group2 capacitor array circuit 12, Group3 capacitor array circuit 13, and Group4 capacitor array circuit 14. The output terminals of Group1 capacitor array circuit 11, Group2 capacitor array circuit 12, Group3 capacitor array circuit 13, and Group4 capacitor array circuit 14 are electrically connected to the positive input terminal of comparator 5 through control switches S1, S2, S3, and S4, respectively. The input terminals of Group1 capacitor array circuit 11, Group2 capacitor array circuit 12, Group3 capacitor array circuit 13, and Group4 capacitor array circuit 14 are all used as input terminals of the P-terminal LSB segment capacitor array circuit and are connected to the VCM signal through control switches.
[0023] The N-terminal LSB segment capacitor array circuit includes Group5 capacitor array circuit 21, Group6 capacitor array circuit 22, Group7 capacitor array circuit 23, and Group8 capacitor array circuit 24. The output terminals of Group5 capacitor array circuit 21, Group6 capacitor array circuit 22, Group7 capacitor array circuit 23, and Group8 capacitor array circuit 24 are electrically connected to the negative input terminal of comparator 5 through control switches S5, S6, S7, and S8, respectively. The input terminals of Group5 capacitor array circuit 21, Group6 capacitor array circuit 22, Group7 capacitor array circuit 23, and Group8 capacitor array circuit 24 are all used as input terminals of the N-terminal LSB segment capacitor array circuit and are connected to the VCM signal through control switches.
[0024] The output of the Group 1 capacitor array circuit 11 is electrically connected to the positive input of the comparator 5 via a control switch S1; the output of the Group 2 capacitor array circuit 12 is electrically connected to the positive input of the comparator 5 via a control switch S2; the output of the Group 3 capacitor array circuit 13 is electrically connected to the positive input of the comparator 5 via a control switch S3; the output of the Group 4 capacitor array circuit 14 is electrically connected to the positive input of the comparator 5 via a control switch S4; the output of the Group 5 capacitor array circuit 21 is electrically connected to the negative input of the comparator 5 via a control switch S5; the output of the Group 6 capacitor array circuit 22 is electrically connected to the negative input of the comparator 5 via a control switch S6; the output of the Group 7 capacitor array circuit 23 is electrically connected to the negative input of the comparator 5 via a control switch S7; and the output of the Group 8 capacitor array circuit 24 is electrically connected to the negative input of the comparator 5 via a control switch S8.
[0025] The Group1 capacitor array circuit 11, Group2 capacitor array circuit 12, Group3 capacitor array circuit 13, Group4 capacitor array circuit 14, Group5 capacitor array circuit 21, Group6 capacitor array circuit 22, Group7 capacitor array circuit 23, and Group8 capacitor array circuit 24 all have the same circuit structure and are all Group capacitor array circuits. Each Group capacitor array circuit includes several capacitors, and there are no fewer than two capacitors in each Group capacitor array circuit. The size of each capacitor is a unit capacitance. The lower plate of each capacitor is connected to the VCM signal through a control switch, and the upper plate of each capacitor serves as the output terminal of the Group capacitor array circuit. The capacitors in each Group capacitor array circuit are all dummy capacitors.
[0026] The positive input terminal of the comparator 5 is connected to the VCM signal via the S9 control switch, and the negative input terminal of the comparator 5 is connected to the VCM signal via the S10 control switch.
[0027] The output terminals of the first reference voltage and common-mode voltage generation circuit 2 and the second reference voltage and common-mode voltage generation circuit 4 both output VREFN, VREFP, and VCM signals; the output terminals of the first reference voltage and common-mode voltage generation circuit 2 and the second reference voltage and common-mode voltage generation circuit 4 both include a VCM signal output terminal, a VREFP signal output terminal, and a VREFN signal output terminal, and respectively output VCM, VREFP, and VREFN signals.
[0028] When performing quantization calibration on several capacitors in the P-terminal capacitor array circuit 1, control switches ST1, ST2, and S10 are closed, while the remaining control switches are open. At this time, the lower plates of the capacitors to be calibrated in the P-terminal capacitor array circuit 1 are alternately connected to either the VREFP signal or the VREFN signal, i.e., the lower plate of the capacitor to be calibrated is first connected to the VREFP signal and then to the VREFN signal; the lower plates of the other capacitors in the P-terminal capacitor array circuit 1 are connected to the VREFN signal.
[0029] At this point, control switch S1 is closed, and the lower plates of several capacitors in Group 1 capacitor array circuit 11 are connected to the VCM signal. Group 1 capacitor array circuit 11 is used to perform quantization calibration on the capacitor to be calibrated. Then, control switch S1 is opened, and control switch S2 is closed, connecting the lower plates of several capacitors in Group 2 capacitor array circuit 12 to the VCM signal. Group 2 capacitor array circuit 12 is used to perform quantization calibration on the capacitor to be calibrated. Then, control switch S2 is opened, and control switch S3 is closed, connecting the lower plates of several capacitors in Group 3 capacitor array circuit 13 to the VCM signal. Group 3 capacitor array circuit 13 is used to perform quantization calibration on the capacitor to be calibrated. The calibration capacitor is quantized and calibrated; then, the S3 control switch is opened and the S4 control switch is closed, and the lower plate of several capacitors in the Group4 capacitor array circuit 14 is connected to the VCM signal. The Group4 capacitor array circuit 14 is used to quantize and calibrate the capacitor to be calibrated; the Group1 capacitor array circuit 11, Group2 capacitor array circuit 12, Group3 capacitor array circuit 13 and Group4 capacitor array circuit 14 sequentially quantize and calibrate the capacitor to be calibrated in the P-end capacitor array circuit 1; thus, the same capacitor is calibrated by grouping multiple Group capacitor array circuits, which effectively reduces the calibration error of the capacitor.
[0030] For example, when quantizing and calibrating each capacitor in the P-terminal capacitor array circuit 1, the ST1 control switch is closed, the ST2 control switch is closed, so that the upper plates of the capacitors in the P-terminal capacitor array circuit 1 are connected to the VCM signal; the S10 control switch is closed, so that the negative input terminal of the comparator 5 is connected to the VCM signal, and the other control switches are all open; at this time, the lower plate of capacitor C1 in the P-terminal capacitor array circuit 1 is connected to the VREFP signal or the VREFN signal, so that the capacitance values at both ends can be obtained. The lower plates of the other capacitors in the P-terminal capacitor array circuit 1 are connected to the VREFN signal, and the C1 capacitor is quantized and calibrated sequentially through the Group1 capacitor array circuit 11, the Group2 capacitor array circuit 12, the Group3 capacitor array circuit 13, and the Group4 capacitor array circuit 14.
[0031] Then, the lower plate of capacitor C2 in capacitor array circuit 1 is connected to the VREFP or VREFN signal to achieve the capacitance value at both positive and negative ends. The lower plates of the remaining capacitors in capacitor array circuit 1 are connected to the VREFN signal, and capacitor C2 is quantized and calibrated sequentially through capacitor array circuits 11, 12, 13, and 14 of Group 1. The same method is used to quantize and calibrate capacitors C1, C2, ..., CN in groups until the lower plate of capacitor CN in capacitor array circuit 1 is connected to the VREFP or VREFN signal to achieve the capacitance value at both positive and negative ends. The lower plates of the remaining capacitors in capacitor array circuit 1 are connected to the VREFN signal, and capacitor CN is quantized and calibrated sequentially through capacitor array circuits 11, 12, 13, and 14 of Group 1.
[0032] When performing quantization calibration on several capacitors in the N-terminal capacitor array circuit 3, control switches ST3, ST4, and S9 are closed, while the remaining control switches are open. At this time, the lower plates of the capacitors to be calibrated in the N-terminal capacitor array circuit 3 are alternately connected to either the VREFP signal or the VREFN signal, i.e., the lower plate of the capacitor to be calibrated is first connected to the VREFP signal and then to the VREFN signal; the lower plates of the other capacitors in the N-terminal capacitor array circuit 3 are connected to the VREFN signal.
[0033] At this point, control switch S5 is closed, and the lower plates of several capacitors in Group 5 capacitor array circuit 21 are connected to the VCM signal. Group 5 capacitor array circuit 21 is used to perform quantization calibration on the capacitor to be calibrated. Then, control switch S5 is opened, and control switch S6 is closed. The lower plates of several capacitors in Group 6 capacitor array circuit 22 are connected to the VCM signal. Group 6 capacitor array circuit 22 is used to perform quantization calibration on the capacitor to be calibrated. Then, control switch S6 is opened, and control switch S7 is closed. The lower plates of several capacitors in Group 7 capacitor array circuit 23 are connected to the VCM signal. Group 7 capacitor array circuit 23 is used to perform quantization calibration on the capacitor to be calibrated. The calibration capacitor is quantized and calibrated; then, the S7 control switch is opened and the S8 control switch is closed, and the lower plates of several capacitors in the Group8 capacitor array circuit 24 are connected to the VCM signal. The Group8 capacitor array circuit 24 is used to quantize and calibrate the capacitor to be calibrated; the Group5 capacitor array circuit 21, Group6 capacitor array circuit 22, Group7 capacitor array circuit 23 and Group8 capacitor array circuit 24 sequentially quantize and calibrate the capacitor to be calibrated in the N-terminal capacitor array circuit 3; thus, the same capacitor is calibrated by grouping multiple Group capacitor array circuits, which effectively reduces the calibration error of the capacitor.
[0034] For example, when quantizing and calibrating each capacitor in the N-terminal capacitor array circuit 3, the ST3 control switch is closed, the ST4 control switch is closed, so that the upper plates of the capacitors in the N-terminal capacitor array circuit 3 are connected to the VCM signal; the S9 control switch is closed, so that the positive input terminal of the comparator 5 is connected to the VCM signal, and the other control switches are all open; at this time, the lower plate of capacitor C11 in the N-terminal capacitor array circuit 3 is connected to the VREFP signal or the VREFN signal, so that the capacitance values at the positive and negative ends can be obtained. The lower plates of the other capacitors in the N-terminal capacitor array circuit 3 are connected to the VREFN signal, and the C11 capacitor is quantized and calibrated sequentially through the Group5 capacitor array circuit 21, the Group6 capacitor array circuit 22, the Group7 capacitor array circuit 23, and the Group8 capacitor array circuit 24.
[0035] Then, the lower plate of capacitor C12 in N-terminal capacitor array circuit 3 is connected to the VREFP or VREFN signal to achieve the capacitance value at both positive and negative ends. The lower plates of the remaining capacitors in N-terminal capacitor array circuit 3 are connected to the VREFN signal, and capacitor C12 is quantized and calibrated sequentially through capacitor array circuits 21 (Group 5), 22 (Group 6), 23 (Group 7), and 24 (Group 8). The same method is then used to quantize and calibrate capacitors C11, C12, ..., C1N in groups until the lower plate of capacitor C1N in N-terminal capacitor array circuit 3 is connected to the VREFP or VREFN signal, thus achieving the capacitance value at both positive and negative ends. The lower plates of the remaining capacitors in N-terminal capacitor array circuit 3 are connected to the VREFN signal, and capacitor C1N is quantized and calibrated sequentially through capacitor array circuits 21 (Group 5), 22 (Group 6), 23 (Group 7), and 24 (Group 8). The control of all the control switches described above can be achieved using logic control circuits.
[0036] The P-terminal LSB segment capacitor array circuit can include several group capacitor array circuits. These group capacitor array circuits sequentially quantize and calibrate the capacitors to be calibrated in the P-terminal capacitor array circuit 1. Similarly, the N-terminal LSB segment capacitor array circuit can include several group capacitor array circuits. These group capacitor array circuits sequentially quantize and calibrate the capacitors to be calibrated in the N-terminal capacitor array circuit 3. If either the P-terminal LSB segment capacitor array circuit or the N-terminal LSB segment capacitor array circuit contains M group capacitor array circuits, then the capacitance error can be reduced to:
[0037]
[0038]
[0039]
[0040] In the formula, M represents the number of groups, j represents the capacitor label, mis represents the capacitor mismatch, cal represents the calibrated capacitor mismatch, N represents the normal distribution, and D... j Represented as a weighting factor; e j,mis,ave This represents the mismatch error averaged across M capacitor groups, where each capacitor group is a Group capacitor array circuit; e j,mis,G1 This is expressed as the mismatch error of a single capacitor in the G1th capacitor bank; e j,mis This is expressed as the mismatch error of a single capacitor; e i,cal,ave This represents the average mismatch error of a single capacitor after calibration. This is expressed as the variance of the capacitor mismatch error.
[0041] As can be seen from the above formula, after group calibration, the error of the ideal small capacitor will be reduced to 1 / M times; the group calibration method can effectively reduce the capacitance error of the small capacitor.
[0042] like Figure 3 The figure shows a comparison between calibrating the capacitors in an ADC using the original bottom-up calibration method and calibrating the capacitors using the Group calibration method proposed in this invention. The Group calibration method of this invention is modeled and applied to an 18-bit ADC model, and the differences between the traditional bottom-up calibration method and the Group calibration method are compared. In the model, capacitors are increased by 0.1% capacitance mismatch, and Monte Carlo simulations are performed with 128 groups of capacitors. The Group calibration uses two groups of capacitor array circuits. The accuracy of the proposed Group calibration method is improved by 0.5 bits compared to the original calibration scheme. This simulation fully demonstrates the effectiveness of the Group calibration method. It can also be seen that the Group calibration method has a higher number of significant ENOB bits compared to the original bottom-up calibration method, and the number of times the number of significant ENOB bits is high is greater than that of the original bottom-up calibration method. Therefore, the Group calibration method of this invention has higher calibration accuracy than the original bottom-up calibration method.
[0043] The above description is merely a preferred embodiment of the present invention. Those skilled in the art can make several modifications and optimizations based on the above disclosure without departing from the basic principles described above. These modifications and optimizations should be considered within the scope of protection as understood by the present invention.
Claims
1. An analog-to-digital converter circuit with group calibration, characterized in that: The circuit includes a capacitor array circuit, a comparator (5), a P-terminal LSB segment capacitor array circuit, and an N-terminal LSB segment capacitor array circuit. The lower plates of several capacitors in the capacitor array circuit are electrically connected to the output terminals of the reference voltage and common-mode voltage generation circuit via switching circuits. The upper plates of several capacitors in the capacitor array circuit are connected to the VCM signal via control switches. Furthermore, the upper plates of several capacitors in the capacitor array circuit are electrically connected to the positive and negative input terminals of the comparator (5) via control switches. The output terminals of the P-terminal LSB segment capacitor array circuit and the N-terminal LSB segment capacitor array circuit... The output terminals of the segment capacitor array circuit are electrically connected to the positive and negative input terminals of the comparator (5) through control switches. The input terminals of the P-terminal LSB segment capacitor array circuit and the N-terminal LSB segment capacitor array circuit are connected to the VCM signal through control switches. The positive and negative input terminals of the comparator (5) are connected to the VCM signal through control switches. The capacitors in the capacitor array circuit are sequentially grouped and calibrated by connecting the P-terminal LSB segment capacitor array circuit and the N-terminal LSB segment capacitor array circuit to the upper plate of the capacitor array circuit.
2. The analog-to-digital converter circuit with group calibration according to claim 1, characterized in that: The capacitor array circuit includes a P-terminal capacitor array circuit (1) and an N-terminal capacitor array circuit (3). The lower plates of several capacitors in the P-terminal capacitor array circuit (1) are electrically connected to the output terminals of the first reference voltage and the common-mode voltage generation circuit (2) through a switching circuit. The lower plates of several capacitors in the N-terminal capacitor array circuit (3) are electrically connected to the output terminals of the second reference voltage and the common-mode voltage generation circuit (4) through a switching circuit. The upper plates of several capacitors in the P-terminal capacitor array circuit (1) are connected to the VCM signal through the ST1 control switch. The upper plates of several capacitors in the N-terminal capacitor array circuit (3) are connected to the VCM signal through the ST3 control switch. The upper plates of several capacitors in the P-terminal capacitor array circuit (1) are electrically connected to the positive input terminal of the comparator (5) through the ST2 control switch. The upper plates of several capacitors in the N-terminal capacitor array circuit (3) are respectively connected to the negative input terminal of the comparator (5) through the ST4 control switch.
3. The analog-to-digital converter circuit with group calibration according to claim 2, characterized in that: The P-terminal LSB segment capacitor array circuit includes Group1 capacitor array circuit (11), Group2 capacitor array circuit (12), Group3 capacitor array circuit (13), and Group4 capacitor array circuit (14). The output terminals of Group1 capacitor array circuit (11), Group2 capacitor array circuit (12), Group3 capacitor array circuit (13), and Group4 capacitor array circuit (14) are electrically connected to the positive input terminal of comparator (5) through control switches S1, S2, S3, and S4, respectively. The input terminals of Group1 capacitor array circuit (11), Group2 capacitor array circuit (12), Group3 capacitor array circuit (13), and Group4 capacitor array circuit (14) are all used as input terminals of the P-terminal LSB segment capacitor array circuit and connected to the VCM signal through control switches.
4. The analog-to-digital converter circuit with group calibration according to claim 3, characterized in that: The N-terminal LSB segment capacitor array circuit includes Group5 capacitor array circuit (21), Group6 capacitor array circuit (22), Group7 capacitor array circuit (23), and Group8 capacitor array circuit (24). The output terminals of Group5 capacitor array circuit (21), Group6 capacitor array circuit (22), Group7 capacitor array circuit (23), and Group8 capacitor array circuit (24) are electrically connected to the negative input terminal of comparator (5) through control switches S5, S6, S7, and S8, respectively. The input terminals of Group5 capacitor array circuit (21), Group6 capacitor array circuit (22), Group7 capacitor array circuit (23), and Group8 capacitor array circuit (24) are all used as input terminals of the N-terminal LSB segment capacitor array circuit and connected to the VCM signal through control switches.
5. The analog-to-digital converter circuit with group calibration according to claim 4, characterized in that: The positive input terminal of the comparator (5) is connected to the VCM signal via the S9 control switch, and the negative input terminal of the comparator (5) is connected to the VCM signal via the S10 control switch.
6. The analog-to-digital converter circuit with group calibration according to claim 5, characterized in that: The output terminals of the first reference voltage and common mode voltage generation circuit (2) and the second reference voltage and common mode voltage generation circuit (4) both output VREFN signal, VREFP signal and VCM signal.
7. The analog-to-digital converter circuit with group calibration according to claim 6, characterized in that: When quantizing and calibrating several capacitors in the P-end capacitor array circuit (1), the ST1 control switch is closed, the ST2 control switch is closed, the S10 control switch is closed, and the remaining control switches are open; at this time, the lower plate of the capacitor to be calibrated in the P-end capacitor array circuit (1) is connected to the VREFP signal or the VREFN signal, and the lower plate of the remaining capacitors in the P-end capacitor array circuit (1) is connected to the VREFN signal. At this time, the S1 control switch is closed, and the lower plates of several capacitors in the Group1 capacitor array circuit (11) are connected to the VCM signal. The Group1 capacitor array circuit (11) is used to quantize and calibrate the capacitor to be calibrated. Then, the S1 control switch is opened, the S2 control switch is closed, and the lower plates of several capacitors in the Group2 capacitor array circuit (12) are connected to the VCM signal. The Group2 capacitor array circuit (12) is used to quantize and calibrate the capacitor to be calibrated. Then, the S2 control switch is opened, the S3 control switch is closed, and the lower plates of several capacitors in the Group3 capacitor array circuit (13) are connected to the VCM signal. The VCM signal is transmitted, and the Group3 capacitor array circuit (13) is used to quantize and calibrate the capacitor to be calibrated; then the S3 control switch is opened, the S4 control switch is closed, and the lower plate of several capacitors in the Group4 capacitor array circuit (14) is connected to the VCM signal. The Group4 capacitor array circuit (14) is used to quantize and calibrate the capacitor to be calibrated; the Group1 capacitor array circuit (11), Group2 capacitor array circuit (12), Group3 capacitor array circuit (13) and Group4 capacitor array circuit (14) are used to quantize and calibrate the capacitor to be calibrated in sequence.
8. The analog-to-digital converter circuit with group calibration according to claim 6, characterized in that: When quantizing and calibrating several capacitors in the N-terminal capacitor array circuit (3), the ST3 control switch is closed, the ST4 control switch is closed, the S9 control switch is closed, and the remaining control switches are open; at this time, the lower plate of the capacitor to be calibrated in the N-terminal capacitor array circuit (3) is connected to the VREFP signal or the VREFN signal, and the lower plate of the remaining capacitors in the N-terminal capacitor array circuit (3) is connected to the VREFN signal. At this time, the S5 control switch is closed, and the lower plates of several capacitors in the Group5 capacitor array circuit (21) are connected to the VCM signal. The Group5 capacitor array circuit (21) is used to quantize and calibrate the capacitor to be calibrated. Then, the S5 control switch is opened, the S6 control switch is closed, and the lower plates of several capacitors in the Group6 capacitor array circuit (22) are connected to the VCM signal. The Group6 capacitor array circuit (22) is used to quantize and calibrate the capacitor to be calibrated. Then, the S6 control switch is opened, the S7 control switch is closed, and the lower plates of several capacitors in the Group7 capacitor array circuit (23) are connected to the VCM signal. The VCM signal is transmitted, and the Group7 capacitor array circuit (23) is used to quantize and calibrate the capacitor to be calibrated; then the S7 control switch is opened, the S8 control switch is closed, and the lower plate of several capacitors in the Group8 capacitor array circuit (24) is connected to the VCM signal. The Group8 capacitor array circuit (24) is used to quantize and calibrate the capacitor to be calibrated; the Group5 capacitor array circuit (21), Group6 capacitor array circuit (22), Group7 capacitor array circuit (23) and Group8 capacitor array circuit (24) are used to quantize and calibrate the capacitor to be calibrated in sequence.