Clock frequency self-adaption test method and device, readable storage medium and chip
By automatically adjusting the number of divider stages in the test machine, the problem of insufficient test accuracy caused by the fixed number of clock oscillator divider stages is solved, achieving more efficient test adaptability and layout area utilization.
Patent Information
- Application Number
- CN202512040419.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-02-24
AI Technical Summary
In the existing technology, the number of frequency divider stages of the clock oscillator is fixed, which cannot adapt to different test devices and test conditions, resulting in insufficient test accuracy and limited layout area.
The test machine performs preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies. Based on the performance matching, the target clock signal is determined, and the number of frequency divider levels is automatically adjusted to broaden the measurable range.
It enables large-scale testing in complex testing scenarios, improves testing accuracy and adaptability, and reduces wasted layout area.
Smart Images
Figure CN121559289A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device testing, and particularly relates to a test method, apparatus, readable storage medium, and chip for clock frequency self-adaptation. Background Technology
[0002] WAT (Wafer Acceptance Test) is an electrical test performed on semiconductor silicon wafers after all manufacturing processes have been completed. This test uses a testing machine and probe station to monitor the electrical parameters to ensure the normality and stability of each process step. Analysis of WAT data can identify problems in the semiconductor manufacturing process, helping to guide adjustments to achieve higher yields.
[0003] Clock oscillators are critical monitoring structures for wafer fabrication plants and chip design companies. The device's delay time (the reciprocal of the clock signal frequency) and the matching range of the test equipment are very important. Therefore, the number of frequency divider stages for the clock signal needs to be carefully considered.
[0004] Taking the mainstream WAT testing equipment in the industry (Guangliwei T4100S) as an example, on the one hand, the upper limit of the frequency range that the frequency measurement unit (FMU) can measure is 20MHz, which restricts the number of FDs (frequency dividers) from being too small. On the other hand, with a limited layout area, increasing the number of frequency dividers will drastically increase the layout area.
[0005] Currently, the existing circuit structure of on-chip clock oscillators can be referenced. Figure 1 A fixed number of clock oscillator rings are typically used. Figure 1 The RO (ring oscillator) in the circuit provides a clock signal at a specific frequency. After passing through an inverter (BUF), it is connected to a frequency divider (FD) with a fixed number of stages (N) to output a clock signal at a fixed frequency. The circuit cannot be changed under different test conditions. However, the output frequency can be affected by different test device structures and test conditions by tens of times, making it impossible to use a single frequency divider to adapt to all devices and test conditions.
[0006] Therefore, there is a great need for a solution that can automatically adapt to a frequency divider that matches the performance of the test machine in device testing, in order to improve test accuracy. Summary of the Invention
[0007] To address all or part of the problems of the prior art, this invention provides a clock frequency self-adaptive testing method, a clock frequency self-adaptive testing device, a computer-readable storage medium, and a chip.
[0008] Firstly, this embodiment provides a clock frequency self-adaptation test method, including: The test machine performs preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies. The preprocessing includes: the test machine starts the test process for the device under test, generates a clock signal, connects it to the frequency divider for frequency division processing, and obtains the working clock signal of the device under test. Based on the performance matching of the multiple working clock signals of different frequencies with the test machine, the target clock signal of the device under test is determined; Based on the target clock signal, the test machine performs measurements on the chip under test and obtains the test results.
[0009] In some embodiments, the test machine performs preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple operating clock signals of different frequencies, including: Obtain the number of prediction divider stages of the device under test; Determine the frequency division step path; Based on the predicted frequency divider stage and frequency division step, multiple frequency divider stages are set as frequency divider stage test groups; The test machine performs multiple preprocessing operations on the device under test, each applying the aforementioned frequency divider stage, to obtain multiple operating clock signals of different frequencies.
[0010] In some embodiments, obtaining the number of predictive divider stages of the device under test includes: The device under test is simulated to determine the number of predictive divider stages that match the performance of the test machine.
[0011] In some embodiments, determining the target clock signal for the device under test based on the performance matching of the plurality of different frequency operating clock signals with the test machine includes: In the frequency divider stage test group, the operating clock signal frequency obtained by applying each of the other frequency divider stages is compared with the operating clock signal frequency obtained by applying the predicted frequency divider stage to obtain multiple ratios; Based on the multiple ratios and the frequencies of the multiple working clock signals, a target clock signal is determined to match the performance of the test machine.
[0012] In some embodiments, determining the target clock signal that matches the performance of the test machine based on the plurality of ratios and the frequencies of the plurality of operating clock signals includes: Determine whether each of the multiple ratios is within a preset ratio error range and satisfies a corresponding preset value: If all of the above ratios are satisfied, then find the target clock signal that matches the ideal operating frequency range of the test machine based on the frequency of the operating clock signal. If at least one of the multiple ratios is not satisfied, the frequency divider stage test group is adjusted according to the distribution of the unsatisfied ratios and the frequency division step size, and then repeated verification is performed. The repeated verification includes: the test machine performing preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies; and determining the target clock signal of the device under test based on the performance matching of the multiple working clock signals of different frequencies with the test machine.
[0013] In some embodiments, finding a target clock signal that matches the ideal operating frequency range of the test machine based on the frequency of the operating clock signal includes: Determine whether, among the plurality of operating clock signals, there is a first operating clock signal whose frequency falls within the ideal operating frequency range of the test machine: If so, the first working clock signal with the fastest frequency is used as the target clock signal of the device under test. That is, when the test machine performs measurement on the chip under test, it connects the frequency divider stages corresponding to the first working clock signal with the fastest frequency to perform frequency division processing of the clock signal in order to obtain the target clock signal. If not, then based on the relationship between the frequencies of the multiple working clock signals and the ideal working frequency range, the frequency divider stage test group is adjusted and repeated verification is performed.
[0014] In some embodiments, determining the target clock signal that matches the performance of the test machine based on the plurality of ratios and the frequencies of the plurality of operating clock signals further includes: If, after at least one repeated verification, it is still impossible for all of the multiple ratios to be satisfied and / or for a target clock signal to be found that matches the ideal operating frequency range of the test machine, then at least one verification parameter shall be adjusted and repeated verification shall be performed. The verification parameters include: ratio error range, frequency division step size, predicted number of frequency divider stages, and the number of frequency divider stages set in the frequency divider stage test group.
[0015] Secondly, this embodiment provides a clock frequency self-adaptive testing device, the device comprising: The pre-test module is used by the test machine to perform preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies; wherein, the preprocessing includes: the test machine starts the test process for the device under test, generates a clock signal and connects it to the frequency divider for frequency division processing to obtain the working clock signal of the device under test; The judgment module is used to determine the target clock signal of the device under test based on the performance matching between the multiple working clock signals of different frequencies and the test machine; The testing module is used to perform measurements on the chip under test based on the target clock signal and obtain test results.
[0016] Thirdly, this embodiment provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the clock frequency self-adaptation test method described in the first aspect above.
[0017] Fourthly, in this embodiment, a chip is provided for the clock frequency self-adaptation test method described in the first aspect above. The chip includes a test device, an addressing circuit, a clock signal generator (RO), and multiple frequency dividers (FD). The clock signal generator is used to generate clock signals; The frequency divider is used to divide the clock signal to obtain the working clock signal of the test device; the multiple frequency dividers have different division levels. The addressing circuit is used to connect the clock signal to a frequency divider of the corresponding frequency division stage based on the received control signal. The aforementioned clock frequency self-adaptive testing method can automatically determine and switch the number of frequency divider stages according to the performance matching of the test machine, thus broadening the testable range of the device and providing a feasible testing solution for large-scale test structures in complex test scenarios.
[0018] Furthermore, a clock frequency self-adaptive test apparatus, a computer-readable storage medium, and a chip are disclosed, each possessing the performance and beneficial effects of the aforementioned clock frequency self-adaptive test method. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a schematic diagram of the existing structure of an on-chip clock oscillator. Figure 2 This is a flowchart of a clock frequency self-adaptation test method in one embodiment; Figure 3 This is a schematic diagram of the test machine performing multiple preprocessing steps on the device under test in one embodiment; Figure 4 A schematic diagram of frequency division processing and the number of frequency divider stages for clock signals; Detailed Implementation
[0021] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0023] It should also be understood that the terms "comprising / including" or "having," etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term "and / or" includes any and all combinations of the associated listed items.
[0024] To automatically adapt a frequency divider that matches the performance of the test equipment during device testing, this embodiment provides a method such as... Figure 2 The clock frequency self-adaptation test method shown includes: The test machine performs preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies. The preprocessing includes: the test machine starts the test process for the device under test, generates a clock signal, connects it to the frequency divider for frequency division processing, and obtains the working clock signal of the device under test. Based on the performance matching of the multiple working clock signals of different frequencies with the test machine, the target clock signal of the device under test is determined; Based on the target clock signal, the test machine performs measurements on the chip under test and obtains the test results.
[0025] The aforementioned clock frequency self-adaptive testing method can automatically determine and switch the number of frequency divider stages according to the performance matching of the test machine, thus broadening the testable range of the device and providing a feasible testing solution for large-scale test structures in complex test scenarios.
[0026] In this embodiment, the test machine performs multiple preprocessing steps on the device under test using frequency dividers of different levels to obtain multiple operating clock signals of different frequencies, including: Obtain the number of prediction divider stages of the device under test; Determine the frequency division step path; Based on the predicted frequency divider stage and frequency division step, multiple frequency divider stages are set as frequency divider stage test groups; The test machine performs multiple preprocessing operations on the device under test, each applying the aforementioned frequency divider stage, to obtain multiple operating clock signals of different frequencies.
[0027] Specifically, such as Figure 3 As shown, the steps are explained through specific application scenarios, including: Step S1: Obtain the number of prediction divider stages N of the device under test. m+1 ; Determine the frequency division step path R; Step S2: Based on the predicted frequency divider stage N m+1 Given the frequency division step size R, determine the number of frequency divider stages N1, ..., N1 in a (2m+1) group. m N m+1 N m+2 ..., N 2m+1 ; Where N1 = N m+1 – m*R,N m = N m+1 – R, N m+2 = N m+1 + R, N 2m+1 = N m+1 + m*R; m is a natural number; Step S3: The test machine performs preprocessing on the device under test using the (2m+1)-stage frequency converter to obtain clock frequencies F1, ..., F1, respectively. m F m+1 F m+2 F 2m+1 The operating clock signal, that is, the corresponding output (OUTPUT1, ..., OUTPUT...). m OUTPUT m+1 OUTPUT m+2 ... OUTPUT 2m+1 ).
[0028] It should be noted that when setting the number of frequency divider stages based on the predicted divider stage number and division step size, the range matching of the test equipment needs to be considered. For clock signal division processing and the set number of divider stages, please refer to... Figure 4 That is, each time the number of stages in the frequency divider increases (from FD=N stage to FD=N+1 stage), the clock signal is divided by two once.
[0029] In this embodiment, the number of frequency divider stages in the frequency divider stage test group is an odd number (i.e., (2m+1) groups of frequency divider stages are determined), that is, the same number of experimental groups are set in two directions with the predicted frequency divider stage as the reference group. However, in other embodiments, the number of frequency divider stages in the test group can also be even, that is, different numbers of experimental groups are set in two directions with the predicted frequency divider stage as the reference group. This application does not make specific limitations.
[0030] In this embodiment, obtaining the number of prediction divider stages of the device under test includes: The device under test is simulated to determine the number of predictive divider stages that match the performance of the test machine.
[0031] In this embodiment, determining the target clock signal of the device under test based on the performance matching of the plurality of operating clock signals of different frequencies with the test machine includes: In the frequency divider stage test group, the operating clock signal frequency obtained by applying each of the other frequency divider stages is compared with the operating clock signal frequency obtained by applying the predicted frequency divider stage to obtain multiple ratios; Based on the multiple ratios and the frequencies of the multiple working clock signals, a target clock signal is determined to match the performance of the test machine.
[0032] Specifically, regarding such as Figure 3 The obtained clock signal frequencies of multiple different frequencies in the frequency divider stage test group are compared with the clock signal frequencies obtained by applying other frequency divider stages and the clock signal frequencies obtained by applying the predicted frequency divider stage, resulting in multiple ratios: Ratio (1): F1 / F m+1 Its corresponding preset value is (m*R). 2 ; … Ratio (m): F m / F m+1 Its corresponding preset value is R 2 ; Ratio (m+1): F m+2 / F m+1 Its corresponding preset value is 1 / R 2 ; … Ratio (2m): F 2m+1 / F m+1 Its corresponding preset value is 1 / (m*R). 2 .
[0033] In this embodiment, determining the target clock signal that matches the performance of the test machine based on the plurality of ratios and the frequencies of the plurality of working clock signals includes: Determine whether each of the multiple ratios is within a preset ratio error range and satisfies a corresponding preset value: If all of the above ratios are satisfied, then find the target clock signal that matches the ideal operating frequency range of the test machine based on the frequency of the operating clock signal. If at least one of the multiple ratios is not satisfied, the frequency divider stage test group is adjusted according to the distribution of the unsatisfied ratios and the frequency division step size, and then repeated verification is performed. The repeated verification includes: the test machine performing preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies; and determining the target clock signal of the device under test based on the performance matching of the multiple working clock signals of different frequencies with the test machine.
[0034] In this embodiment, finding the target clock signal that matches the ideal operating frequency range of the test machine based on the frequency of the operating clock signal includes: Determine whether, among the plurality of operating clock signals, there is a first operating clock signal whose frequency falls within the ideal operating frequency range of the test machine: If so, the first working clock signal with the fastest frequency is used as the target clock signal of the device under test. That is, when the test machine performs measurement on the chip under test, it connects the frequency divider stages corresponding to the first working clock signal with the fastest frequency to perform frequency division processing of the clock signal in order to obtain the target clock signal. If not, then based on the relationship between the frequencies of the multiple working clock signals and the ideal working frequency range, the frequency divider stage test group is adjusted and repeated verification is performed.
[0035] Specifically, first determine whether the operating clock signal frequency obtained by applying the smallest frequency divider stage in the frequency divider stage test group is within the ideal operating frequency range of the test machine: If the frequency of the working clock signal obtained by applying the minimum frequency divider stage is within the ideal working frequency range, then the working clock signal is used as the target clock signal of the device under test. That is, when the test machine performs measurement on the chip under test, it connects the minimum frequency divider stage to perform frequency division processing on the clock signal to obtain the target clock signal. If the operating clock signal frequency obtained by applying the minimum divider stage is lower than the ideal operating frequency range, then the minimum divider stage is updated to the predicted divider stage and the verification is repeated. If the operating clock signal frequency obtained by applying the minimum divider stage is higher than the ideal operating frequency range, then in ascending order of divider stage number, it is determined whether the operating clock signal frequency obtained by applying the corresponding divider stage is within the ideal operating frequency range of the test machine. The first operating clock signal whose frequency is within the ideal operating frequency range is taken as the target clock signal of the device under test. If, in the divider stage test group, the operating clock signal frequency obtained by applying the maximum divider stage is still higher than the ideal operating frequency range, then the maximum divider stage is updated to the predicted divider stage and the verification is repeated.
[0036] It should be noted that in this embodiment, the frequency of the working clock signal obtained by applying the minimum frequency divider stage in the frequency divider stage test group is first determined to be within the ideal working frequency range of the test machine, and then the target clock signal is further analyzed and found. However, based on different application scenario requirements, other methods can also be used to find the target clock signal, and this application does not make specific limitations.
[0037] In this embodiment, determining the target clock signal that matches the performance of the test machine based on the plurality of ratios and the frequencies of the plurality of working clock signals further includes: If, after at least one repeated verification, it is still impossible for all of the multiple ratios to be satisfied and / or for a target clock signal to be found that matches the ideal operating frequency range of the test machine, then at least one verification parameter shall be adjusted and repeated verification shall be performed. The verification parameters include: ratio error range, frequency division step size, predicted number of frequency divider stages, and the number of frequency divider stages set in the frequency divider stage test group.
[0038] The following specific application example illustrates how to determine the target clock signal of the device under test based on the performance matching of multiple working clock signals of different frequencies with the test machine.
[0039] For example Figure 3 Multiple working clock signals of different frequencies were obtained. Taking m=2 as an example, the five frequency divider stages in the frequency divider stage test group were: N1= N–4, N2= N–2, N3= N, N4= N+2, N5= N+4, corresponding to working clock signals with clock frequencies of F1, F2, F3, F4, and F5, respectively. The preset ratio error range is (-2%, +2%), the frequency division step is 2, and the ratios and their corresponding preset values are as follows: Ratio (1): F1 / F3, with a corresponding preset value of 16; Ratio (2): F2 / F3, with a corresponding preset value of 4; Ratio (3): F4 / F3, with a corresponding preset value of 1 / 4; Ratio (4): F5 / F3, with a corresponding preset value of 1 / 16.
[0040] Based on various considerations for specific application scenarios, the ideal operating frequency range for the test machine is a safe 1MHz to 10MHz.
[0041] The system determines whether multiple ratios are within the preset ratio error range and meet the corresponding preset values, resulting in 9 possible outcome scenarios. For details, please refer to the judgment logic table in Table 1.
[0042] Table 1 Decision Logic Table It should be noted that in the case of repeated verification in Result Scenario 9, since no ratio is satisfied, a direct retest can be performed. If the result still does not conform to Result Scenario 1-Result Scenario 8, a warning will be issued to prompt manual intervention. Alternatively, at least one verification parameter can be adjusted (for example, changing the frequency division step path R from level 2 to level 1) before repeated verification.
[0043] In practical applications, there may be instances where the automatically adjusted divider stage is not present in the chip's circuitry, in which case a warning may be issued to prompt manual intervention.
[0044] Based on the same inventive concept, this application also provides an apparatus for implementing the aforementioned clock frequency self-adaptation test method. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more clock frequency self-adaptation test apparatus embodiments provided below can be found in the limitations of the clock frequency self-adaptation test method described above, and will not be repeated here.
[0045] In one embodiment, a clock frequency self-adaptive testing apparatus is provided, comprising: a pre-test module, a judgment module, and a test module, wherein: The pre-test module is used by the test machine to perform preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies; wherein, the preprocessing includes: the test machine starts the test process for the device under test, generates a clock signal, connects it to the frequency divider for frequency division processing, and then obtains the working clock signal of the device under test; The judgment module is used to determine the target clock signal of the device under test based on the performance matching between the multiple working clock signals of different frequencies and the test machine; The testing module is used to perform measurements on the chip under test based on the target clock signal and obtain test results.
[0046] The functional modules of this clock frequency self-adaptive test device implement the steps in the above-described clock frequency self-adaptive test method embodiments.
[0047] Each module in the aforementioned clock frequency self-adaptation test device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0048] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above embodiments of the clock frequency self-adaptation test method.
[0049] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0050] In one embodiment, a chip is provided that utilizes the steps in the above-described clock frequency self-adaptation test method embodiments, the chip comprising a test device, an addressing circuit, a clock signal generator (RO), and multiple frequency dividers (FD). The clock signal generator is used to generate clock signals; The frequency divider is used to divide the clock signal to obtain the working clock signal of the test device; the multiple frequency dividers have different division levels. The addressing circuit is used to connect the clock signal to a frequency divider of the corresponding frequency division level based on the received control signal.
[0051] In this embodiment, the chip also includes an inverter (BUF) that connects the clock signal generator and the frequency divider to eliminate interference and stabilize the signal.
[0052] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0053] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0055] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A clock frequency self-adaptation test method, characterized in that, include: The test machine performs preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies. The preprocessing includes: the test machine starts the test process for the device under test, generates a clock signal and connects it to the frequency divider for frequency division processing, and obtains the working clock signal of the device under test; Based on the performance matching of the multiple working clock signals of different frequencies with the test machine, the target clock signal of the device under test is determined; Based on the target clock signal, the test machine performs measurements on the chip under test and obtains the test results.
2. The clock frequency self-adaptation test method according to claim 1, characterized in that, The test machine performs multiple preprocessing steps on the device under test using frequency dividers of different levels to obtain multiple operating clock signals of different frequencies, including: Obtain the number of prediction divider stages of the device under test; Determine the frequency division step path; Based on the predicted frequency divider stage and frequency division step, multiple frequency divider stages are set as frequency divider stage test groups; The test machine performs multiple preprocessing operations on the device under test, each applying the aforementioned frequency divider stage, to obtain multiple operating clock signals of different frequencies.
3. The clock frequency self-adaptation test method according to claim 2, characterized in that, The step of obtaining the predictive divider stage of the device under test includes: The device under test is simulated to determine the number of predictive divider stages that match the performance of the test machine.
4. The clock frequency self-adaptation test method according to claim 2, characterized in that, The determination of the target clock signal for the device under test based on the performance matching of the multiple operating clock signals of different frequencies with the test machine includes: In the frequency divider stage test group, the operating clock signal frequency obtained by applying each of the other frequency divider stages is compared with the operating clock signal frequency obtained by applying the predicted frequency divider stage to obtain multiple ratios; Based on the multiple ratios and the frequencies of the multiple working clock signals, a target clock signal is determined to match the performance of the test machine.
5. The clock frequency self-adaptation test method according to claim 4, characterized in that, The determination of the target clock signal matching the performance of the test machine based on the multiple ratios and the frequencies of the multiple working clock signals includes: Determine whether each of the multiple ratios is within a preset ratio error range and satisfies a corresponding preset value: If all of the above ratios are satisfied, then find the target clock signal that matches the ideal operating frequency range of the test machine based on the frequency of the operating clock signal. If at least one of the multiple ratios is not satisfied, the frequency divider stage test group is adjusted according to the distribution of the unsatisfied ratios and the frequency division step size, and then repeated verification is performed. The repeated verification includes: the test machine performing preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies; and determining the target clock signal of the device under test based on the performance matching of the multiple working clock signals of different frequencies with the test machine.
6. The clock frequency self-adaptation test method according to claim 5, characterized in that, Finding the target clock signal that matches the ideal operating frequency range of the test machine based on the frequency of the operating clock signal includes: Determine whether, among the plurality of operating clock signals, there is a first operating clock signal whose frequency falls within the ideal operating frequency range of the test machine: If so, the first working clock signal with the fastest frequency is used as the target clock signal of the device under test. That is, when the test machine performs measurement on the chip under test, it connects the frequency divider stages corresponding to the first working clock signal with the fastest frequency to perform frequency division processing of the clock signal in order to obtain the target clock signal. If not, then based on the relationship between the frequencies of the multiple working clock signals and the ideal working frequency range, the frequency divider stage test group is adjusted and repeated verification is performed.
7. The clock frequency self-adaptation test method according to claim 5, characterized in that, The step of determining the target clock signal that matches the performance of the test machine based on the multiple ratios and the frequencies of the multiple working clock signals further includes: If, after at least one repeated verification, it is still impossible for all of the multiple ratios to be satisfied and / or for a target clock signal to be found that matches the ideal operating frequency range of the test machine, then at least one verification parameter shall be adjusted and repeated verification shall be performed. The verification parameters include: ratio error range, frequency division step size, predicted number of frequency divider stages, and the number of frequency divider stages set in the frequency divider stage test group.
8. A clock frequency self-adaptive testing device, characterized in that, The device includes: The pre-test module is used by the test machine to perform preprocessing on the device under test multiple times using frequency dividers of different levels to obtain multiple working clock signals of different frequencies; wherein, the preprocessing includes: the test machine starts the test process for the device under test, generates a clock signal and connects it to the frequency divider for frequency division processing to obtain the working clock signal of the device under test; The judgment module is used to determine the target clock signal of the device under test based on the performance matching between the multiple working clock signals of different frequencies and the test machine; The testing module is used to perform measurements on the chip under test based on the target clock signal and obtain test results.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the clock frequency self-adaptation test method according to any one of claims 1 to 7.
10. A chip, characterized in that, The test method for clock frequency self-adaptation according to any one of claims 1 to 7, wherein the chip includes a test device, an addressing circuit, a clock signal generator, and multiple frequency dividers; The clock signal generator is used to generate clock signals; The frequency divider is used to divide the clock signal to obtain the working clock signal of the test device; the multiple frequency dividers have different division levels. The addressing circuit is used to connect the clock signal to a frequency divider of the corresponding frequency division level based on the received control signal.