Optical proximity correction method based on fragmentation density configuration error feedback coefficient

Abstract

The invention provides an optical proximity correction method based on a fragment density configuration error feedback coefficient. The optical proximity correction method comprises the following steps: S1, dividing a to-be-corrected chip layout into a plurality of independent fragment units; s2, calculating the pattern density of each fragmentation unit, and grading the fragmentation units according to the pattern density to obtain at least two density grades; s3, corresponding error feedback coefficients are configured for the fragment units of different density grades, and the absolute value of the error feedback coefficient of the fragment unit with the higher pattern density is smaller; s4, performing iterative correction on each fragment unit, and during iterative correction, calculating the pattern adjustment amount of each fragment unit based on the error value of each fragment unit and the corresponding error feedback coefficient, the adjustment amount = the error value * the error feedback coefficient; and S5, performing iterative correction on each fragment unit according to the adjustment amount to complete correction of the chip layout. The technical effects of fine correction of a high-density region and rapid convergence of a low-density region are achieved, and then the OPC overall correction precision and efficiency are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to an optical proximity correction method based on a patch density configuration error feedback coefficient. Background Technology

[0002] When performing optical proximity correction (OPC) on a complete chip layout, the large layout size and complex circuit pattern result in a huge amount of simulation and computation during the correction process, directly affecting the correction efficiency. To solve this problem, existing technologies generally adopt a "slicing" strategy: the complete chip layout is divided into multiple independent small regions (tiles), and each tile performs simulation calculations and correction operations independently, which significantly reduces the amount of data in a single calculation, thereby shortening the overall correction runtime.

[0003] In the OPC iterative calibration process, the error feedback coefficient is one of the core parameters. Its working principle is as follows: Figure 2 As shown, the dimensional deviation (EPE) between the actual pattern and the target pattern is obtained based on the current simulation results. By multiplying the EPE by the feedback coefficient, the movement distance and direction of the pattern fragment in the next iteration can be obtained. Through multiple iterations, the deviation is gradually reduced, so that the simulation results approximate the preset target pattern.

[0004] However, traditional OPC technology uses a globally uniform feedback parameter configuration mode, which does not consider the pattern density differences between different tiles. For example... Figure 3 As shown, the circuit patterns of high-density tiles are densely distributed, and the influence range of the correction operation is correlated. If the feedback coefficient is too large, the correction amplitude of a single pattern will exceed the reasonable range, which will easily interfere with the accuracy of surrounding patterns and lead to repeated correction problems. On the other hand, the circuit patterns of low-density tiles are sparsely distributed, and the correlation of the correction operation is smaller. If the same small feedback coefficient as high-density tiles is used, the correction convergence speed will be slow, which will ultimately affect the OPC correction efficiency and overall accuracy of the entire chip layout, making it difficult to meet the requirements of high-precision chip manufacturing. Summary of the Invention

[0005] To address all or part of the problems in the prior art, this invention provides an optical proximity correction method based on the error feedback coefficient configured by the chip layout slicing unit. By classifying the chip layout slicing unit according to the pattern density and configuring differentiated error feedback coefficients, it achieves fine correction in high-density areas and rapid convergence in low-density areas, thereby improving the overall correction accuracy and efficiency of OPC.

[0006] To achieve the above objectives, the present invention provides the following technical solution: The optical proximity correction method based on the patch density configuration error feedback coefficient includes the following steps: S1. Divide the chip layout to be corrected into multiple independent slice units; S2. Calculate the pattern density of each segmented unit, and classify the segmented units according to the pattern density to obtain at least two density levels; S3. Configure corresponding error feedback coefficients for the segmentation units of different density levels respectively, and the absolute value of the error feedback coefficient of the segmentation unit with higher pattern density is smaller; S4. Perform iterative correction on each of the segmented units. During iterative correction, calculate the pattern adjustment amount for each segmented unit based on the error value of each segmented unit and the corresponding error feedback coefficient. The adjustment amount = error value × error feedback coefficient. S5. Perform iterative correction on each of the slice units according to the adjustment amount to complete the correction of the chip layout.

[0007] The density levels are divided into four grades, with the following specific grading standards: Grade 1, pattern density > 30%; Grade 2, 20% < pattern density ≤ 30%; Grade 3, 10% < pattern density ≤ 20%; Grade 4, pattern density ≤ 10%.

[0008] Let the initial value K be the error feedback coefficient of the segmentation unit at level 1, where K is a non-zero negative number; in subsequent density levels, the error feedback coefficient of the segmentation unit at the next level = the error feedback coefficient of the segmentation unit at the previous level × the scaling factor, where the scaling factor takes a value of 1.1 to 1.4.

[0009] The scaling factor is set to 1.1, the error feedback coefficient of the level 2 segmentation unit is 1.1 × K, the error feedback coefficient of the level 3 segmentation unit is 1.1 × level 2 error feedback coefficient, and the error feedback coefficient of the level 4 segmentation unit is 1.1 × level 3 error feedback coefficient.

[0010] The initial value K ranges from -0.1 to -0.9.

[0011] The pattern density in step S2 is the ratio of the chip pattern area within the slicing unit to the total area of ​​the slicing unit.

[0012] The error value in step S4 is the size deviation between the actual pattern and the target pattern of the chip circuit in the segmentation unit.

[0013] The error value is negative when the actual pattern size is smaller than the target pattern size; the error value is positive when the actual pattern size is larger than the target pattern size.

[0014] When the error value is positive, the adjustment amount is negative; when the error value is negative, the adjustment amount is positive.

[0015] The termination condition for the iterative correction in step S5 is that the number of iterations reaches a preset value. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the optical proximity correction method based on the error feedback coefficient of the slice density configuration according to an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the OPC iterative correction process described in the background art.

[0019] Figure 3 This is a schematic diagram comparing the OPC iterative correction process of high-density and low-density slicing units using the same error feedback coefficient in the background technology.

[0020] Figure 4 This is a schematic diagram comparing the OPC iterative correction process of the first-level and fourth-level slicing units using differentiated error feedback coefficients in the optical proximity correction method based on slicing density configuration error feedback coefficients according to an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions in specific embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention relates to the field of optical proximity correction (OPC) technology, specifically disclosing an optical proximity correction method based on the error feedback coefficient configured by the slice density. The aim is to solve the technical problem that when the existing OPC correction process uses a globally uniform error feedback coefficient, it cannot adapt to the correction requirements of slice units with different pattern densities. This results in high-density areas being prone to over-correction and interference with surrounding patterns, and low-density areas having slow convergence speed, thereby affecting the overall correction accuracy and efficiency of the chip layout.

[0023] In this embodiment of the invention, in conjunction with reference to the reference Figures 1 to 4 As shown, an optical proximity correction method based on patch density configuration error feedback coefficients is provided, including the following steps: S1. Divide the chip layout to be corrected into multiple independent slice units; S2. Calculate the pattern density of each segmented unit, and classify the segmented units according to the pattern density to obtain at least two density levels; S3. Configure corresponding error feedback coefficients for segmentation units of different density levels. The absolute value of the error feedback coefficient of segmentation units with higher pattern density is smaller. S4. Perform iterative correction on each segment unit. During iterative correction, calculate the pattern adjustment amount for each segment unit based on the error value and the corresponding error feedback coefficient. Adjustment amount = error value × error feedback coefficient. S5. Perform iterative correction on each slice unit according to the adjustment amount to complete the correction of the chip layout.

[0024] The following provides a detailed explanation of each of the above steps and related technical details.

[0025] First, step S1 is executed: the chip layout to be corrected is divided into multiple independent tile units. Due to the high graphic complexity and massive data volume of the complete chip layout, directly performing overall OPC correction would generate an enormous computational load, resulting in excessively long correction times and low efficiency. Therefore, this embodiment uses a tiled processing method, dividing the entire chip layout into multiple independent tile units according to preset rules. Each tile unit can perform subsequent simulation calculations and correction operations independently, which reduces the computational load of a single correction round while ensuring the independence and efficiency of the correction process in each region. The tile unit size can be flexibly adjusted according to the actual application scenario. For example, considering the overall scale of the chip layout, the complexity of the graphic distribution, and the process parameter requirements of the lithography machine, smaller tile units can be used for densely patterned and structurally complex areas to improve local correction accuracy, while larger tile units can be used for sparsely patterned and structurally simple areas to improve correction efficiency, ensuring a balance between correction accuracy and processing efficiency.

[0026] Then, step S2 is executed: the pattern density of each slice unit is calculated, and the slice units are graded according to the pattern density to obtain at least two density levels. Pattern density is a core indicator reflecting the density of pattern distribution within a slice unit. In this embodiment, the pattern density is calculated as the ratio of the actual area of ​​the chip pattern within the slice unit to the total area of ​​the slice unit, providing an accurate basis for the subsequent differential configuration error feedback coefficient. In this embodiment, the density levels are preferably divided into 4 levels, with the specific grading standards as follows: Level 1 slice units correspond to areas with a pattern density > 30%, which are the densest pattern areas; Level 2 slice units correspond to areas with a pattern density ≤ 30%; Level 3 slice units correspond to areas with a pattern density ≤ 20%; and Level 4 slice units correspond to areas with a pattern density ≤ 10%, which are the sparsest pattern areas. It should be noted that the above-mentioned number of grades and grading standards are only preferred embodiments. In other specific embodiments, the density level can be divided into more levels (such as level 2, level 3, level 5, etc.) according to the actual situation such as the design requirements of the chip layout and the process accuracy requirements. The grading standards can also be adjusted accordingly (such as adjusting the pattern density threshold corresponding to each level). All of these are within the protection scope of this invention.

[0027] Next, step S3 is executed: Corresponding error feedback coefficients are configured for each segmentation unit at different density levels, with higher-density segmentation units having smaller absolute values ​​for their error feedback coefficients. The core logic of this configuration rule is that in high-density areas, the pattern distribution is dense, and the correction of a single pattern has a significant impact on surrounding adjacent patterns. Using a larger absolute value error feedback coefficient can easily lead to over-correction, which in turn triggers a chain reaction of interference to surrounding patterns. Therefore, a smaller absolute value error feedback coefficient is needed for fine-tuning. Conversely, in low-density areas, the pattern spacing is larger, and the correction of a single pattern has a smaller impact on surrounding patterns. Using a larger absolute value error feedback coefficient can accelerate the iteration convergence speed and reduce the number of invalid iterations. The specific configuration method is as follows: Let the error feedback coefficient of the level 1 segmentation unit (with the densest pattern) be the initial value K, where K is a non-zero negative number, and the initial value K ranges from -0.1 to -0.9. For subsequent segmentation units at various density levels, the error feedback coefficient of the next level segmentation unit is the error feedback coefficient of the previous level segmentation unit multiplied by a scaling factor, and the scaling factor ranges from 1.1 to 1.4. Extensive experimental verification has shown that a scaling factor value within the range of 1.1-1.2 optimally balances the correction accuracy in high-density regions and the convergence efficiency in low-density regions. Therefore, in this embodiment, a scaling factor value of 1.1 is preferred, meaning the error feedback coefficient of the level 2 segmentation unit is 1.1 × K, and the error feedback coefficient of the level 3 segmentation unit is 1.1 × the error feedback coefficient of the level 2 segmentation unit (i.e., 1.1). 2 ×K), the error feedback coefficient of the 4th level fragmentation unit = 1.1 × the error feedback coefficient of the 3rd level fragmentation unit (i.e., 1.1).3 ×K), through this proportionally increasing method, the error feedback coefficient and the pattern density are precisely matched.

[0028] Next, step S4 is executed: iterative correction is performed on each slice unit. During the iterative correction process, based on the error value and corresponding error feedback coefficient of each slice unit, the pattern adjustment amount of each slice unit is calculated, where the adjustment amount = error value × error feedback coefficient. The error value is the dimensional deviation between the actual pattern and the target pattern of the chip circuit within the slice unit. This error value can be obtained by simulating the chip exposure and imaging process using a photolithography simulation model. Specifically, based on the graphic parameters of the slice unit (such as graphic size, line spacing, graphic layout, etc.) and the photolithography machine process parameters (such as exposure dose, focal length, photoresist characteristics, etc.), the edge placement error (EPE) between the actual imaging contour and the designed target contour is calculated. This error value directly reflects the degree of deviation between the current pattern and the target pattern. The positive and negative definitions of the error value follow these rules: when the actual pattern size is smaller than the target pattern size, the error value is negative; when the actual pattern size is larger than the target pattern size, the error value is positive. Since the error feedback coefficient K is a non-zero negative number, combined with the calculation formula of the adjustment amount, it can be seen that the sign of the adjustment amount is always opposite to the sign of the error value. That is, when the error value is positive (the actual pattern is too large), the adjustment amount is negative, and the pattern is adjusted to shrink accordingly; when the error value is negative (the actual pattern is too small), the adjustment amount is positive, and the pattern is adjusted to enlarge accordingly, so that the actual pattern gradually approaches the target pattern in each iteration.

[0029] Finally, step S5 is executed: Based on the adjustment amount calculated above, iterative correction is performed on each slice unit. The error value calculation, adjustment amount calculation, and pattern adjustment process of step S4 are repeated until the preset iterative correction termination condition is met, thus completing the optical proximity correction of the entire chip layout. The termination condition for iterative correction is that the number of iterations reaches a preset value. For example, it can be set that the absolute value of the error value of each slice unit is less than a preset accuracy threshold (such as ±0.5nm, ±1nm, etc.), or the number of iterations reaches a preset maximum number of iterations (such as 10 rounds, 15 rounds, etc.), or the change in adjustment amount of each slice unit in two adjacent iterations is less than a preset threshold, ensuring that the correction result meets the process accuracy requirements of chip manufacturing. During the iteration process, each slice unit performs simulation calculations and pattern adjustments independently without interference. This ensures the correction accuracy of individual slice units and, through differentiated error feedback coefficient configuration, enables fine correction in high-density areas and rapid convergence in low-density areas.

[0030] like Figure 4As shown in the figure, taking a level 1 sharding unit (tile1) and a level 4 sharding unit (tile2) as examples, this paper illustrates the OPC iterative correction process and effect after configuring the differential error feedback coefficient based on the sharding density in this invention.

[0031] For the level 1 segmentation unit corresponding to tile1, since it belongs to a region with high pattern density, the configured error feedback coefficient is -0.3 (small absolute value). After the first round of iterations, the edge placement error (epe) of this segmentation unit is -3nm. According to the calculation rule of "adjustment amount (fragment movement amount) = error value × error feedback coefficient", the movement amount is -3 × (-0.3) = 0.9nm, that is, the pattern fragment moves outward by 0.9nm. After this round of adjustment, the epe of the second round of iterations is reduced to -1.5nm, which reflects the characteristics of "fine correction" - the small feedback coefficient avoids the single movement amount being too large, and prevents interference with the densely distributed adjacent patterns.

[0032] For the 4th-level segmentation unit corresponding to tile2, since it belongs to a region with low pattern density, the configured error feedback coefficient is -0.4 (the absolute value is greater than the feedback coefficient of level 1). After the first iteration, the epe of this segmentation unit is -3.1nm, and the calculated movement is -3.1×(-0.4)=1.24nm, with the pattern fragment moving outward by 1.24nm. After this round of adjustment, the epe of the second iteration quickly shrinks to -0.8nm, achieving the effect of "accelerated convergence"—the larger feedback coefficient increases the adjustment range of a single iteration, rapidly reducing the error in sparse regions (without too much interference from adjacent patterns).

[0033] As can be seen, by configuring differentiated error feedback coefficients for the level 1 and level 4 slicing units, this invention not only ensures the correction accuracy of high-density areas (avoiding interference from surrounding patterns) but also improves the iteration efficiency of low-density areas (reducing invalid iterations), ultimately achieving synergistic optimization of the overall correction accuracy and convergence efficiency of the chip layout OPC.

[0034] This invention, through the aforementioned technical solution, achieves dynamic and differentiated configuration of error feedback coefficients during OPC correction. Its beneficial effects are specifically reflected in the following aspects: Firstly, it configures appropriate error feedback coefficients for slab units with different pattern densities. High-density areas use error feedback coefficients with smaller absolute values, effectively avoiding interference from excessive correction of a single pattern on surrounding patterns, reducing repeated corrections, and ensuring local correction accuracy. Secondly, low-density areas use error feedback coefficients with larger absolute values, significantly accelerating iterative convergence and reducing the overall correction time cost. Simultaneously, the independent processing mode of each slab unit, combined with differentiated coefficient configuration, achieves synergistic optimization of correction accuracy and efficiency, ultimately significantly improving the overall OPC correction accuracy of the chip layout and better meeting the stringent requirements of advanced lithography processes for chip layout correction.

[0035] It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this invention.

Claims

1. An optical proximity correction method based on patch density configuration error feedback coefficients, characterized in that, Includes the following steps: S1. Divide the chip layout to be corrected into multiple independent slice units; S2. Calculate the pattern density of each segmented unit, and classify the segmented units according to the pattern density to obtain at least two density levels; S3. Configure corresponding error feedback coefficients for the segmentation units of different density levels respectively, and the absolute value of the error feedback coefficient of the segmentation unit with higher pattern density is smaller; S4. Perform iterative correction on each of the segmented units. During iterative correction, calculate the pattern adjustment amount for each segmented unit based on the error value of each segmented unit and the corresponding error feedback coefficient. The adjustment amount = error value × error feedback coefficient. S5. Perform iterative correction on each of the slice units according to the adjustment amount to complete the correction of the chip layout.

2. The method according to claim 1, characterized in that, The density levels are divided into four grades, with the following specific grading standards: Grade 1, pattern density > 30%; Grade 2, 20% < pattern density ≤ 30%; Grade 3, 10% < pattern density ≤ 20%; Grade 4, pattern density ≤ 10%.

3. The method according to claim 2, characterized in that, Let the initial value K be the error feedback coefficient of the segmentation unit at level 1, where K is a non-zero negative number; in subsequent density levels, the error feedback coefficient of the segmentation unit at the next level = the error feedback coefficient of the segmentation unit at the previous level × the scaling factor, where the scaling factor takes a value of 1.1 to 1.

4.

4. The method according to claim 3, characterized in that, The scaling factor is set to 1.1, the error feedback coefficient of the level 2 segmentation unit is 1.1 × K, the error feedback coefficient of the level 3 segmentation unit is 1.1 × level 2 error feedback coefficient, and the error feedback coefficient of the level 4 segmentation unit is 1.1 × level 3 error feedback coefficient.

5. The method according to claim 3, characterized in that, The initial value K ranges from -0.1 to -0.

9.

6. The method according to claim 1, characterized in that, The pattern density in step S2 is the ratio of the chip pattern area within the slicing unit to the total area of ​​the slicing unit.

7. The method according to claim 1, characterized in that, The error value in step S4 is the size deviation between the actual pattern and the target pattern of the chip circuit in the segmentation unit.

8. The method according to claim 7, characterized in that, The error value is negative when the actual pattern size is smaller than the target pattern size; the error value is positive when the actual pattern size is larger than the target pattern size.

9. The method according to claim 8, characterized in that, When the error value is positive, the adjustment amount is negative; when the error value is negative, the adjustment amount is positive.

10. The method according to claim 1, characterized in that, The termination condition for the iterative correction in step S5 is that the number of iterations reaches a preset value.

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