Hardware accelerator and hardware security module

Abstract

The application belongs to the chip technical field. The embodiment of the application provides a hardware accelerator and a hardware security module. A distribution unit is arranged in the hardware accelerator, so that the intermediate data stream is distributed to the subsequent encryption unit by the distribution unit in the case that the intermediate data stream is generated in the encryption unit. The number of interactions between the hardware accelerator and the running memory through the bus when performing the ciphertext task is effectively reduced, the security of the ciphertext task processing is improved, the occupancy rate of the bus bandwidth in the process of performing the ciphertext task is effectively reduced, and the performance of the chip to which the hardware accelerator belongs is maintained.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to hardware accelerators and hardware security modules. Background Technology

[0002] A hardware security module (HSM) can be integrated into the chip. The hardware security module can be used to manage and protect digital keys, perform encryption and decryption operations, and provide other core security functions for physical computing devices.

[0003] The hardware security module can read data from the chip's RAM and perform security operations such as encryption and decryption. To improve data security, the hardware security module can integrate multiple encryption units such as AES, RSA, and hash. However, during the process of multiple computing cores performing security operations on data, one encryption unit needs to write the encryption result back to RAM after performing an encryption operation on the data read from RAM. A second encryption unit then needs to read the encryption result from RAM, perform another encryption operation, obtain the result, and write it back to RAM. Therefore, both encryption units need to access RAM during encryption operations, leading to excessive consumption of bus bandwidth used for data transmission. This is especially problematic in scenarios where encryption operations require more than two encryption units, as excessive bus bandwidth consumption can easily affect the chip's operational stability. Summary of the Invention

[0004] This application provides a hardware accelerator and a hardware security module to solve the problem that repeated access to running memory by multiple encryption units in the hardware security module leads to excessive bandwidth consumption, which in turn affects the stability of chip operation.

[0005] In a first aspect, embodiments of this application provide a hardware accelerator applied to a hardware security module, the hardware security module being integrated into a chip; the hardware accelerator includes:

[0006] The first encryption unit is configured to: when reading the data stream to be processed from the chip's running memory, perform a first ciphertext operation on the data stream to be processed; and write the first ciphertext data stream generated by the first ciphertext operation to the shared register group;

[0007] The distribution unit is configured to: upon detecting that a first ciphertext data stream has been written to the shared register set, read the first ciphertext data stream from the shared register set; and send the first ciphertext data stream to the second arithmetic unit.

[0008] The read / write unit is configured to write the first ciphertext data stream to the running memory upon detecting that a first ciphertext data stream has been written to the shared register group;

[0009] The second encryption unit is configured to: when reading the first ciphertext data stream from the distribution unit, perform a second ciphertext operation on the first ciphertext data stream; and write the second ciphertext data stream generated by the second ciphertext operation to the shared register group;

[0010] The read / write unit is also configured to write the second ciphertext data stream to the running memory upon detecting that a second ciphertext data stream has been written to the shared register set.

[0011] In some feasible embodiments, the hardware accelerator is electrically connected to the processor of the hardware security module, and the hardware accelerator further includes:

[0012] The mode configuration register is configured to store the operating mode configuration value, which is the value that the processor writes to the physical address corresponding to the mode configuration unit.

[0013] The control unit is configured to: read a working mode configuration value from a mode configuration unit; determine a control signal sequence based on the working mode configuration value; electrically connect the control unit to a first encryption unit, a second encryption unit, and a distribution unit; the control signal sequence is used at least to indicate the electrical connection relationship between the first encryption unit, the second encryption unit, and the distribution unit; the electrical connection relationship is used to determine the data flow direction of the data generated by the first encryption unit, the second encryption unit, and the distribution unit.

[0014] In some feasible implementations, the hardware accelerator also includes a data buffer; the control signal sequence includes read / write control signals and distribution control signals; and the distribution unit includes a multiplexing subunit.

[0015] After the control unit executes the control signal sequence determined according to the working mode configuration value, it is also configured to: send read / write control signals to the read / write unit; and send distribution control signals to the distribution unit.

[0016] The read / write unit is configured to read the data stream to be processed from the running memory into the data buffer according to the address indicated by the read / write control signal when the read / write control signal is read from the control unit.

[0017] The multiplexing subunit is configured to send the data stream to be processed to the first encryption unit based on the electrical connection relationship indicated by the distribution control signal when the distribution control signal is read from the control unit.

[0018] In some feasible embodiments, the control signal sequence further includes a first operational control signal and a second operational control signal; the distribution unit further includes a routing subunit;

[0019] After the control unit executes the control signal sequence determined according to the working mode configuration value, it is also configured to: send a first operation control signal to the first encryption unit and send a second operation control signal to the second encryption unit;

[0020] When the first encryption unit reads the data stream to be processed from the chip's running memory, it performs a first ciphertext operation on the data stream to be processed. Specifically, it is configured to perform a first ciphertext operation on the data stream to be processed according to the operation type indicated by the first operation control signal.

[0021] The routing subunit executes the sending of the first ciphertext data stream to the second encryption unit, specifically configured to: upon detecting that the first ciphertext data stream is written to the shared register group, read the first ciphertext data stream from the shared register group; and send the first ciphertext data stream to the second encryption unit based on the electrical connection relationship indicated by the distribution control signal.

[0022] When the second encryption unit reads the first ciphertext data stream from the distribution unit, it performs a second ciphertext operation on the first ciphertext data stream. Specifically, it is configured to perform a second ciphertext operation on the first ciphertext data stream according to the operation type indicated by the second operation control signal when reading the first ciphertext data stream from the routing subunit.

[0023] In some feasible embodiments, the distribution unit further includes a data caching subunit;

[0024] When the routing subunit sends the first ciphertext data stream to the second encryption unit based on the electrical connection relationship indicated by the distribution control signal, it is specifically configured to write the first ciphertext data stream to the data buffer subunit.

[0025] The data caching subunit is configured to send the first ciphertext data stream to the second encryption unit when it reads the first ciphertext data stream from the routing subunit.

[0026] In some feasible embodiments, the hardware accelerator further includes a random number generation unit; the control signal sequence further includes a random number generation signal;

[0027] After the control unit executes the determination of the control signal sequence based on the operating mode configuration value, it is also configured to send a random number generation signal to the random number generation unit.

[0028] The random number generation unit is configured to send a random number to the encryption unit indicated by the random number generation signal when the random number generation signal is read from the control unit; the random number is used to perform ciphertext operations.

[0029] In some feasible embodiments, the hardware accelerator further includes a shared computing unit; the shared computing unit includes an S-BOX and / or a matrix multiplier; the control signal sequence further includes computing unit reconstruction signals;

[0030] After the control unit executes the control signal sequence determined according to the operating mode configuration value, it is also configured to send an arithmetic unit reconstruction signal to the shared arithmetic unit;

[0031] The shared arithmetic unit is configured to: upon reading the arithmetic unit reconstruction signal from the control unit, switch the logic operation circuit and / or update the matrix coefficients based on the operation type indicated by the arithmetic unit reconstruction signal.

[0032] In some feasible embodiments, the hardware accelerator further includes a clock generation unit; the control signal sequence further includes a clock control signal;

[0033] After the control unit executes the determination of the control signal sequence based on the operating mode configuration value, it is also configured to send a clock control signal to the clock generation unit.

[0034] The clock generation unit is configured to: when a clock control signal is read from the control unit, configure the clock generation circuit based on the clock frequency indicated by the clock control signal, so that the clock generation circuit generates a first clock signal and a second clock signal; the first clock signal is used to drive the reading and writing of the control signal sequence; the second clock signal is used to drive the reading and writing of the data to be processed, the first encrypted data, and the second encrypted data.

[0035] In some feasible embodiments, the hardware accelerator also includes an interrupt control unit;

[0036] The interrupt control unit is configured to generate an interrupt signal when a preset signal is detected; the interrupt signal is used to indicate the processing result of the task processing flow corresponding to the preset signal; the preset signal is at least a level signal generated by one of the first encryption unit, the second encryption unit, the read / write unit, and the distribution unit.

[0037] In a second aspect, embodiments of this application provide a hardware security module, including a processor and the hardware accelerator mentioned in the first aspect. The hardware security module is applied to a chip, and the hardware accelerator is electrically connected to the chip's running memory.

[0038] The processor is configured to write the operating mode configuration value to the mode configuration register of the hardware accelerator;

[0039] The hardware accelerator is configured to: retrieve data to be processed from running memory based on the ciphertext task type indicated by the working mode configuration value; and execute the ciphertext task indicated by the ciphertext task type based on the data to be processed.

[0040] As described above, this embodiment of the application sets up a distribution unit inside the hardware accelerator. This distribution unit distributes intermediate data to subsequent encryption units when the encryption unit generates intermediate data. This effectively reduces the number of interactions between the hardware accelerator and the running memory via the bus when performing ciphertext tasks. This improves the security of ciphertext task processing and effectively reduces the bus bandwidth usage during ciphertext task execution, thus helping to maintain the performance of the chip to which the hardware accelerator belongs. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This application illustrates a security architecture diagram for an embedded system provided by an embodiment of the present application.

[0044] Figure 2 A schematic diagram of the first type of hardware security module provided in an embodiment of this application is shown;

[0045] Figure 3 A schematic diagram of a first type of hardware accelerator provided in an embodiment of this application is shown;

[0046] Figure 4 A schematic diagram of a second type of hardware security module provided in an embodiment of this application is shown;

[0047] Figure 5 A schematic diagram of a second type of hardware accelerator provided in an embodiment of this application is shown;

[0048] Figure 6 A schematic diagram of a third type of hardware accelerator provided in an embodiment of this application is shown;

[0049] Figure 7 A schematic diagram of a fourth type of hardware accelerator provided in an embodiment of this application is shown;

[0050] Figure 8 A schematic diagram of the fifth type of hardware accelerator provided in this application embodiment is shown;

[0051] Figure 9 A schematic diagram of a sixth type of hardware accelerator provided in an embodiment of this application is shown;

[0052] Figure 10 A schematic diagram of the seventh type of hardware accelerator provided in this application embodiment is shown;

[0053] Figure 11 A schematic diagram of the eighth type of hardware accelerator provided in this application embodiment is shown;

[0054] Figure 12 A schematic diagram of the ninth type of hardware accelerator provided in this application embodiment is shown. Detailed Implementation

[0055] To better understand the above-mentioned objectives, features, and advantages of this application, the solution of this application will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0056] like Figure 1 As shown, the relevant chips in advanced driver assistance systems integrate a hardware security module (HSM). A hardware security module is a physical computing device used to manage and protect digital keys, perform encryption and decryption operations, and provide other core security functions.

[0057] Hardware security modules can be set in the chip's Trusted Execution Environment (TEE), which can run in parallel with the chip's Rich Execution Environment (REE).

[0058] Because advanced driver assistance systems (ADAS) directly affect critical performance indicators such as driving safety, it is essential to ensure the security of data streams to enhance the stability and security of the ADAS. Therefore, sensitive data required by ADAS can be sent to a trusted execution environment during the execution process, where it is encrypted, decrypted, and verified by a hardware security module before being used to execute ADAS algorithms.

[0059] When processing data, advanced driver assistance systems (ADAS) utilize the DDR controller (DDRC) to store data in DDR (Double Data Rate Synchronous Dynamic Random Access Memory). DDR can be divided into non-secure and secure regions, corresponding to normal operating and trusted execution environments, respectively. Thus, data can be placed in either the non-secure or secure region based on its security level. Furthermore, ADAS can also rely on Flash memory, eMMC (Embedded MultiMediaCard), and efuse to facilitate data and command exchange.

[0060] The non-secure area of ​​RAM can store data that can be directly accessed in a normal operating environment. This type of data has little impact on the security of advanced driver assistance systems (ADAS). It can also store some low-security encrypted data, such as map navigation data, human-machine interaction data, and other commonly used data, as well as low-security encrypted data such as target detection results encrypted by a hardware security module.

[0061] The secure area of ​​RAM can store dedicated data for the trusted execution environment. This type of data has a significant impact on the security of advanced driver assistance systems (ADAS), and therefore must be placed in an area isolated from the normal operating environment to prevent the security of ADAS from being compromised by dangerous operations such as unauthorized access. Examples include unencrypted data that needs to be protected from malicious access, such as keys required for firmware verification and authentication, camera frame data, and radar point cloud data.

[0062] Understandably, when data stored in RAM is accessed by an advanced driver assistance system (ADAS), it needs to be verified by a hardware security module to ensure the security of the data processing flow, thereby ensuring the stability and security of ADAS functions.

[0063] like Figure 2 As shown, the hardware security module can integrate multiple encryption units, including but not limited to Advanced Encryption Standard (AES), Rivest-Shamir-Adleman (RSA) asymmetric encryption units, and hash encryption units. The AES core can efficiently encrypt and decrypt large amounts of data, such as video streams and point cloud data, to improve the throughput of the advanced driver assistance system (ADAS) and meet its computational speed requirements. The asymmetric encryption unit can be used to verify firmware and sensor signatures to ensure data originates from legitimate sensors. The hash encryption unit can calculate a hash digest of the data, which is then compared with the ciphertext / decrypted plaintext of the data during subsequent data retrieval to determine data security.

[0064] During data requests, the Advanced Driver Assistance System (ADAS) can read the data stream to be processed from the running memory into a data buffer via Direct Memory Access (DMA). Multiple encryption units then perform ciphertext processing on the data stream. This ciphertext processing flow is related to the current ciphertext task to be executed, and the multiple encryption units must process the data stream according to the ciphertext processing flow indicated by the ciphertext task. For example, if the current ciphertext task indicates a ciphertext processing flow of "first executing Advanced Encryption Standard (AES) on the data stream, then calculating the hash digest of the encrypted data," the hash digest is calculated based on the encrypted ciphertext. Therefore, the AES encryption unit and the hash encryption unit must strictly follow the processing order indicated by the ciphertext processing flow to process the data stream.

[0065] Therefore, in scenarios involving ciphertext processing, the Advanced Encryption Standard (AES) Encryption Unit (ACE) and the Hash Encryption Unit (HUZU) cannot process the data stream in parallel. Thus, after encrypting the data stream, the AES Encryption Unit needs to write the encrypted ciphertext data into runtime memory, then use Direct Memory Access (DMI) to read the ciphertext data into a data buffer. The Hash Unit then reads the ciphertext data from the data buffer, calculates a hash digest based on the ciphertext data, and writes the hash digest into runtime memory.

[0066] like Figure 2 As shown, the data stream to be processed, encrypted data, and hash digests can be read or written to or retrieved from running memory using the BUS bus and serial communication interface (MIPI_RX & MIPI Interface). However, frequent reads and writes can lead to excessive bus bandwidth consumption, resulting in a decrease in the performance of the advanced driver assistance system (ADAS). Furthermore, when accessing high-quality data such as image data, the large volume of image data itself further increases bus bandwidth consumption, thus impacting the performance of the ADAS.

[0067] To solve the above problems, such as Figure 3 As shown, this application embodiment provides a hardware accelerator 10. The hardware accelerator 10 integrates a first encryption unit 301, a second encryption unit 302, a distribution unit 400, and a read / write unit 200. The hardware accelerator 10 can be applied to a hardware security module, which is integrated into the chip of an advanced driver assistance system. The hardware accelerator 10 is electrically connected to the chip's RAM 20.

[0068] In some embodiments, the first encryption unit 301 and the second encryption unit 302 are different encryption units, which can be one of AES unit, RSA unit, or hash unit, respectively. The AES unit includes functional units such as byte substitution (SubBytes), row shifting (ShiftRows), column mixing (MixColumns), and round key addition (AddRoundKey). The hash unit includes a message scheduler and a compression function. The message scheduler can split the data stream to be processed into the number of bits required by the compression function, which is used to calculate the hash digest. The RSA unit includes a modular exponentiation controller and a Montgomery modular multiplier.

[0069] The hardware accelerator 10 in this embodiment includes, but is not limited to, two encryption units. In some examples, the hardware accelerator 10 includes an AES unit, an RSA unit, and a hash unit. For the sake of brevity and convenience in describing the design concept of this application embodiment, the first encryption unit 301 and the second encryption unit 302 will be described as the AES encryption unit and the hash encryption unit, respectively, in the following embodiments.

[0070] In some examples, the distribution unit 400 includes devices or logic circuits with data distribution capabilities and a data buffer subunit 403 for implementing data distribution. The input ports of the distribution unit 400 are connected in parallel with the input ports of each functional unit in the main data channel and the bus used for data transmission. Thus, when data transmission occurs in the main data channel, the distribution unit 400 can also acquire the data driven onto the bus and copy and distribute the data. The main data channel refers to the data transmission channel where the current encryption unit is located. For example, if the first encryption unit 301 is connected to the shared register group, the data channel formed by the first encryption unit 301 writing encrypted data to the shared register group through the bus can be considered the main data channel. The data channel formed by the distribution unit 400 reading encrypted data from the bus through its input port, copying the data, and then sending the copied data to the second encryption unit 302 can be considered a bypass data channel.

[0071] The read / write unit 200 can refer to a direct access memory unit, i.e., DMA. The read / write unit 200 can drive data read from the running memory 20 to the bus so that the encryption unit or distribution unit 400 in the hardware accelerator 10 can read this data from the bus. In addition, the read / write unit 200 can also drive data in the shared register set to the bus so as to write data to the running memory 20 via the bus.

[0072] The shared register set is a group of registers used to store intermediate or final data generated by the encryption unit. The shared register set is electrically connected to the first encryption unit 301 so that the encryption unit can directly write the generated data into the shared register set via the bus.

[0073] In some embodiments, the first encryption unit is configured to: when reading a data stream to be processed from the running memory of the chip, perform a first ciphertext operation on the data stream to be processed; and write the first ciphertext data stream generated by the first ciphertext operation to a shared register group;

[0074] The distribution unit is configured to: upon detecting that the first ciphertext data stream is written into the shared register group, read the first ciphertext data stream from the shared register group; and send the first ciphertext data stream to the second arithmetic unit.

[0075] The read / write unit is configured to: upon detecting that the first ciphertext data stream is written into the shared register group, write the first ciphertext data stream into the running memory;

[0076] The second encryption unit is configured to: when reading the first ciphertext data stream from the distribution unit, perform a second ciphertext operation on the first ciphertext data stream; and write the second ciphertext data stream generated by the second ciphertext operation to the shared register group;

[0077] The read / write unit is further configured to write the second ciphertext data stream into the running memory when it detects that the second ciphertext data stream has been written into the shared register group.

[0078] In some examples, the first encryption unit 301 is an AES encryption unit, the second encryption unit 302 is a hash encryption unit, and the read / write unit 200 is a DMA. When the first encryption unit 301 receives driving environment image data read from memory, it performs ciphertext operations such as byte substitution, row shifting, column mixing, and wheel key addition on the driving environment image data, and then writes the encrypted first ciphertext data stream into the shared register group through the bus.

[0079] When the first ciphertext data stream is driven onto the bus by the AES encryption unit, the distribution unit 400 reads the first ciphertext data stream through the input port and copies the read first ciphertext data stream to obtain a copy of the first ciphertext data stream. The first ciphertext data stream and the copy of the first ciphertext data stream are identical data. Then, the distribution unit 400 can send the copy of the first ciphertext data stream to the second encryption unit 302.

[0080] Alternatively, when the distribution unit 400 detects that a first ciphertext data stream has been written into the shared register group, it can copy the first ciphertext data stream read from the shared register group and send the copied first ciphertext data stream to the second encryption unit 302.

[0081] The read / write unit 200 can obtain the data volume / data storage status in the shared register group. Therefore, when the shared register group is written with a first encrypted data stream, the read / write unit 200 can drive the first encrypted data stream to the bus and write it to the running memory 20 via the bus. Alternatively, the read / write unit 200 can wait until the data volume in the shared register group reaches a data volume threshold before driving the first encrypted data stream to the bus and writing it to the running memory 20.

[0082] Upon receiving a copy of the first ciphertext data stream sent by the distribution unit 400, the second encryption unit 302 can perform a hash operation on the copy of the first ciphertext data stream to calculate a hash digest of the copy of the first ciphertext data stream, and write the calculated hash digest into the shared register group via the bus.

[0083] When the read / write unit 200 detects that a second ciphertext data stream has been written into the shared register group, it can drive the second ciphertext data stream to the bus and write the second ciphertext data stream into the running memory 20 via the bus.

[0084] In some other examples, AES-encrypted data can be placed in the secure or insecure area of ​​the running memory 20 according to its security level. When the first ciphertext data stream is called again, the processor 30 (secure CPU) integrated in the hardware security module can call the hash digest corresponding to the first ciphertext data stream in the running memory 20 to determine the security of the first ciphertext data stream.

[0085] By adding a distribution unit 400 to the hardware accelerator 10, and by copying and forwarding the intermediate data (such as the first ciphertext data stream) generated by the encryption unit based on the connection relationship between the distribution unit 400 and the bus, the execution process of the ciphertext task conforms to the pipelined processing process. This reduces the number of times each unit in the hardware accelerator 10 accesses the running memory 20 through the bus, thereby reducing the bus bandwidth occupancy during the execution of the ciphertext task and improving the operational stability of the chip / system to which the hardware accelerator 10 belongs.

[0086] It is understandable that the first encryption unit 301, the second encryption unit 302, the read / write unit 200, and the distribution unit 400 are all configurable units. This means that these units need to be configured before the ciphertext task is executed so that they can execute the ciphertext task sequentially. Configuring these units may refer to configuring their electrical connections to determine the main data channel and bypass data channel, as well as configuring their read / write addresses, read / write data volumes, task modes, etc., to ensure that each unit executes the ciphertext task sequentially.

[0087] like Figure 4 As shown, in some embodiments, the hardware accelerator 10 is electrically connected to the processor 30 of the hardware security module. The processor 30 of the hardware security module is a dedicated processor 30 for managing the hardware security module. This processor 30 can receive data processing requests initiated by the processor 30 or processing core in the chip where the hardware security module is located, and configure the hardware accelerator 10 according to the data processing requests to drive the hardware accelerator 10 to perform corresponding encrypted tasks.

[0088] The hardware security module also includes a read-only memory (ROM) unit 40 and a random access memory (RAM) unit 40 electrically connected to the processor 30. The ROM unit 40 is used to store the lowest-level boot program and security monitoring program of the hardware security module. The processor 30 of the hardware security module can read the boot program in the ROM to complete the startup, initialization and other behaviors and then enter the running state.

[0089] Random access memory (RAM) can be used to provide runtime space for a trusted operating system, and can also be used to store encrypted firmware, keys, and small amounts of sensitive data, thereby providing data support for the encryption unit's ciphertext tasks and for the processor 30's data verification processes. For example, after the hardware security module's DMA reads the hash digest corresponding to the encrypted data and the hash digest obtained in real-time from the running memory 20 into RAM, the processor 30 can read these two hash digests from RAM and compare them to determine whether the encrypted data is secure.

[0090] like Figure 5As shown, the hardware accelerator 10 also includes a mode configuration register 500 and a control unit 100. The mode configuration register 500 includes multiple data bits for storing operating mode configuration values. The operating mode configuration values ​​determine the encrypted task executed by the hardware accelerator 10. The control unit 100 can be a unit with logic control capabilities implemented based on a state machine. The control unit 100 is electrically connected to the mode configuration register 500, the first encryption unit 301, the second encryption unit 302, and the distribution unit 400. Therefore, the control unit 100 can determine the encrypted task by reading the operating mode configuration value and generate a corresponding control signal sequence based on the encrypted task, so as to control each unit in the hardware accelerator 10 to execute the encrypted task through the control signal sequence. Furthermore, based on the operating characteristics of the state machine, the control unit 100 can switch state values ​​according to the monitored level changes generated by each unit and execute the operating logic corresponding to the switched state value, thereby controlling the execution flow of the encrypted task.

[0091] In some embodiments, the mode configuration register 500 is configured to store a working mode configuration value, which is a value written by the processor 30 to a physical address corresponding to the mode configuration unit.

[0092] The control unit 100 is configured to: read the operating mode configuration value from the mode configuration unit; and determine a control signal sequence based on the operating mode configuration value. The control signal sequence is used at least to indicate the electrical connection relationship between the first encryption unit 301, the second encryption unit 302, and the distribution unit 400, and the electrical connection relationship can determine the data flow direction of the data generated by the first encryption unit 301, the second encryption unit 302, and the distribution unit 400.

[0093] In some examples, the processor 30 of the hardware security module receives a request instruction from the processor 30 of the chip to ensure that the ciphertext task of "performing AES on the data stream to be processed first, and then performing hash digest operation" is performed, and writes the corresponding working mode configuration value into the mode configuration register 500.

[0094] The control unit 100 can monitor the register bits in the mode configuration register 500 at a preset monitoring frequency. After recognizing the working mode configuration value, it generates a control signal sequence corresponding to the encrypted task pointed to by the working mode configuration value. Specifically, after recognizing the working mode configuration value, the control unit 100 can switch its own state value to the state value corresponding to that working mode configuration value. Accordingly, after switching the state value, the control unit 100 will determine the corresponding control signal sequence.

[0095] It is understandable that the control signal sequence contains control signals that are actually changes in the level signals generated by the interfaces connecting the control unit 100 and each unit. When each unit detects the changes in the level signals, it can change its own circuit connection relationship and the connection relationship with other units, thereby adapting to the current encrypted task.

[0096] In some embodiments, the control signal sequence includes read / write control signals and distribution control signals. The read / write control signals can configure the DMA and drive the DMA to read the data stream to be processed from the running memory 20. For example... Figure 5 As shown, the hardware accelerator 10 also includes a data buffer. After the DMA reads the data stream to be processed from the running memory 20, it can drive the data stream to the bus, and then transfer the data stream to the data buffer via the bus. The DMA integrates a DMA register, which can store information related to data read / write, such as the data source address and data length. The DMA can read data from the running memory 20 based on the information stored in the DMA register.

[0097] The distribution control signal can control the electrical connection between the distribution unit 400 and the encryption unit, that is, the distribution control signal can control the flow of data read by the distribution unit 400. For example... Figure 6 As shown, the distribution unit 400 includes a multi-channel distribution subunit 401, which is electrically connected to the data buffer. The multi-channel distribution subunit 401 can be a demultiplexer (DEMUX) and features single-input multiple-output characteristics. Each output interface is connected to an encryption unit. Therefore, the multi-channel distribution subunit 401 can read the data stream to be processed from the data buffer and distribute it to the first encryption unit 301 or the second encryption unit 302. That is, the multi-channel distribution subunit 401 can transmit the data stream to be processed to the corresponding encryption unit according to the electrical connection relationship indicated by the distribution control signal.

[0098] In some embodiments, after the control unit 100 determines the control signal sequence according to the operating mode configuration value, it is further configured to: send the read / write control signal to the read / write unit 200; and send the distribution control signal to the distribution unit 400.

[0099] The read / write unit 200 is configured to: when the read / write control signal is read from the control unit 100, read the data stream to be processed from the running memory 20 into the data buffer according to the address indicated by the read / write control signal;

[0100] The multiplexing subunit 401 is configured to send the data stream to be processed to the first encryption unit 301 based on the electrical connection relationship indicated by the distribution control signal when the distribution control signal is read from the control unit 100.

[0101] In some examples, the control unit 100 writes the data source address and data length of the data stream to be processed into the DMA register. Additionally, the control unit 100 sends a distribution control signal to the multiplexing subunit 401, which, in response to the level change generated by the distribution control signal, connects to the output interface connected to the first encryption unit 301 and closes the output interface connected to the second encryption unit 302.

[0102] The DMA register reads the data stream to be processed from the running memory 20 into the data buffer via the bus according to the data source address and data length. Then, the multiplexing subunit 401 can read the data stream to be processed from the data buffer and send the data stream to be processed to the first encryption unit 301 through the connected output interface.

[0103] Understandably, the control unit 100 can monitor the circuit connection status of the DMA and the multiplexing subunit 401 based on their electrical connection relationship to determine whether the DMA and the multiplexing subunit 401 are configured correctly. For example, if the control unit 100 detects that the output interface between the multiplexing subunit 401 and the first encryption unit 301 is high (on), it can switch its own state value and, based on the change in state value, trigger the sending of a level signal to the multiplexing subunit 401 to read the data stream to be processed from the data buffer.

[0104] By setting up a multiplexing subunit 401 in the hardware accelerator 10, and cooperating with the control signal sequence issued by the control unit 100, the data flow direction after the data stream to be processed enters the hardware accelerator 10 can be effectively controlled. However, during the execution of the encrypted task, it is usually completed sequentially by multiple encryption units in a certain execution order. Therefore, it is necessary to further control the data flow direction of the intermediate data generated by the encryption units.

[0105] like Figure 7As shown, the distribution unit 400 further includes a routing subunit 402, which is electrically connected to the first encryption unit 301 and / or the second encryption unit 302. The routing subunit 402 can be a digital logic circuit with routing capabilities. Both the routing subunit 402 and the shared register group are connected to the bus used to transmit the first ciphertext data stream generated by the first encryption unit 301; that is, the routing subunit 402 and the shared register group can read the first ciphertext data stream from the bus in parallel. The routing subunit 402 can determine which encryption unit to connect to based on control signals initiated by the control unit 100, and routes the intermediate data generated during ciphertext execution to the encryption unit electrically connected to it.

[0106] The first encryption unit 301 and the second encryption unit 302 may also have corresponding registers integrated inside, which are used to store information such as working mode and key acquisition address.

[0107] The control signal sequence also includes a first operation control signal and a second operation control signal. That is, the control unit 100 can write the working mode and key acquisition address corresponding values ​​to the registers inside the first encryption unit 301 and the second encryption unit 302. The first encryption unit 301 and the second encryption unit 302 can read the configuration values ​​stored in their internal registers to execute the ciphertext task according to the working mode and key acquisition address indicated by the configuration values.

[0108] In some embodiments, after the control unit 100 executes the determination of the control signal sequence according to the working mode configuration value, it is further configured to: send a first operation control signal to the first encryption unit 301 and send a second operation control signal to the second encryption unit 302;

[0109] When the first encryption unit 301 reads the data stream to be processed from the running memory 20 of the chip, it performs a first ciphertext operation on the data stream to be processed. Specifically, it is configured to perform a first ciphertext operation on the data stream to be processed according to the operation type indicated by the first operation control signal.

[0110] The routing subunit 402 is configured to send the first ciphertext data stream to the second encryption unit 302, specifically by: reading the first ciphertext data stream from the shared register group when the first ciphertext data stream is detected being written into the shared register group; and sending the first ciphertext data stream to the second encryption unit 302 based on the electrical connection relationship indicated by the distribution control signal.

[0111] When the second encryption unit 302 reads the first ciphertext data stream from the distribution unit 400, it performs a second ciphertext operation on the first ciphertext data stream. Specifically, it is configured to perform a second ciphertext operation on the first ciphertext data stream according to the operation type indicated by the second operation control signal when reading the first ciphertext data stream from the routing subunit 402.

[0112] In some examples, the configuration values ​​read by the first encryption unit 301 from its integrated registers correspond to the "encryption" task and the "key 1 acquisition address," respectively. The first encryption unit 301 obtains the key according to the key 1 acquisition address and performs encryption operations to obtain the first ciphertext data stream. The first encryption unit 301 further drives the first ciphertext data stream to the bus to transmit the first ciphertext data stream to the shared register group via the bus. When the read / write unit 200 detects the first ciphertext data stream being written to the shared register group, it drives the first ciphertext data stream in the shared register group to the bus to store the first ciphertext data stream into the running memory 20 via the bus.

[0113] Based on its electrical connection with the bus, the routing subunit 402 reads the first ciphertext data stream driven to the bus. Upon reading the first ciphertext data stream, the routing subunit 402 synchronously copies the first ciphertext data stream to obtain a copy of the first ciphertext data stream, and routes the copy of the first ciphertext data stream to the second encryption unit 302.

[0114] The second encryption unit 302 determines its ciphertext task based on the configuration value corresponding to "calculate hash digest" read from its integrated registers. Upon receiving a copy of the first ciphertext data stream, it calculates the hash digest of the copy using a message scheduler and compression algorithm. The second encryption unit 302 further transmits the second ciphertext data stream to a shared register set. Upon detecting that the second ciphertext data stream is being written to the shared register set, the read / write unit 200 drives the second ciphertext data stream in the shared register set to the bus, thereby storing the second ciphertext data stream into the running memory 20 via the bus.

[0115] It is understood that the timing of the first ciphertext data stream and the second ciphertext data stream via the bus by the read / write unit 200 can be adjusted according to actual needs, and this application embodiment does not limit this. This application embodiment aims to synchronously copy the intermediate data (first ciphertext data stream) generated by the first encryption unit 301 and route the copied first ciphertext data stream copy to the second encryption unit 302 based on the design of the routing subunit 402. This can effectively reduce the number of times the hardware accelerator 10 accesses the running memory 20, thereby reducing the bus bandwidth occupancy rate of the chip by the hardware accelerator 10 during the execution of the ciphertext task.

[0116] like Figure 8 As shown, the distribution unit 400 further includes a data buffer subunit 403, which can be a FIFO (First-In-First-Out) memory / first-in-first-out buffer. The data buffer subunit 403 is electrically connected to the routing subunit 402, and can receive a copy of the first ciphertext data stream generated by the routing subunit 402. The data buffer subunit 403 can also be electrically connected to the first encryption unit 301 and / or the second encryption unit 302, thereby enabling it to send a copy of the first ciphertext data stream to either the first encryption unit 301 or the second encryption unit 302.

[0117] In some embodiments, after reading the first ciphertext data stream, the routing subunit 402 copies the first ciphertext data stream to obtain a copy of the first ciphertext data stream, and is further configured to write the first ciphertext data stream to the data buffer subunit 403.

[0118] The data caching subunit 403 is configured to send the first ciphertext data stream to the second encryption unit 302 when the first ciphertext data stream is read from the routing subunit.

[0119] In some examples, after the control unit 100 issues a distribution control signal, the data buffer subunit 403 connects to the output interface of the second encryption unit 302. Then, upon receiving a copy of the first ciphertext data stream from the routing subunit 402, the data buffer subunit 403 sends the copy of the first ciphertext data stream to the second encryption unit 302. Upon receiving the copy of the first ciphertext data stream, the second encryption unit 302 executes the ciphertext task.

[0120] By setting up the data cache subunit 403, it can form a cache area for the first ciphertext data stream copy together with the routing subunit 402. Thus, the hardware accelerator 10 does not need to write the intermediate data (first ciphertext data stream) generated by the encryption unit back to the running memory 20 during the execution of the ciphertext task. This can effectively reduce the number of times the hardware accelerator 10 accesses the running memory 20, thereby reducing the bus bandwidth occupancy rate and helping to maintain the performance stability of the chip to which the hardware accelerator 10 belongs.

[0121] On the other hand, the data cache subunit 403 can be used to offset the decrease in throughput caused by the different data processing cycles of the first encryption unit 301 and the second encryption unit 302. For example, the AES encryption unit outputs a calculation result every two clock cycles, while the hash unit outputs a calculation result every three clock cycles. This means the data processing rates of the AES encryption unit and the hash unit are not perfectly matched, leading to a decrease in data throughput. By setting the data cache subunit 403, the data output by the AES encryption unit can be cached, and the hash unit can also read data from the data cache subunit 403 as needed. The AES unit will not stop operating because the hash unit has not finished processing data, thus ensuring data throughput and improving chip performance.

[0122] For example, during the encryption process of the AES encryption unit, random numbers can be used to make the encryption results of different data different, so as to distinguish the ciphertext corresponding to different data streams.

[0123] like Figure 9 As shown, the hardware accelerator 10 further includes a random number generation unit 600, which is electrically connected to the first encryption unit 301 and the second encryption unit 302. The random number generation unit 600 can generate a random number during each encryption process. The addition of random numbers makes operations such as encryption more specific, preventing different data from resulting in the same ciphertext. The control unit 100 can drive the random number generation unit 600 to send random numbers to the first encryption unit 301 or the second encryption unit 302 by sending a start signal to the random number generation unit 600.

[0124] In some embodiments, the control signal sequence further includes a random number generation signal;

[0125] After the control unit 100 executes the determination of the control signal sequence according to the working mode configuration value, it is further configured to send the random number generation signal to the random number generation unit 600.

[0126] The random number generation unit 600 is configured to send a random number to the encryption unit indicated by the random number generation signal when it reads the random number generation signal from the control unit 100; the random number is used to perform ciphertext operations.

[0127] In some examples, when the first encryption unit 301 receives the data stream to be processed, the control unit 100 switches to the corresponding state value and triggers an action to send a random number generation signal to the random number generation unit 600 based on the switched state value. This causes the random number generation unit 600 to connect to the output interface of the first encryption unit 301. Upon receiving a random number and the data stream to be processed, the first encryption unit 301 can encrypt the data stream according to the random number, key, and other encryption information.

[0128] In other examples, when the second encryption unit 302 receives a copy of the first ciphertext data stream, the control unit 100 switches to a corresponding state value and triggers an action to send a random number generation signal to the random number generation unit 600 based on the switched state value. The random number generation unit 600 then connects to the output interface of the second encryption unit 302. Upon receiving the random number and the data stream to be processed, the second encryption unit 302 calculates a hash digest based on the random number, the key, and the copy of the first ciphertext data stream.

[0129] By setting the random number generation unit 600, the specificity of the ciphertext operation result can be effectively guaranteed, so that the ciphertext operation result corresponding to different data is unique, so as to distinguish different data.

[0130] The first encryption unit 301 and the second encryption unit 302 integrate execution standards related to ciphertext tasks. The first encryption unit 301 and the second encryption unit 302 call the computing tools to execute the ciphertext tasks according to the execution standards.

[0131] like Figure 10 As shown, the hardware accelerator 10 also includes a shared computing unit 700. The shared computing unit 700 is electrically connected to the first encryption unit 301 and the second encryption unit 302. The first encryption unit 301 and the second encryption unit 302 can utilize the shared computing unit 700 to complete the ciphertext task during execution. The shared computing unit 700 is a computing circuit integrating multiple computational logics, such as a matrix multiplier or a Substitution-Box (S-BOX) circuit integrating multiple mapping relationships. The internal circuitry of the shared computing unit 700 can be adjusted to perform different operations. For example, the matrix multiplier can be used to perform, but is not limited to, the MixColumns transformation in the AES standard or the ∑0, ∑1 function calculation in SHA-256; the S-BOX can be used to perform, but is not limited to, the SubBytes transformation in AES or the Ch, Maj logic functions in SHA-256.

[0132] The control unit 100 is electrically connected to the shared computing unit 700, thereby enabling the control unit 100 to control the adjustment of the internal circuitry of the shared computing unit 700. Specifically, the control signal sequence also includes a computing unit reconstruction signal. Based on the specific process of the encrypted task, the control unit 100 controls the internal circuitry of the shared computing unit 700 to adjust to the corresponding circuitry.

[0133] In some embodiments, after the control unit 100 executes the determination of the control signal sequence based on the operating mode configuration value, it is further configured to send an arithmetic unit reconstruction signal to the shared arithmetic unit 700.

[0134] The shared arithmetic unit 700 is configured to: switch the lookup table, and / or switch the logic operation circuit, and / or update the matrix coefficients based on the operation type indicated by the arithmetic unit reconstruction signal when the arithmetic unit reconstruction signal is read from the control unit 100.

[0135] In some examples, before the AES encryption unit performs encryption operations, the control unit 100 sends an arithmetic unit reconstruction signal to the shared arithmetic unit 700, that is, by changing the level of the interface connected to the shared arithmetic unit 700, the shared arithmetic unit 700 is driven to adjust its internal circuit to the encryption operation circuit.

[0136] Specifically, the internal circuitry of the S-BOX is adapted to a lookup table circuit corresponding to the encryption operation, the internal circuitry of the matrix multiplier is adapted to a logic operation circuit corresponding to the encryption operation, and the matrix coefficients are adjusted to coefficients corresponding to the current encryption operation.

[0137] By setting up the shared computing unit 700 and combining it with the reconfigurable design concept of the shared computing unit 700, both the first encryption unit 301 and the second encryption unit 302 can call the shared computing unit 700 during the operation process, but the shared computing unit 700 plays a different role in different stages.

[0138] It should be noted that the electrical connections between the first encryption unit 301, the second encryption unit 302, the distribution unit 400, and other units integrated in the hardware accelerator 10 can all be configured by the control unit 100 according to the specific ciphertext task indicated by the working mode configuration value. That is, the hardware accelerator 10 as a whole can also be regarded as a reconfigurable device. When the hardware accelerator 10 is reconfigurable, it can effectively adapt to various ciphertext task execution scenarios, effectively save hardware layout resources, reduce the number of hardware components, and thus help reduce the area of ​​the chip to which the hardware accelerator 10 belongs.

[0139] The control unit 100 plays the role of managing, coordinating and configuring each unit in the hardware accelerator 10. The control unit 100 and each encryption unit rely on the clock cycle when reading and writing data. Under the control of the clock cycle, the control unit 100 can control each unit to perform corresponding actions in sequence.

[0140] like Figure 11 As shown, the hardware accelerator 10 also includes a clock generation unit 800. The clock generation unit 800 can provide multiple clock domains, each with a different clock period. These different clock periods correspond to different data read / write frequencies, which in turn are related to data throughput. That is, the smaller the clock period, the higher the data read / write frequency, and the greater the data throughput. Thus, in scenarios with high data throughput requirements, a clock domain with a smaller clock period can be activated. Conversely, a clock domain with a larger clock period can be activated.

[0141] The basic operating framework of the clock generation unit 800 can be built by the processor 30 in the hardware security module based on the boot program and code in the ROM. The control unit 100 can control which clock domains the clock generation unit 800 provides to the hardware accelerator 10, that is, the control unit 100 can adjust the clock domains provided by the clock generation circuit through the clock control signal.

[0142] In some embodiments, after the control unit 100 determines the control signal sequence according to the operating mode configuration value, it is further configured to send the clock control signal to the clock generation unit 800.

[0143] The clock generation unit 800 is configured to: when reading the clock control signal from the control unit 100, configure the clock generation circuit based on the clock frequency indicated by the clock control signal, so that the clock generation circuit generates a first clock signal and a second clock signal; the first clock signal is used to drive the reading and writing of the control signal sequence; the second clock signal is used to drive the reading and writing of the data to be processed, the first ciphertext data, and the second ciphertext data.

[0144] In some examples, the frequency of the first clock signal is lower than the frequency of the second clock signal. For example, the frequency of the first clock signal is 100-200MHz, and the frequency of the second clock signal is 1GHz.

[0145] In some other examples, due to the increased data throughput requirements of the ciphertext task, the control unit 100 adjusts the frequency of the second clock signal to 1.2 GHz by sending a clock control signal to the clock generation unit 800.

[0146] By setting the frequency of the first clock signal to a lower value, it is possible to ensure that control signals are read, written or transmitted correctly. By setting the frequency of the second clock signal to a higher value, it is possible to adapt to the demand for high data throughput. This ensures both the normal execution of the control logic of the hardware accelerator 10 and the chip performance requirements for high data throughput.

[0147] The hardware accelerator 10 and the processor 30 need to interact to ensure that the processor 30 can send new encrypted tasks to the hardware accelerator 10 or perform error correction when the hardware accelerator 10 malfunctions.

[0148] like Figure 12 As shown, the hardware accelerator 10 also includes an interrupt control unit 900. The interrupt control unit 900 may integrate one or more registers, and different register bits in the registers can be used to monitor the operating status of different units. The operating status of each unit can be represented by updating the values ​​of the register bits. The processor 30 can read the register bits in the interrupt register to determine the operating status of each unit.

[0149] In some embodiments, the interrupt control unit 900 is configured to generate an interrupt signal upon detecting a preset signal. The interrupt signal is used to indicate the processing result of the task processing flow corresponding to the preset signal.

[0150] The preset signals include, but are not limited to, signals generated by the first encryption unit 301 and the second encryption unit 302 when reading or writing is completed, signals generated when data is written to / written out of the shared register group, and signals generated after the shared arithmetic unit 700 circuit is reconfigured. When these units generate preset signals, the register bits in the interrupt control unit 900 will adaptively record the corresponding identifier value according to the preset signal.

[0151] In some examples, after generating the first ciphertext data stream, the first encryption unit 301 writes the first ciphertext data stream to a shared register group via a bus. The register bit of the interrupt control unit 900 detects the bit change caused by the first encryption unit 301 writing data to the shared register group and updates the flag bit from 0 to 1. Furthermore, the processor 30 of the hardware security module can also read the change in the flag from the register bit in the interrupt register to determine that the ciphertext task of the first encryption unit 301 is being executed normally.

[0152] By setting the interrupt control unit 900, the processor 30 of the hardware security module can determine the circuit status and ciphertext task completion status of the hardware accelerator 10 based on the identifier values ​​stored in multiple register bits, and then determine and issue subsequent ciphertext tasks, effectively ensuring the stability of ciphertext task execution.

[0153] In some embodiments, this application also provides a hardware security module, including a processor 30 and a hardware accelerator 10. The processor 30 and the hardware accelerator 10 are electrically connected, and the hardware accelerator 10 is electrically connected to the running memory 20 of the chip where the hardware security module is located.

[0154] In some embodiments, the processor 30 is configured to write a working mode configuration value into the mode configuration register 500 of the hardware accelerator 10.

[0155] Hardware accelerator 10 is configured to: acquire a stream of data to be processed from runtime memory 20 based on the ciphertext task type indicated by the operating mode configuration value; and execute the ciphertext task indicated by the ciphertext task type based on the data stream to be processed.

[0156] In some examples, the processor 30 of the hardware security module receives a ciphertext data request sent by the processor 30 or processing core of the chip, determines the working mode configuration value according to the ciphertext task type indicated by the ciphertext data request, and writes the working mode configuration value into the working mode register of the hardware accelerator 10.

[0157] After reading the working mode configuration value in the working mode register, the control unit 100 built into the hardware accelerator 10, based on a state machine, sends control signals to multiple encryption units, distribution units 400, and shared computing units 700 within the hardware accelerator 10 to control each unit to execute the ciphertext task. Specifically, the distribution unit 400 within the hardware accelerator 10 can copy intermediate data generated by the encryption units and send the copied copy to subsequent encryption units, thereby reducing the data transfer overhead between the hardware accelerator 10 and the running memory 20, and effectively reducing the bus bandwidth occupancy during the ciphertext task execution process.

[0158] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A hardware accelerator, characterized in that, The hardware accelerator is applied to a hardware security module, which is integrated into a chip; the hardware accelerator includes: The first encryption unit is configured to: when reading a data stream to be processed from the running memory of the chip, perform a first ciphertext operation on the data stream to be processed; and write the first ciphertext data stream generated by the first ciphertext operation to the shared register group; The distribution unit is configured to: upon detecting that the first ciphertext data stream is written to the shared register group, read the first ciphertext data stream from the shared register group; and send the first ciphertext data stream to the second arithmetic unit. The read / write unit is configured to write the first ciphertext data stream into the running memory when it is detected that the first ciphertext data stream is written into the shared register group; The second encryption unit is configured to: when reading the first ciphertext data stream from the distribution unit, perform a second ciphertext operation on the first ciphertext data stream; and write the second ciphertext data stream generated by the second ciphertext operation to the shared register group; The read / write unit is further configured to write the second ciphertext data stream into the running memory when it detects that the second ciphertext data stream has been written into the shared register group.

2. The hardware accelerator according to claim 1, characterized in that, The hardware accelerator is electrically connected to the processor of the hardware security module, and the hardware accelerator further includes: A mode configuration register is configured to store an operating mode configuration value, which is a value written by the processor to the physical address corresponding to the mode configuration unit. The control unit is configured to: read the working mode configuration value from the mode configuration unit; determine a control signal sequence based on the working mode configuration value; the control unit is electrically connected to the first encryption unit, the second encryption unit, and the distribution unit; the control signal sequence is used to at least indicate the electrical connection relationship between the first encryption unit, the second encryption unit, and the distribution unit; the electrical connection relationship is used to determine the data flow direction of the data generated by the first encryption unit, the second encryption unit, and the distribution unit.

3. The hardware accelerator according to claim 2, characterized in that, The hardware accelerator also includes a data buffer; the control signal sequence includes read / write control signals and distribution control signals; the distribution unit includes a multi-path distribution subunit; After the control unit executes the determination of the control signal sequence according to the working mode configuration value, it is further configured to: send the read / write control signal to the read / write unit; and send the distribution control signal to the distribution unit. The read / write unit is configured to: when the read / write control signal is read from the control unit, read the data stream to be processed from the running memory into the data buffer according to the address indicated by the read / write control signal; The multiplexing subunit is configured to send the data stream to be processed to the first encryption unit based on the electrical connection relationship indicated by the distribution control signal when the distribution control signal is read from the control unit.

4. The hardware accelerator according to claim 3, characterized in that, The control signal sequence further includes a first operational control signal and a second operational control signal; the distribution unit further includes a routing subunit; After the control unit executes the determination of the control signal sequence according to the working mode configuration value, it is further configured to: send a first operation control signal to the first encryption unit and send a second operation control signal to the second encryption unit; When the first encryption unit reads the data stream to be processed from the running memory of the chip, it performs a first ciphertext operation on the data stream to be processed. Specifically, it is configured to perform a first ciphertext operation on the data stream to be processed according to the operation type indicated by the first operation control signal. The routing subunit is configured to send the first ciphertext data stream to the second encryption unit by: upon detecting that the first ciphertext data stream is written to the shared register group, reading the first ciphertext data stream from the shared register group; and sending the first ciphertext data stream to the second encryption unit based on the electrical connection relationship indicated by the distribution control signal. When the second encryption unit reads the first ciphertext data stream from the distribution unit, it performs a second ciphertext operation on the first ciphertext data stream. Specifically, it is configured to perform a second ciphertext operation on the first ciphertext data stream according to the operation type indicated by the second operation control signal when reading the first ciphertext data stream from the routing subunit.

5. The hardware accelerator according to claim 4, characterized in that, The distribution unit further includes a data caching subunit; When the routing subunit sends the first ciphertext data stream to the second encryption unit based on the electrical connection relationship indicated by the distribution control signal, it is specifically configured to write the first ciphertext data stream into the data buffer subunit. The data caching subunit is configured to send the first ciphertext data stream to the second encryption unit when it reads the first ciphertext data stream from the routing subunit.

6. The hardware accelerator according to claim 5, characterized in that, The hardware accelerator further includes a random number generation unit; the control signal sequence further includes a random number generation signal; After the control unit executes the determination of the control signal sequence according to the working mode configuration value, it is further configured to send the random number generation signal to the random number generation unit. The random number generation unit is configured to send a random number to the encryption unit indicated by the random number generation signal when it reads the random number generation signal from the control unit; the random number is used to perform ciphertext operations.

7. The hardware accelerator according to claim 5, characterized in that, The hardware accelerator also includes a shared computing unit; the shared computing unit includes an S-BOX and / or a matrix multiplier; the control signal sequence also includes a computing unit reconstruction signal; After the control unit executes the determination of the control signal sequence according to the working mode configuration value, it is also configured to send the computing unit reconstruction signal to the shared computing unit. The shared computing unit is configured to: when reading the computing unit reconstruction signal from the control unit, switch the logic operation circuit and / or update the matrix coefficients based on the operation type indicated by the computing unit reconstruction signal.

8. The hardware accelerator according to claim 7, characterized in that, The hardware accelerator also includes a clock generation unit; the control signal sequence also includes a clock control signal; After the control unit executes the determination of the control signal sequence according to the working mode configuration value, it is further configured to send the clock control signal to the clock generation unit. The clock generation unit is configured to: when reading the clock control signal from the control unit, configure the clock generation circuit based on the clock frequency indicated by the clock control signal, so that the clock generation circuit generates a first clock signal and a second clock signal; The first clock signal is used to drive the reading and writing of the control signal sequence; The second clock signal is used to drive the reading and writing of the data to be processed, the first ciphertext data, and the second ciphertext data.

9. The hardware accelerator according to claim 1, characterized in that, The hardware accelerator also includes an interrupt control unit; The interrupt control unit is configured to generate an interrupt signal upon detecting a preset signal; the interrupt signal is used to indicate the processing result of the task processing flow corresponding to the preset signal. The preset signal is at least a level signal generated by one of the first encryption unit, the second encryption unit, the read / write unit, and the distribution unit.

10. A hardware security module, characterized in that, Includes the hardware accelerator and processor according to any one of claims 1-9, wherein the hardware security module is applied to the chip; The processor is configured to write a working mode configuration value into the mode configuration register of the hardware accelerator; The hardware accelerator is configured to retrieve a data stream to be processed from the chip's RAM based on the encrypted task type indicated by the operating mode configuration value. Execute the ciphertext task indicated by the ciphertext task type based on the data stream to be processed.

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