Free layer in magnetoresistive random access memory

Abstract

An embodiment of the invention provides a magnetoresistive random access memory (MRAM). The MRAM includes a reference layer; a tunnel barrier layer of magnesium oxide (MgO); and a free layer, wherein the free layer includes a first cobalt iron boron (CoFeB) layer on top of the tunnel barrier layer; the spacing layer is positioned on the top of the first CoFeB layer; the second CoFeB layer is positioned on the top of the spacing layer; and a cap layer of MgO on top of the second CoFeB layer. Further, the first CoFeB layer and the second CoFeB layer are substantially depleted of boron (B) to respectively include a first region adjacent to the tunnel barrier layer and the cap layer, respectively, and a second region adjacent to the spacer layer, where the first region of the first CoFeB layer and the second CoFeB layer includes crystalline ferrocobalt (CoFe), and the second region of the first CoFeB layer and the second CoFeB layer includes an amorphous CoFe alloy.

Description

Background Technology

[0001] This application relates to the manufacture of semiconductor integrated circuits. More specifically, it relates to a method for forming free layers in a magnetoresistive random access memory and the structure formed therefrom.

[0002] As is well known, semiconductor memory devices play a crucial role in managing and organizing digital information. In recent years, digital information has experienced explosive growth and is continuously transforming our society. Magnetoresistive random access memory (MRAM) is a type of non-volatile memory (NVM), and spin-transfer torque MRAM (STT-MRAM) is known as embedded NVM (eNVM), which can retain stored digital information even in the event of a power outage or accidental disconnection. Compared to other types of MRAM devices, using STT-MRAM enables higher density, lower power consumption, and reduced manufacturing costs for memory devices.

[0003] MRAM technology, including STT-MRAM, is based on magnetic tunnel junction (MTJ) stacks, which typically include a tunnel barrier layer placed or sandwiched between a reference layer and a free layer. Traditionally, the free layer is made of a cobalt-iron-boron alloy. The properties of cobalt-iron-boron alloys have a significant impact on the performance of MRAMs and are being investigated for further improvement.

[0004] STT-MRAM is an advanced eNVM device that relies on MTJ stacks to realize its functionality. Cobalt-iron-boron (CoFeB) alloys are typically used as the material for forming free layers within the MTJ stacks. It is known to the inventors that the properties of the CoFeB alloy and the formation process of the free layers using the CoFeB alloy have a significant impact on the functionality of the MTJ stack and the overall operation of the STT-MRAM. For example, when forming STT-MRAM (especially MTJ stacks), the free layers need to be deposited in an amorphous state on a crystalline tunnel barrier layer (typically magnesium oxide (MgO)). To maintain CoFeB in its amorphous state during and after deposition, CoFeB alloys are typically deposited from a target containing approximately 20 to 40 at.% boron (B).

[0005] A high boron content helps wet the MgO surface, resulting in better uniformity during the formation of the CoFeB free layer. On the other hand, the high boron content keeps CoFe in an amorphous state, thus reducing the magnetoresistance (TMR) of the resulting free layer, which is undesirable for the performance of the MTJ. Free layer structures with a refractory metal layer placed between the first and second CoFeB layers have been introduced to help absorb excess boron. The refractory metal layer is typically made thin enough not to cause magnetic decoupling between the first and second CoFeB layers, which could lead to malfunction of the MTJ device. However, a thin refractory metal layer is insufficient to absorb excess boron in the free layer. Summary of the Invention

[0006] Embodiments of the present invention provide a magnetoresistive random access memory (MRAM). The MRAM includes: a reference layer; a magnesium oxide (MgO) tunnel barrier layer; and a free layer, wherein the free layer includes: a first cobalt-iron-boron (CoFeB) layer on top of the tunnel barrier layer; a spacer layer on top of the first CoFeB layer; a second CoFeB layer on top of the spacer layer; and a capping layer of MgO on top of the second CoFeB layer. Furthermore, the first and second CoFeB layers are substantially depleted of boron (B) to include, respectively, a first region adjacent to the tunnel barrier layer and the capping layer, and a second region adjacent to the spacer layer, wherein the first region of the first and second CoFeB layers comprises crystalline cobalt-iron (CoFe), and the second region comprises an amorphous CoFe alloy. The localized crystallinity of the first region contributes to achieving high tunnel magnetoresistance (TMR), high perpendicular magnetic anisotropy (PMA), and high state retention compared to existing technologies. The localized amorphous state of the second region results in a smaller magnetic moment, thus enabling faster write times and improved device property distribution.

[0007] In one embodiment, the spacer layer comprises an alloy of a refractory metal and iron, wherein the refractory metal is zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re), or tungsten (W).

[0008] In another embodiment, the spacer layer comprises an iron concentration level ranging from about 20 atomic percent (at.%) to about 80 at.%.

[0009] In yet another embodiment, the first CoFeB layer and the second CoFeB layer comprise less than 5 at.% boron.

[0010] In one embodiment, a first region of the first CoFeB layer has a thickness between about 20% and about 40% of the thickness of the first CoFeB layer.

[0011] In another embodiment, the thickness of a first region of the first CoFeB layer is between about 0.2 nm and about 0.5 nm, and the thickness of a second region of the first CoFeB layer is between about 0.2 nm and about 0.7 nm. In another aspect of the invention, a magnetoresistive random access memory (MRAM) is provided, comprising: a reference layer; a tunnel barrier layer above the reference layer; and a free layer above the tunnel barrier layer, wherein the free layer comprises: a first cobalt-iron-boron (CoFeB) layer above the tunnel barrier layer; a spacer layer above the first CoFeB layer; a second CoFeB layer above the spacer layer; and a capping layer above the second CoFeB layer; wherein the spacer layer is an alloy of a refractory metal and iron, the iron having a concentration level ranging from about 20 at.% to about 80 at.%.

[0012] In another aspect of the invention, a magnetic tunnel junction (MTJ) stack is provided, comprising: a reference layer; a tunnel barrier layer above the reference layer; and a free layer above the tunnel barrier layer, wherein the free layer comprises: a first cobalt-iron-boron (CoFeB) layer; a spacer layer comprising an alloy of a refractory metal and iron; a second CoFeB layer; and a capping layer, wherein the refractory metal is zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re), or tungsten (W), and the spacer layer is sandwiched between the first CoFeB layer and the second CoFeB layer. Attached Figure Description

[0013] The invention will be more fully understood and appreciated in the following detailed description of embodiments of the invention in conjunction with the accompanying drawings, wherein:

[0014] Figure 1 This is an exemplary illustration of a cross-sectional view of a semiconductor structure according to an embodiment of the present invention;

[0015] Figure 2 This is an exemplary illustration of a cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

[0016] Figure 3 This is an exemplary illustration of a cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention; and

[0017] Figure 4-11 This is an exemplary illustration of cross-sectional views of a semiconductor structure at various stages of its manufacture according to several embodiments of the present invention.

[0018] It should be understood that, for simplicity and clarity, the elements shown in the accompanying drawings are not necessarily drawn to scale. Furthermore, where applicable, in various functional block diagrams, two connected devices and / or elements may not necessarily be shown as connected. In some other cases, the grouping of certain elements in a functional block diagram is for descriptive purposes only and does not necessarily imply that they are in a single physical entity or that they are embodied in a single physical entity. Detailed Implementation

[0019] In the following detailed description and accompanying drawings, it should be understood that the various layers, structures, and regions shown in the drawings are exemplary and schematic illustrations, and not drawn to scale. Furthermore, for ease of explanation, one or more types of layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in the given illustrations or drawings. This does not mean that any un-explicitly shown layers, structures, and regions have been omitted from actual semiconductor structures. Moreover, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, regarding semiconductor processing steps, it should be emphasized that the description provided herein is not intended to cover all processing steps required to form functional semiconductor integrated circuit devices. Instead, certain processing steps commonly used to form semiconductor devices (such as, for example, wet cleaning and annealing steps) are intentionally omitted herein for descriptive economic purposes.

[0020] It should be understood that the terms “about” or “substantially” used herein with respect to thickness, width, percentage, range, etc., mean close to or approximately, rather than precisely. For example, the terms “about” or “substantially” as used herein mean that there may be a small margin of error, such as, by way of example only, 1% or less of the stated amount. Similarly, the terms “on,” “above,” or “top” used herein to describe the positional relationship between two layers or structures are intended to be interpreted broadly and should not be construed as excluding the presence of one or more intermediate layers or structures.

[0021] Furthermore, although various reference numerals may be used across different figures, the same or similar reference numerals are used throughout the figures to denote the same or similar features, elements, or structures. Therefore, for the sake of economy of description, detailed descriptions of the same or similar features, elements, or structures may not be repeated for each figure. To avoid making the figures too crowded, the designations of the same or similar elements in some figures may also be omitted.

[0022] Embodiments of the present invention provide a free-layer structure that can be used in MTJ stacks to improve the functionality of the formed MTJ device. The free layer includes a multi-layered sandwich spacer disposed between a first cobalt-iron-boron (CoFeB) layer and a second CoFeB layer. The multi-layered sandwich spacer includes multiple non-magnetic spacers separated by and / or sandwiched between multiple iron interlayers. The multiple non-magnetic spacers (such as multiple refractory metal layers) can provide significant boron (B) absorption, while the multiple iron interlayers can magnetically couple the multiple non-magnetic spacers together and ultimately couple them to the first and second CoFeB layers. Simultaneously, the multiple iron interlayers can also attract, distribute, and / or absorb some boron. By using a free-layer structure with multi-layered sandwich spacers to absorb boron, embodiments of the present invention enable the use of CoFeB targets with very high boron content (up to 50 to 60 atomic percent (at.%)) during the free-layer deposition process. The high boron content in the CoFeB target produces better wetting conditions on the magnesium oxide (MgO) tunnel barrier layer, resulting in more uniform deposition of the CoFeB material.

[0023] Figure 1 This is an exemplary illustration of a cross-sectional view of a semiconductor structure according to an embodiment of the present invention. More specifically, an embodiment of the present invention provides an MRAM device including an MTJ stack 10. The MTJ stack 10 may include a reference layer 300, a tunnel barrier layer 401 on top of the reference layer 300, and a free layer 510 on top of the tunnel barrier layer 401. In one embodiment, the free layer 510 may include: a first CoFeB layer 511, a spacer layer 512 on top of the first CoFeB layer 511, a second CoFeB layer 513 on top of the spacer layer 512, and a capping layer 514 on top of the second CoFeB layer 513.

[0024] In one embodiment, spacer layer 512 may be a multilayer spacer, such as an alloy formed by alternating layers of non-magnetic metals (such as refractory metals) and magnetic metals (such as iron (Fe)). For example, spacer layer 512 may be formed of a set of refractory metal layers 5121 and a set of iron layers 5122, and the set of refractory metal layers 5121 and the set of iron layers 5122 may be alternately placed. Hereinafter, the term "set" may include one or more. In other words, the set of refractory metal layers 5121 may be separated by the set of iron layers 5122, or the set of iron layers 5122 may be separated by the set of refractory metal layers 5121. In one embodiment, the stack of alternating layers may include at least two layers of refractory metal and one layer of iron. For example, the refractory metal may be zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re), and / or tungsten (W).

[0025] During the formation of spacer layer 512, refractory metal layers 5121 can each be formed to have a thickness between about 0.05 nm and about 0.4 nm. This thickness range is important because it ensures that the spacer layer 512 thus formed has a sufficient amount of refractory metal to provide adequate boron absorption, without causing the iron layers 5122 placed above and below the refractory metal layer 5121 to become magnetically decoupled from each other due to the thickness of the refractory metal layer 5121. Further, for example, the iron layers 5122 can each be formed to have a thickness between about 0.3 nm and about 1.0 nm. This thickness range is also important because it ensures that the iron layers 5122 have sufficient magnetic force to couple with each other and with the first CoFeB layer 511 and the second CoFeB layer 513 below and above the spacer layer 512. The refractory metal layer 5121 and the iron layer 5122 can be combined together to form an alloy. The first CoFeB layer 511 and the second CoFeB layer 513 can essentially deplete boron due to the unique multilayer structure of the spacer layer 512, especially due to the multiple refractory metal layers 5121 that absorb boron.

[0026] The tunnel barrier layer 401 may be a magnesium oxide (MgO) layer, and the capping layer 514 may also be an MgO layer. The first CoFeB layer 511 may include a first region 5111 adjacent to the tunnel barrier layer 401. The first region 5111 of the first CoFeB layer 511 comprises highly crystalline cobalt iron (CoFe) by contacting the MgO of the tunnel barrier layer 401 and being located away from the spacer layer 512 relative to the second region 5112 of the first CoFeB layer 511. The highly crystalline first region 5111 of the first CoFeB layer 511 contributes to providing high tunnel magnetoresistance (TMR) to improve the performance of the MRAM device.

[0027] On the other hand, the capping layer 514 can also be an MgO layer. The second CoFeB layer 513 may include a first region 5131 adjacent to the capping layer 514. By contacting the MgO of the capping layer 514 and being located away from the spacer layer 512 relative to the second region 5132 of the second CoFeB layer 513, the first region 5131 of the second CoFeB layer 513 also includes highly crystalline CoFe. The highly crystalline first region 5131 of the second CoFeB layer 513 contributes to providing high vertical magnetic anisotropy (PMA) and high state retention.

[0028] Simultaneously, the first CoFeB layer 511 may include a second region 5112 adjacent to the spacer layer 512, and the second CoFeB layer 513 may include a second region 5132 also adjacent to the spacer layer 512. By being closer to the spacer layer 512 and particularly closer to a refractory metal (such as Nb) than the first regions 5111 and 5131, respectively, the second regions 5112 and 5132 are largely maintained in an amorphous state to include an amorphous CoFe alloy. The amorphous CoFe alloy helps improve the uniformity of the first CoFeB layer 511 and the second CoFeB layer 513 to achieve more uniform device performance.

[0029] In a non-limiting example, a first region 5111 of the first CoFeB layer 511 may have a thickness between approximately 20% and approximately 40% of the total thickness of the first CoFeB layer 511. For example, the first region 5111 may have a thickness between approximately 0.2 nm and approximately 0.5 nm, while the second region 5112 may have a thickness between approximately 0.2 nm and approximately 0.7 nm. Similarly, a first region 5131 of the second CoFeB layer 513 may have a thickness between approximately 20% and approximately 40% of the total thickness of the second CoFeB layer 513. For example, the first region 5131 may have a thickness between approximately 0.2 nm and approximately 0.5 nm, while the second region 5132 may have a thickness between approximately 0.2 nm and approximately 0.7 nm.

[0030] like Figure 1 As shown, the spacer layer 512 can be formed starting from a refractory metal layer 5121 directly above the first CoFeB layer 511 and ending with another refractory metal layer 5121 directly below the second CoFeB layer 513. In this case, the spacer layer 512 thus formed can have an overall iron content in the range of about 20 at.% to about 80 at.%. However, embodiments of the invention are not limited in this respect. The spacer layer 512 can be arranged with different refractory metal layers (i.e., non-magnetic layers) and iron layers (i.e., magnetic layers), as described in more detail below.

[0031] Figure 2 This is an exemplary illustration of a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. More specifically, embodiments of the present invention provide an MRAM device including an MTJ stack 20. Figure 1Similar to the MTJ stack 10 shown, the MTJ stack 20 may include a reference layer 300, a tunnel barrier layer 401 on top of the reference layer 300, and a free layer 520 on top of the tunnel barrier layer 401. In one embodiment, the free layer 520 may include a first CoFeB layer 521, a spacer layer 522 on top of the first CoFeB layer 521, a second CoFeB layer 523 on top of the spacer layer 522, and a capping layer 524 on top of the second CoFeB layer 523.

[0032] For example, spacer layer 522 can be formed by stacking alternating layers comprising a set of refractory metal layers 5221 of non-magnetic metal and a set of iron layers 5222 of magnetic metal. However, embodiments of the invention are not limited in this respect. In one embodiment, spacer layer 522 can be formed by sputtering from an alloy target containing refractory metal (such as Nb) and magnetic metal (such as Fe), rather than forming a multilayer structure of refractory metal layers and magnetic metal layers.

[0033] and Figure 1 Unlike the spacer layer 512, the spacer layer 522 can begin with an iron layer 5222 directly on top of the first CoFeB layer 521 and end with another iron layer 5222 directly below the second CoFeB layer 523. In this case, the resulting spacer layer 522 can have an overall iron content ranging from about 20 at.% to about 80 at.%. Starting with an iron layer 5222 helps prevent refractory metals (such as niobium (Nb)) forming the refractory metal layer 5221 from migrating to the MgO layer at the interface between the first CoFeB layer 521 and the tunnel barrier layer 401. Such migration could occur if heavy iron atoms were absent from the iron layer 5222, since the first CoFeB layer 521 is typically very thin, on the order of 1 nm. Since niobium atoms do not carry spin polarization, preventing niobium atoms from migrating down to the interface with the MgO layer helps prevent a potential decrease in overall TMR. On the other hand, controlling the amount of iron is also important, as excessive iron can lead to a decrease in PMA.

[0034] The first CoFeB layer 521 and the second CoFeB layer 523 are essentially depleted of boron due to the unique multilayer structure of the spacer layer 522, which includes a sufficient amount of niobium atoms to absorb boron. The first CoFeB layer 521 may comprise a first region 5211 of predominantly highly crystalline CoFe and a second region 5212 of an amorphous CoFe alloy. Similarly, the second CoFeB layer 523 may comprise a first region 5231 of predominantly highly crystalline CoFe and a second region 5232 of an amorphous CoFe alloy. The local crystallinity of the highly crystalline CoFe near MgO, and the amorphous CoFe alloy in the remainder of the first CoFeB layer 521 and the second CoFeB layer 523, contribute to the structure of the free layer 520, which, compared to MRAMs using conventional free layers, contributes to higher TMR, higher PMA, and improved state retention, while maintaining low write current when used to fabricate MRAMs.

[0035] Figure 3 This is an exemplary illustration of a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. More specifically, embodiments of the present invention provide an MRAM device including an MTJ stack 30. Figure 1 Similar to the MTJ stack 10 shown, the MTJ stack 30 may include a reference layer 300, a tunnel barrier layer 401 on top of the reference layer 300, and a free layer 530 on top of the tunnel barrier layer 401. In one embodiment, the free layer 530 may include a first CoFeB layer 531, a spacer layer 532 on top of the first CoFeB layer 531, a second CoFeB layer 533 on top of the spacer layer 532, and a capping layer 534 on top of the second CoFeB layer 533.

[0036] Spacer layer 532 can be a multilayer spacer and can be formed by stacking alternating layers comprising a set of refractory metal layers 5321 of nonmagnetic metal and a set of iron layers 5322 of magnetic metal. In this case, the spacer layer 522 thus formed can have a total iron content ranging from about 20 at.% to about 80 at.%. Figure 1 Spacer layer 512 and Figure 2 Unlike the spacer layer 522, the spacer layer 532 can start from the iron layer 5322 (or refractory metal layer) directly on top of the first CoFeB layer 531 and end with the refractory metal layer 5321 (or iron layer) directly below the second CoFeB layer 533.

[0037] The first CoFeB layer 531 may comprise a first region 5311 of predominantly highly crystalline CoFe and a second region 5312 of an amorphous CoFe alloy. Similarly, the second CoFeB layer 533 may comprise a first region 5331 of predominantly highly crystalline CoFe and a second region 5332 of an amorphous CoFe alloy. Due to the unique multilayer structure of the spacer layer 532, both the first CoFeB layer 531 and the second CoFeB layer 533 are substantially depleted of boron. Unlike conventional spacer layers, the spacer layer 532 comprises a sufficient amount of niobium atoms that absorb boron.

[0038] Figure 4-11 This is an exemplary illustration of cross-sectional views of a semiconductor structure at various stages of its manufacture according to several embodiments of the present invention. More specifically, embodiments of the invention provide for receiving or providing a semiconductor substrate 101 (such as a silicon (Si) substrate) and as... Figure 4 As shown, a diffusion barrier layer 201 is formed on top of a semiconductor substrate 101 to form an MTJ stack 40. The diffusion barrier layer 201 may be an amorphous tantalum (Ta) and / or tantalum nitride (TaN) layer. Subsequently, as... Figure 5 As shown, the CoFeB layer 202 can be deposited in an amorphous state onto the diffusion barrier layer 201 of the amorphous Ta / TaN layer.

[0039] Embodiments of the present invention also provide, such as Figure 6 As shown, a seed layer 203 (such as a ruthenium (Ru) layer and / or a platinum (Pt) layer) is formed on top of an amorphous CoFeB layer 202, such that the seed layer 203 remains in an amorphous state; a reference layer 300 is formed on top of the seed layer 203; and a tunnel barrier layer 401 is formed on top of the reference layer 300.

[0040] In one embodiment, the reference layer 300 may have a multilayer structure. For example, the reference layer 300 may include a first stack 301 of alternating layers of cobalt and platinum; a second stack 302 of alternating layers of cobalt and iridium on top of the first stack of alternating layers 301; a tungsten (W) layer 303 on top of the second stack of alternating layers 302; and another amorphous CoFeB layer 304 on top of the tungsten layer 303.

[0041] Embodiments of the present invention may also provide a free layer structure formed on top of the tunnel barrier layer 401. To this end, embodiments of the present invention provide, as follows: Figure 7 As shown, a first CoFeB layer 501 is formed on top of the tunnel barrier layer 401 in an amorphous state; as Figure 8 As shown, a spacer layer 502 is formed on top of the first CoFeB layer 501; and as shown Figure 9As shown, a second CoFeB layer 503 is formed on top of the spacer layer 502, and a capping layer 504 is formed on top of the second CoFeB layer 503. The spacer layer 502 may have a similar shape to... Figure 1 , Figure 2 and Figure 3 The structures of any one of spacers 512, 522, and 532 shown in the figures are described in detail above with respect to their respective figures. Cap layer 504 may be an MgO layer that helps increase the PMA of free layer 500, thereby reducing the write voltage of the MRAM device.

[0042] After forming the free layer according to an embodiment of the invention, another CoFeB layer 601 can be deposited on top of the free layer 500 in an amorphous state, and a capping layer 602 can be deposited on top of the CoFeB layer 601, both of which can further help or improve the PMA of the free layer 500.

[0043] According to one embodiment of the invention, the MTJ stack 40 can undergo one or more annealing processes in a temperature range from about 300°C to about 435°C, typically between about 380°C and 420°C. The annealing process can be combined with thermal cycling of other CMOS devices, with a total duration ranging from about tens of minutes to several hours. During the annealing process, boron atoms, particularly those in the first CoFeB layer 501 and the second CoFeB layer 503, can be attracted and / or absorbed by refractory metal layers (such as niobium metal layers) and iron layers in the spacer layer 502, some of which may diffuse into the nearby tunnel barrier layer 401 and the MgO layer of the capping layer 504, resulting in a first CoFeB layer 501 and the second CoFeB layer 503 that are substantially depleted of boron. For example, the first CoFeB layer 501 and the second CoFeB layer 503 may have a boron content or concentration level of less than 5 at.%.

[0044] Meanwhile, the first regions 5011 and 5031 in contact with MgO may include crystalline CoFe, resulting in higher TMR and PMA in the free layer 500. On the other hand, the second regions 5012 and 5032 near the niobium in the spacer layer 502 may include amorphous CoFe alloys, which helps improve the wettability and overall uniformity of the MRAM device.

[0045] It should be understood that the exemplary methods discussed herein can be readily combined with other semiconductor processing flows, semiconductor devices, and integrated circuits having various analog and digital or mixed-signal circuits. Specifically, the integrated circuit die can be fabricated using various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. The integrated circuits according to the invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones), solid-state storage devices, functional circuits, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. In view of the teachings of the invention provided herein, those skilled in the art will be able to conceive of other embodiments and applications of the technology of the invention.

[0046] Therefore, at least a portion of one or more semiconductor structures described herein can be implemented in an integrated circuit. The resulting integrated circuit chip can be distributed by the manufacturer in the form of a raw wafer (i.e., as a single wafer with multiple unpackaged chips), a bare die, or a package. In the latter case, the chip can be mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other advanced carrier) or in a multi-chip package (such as a ceramic carrier with surface interconnects and / or embedded interconnects). In any case, the chip can be subsequently integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product (such as a motherboard) or a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0047] The above description is presented for the purpose of illustrating various embodiments of the invention, and is not intended to be exhaustive, nor is the invention limited to the disclosed embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements relative to the technology on the market, and to enable those skilled in the art to understand the embodiments disclosed herein. Many modifications, substitutions, alterations, and equivalents will now occur to those skilled in the art. Such alterations, modifications, and / or alternative embodiments can be made without departing from the scope of the invention, and all of these are considered to be within the scope of the invention. Therefore, it should be understood that the appended claims are intended to cover all such modifications and alterations falling within the scope of the invention.

Claims

1. A magnetoresistive random access memory (MRAM), comprising: Reference layer; The tunnel barrier layer of magnesium oxide (MgO); and Free layer, wherein the free layer comprises: The first cobalt-iron-boron (CoFeB) layer is located on top of the tunnel barrier layer; A spacer layer located on top of the first CoFeB layer; The second CoFeB layer located on top of the spacer layer; and The MgO capping layer located on top of the second CoFeB layer, The first CoFeB layer and the second CoFeB layer are substantially depleted of boron (B) to include a first region adjacent to the tunnel barrier layer and the capping layer, and a second region adjacent to the spacer layer, respectively. The first region of the first CoFeB layer and the second CoFeB layer comprises crystalline cobalt iron (CoFe), and the second region of the first CoFeB layer and the second CoFeB layer comprises an amorphous CoFe alloy.

2. The MRAM according to claim 1, wherein the spacer layer comprises an alloy of a refractory metal and iron, wherein the refractory metal is zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re) or tungsten (W).

3. The MRAM of claim 1, wherein the spacer layer comprises an iron concentration level ranging from about 20 at.% to about 80 at.%.

4. The MRAM of claim 1, wherein the first CoFeB layer and the second CoFeB layer comprise less than 5 at.% boron.

5. The MRAM of claim 1, wherein the first region of the first CoFeB layer has a thickness between about 20% and about 40% of the thickness of the first CoFeB layer.

6. The MRAM of claim 1, wherein the thickness of the first region of the first CoFeB layer is between about 0.2 nm and about 0.5 nm, and the thickness of the second region of the first CoFeB layer is between about 0.2 nm and about 0.7 nm.

7. A magnetoresistive random access memory (MRAM), comprising: Reference layer; The tunnel barrier layer located above the reference layer; and A free layer located above the tunnel barrier layer, wherein the free layer comprises: The first cobalt-iron-boron (CoFeB) layer is located on top of the tunnel barrier layer; A spacer layer located on top of the first CoFeB layer; The second CoFeB layer located on top of the spacer layer; and A capping layer located on top of the second CoFeB layer; The spacer layer is an alloy of a refractory metal and iron, wherein the iron has a concentration level ranging from about 20 at.% to about 80 at.%.

8. The MRAM according to claim 7, wherein the refractory metal is selected from the group consisting of zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re) and tungsten (W).

9. The MRAM of claim 7, wherein the tunnel barrier layer is a layer of magnesium oxide (MgO), and the first CoFeB layer is located directly on top of the tunnel barrier layer, the first CoFeB layer being substantially depleted of boron (B) to include a first region adjacent to the tunnel barrier layer and a second region adjacent to the spacer layer; wherein the first region comprises crystalline cobalt iron (CoFe), and the second region comprises an amorphous CoFe alloy.

10. The MRAM of claim 7, wherein the capping layer is a layer of magnesium oxide (MgO) and is located directly on top of the second CoFeB layer, the second CoFeB layer being substantially depleted of boron (B) to include a first region adjacent to the capping layer and a second region adjacent to the spacer layer; wherein the first region comprises crystalline cobalt iron (CoFe) and the second region comprises an amorphous CoFe alloy.

11. The MRAM of claim 7, wherein the first region of the first CoFeB layer has a thickness between about 20% and about 40% of the thickness of the first CoFeB layer.

12. The MRAM of claim 7, wherein the thickness of the first region of the first CoFeB layer is between about 0.2 nm and about 0.5 nm, and the thickness of the second region of the first CoFeB layer is between about 0.2 nm and about 0.7 nm.

13. The MRAM of claim 7, wherein the spacer layer is formed by a stack of alternating layers of the refractory metal and iron, each of the alternating layers having a thickness between about 0.3 nm and about 1.0 nm.

14. The MRAM of claim 7, wherein the spacer layer is formed by a sputtering deposition process using an alloy target comprising the refractory metal and iron, and the iron having a concentration level ranging from about 20 at.% to about 80 at.%.

15. A magnetic tunnel junction (MTJ) stack, comprising: Reference layer; The tunnel barrier layer located above the reference layer; and The free layer located above the tunnel barrier layer, The free layer comprises a first cobalt-iron-boron (CoFeB) layer; a spacer layer comprising an alloy of a refractory metal and iron; a second CoFeB layer; and a capping layer, wherein the refractory metal is zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), rhenium (Re), or tungsten (W), and the spacer layer is sandwiched between the first CoFeB layer and the second CoFeB layer.

16. The MTJ stack of claim 15, wherein the tunnel barrier layer is a layer of magnesium oxide (MgO), and the first CoFeB layer is located directly on top of the tunnel barrier layer to include a first region adjacent to the tunnel barrier layer and a second region adjacent to the spacer layer; wherein the first region is substantially depleted of boron (B) to include crystalline cobalt iron (CoFe), and the second region is substantially depleted of boron to include an amorphous CoFe alloy.

17. The MTJ stack of claim 16, wherein both the first region and the second region of the first CoFeB layer comprise less than 5 at.% boron.

18. The MTJ stack of claim 16, wherein the thickness of the first region of the first CoFeB layer is between about 0.2 nm and about 0.5 nm, and the thickness of the second region of the first CoFeB layer is between about 0.2 nm and about 0.7 nm.

19. The MTJ stack of claim 16, wherein the spacer layer is formed by stacking alternating layers of the refractory metal and iron, each of the alternating layers having a thickness between about 0.3 nm and about 1.0 nm.

20. The MTJ stack of claim 15, wherein the spacer layer comprises an iron concentration level ranging from about 20 at.% to about 80 at.%.

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