Multilayer deep trench capacitor

Abstract

The present invention relates to an integrated capacitor on a substrate, the integrated capacitor comprising: at least one trench within the substrate; a multi-layer stack comprising at least three electrically conductive layers deposited on the substrate and separated by electrically isolating layers, and wherein the multi-layer stack comprises a first set of odd-numbered layers and a second set of even-numbered layers, and wherein the multi-layer stack is arranged in substantially vertical and substantially horizontal directions along a plurality of surfaces of the substrate; the first terminal is in contact with the first group of odd-numbered layers, and the second terminal is in contact with the second group of even-numbered layers. Also disclosed are a method of manufacturing an integrated capacitor and a method for manufacturing a via connecting at least two layers included in a multilayer stack of at least three layers disposed on a substrate, and various embodiments of an integrated capacitor.

Description

Technical Field

[0001] This disclosure relates to an integrated capacitor comprising a multilayer stack arranged such that the capacitor includes a deep trench. Background Technology

[0002] Integrated capacitors are common passive electronic components in microelectronic circuits. A capacitor stores electrical energy by accumulating charge on two parallel plates separated by an insulating material called a dielectric. In microelectronic circuits, integrated capacitors are used for a variety of purposes, such as filtering unwanted noise, providing power supply decoupling, and tuning circuit resonant frequencies. Integrated capacitors can be manufactured using various materials and structures, including metal-oxide-semiconductor (MOS) capacitors, metal-insulator-metal (MiM) capacitors, and film capacitors.

[0003] MOS capacitors are formed by creating a sandwich structure of metal electrodes, a dielectric layer, and a semiconductor substrate. The capacitance of a MOS capacitor can be controlled by adjusting the thickness and dielectric constant of the dielectric layer and the surface area of ​​the metal electrodes. On the other hand, MiM capacitors consist of two metal electrodes separated by a dielectric material. The capacitance of a MiM capacitor can be adjusted by changing the thickness and dielectric constant of the dielectric layer and the surface area of ​​the metal electrodes. Thin-film capacitors are made by depositing thin layers of metal and dielectric material on a substrate. The capacitance of a thin-film capacitor can be adjusted by changing the thickness and dielectric constant of the dielectric layer and the surface area of ​​the metal electrodes.

[0004] Each type of capacitor has its own advantages and disadvantages. While MiM capacitors exhibit one of the highest capacitance densities on the market, their relatively low breakdown voltage makes them unsuitable for high-voltage applications. Furthermore, manufacturing such capacitors requires a relatively large number of masks. A mask is a patterned layer used to selectively define areas on a substrate where various materials or structures will be deposited or removed during the manufacturing process. Masks are typically made of thin materials such as glass or chromium and contain openings or "windows" at specific locations that allow light or other forms of energy to pass through and selectively pattern the underlying material. The pattern on the mask is transferred to the substrate using a process called photolithography. Masks are generally expensive, so limiting the number of masks during the manufacturing process is crucial for cost reduction. Moreover, manufacturing time increases dramatically when using multiple masks, as each mask requires proper alignment and several additional steps that must be performed sequentially.

[0005] Deep trench capacitors are another type of capacitor in which layers are arranged within trenches, which are preferably etched into a semiconductor substrate. They offer very high capacitance density by maximizing the area through the 3D provided by the semiconductor substrate. However, deep trench capacitors suffer from layer count limitations, typically limited to two layers, and require different masks to create the connection points during fabrication. They also have a breakdown voltage issue, which is limited by the thickness of the dielectric separating the metal layers, which is often quite thin. Summary of the Invention

[0006] Therefore, there is a need for an integrated capacitor with more than two layers, where capacitance density is maximized and a limited number of masks are used during manufacturing or production to create connection points or contacts. Furthermore, the breakdown voltage can be advantageously high enough to sustain high-voltage applications.

[0007] As described herein, this can be achieved by an integrated capacitor on a substrate, the integrated capacitor comprising: at least one trench within the substrate; a multilayer stack comprising at least three conductive layers deposited on the substrate and separated by an electrical isolation layer, wherein the multilayer stack comprises a first set of odd-numbered layers and a second set of even-numbered layers, and wherein the multilayer stack is arranged along a plurality of surfaces of the substrate in substantially vertical and substantially horizontal directions; at least a first terminal and a second terminal, wherein the first terminal contacts the first set of odd-numbered layers and the second terminal contacts the second set of even-numbered layers.

[0008] The integrated capacitor comprises at least three conductive layers separated by an electrically insulating layer, thereby giving the capacitor a high capacitance value. Advantageously, the integrated capacitor may comprise at least five, at least ten, or at least twenty layers. The more layers, the greater the capacitance that can be achieved within the same area.

[0009] By incorporating at least one trench, this integrated capacitor provides a larger area for depositing multiple stacks, thereby increasing the capacitance and maximizing capacitance density. Capacitance density is a measure of the amount of charge a capacitor can store per unit area. The higher this value, the greater the capacitance per unit area.

[0010] This multilayer stack is deposited not only on top of the substrate but also within at least one trench, such that a conductive layer and an electrical isolation layer are deposited on the sidewalls and bottom of at least one trench disposed within the substrate. This structure allows for a relatively simple deposition process and allows for a relatively large thickness of the electrical isolation layer. This can improve the breakdown voltage of the integrated capacitor disclosed herein.

[0011] On the other hand, the present invention discloses a method for manufacturing an integrated capacitor on a substrate. The method includes the following steps: creating at least one trench on the substrate; arranging a multilayer stack on the substrate, the multilayer stack comprising at least three conductive layers separated by an electrical isolation layer, wherein the multilayer stack comprises a first set of odd-numbered layers and a second set of even-numbered layers, and wherein the multilayer stack is arranged along a plurality of surfaces of the substrate in substantially vertical and substantially horizontal directions; creating at least two trenches in the multilayer stack down to the lowest layer of the multilayer stack, thereby defining at least a first terminal trench and a second terminal trench; removing a majority of the first set of odd-numbered layers within the first terminal trench; removing a majority of the second set of even-numbered layers within the second terminal trench; arranging an auxiliary conductive layer on the multilayer stack, wherein the auxiliary conductive layer is further arranged within at least the first terminal trench and the second terminal trench and contacts the first set of odd-numbered layers and the second set of even-numbered layers; removing a majority of the auxiliary conductive layer such that the first terminal is electrically isolated from the second terminal.

[0012] By creating at least two trenches down to the lowest layer of the multilayer stack, this step can be performed using only one mask, wherein the same mask can be reused to perform subsequent steps of the method, such as: removing most of the first set of odd-numbered layers in the first terminal trench; removing most of the second set of even-numbered layers in the second terminal trench; and disposing an auxiliary conductive layer on the multilayer stack, wherein the auxiliary conductive layer is further disposed in at least the first and second terminal trenches and contacts the first set of odd-numbered layers and the second set of even-numbered layers.

[0013] Most of the first set of odd-numbered layers in the first terminal trench can be removed by giving the first set of odd-numbered layers different characteristics from the second set of even-numbered layers. Similarly, most of the second set of even-numbered layers in the second terminal trench can be removed by giving the second set of even-numbered layers different characteristics from the first set of odd-numbered layers. Advantageously, selective etching can be performed using a suitable etchant based on the characteristics to be etched, the characteristics of the first set of odd-numbered layers, or the characteristics of the second set of even-numbered layers.

[0014] Then, an auxiliary conductive layer can be deposited on the multilayer stack, wherein the auxiliary conductive layer is in contact with both the first set of odd-numbered layers in the first terminal trench and the second set of even-numbered layers in the second terminal trench. By removing most of the auxiliary conductive layer to electrically isolate the first terminal trench from the second terminal trench, an integrated capacitor with high capacitance density can be realized.

[0015] In one aspect, a method for manufacturing a via connecting at least two layers, the at least two layers comprising a multilayer stack of at least three layers disposed on a substrate, wherein the method comprises the steps of: disposing of a multilayer stack on the substrate, the multilayer stack comprising at least three conductive layers separated by an electrically insulating layer, and wherein the multilayer stack comprises a first set of odd-numbered layers and a second set of even-numbered layers; creating at least one trench in the multilayer stack down to the lowest layer of the multilayer stack; removing a majority of the first set of odd-numbered layers or the second set of even-numbered layers through the at least one trench; and disposing of an auxiliary conductive layer on the multilayer stack, wherein the auxiliary conductive layer is further disposed within the at least one trench and contacts the first set of odd-numbered layers or the second set of even-numbered layers.

[0016] Electrical isolation between the first set of odd-numbered layers and the second set of even-numbered layers can be achieved by selectively removing a large portion of either the first set of odd-numbered layers or the second set of even-numbered layers. Advantageously, only one mask is needed to fabricate vias connecting at least two layers included in a multilayer stack. This reduces fabrication time and the number of masks required to process the connection between at least two layers.

[0017] In another aspect, an integrated capacitor device includes the integrated capacitor disclosed herein and at least two external terminals, wherein the at least two external terminals are connected to at least a first terminal and a second terminal of the integrated capacitor disclosed herein.

[0018] In different aspects, an integrated capacitor device includes at least one integrated capacitor disclosed herein; one or more through-holes, such as through-substrate through-holes, arranged in the substrate and connected to at least a first terminal and a second terminal of at least one integrated capacitor disclosed herein, wherein the through-substrate through-hole provides a plurality of terminals on both sides of the substrate.

[0019] In another aspect, an integrated circuit assembly includes at least one integrated circuit; at least one integrated capacitor disclosed herein; wherein at least one integrated circuit and at least one integrated capacitor are integrated in a substrate and electrically connected, and wherein the integrated circuit assembly further includes at least two external terminals.

[0020] In one aspect, an integrated circuit assembly includes at least one integrated circuit; at least one integrated capacitor disclosed herein; one or more through-holes, such as through-substrate vias, arranged in the substrate and connected to at least a first terminal and a second terminal of at least one integrated capacitor disclosed herein and / or connected to at least one integrated circuit, wherein the through-substrate vias provide a plurality of external terminals on both sides of the substrate. Attached Figure Description

[0021] The following embodiments and examples will be described in more detail with reference to the accompanying drawings: Figure 1A-Figure 1BAn embodiment of an integrated capacitor is shown in the schematic diagram; Figures 2A-2B An embodiment of an integrated capacitor with two terminals is shown in 3D view, wherein the integrated capacitor includes a plurality of interlayer vias, and a schematic top view and a cross section A-A' of the embodiment of the integrated capacitor in 3D view are shown. Figure 3 An embodiment illustrating the steps of the method disclosed in this invention for a thin conductive layer is shown; Figure 4 An embodiment illustrating the steps of the method disclosed in this invention for thick conductive layers is shown; Figure 5 The embodiments of two scenarios are illustrated, wherein the first scenario shows an embodiment in which one of the terminals has an ohmic contact with the substrate, and the second scenario shows an embodiment in which the two terminals are isolated from the substrate. Figures 6A-6B An embodiment of an integrated capacitor with external terminals is shown, wherein the external terminals are arranged on one side and both sides of a substrate having through-holes in the substrate. Figures 7A-7C An embodiment of a schematic diagram showing an integrated capacitor integrated with an integrated circuit in a substrate is shown; Figures 8A-8B An example of a schematic diagram illustrating a possible application of integrated capacitors in stacked electronic components is shown; Figures 9A-9I An example of a schematic diagram illustrating a possible application of integrated capacitors in stacked electronic components is shown; Figures 10A-10B An embodiment of an integrated capacitor is shown as a cross-section viewed from a side view and a top view, wherein the embodiment of the integrated capacitor includes a through-hole in the substrate and a redistribution layer on both sides of the substrate. Figure 11 A schematic embodiment of an integrated capacitor is shown, which includes multiple trenches and through-substrate vias connecting redistribution layers disposed on both sides of a substrate. Detailed Implementation

[0022] In the context of this patent application, it should be noted that the use of the terms "made of," "may be made of," "made with," and "available for making" to describe the composition of a component or material is not intended to be limiting. Rather, these phrases are used to indicate examples of materials or components suitable for use in this invention. It should be understood that the use of "made of," "may be made of," "made with," and "available for making" covers any equivalent material or component that performs the same or similar function without departing from the scope of this invention. Therefore, the phrases "made of," "may be made of," "made with," and "available for making" should be interpreted in a manner consistent with the concept of "comprising," indicating that the invention may include additional elements or materials in addition to those expressly mentioned.

[0023] The present invention discloses an integrated capacitor on a substrate, the integrated capacitor including at least one trench; a multilayer stack including at least three conductive layers separated by an electrical isolation layer; and wherein the multilayer stack includes a first set of odd-numbered layers and a second set of even-numbered layers; at least a first terminal and a second terminal, wherein the first terminal may contact the first set of odd-numbered layers and the second terminal may contact the second set of even-numbered layers.

[0024] The substrate can be a semiconductor substrate, a glass substrate, a sapphire substrate, or a polyamide substrate. Semiconductor substrates can be made of semiconductor materials such as silicon, germanium, or gallium arsenide, which may possess specific electrical properties that allow them to be used to construct electronic devices. The properties of the substrate, such as its conductivity, resistivity, and band gap, are crucial to the performance of the electronic components built on top of it. Other substrates, such as glass substrates, sapphire substrates, or polyamide substrates, can also be used.

[0025] The multilayer stack may include at least four layers, preferably at least five layers, more preferably at least ten layers, even more preferably at least fifteen layers, and most preferably at least twenty conductive layers. Adding more layers to the multilayer stack increases the capacitance of the integrated capacitor. Advantageously, each additional layer can add more surface area to the capacitor, thereby increasing the amount of charge that can be stored. Preferably, adding layers can increase the rated voltage of the integrated capacitor, such as its breakdown voltage. The voltage can be distributed among multiple layers, thereby reducing the stress on each individual layer. Adding multiple layers to the multilayer stack can also help reduce the area of ​​the integrated capacitor. For the same area, having more layers can provide higher capacitance, thereby maximizing capacitance density.

[0026] In a preferred embodiment, the integrated capacitor includes at least two trenches within the substrate, preferably at least three trenches, and more preferably at least four trenches. By adding more trenches to the substrate, the surface area on which the multilayer stack is deposited can be expanded. Advantageously, each trench provides additional dimensions to the multilayer stack, for example, maximizing the area of ​​the multilayer stack within the substrate.

[0027] Figure 1A-Figure 1B An embodiment of a schematic diagram of an integrated capacitor is shown. Figure 1A An embodiment of an integrated capacitor 100 is shown in schematic diagram. The integrated capacitor 100 includes three trenches 107 in a substrate 106. A multilayer stack is disposed on the substrate and further within the three trenches. The multilayer stack includes 12 layers, wherein a first group of odd-numbered layers 103 includes 6 layers and a second group of even-numbered layers 10 includes 6 layers. The multilayer stack includes dielectric layers 105 separating the layers. The first group of odd-numbered layers is connected to a first terminal 101, while the second group of even-numbered layers is connected to a second terminal 102. The first and second terminals are through-holes filled with metal. Contacts are also deposited on top of the through-holes to allow electrical connection from the through-holes. Figure 1A As shown, compared to an integrated capacitor without trenches in the substrate, three trenches allow for an increase in the length of the multilayer stack. This advantageously enables higher capacitance to be achieved on the same surface or area. Figure 1B An embodiment of an integrated capacitor 100 is shown in schematic diagram. The integrated capacitor 100 includes a trench 107 in a substrate 106. A multilayer stack is disposed on the substrate and further within the trench. The multilayer stack includes 12 layers, wherein a first set of odd-numbered layers 103 includes 6 layers and a second set of even-numbered layers 104 includes 6 layers. The multilayer stack includes a dielectric layer 105, which serves as a separator. The first set of odd-numbered layers is connected to a first terminal 101, while the second set of even-numbered layers is connected to a second terminal 102. The first and second terminals are through-holes filled with metal. Contacts are also deposited on top of the through-holes to allow electrical connection from the through-holes.

[0028] An integrated capacitor may include at least three terminals, preferably at least five terminals, more preferably at least ten terminals, and even more preferably at least twenty terminals. Advantageously, more terminals can reduce the equivalent series resistance (ESR) of the integrated capacitor. Preferably, terminals connected to the first set of odd-numbered layers can be connected together, and terminals connected to the second set of even-numbered layers can be connected together. By connecting terminals to the same set of layers, preferably using low-ohmic electrical connections, the equivalent series resistance of the integrated capacitor can be significantly reduced.

[0029] Figure 2A An embodiment of an integrated capacitor with two terminals is shown in 3D view, but wherein the integrated capacitor includes multiple interlayer vias. The interlayer vias are arranged to reduce or minimize ESR. The interlayer vias connected to a first set of odd-numbered layers are electrically connected together and further connected to terminal 1; and the second set of even-numbered layers are electrically connected together and further connected to terminal 2. The integrated capacitor includes more than 50 deep trench structures arranged in the substrate. Figure 2B It shows Figure 2AThe diagram shows a schematic top view of an embodiment of the integrated capacitor in 3D view, and a cross-section A-A' of the top view. This top view illustrates the electrical connections between interlayer vias, further to terminal 1 or terminal 2. Via 1 is a different via electrically connecting a first set of odd-numbered layers in the multilayer stack, and via 2 is a different via electrically connecting a second set of even-numbered layers in the multilayer stack. This is an example, and via 1 can connect to the second set of even-numbered layers, while via 2 can connect to the first set of odd-numbered layers. Preferably, via 1 connects to one set of layers, i.e., either odd or even layers, while via 2 connects to another set of layers. This cross-section shows a multilayer stack arranged horizontally and vertically on a substrate. This cross-section shows a multilayer stack comprising four layers, but those skilled in the art will understand that more layers can be easily arranged using trenches with greater width.

[0030] In one embodiment, at least one trench has an opening width ranging from 0.1 µm to 10 µm. In a preferred embodiment, at least one trench has a depth ranging from 10 µm to 725 µm. Preferably, the maximum depth of at least one trench is substantially equal to the substrate thickness.

[0031] At least the first and second terminals can be through-holes. These through-holes may be filled with conductive metal or may not be filled. Unfilled through-holes are those that ensure, for example, connectivity between different layers of conductive metal, even when not filled. Preferably, the integrated capacitor may have at least three terminals, more preferably at least five terminals, and even more preferably at least ten terminals. Having more terminals reduces the series resistance of the integrated capacitor. This is advantageous for applications where minimizing series resistance in the integrated capacitor is crucial. For example, high ESR increases power dissipation, reduces efficiency, and leads to higher operating temperatures, which can ultimately cause premature capacitor failure.

[0032] To minimize the ESR of the integrated capacitor, the terminals connecting the first or second group can be connected together. The terminals can also be connected in groups, where at least the first group of terminals connected to the first group can be connected together, and the other group of terminals connected to the first group can be connected together. Similarly, for the second group, the terminals can be connected in groups, where at least the first group of terminals connected to the second group can be connected together, and the other group of terminals connected to the second group can be connected together.

[0033] The via may have a redistribution layer. The via can be included in the redistribution layer. The redistribution layer can be used to connect the via to external devices, such as one or more integrated circuits, one or more passive devices, and / or one or more external terminals. External terminals can be terminals used to connect the substrate to external printed circuit boards or other substrates. External terminals can be bonded by wire bonding or connected by flip-chip technology.

[0034] The redistribution layer can be disposed on the upper surface of the via, and the upper surface of the via can be disposed at substantially the same height as the upper surface of the multilayer stack.

[0035] In one embodiment, the diameter of the through hole is in the range of 1 to 50 µm.

[0036] In a preferred embodiment, the thickness of the redistribution layer is in the range of 1 to 30 µm.

[0037] Through-silicon vias (TSVs) or through-substrate vias. A through-substrate via is a vertical interconnect structure that passes through a substrate or semiconductor substrate to provide electrical connections between the front and back sides of a die, substrate, or semiconductor substrate.

[0038] The through-silicon vias (TSVs) described herein can be through-substrate vias. Depending on the type of substrate, if a through-substrate via is a via that passes through a substrate that may not be a silicon substrate, then a TSV can be understood as a through-substrate via.

[0039] At least the first and second terminals may be configured to have an auxiliary conductive layer deposited on them. This auxiliary conductive layer may be made of copper (Cu). Copper is preferred because it has good electrical conductivity and is easy to pattern and etch, making it an ideal material for interconnects. Copper also has good thermal conductivity, which can aid in heat dissipation. Some alternatives to copper may include aluminum and gold, which are also good electrical conductors. Another advantage is that copper can have high corrosion resistance. The auxiliary conductive layer may be deposited using any of the deposition methods described in this disclosure.

[0040] The auxiliary conductive layer can be configured to have a seed layer deposited thereon. This seed layer may consist of an attachment layer made of an attachment material such as chromium (Cr), titanium (Ti), or tantalum (Ta), and a seed metal layer made of a seed metal material such as copper (Cu), aluminum (Al), or gold (Au). The auxiliary conductive layer can be deposited using an electroless nickel immersion gold (ENIG) method. The seed layer can be a thin film of a specific material deposited as the first step in the deposition process. The seed layer can serve as a nucleation site for the growth of additional layers of the same material, preferably through processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The role of the seed layer is to ensure uniform growth of subsequent material layers and good adhesion to the surface on which they are deposited. The thickness of the seed layer is typically on the order of nanometers to micrometers, depending on the specific application.

[0041] The ENIG process can be used to deposit electroless nickel and gold thin layers onto the surface of multilayer stacks. The purpose of applying ENIG to multilayer stacks, or preferably to any surface, can be to provide a protective and corrosion-resistant coating that ensures the long-term reliability of the structure. The electroless nickel layer can act as a barrier layer to prevent diffusion between different layers in the stack, while the gold layer provides a smooth, uniform surface suitable for bonding or soldering.

[0042] The conductive layer can be made of copper (Cu), gold (Au), chromium (Cr), titanium (Ti), platinum (Pt), aluminum (Al), tantalum (Ta), titanium carbide (TiC), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium-doped zinc oxide (TZO), and / or aluminum-doped zinc oxide (AZO). As described herein, the multilayer stack may include a first set of odd-numbered layers and a second set of even-numbered layers. Advantageously, the first set of odd-numbered layers and the second set of even-numbered layers may have different properties. One property may be two sets made of different materials. Different materials allow for selective etching of either the first set or the second set of layers included in the multilayer stack. To reduce the equivalent series resistance of the integrated capacitor, the conductive layer may preferably have good electrical conductivity. Preferably, the conductive layer may be doped with elements or compounds. Doping refers to the process of intentionally adding impurities to a material to change its properties. An example of copper doping is adding a small amount of silver or other elements to copper, which can produce a material called a copper alloy. Copper alloys may have higher electrical conductivity than pure copper.

[0043] Conductive layers can be deposited using deposition methods such as evaporation, sputtering, or atomic layer deposition (ALD). Conductive layers can also be deposited via physical vapor deposition (PVD), chemical vapor deposition (CVD), or spin coating. Each deposition method has its own advantages and disadvantages compared to the others. Evaporation is simple and inexpensive, providing high purity and good adhesion to the substrate, and can deposit a wide variety of materials, including metals and organic compounds, making it suitable for both conductive and insulating layers. Due to the line-of-sight nature of the evaporation process, evaporation may be limited to small-area deposition and may restrict the production of layers with precise thickness control. Sputtering can also deposit a wide variety of materials and can produce thin films with precise thickness and uniformity. Sputtering can be used over large areas but may require high equipment and maintenance costs and may be limited to substrates that can withstand high temperatures and / or reactive gases. ALD provides precise thickness control down to the atomic level, high uniformity, can deposit a wide range of materials, and is suitable for depositing ultrathin films. Compared to other methods, ALD deposition rates may be lower, and equipment and maintenance costs are higher. In addition, since the ALD process may require multiple deposition and reaction steps, the process time may also increase significantly.

[0044] The thickness of the conductive layer can range from 5 to 500 nm. The thickness can be selected based on various criteria. Thicker conductive layers provide lower equivalent series resistance and better mechanical properties. Thinner conductive layers provide better conductivity and can increase capacitance density because, for a given space, thinner layers allow for the assembly of more layers within a multilayer stack.

[0045] The electrical isolation layer can be a dielectric layer. Each of the electrical isolation layers included in a multilayer stack can have different thicknesses and different properties, such as different materials. One or more of the dielectric layers are preferably non-conductive materials. The dielectric layer may have the ability to store electrical energy in the form of an electric field when a voltage is applied to it. Advantageously, this property makes it useful in applications such as capacitors or integrated capacitors. The dielectric layer can be used as an insulating or isolating material between two conductive layers in a multilayer stack, allowing the integrated capacitor to store charge without discharging through the dielectric layer.

[0046] In one embodiment, the dielectric layer is made of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), hafnium oxide (HfO2), or titanium dioxide (TiO2). Other materials that may have dielectric properties can also be used as the dielectric layer. Preferably, the material used for the dielectric layer can be selected based on the material used for the conductive layer. The materials used for the dielectric layer and the materials used for the conductive layer may need to be compatible so that the manufacturing process of the integrated capacitor can still be feasible, and preferably fast and low cost. In the same integrated capacitor, the dielectric layer can be made or deposited using different materials.

[0047] The thickness of the dielectric layer can range from 5 to 3000 nm. The thickness of the dielectric layer in an integrated capacitor depends on the specific requirements of the application in which the integrated capacitor can be used. These requirements can be summarized as follows: • Capacitance: The thickness of the dielectric layer affects the capacitance of an integrated capacitor. A thicker dielectric layer results in a lower capacitance, while a thinner dielectric layer results in a higher capacitance.

[0048] • Breakdown voltage: The thickness of the dielectric layer also affects the breakdown voltage of an integrated capacitor. A thicker dielectric layer results in a higher breakdown voltage, while a thinner dielectric layer results in a lower breakdown voltage.

[0049] • Operating conditions: The operating conditions of an integrated capacitor, such as voltage and temperature, will also affect the choice of dielectric layer thickness. If the integrated capacitor may be subjected to high voltage, a thicker dielectric layer may be required to prevent breakdown.

[0050] • Size constraints: In some applications, the available space for the capacitor may be limited, which can affect the choice of dielectric layer thickness.

[0051] • Cost: The cost of dielectric materials and deposition processes also influences the determination of dielectric layer thickness. Thicker layers require more material and / or longer processing time, thus increasing the cost of the device.

[0052] A dielectric layer can be disposed between two consecutive conductive layers in a multilayer stack. Each dielectric layer included in the multilayer stack can have different thicknesses and different properties, such as different materials.

[0053] In one embodiment, the integrated capacitor includes an auxiliary electrical isolation layer. This auxiliary electrical isolation layer may be disposed between a substrate and a multilayer stack. Preferably, the auxiliary electrical isolation layer may be an insulating layer. The insulating layer is preferably used to provide electrical isolation between the substrate and layers deposited on top of the insulating layer. More generally, the insulating layer can prevent unwanted electrical connections or short circuits.

[0054] The insulating layer can be made of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), or aluminum nitride (AlN). Other materials that possess insulating properties can also be used as the insulating layer. The insulating property can be the ability to provide electrical insulation.

[0055] The thickness of the insulating layer ranges from 5 to 3000 nm. The thickness of the insulating layer can be selected based on the specific requirements of the application in which it will be used (e.g., integrated capacitors). These requirements can be summarized as follows: • Breakdown voltage: The thickness of an insulating layer may need to be sufficient to withstand the maximum voltage applied to it without breakdown. The breakdown voltage of the insulating material can be measured and used to calculate the minimum required thickness.

[0056] • Parasitic capacitance: The thickness of the insulating layer can be used to reduce capacitive coupling with the substrate. The capacitance of a capacitor is directly proportional to the area of ​​the plates and inversely proportional to the distance between the plates. Therefore, a thicker insulating layer results in lower parasitic capacitance.

[0057] • Process constraints: The thickness of the insulating layer may be limited by the deposition method or process used to produce the insulating layer. For example, some deposition techniques may not be able to produce an insulating layer thicker than a certain amount.

[0058] • Mechanical considerations: The thickness of the insulating layer may also be affected by mechanical factors, such as the need for the layer to provide structural support or to prevent delamination or cracking.

[0059] The electrical isolation layer can be configured to be deposited using auxiliary deposition methods, such as thermal oxidation, evaporation, sputtering, atomic layer deposition, or chemical vapor deposition (CVD). CVD can be used to deposit thin layers of material onto a substrate. CVD methods offer high purity, precise control, and scalability. Compared to other deposition methods, CVD can be relatively more complex because it may require careful control of multiple parameters, such as temperature, pressure, and gas flow rate, and CVD methods are limited by substrate characteristics. CVD may require cleaning and smoothing the substrate surface, which limits the types of substrates that can be used and can potentially increase process costs.

[0060] The semiconductor substrate can be a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or a gallium arsenide (GaAs) substrate.

[0061] The substrate thickness ranges from 50 to 750 µm. The substrate thickness can be selected based on the specific requirements of applications such as capacitors and the properties of the substrate material. The substrate thickness can be selected to ensure mechanical stability and prevent warping or bending during processing and use. The substrate thickness affects the thermal conductivity of the integrated capacitor, which in turn affects heat dissipation. Thicker substrates generally have higher thermal conductivity but can also increase thermal resistance and reduce heat dissipation. Different substrate materials have different mechanical, thermal, and electrical properties, which affect the optimal substrate thickness. For example, SiC substrates can have higher thermal conductivity than Si substrates, which allows for equivalent heat dissipation using thinner substrates. Advantageously, the substrate thickness can be selected to ensure compatibility with manufacturing processes and equipment. Thicker substrates may require longer processing times and higher temperatures, which can affect device quality and yield.

[0062] Integrated capacitors may also include a diffusion barrier layer. The diffusion barrier layer can be disposed between the insulating layer and the multilayer stack. The thickness of the diffusion barrier layer can range from 5 to 100 nm. The diffusion barrier layer serves to prevent temperature or current-driven diffusion of conductive elements into the substrate. Otherwise, increased parasitic coupling to the substrate would lead to a deterioration in the performance of the integrated capacitor.

[0063] In one embodiment, at least one trench is at least one through-substrate trench, and wherein the at least one through-substrate trench is configured to be etched through the substrate. The at least one through-substrate trench can be etched using various methods, such as wet etching, dry etching, and other hybrid methods, such as reactive ion etching or deep reactive ion etching. The at least one through-substrate trench can be etched over a predefined through-substrate trench region, wherein the predefined through-substrate trench region can be defined by a through-substrate trench photomask. At least one trench can be etched over a predefined trench region, wherein the predefined trench region can be defined by a trench photomask. The trench photomask can be a through-substrate trench photomask. It is advantageous to have a photomask define both the predefined through-substrate trench region and the predefined trench region. The at least one through-substrate trench can be etched from one side of the substrate to the other side of the substrate.

[0064] The multilayer stack can be configured to be deposited on a first side and a second side of a substrate. Advantageously, if atomic layer deposition can be used, the multilayer stack can be deposited on the first and second sides of the substrate in a single process. The multilayer stack can be deposited on the first side of the substrate, and then the substrate can be flipped to deposit the multilayer stack on the second side of the substrate.

[0065] The first side and the second side of the substrate can be opposite sides of the substrate. The first side can be the top of the substrate, and the second side can be the bottom of the substrate. The first side can be the bottom of the substrate, and the second side can be the top of the substrate.

[0066] In a preferred embodiment, the multilayer stack is configured to be deposited on at least one side of a through-substrate trench, and for example, the multilayer stack is configured to connect from a first side to a second side via at least one through-substrate trench. Preferably, at least one trench and / or at least one through-substrate trench may be etched prior to depositing the multilayer stack. Subsequently, the multilayer stack may be deposited using a deposition method such as atomic layer deposition (ALD), which deposits the multilayer stack on at least a first side of the substrate and in the side of at least one through-substrate trench and / or the side of at least one trench.

[0067] At least one side of a through-substrate trench can be an inner side of the at least one through-substrate trench. The inner side of at least one through-substrate trench can be defined as a through-substrate trench sidewall, or simply a sidewall. This emphasizes their role as vertical or inclined surfaces defining the through-substrate trench cavity. In this patent application, it should be understood that when defining the sidewall of at least one trench, the same terminology can be applied to at least one trench, as described in this paragraph, where a sidewall can be defined as an inner surface or an inner sidewall.

[0068] In one embodiment, at least one through-substrate trench is configured to be filled with a through-substrate via material, for example, the substrate includes at least one through-substrate via. The at least one through-substrate via material may be filled with a through-substrate via material such as copper, tungsten, gold, silver, nickel, graphene, or any combination thereof. At least one through-substrate trench may be completely filled with the through-substrate via material. Preferably, the entire void or cavity of at least one through-substrate trench may be completely filled with the through-substrate via material. Advantageously, a filled via is preferred where high electrical conductivity, low resistance, and good mechanical stability are critical. Once at least one through-substrate trench is filled with the through-substrate material, at least one through-substrate via is created within the substrate. At least one through-substrate via electrically and thermally connects a first side of the substrate to a second side of the substrate. Advantageously, the through-substrate via material may have high thermal conductivity and high electrical conductivity, thereby facilitating heat dissipation from one side of the substrate to the other side, for example, from the first side to the second side, and vice versa.

[0069] At least one through-substrate via can be configured to connect to the redistribution layer. At least one through-substrate via can be electrically connected to the redistribution layer. Advantageously, the redistribution layer and the through-substrate via comprise the same or compatible materials, thereby enabling efficient conductivity between the at least one through-substrate via and the redistribution layer.

[0070] A redistribution layer (RDL) can include a first redistribution layer and a second redistribution layer. The redistribution layer can be segmented or divided into multiple sub-segments, each of which can perform a different functional role, such as signal routing, power distribution, and / or grounding. This division enables efficient management of electrical connections and allows for optimization of signal routing and power. The redistribution layer can be used for a variety of purposes, such as signal routing, power distribution, grounding, and / or isolation.

[0071] Different sections of the RDL can be specifically used to route signals to different locations on the substrate. This allows for efficient and optimized routing of signals, such as those going to and from integrated capacitors. Segments of the RDL can be designated for distributing power to different areas, ensuring efficient power transmission with minimal impedance. Individual sections of the RDL can be used for grounding purposes, providing a low-impedance path for ground signals and reducing system noise. For example, the first and / or second terminals of an integrated capacitor can be routed to ground, where the impedance between the first and / or second terminals and ground should be minimized. Efficient routing through the RDL can efficiently provide minimal grounding impedance to the first and / or second terminals of the integrated capacitor. This can be advantageously used in cases of efficient local grounding decoupling. By dividing the RDL into multiple sections, isolation between different signal or power domains can be achieved, thereby reducing crosstalk and interference between different parts of the substrate.

[0072] The first redistribution layer may be disposed on the first side of the substrate, and the second redistribution layer may be disposed on the second side of the substrate.

[0073] The redistribution layer may include at least a first terminal and / or a second terminal. The first and / or second terminals may be terminals of an integrated capacitor as defined in this disclosure. Thus, the redistribution layer can connect the first and / or second terminals of the integrated capacitor to auxiliary devices disposed on the substrate, or to pads disposed or arranged on the substrate, to connect the integrated capacitor to external devices or the substrate.

[0074] Figures 10A-10B A schematic embodiment of the integrated capacitor 100 is shown, as viewed from a side cross-section and a top view, wherein, as... Figures 10A-10B The integrated capacitor 100 embodiment shown includes a through-hole 141 through the substrate and redistribution layers 151, 152 on both sides of the substrate. Figure 10A A substrate 106 is shown, wherein the substrate 106 includes at least one through-substrate via 141. Four through-substrate vias 141 are arranged within the substrate 106. A multilayer stack is deposited on both sides of the substrate 106 and on the inner surface of at least one through-substrate trench or via 141. This advantageously maximizes the area where the odd-numbered layers 103 and even-numbered layers 104 are close to each other, thereby maximizing the capacitance of the integrated capacitor 100 within a given area of ​​the substrate 106. In this embodiment, four layers are arranged in the multilayer stack, but more layers may be arranged to increase the capacitance of the integrated capacitor 100. A dielectric layer 105 is arranged between the layers to provide electrical isolation. This dielectric layer is the dielectric layer described in this disclosure. The multilayer stack is arranged on an insulating layer 121, for example, the insulating layer is arranged between the substrate 106 and the first layer of the multilayer stack. The first layer of the multilayer stack is the bottom layer of the multilayer stack, which is the layer closest to the substrate. The multilayer stack includes four layers, wherein the first group of odd-numbered layers 103 includes two layers and the second group of even-numbered layers 104 includes two layers. The multilayer stack includes a dielectric layer 105 that separates the layers. A first set of odd-numbered layers 103 are connected to two first terminals 101, while a second set of even-numbered layers 104 are connected to two second terminals 102. The first and second terminals are through-holes filled with metal. The first and second terminals are directly connected to redistribution layers 151 and 152. Figure 10AAs shown, the redistribution layers include a first redistribution layer 151 and a second redistribution layer 152 disposed on both sides of the substrate 106. These two redistribution layers are electrically connected via a through-hole 141 in the substrate. This embodiment allows for flexibility in the integrated capacitor 100. A large capacitance is achieved between the first redistribution layer 151 and the second redistribution layer 152. Flexibility regarding electrical connections is also achieved because one port can be connected to the top side of the integrated capacitor, while the other port can be connected to the bottom side. This advantageously allows for 3D integration of such integrated capacitors, as the integrated capacitors can be connected to external devices from both sides, thereby allowing for the stacking of electronic components. Figure 10B As shown Figure 10A Top view of the embodiments shown and described. Figure 10B A top view is shown, in which all through-holes 141 of the substrate are visible from the top, and in which the dielectric layer 105 covers the top of the substrate 106. Those skilled in the art will understand that, Figure 10B As shown, odd-numbered layers and even-numbered layers are deposited beneath dielectric layer 105. The top layer of odd-numbered layer 103 and the top layer of even-numbered layer 104 are exposed on the right and left sides, respectively. Dielectric layer 105 can cover the exposed top layers of odd-numbered layer 103 and even-numbered layer 104, thus preventing the odd-numbered layers from being exposed. Figure 10B The diagram shows twelve through-substrate vias 141. More through-substrate vias can reduce the resistance between the first redistribution layer 151 and the second redistribution layer, the first redistribution layer being disposed on the top side of the substrate, and the second redistribution layer being disposed on the bottom side of the substrate. Those skilled in the art will understand that "disposed on the top side" or "disposed on the bottom side" does not indicate that the redistribution layer is disposed directly on the substrate, but rather on a layer or via contact disposed on the top and / or bottom side of the substrate. The first redistribution layer 151 covers the through-substrate vias. For ease of illustration, Figure 10B The image shows a through-substrate via 141, but this through-substrate via is located below the redistribution layer. This is in Figure 10A As shown, the first redistribution layer 151 and the second redistribution layer 152 cover the through-hole 141 of the substrate.

[0075] Figure 11 An embodiment of an integrated capacitor is shown, which includes a plurality of trenches 107 and through-substrate vias 141 that connect redistribution layers 151, 152 disposed on both sides of a substrate 106. Figure 11One embodiment is shown in which the multilayer stack is not deposited on the inner surface of at least one through-substrate via 141, but rather within at least one trench 107, as disclosed and described in some embodiments of this disclosure. In this embodiment, the through-substrate via 141 is used to connect a first redistribution layer 151 to a second redistribution layer 152. The through-substrate trench does not allow the multilayer stack to be deposited on the inner surface of the through-substrate trench before the through-substrate via material is filled. Electrical connections to the integrated capacitor 100 provide electrical flexibility, as one port can be connected to the top side of the integrated capacitor while another port can be connected to the bottom side. This advantageously allows for 3D integration of such an integrated capacitor 100, as the integrated capacitor can be connected to external devices from both sides, thus allowing for the stacking of electronic components. A first terminal 101 and a second terminal 102 are arranged on one side of the redistribution layer, which in this embodiment is the first redistribution layer 151, since the multilayer stack is arranged on one side of the substrate. Through-hole 141 in the substrate electrically connects the first and / or second terminals of the integrated capacitor to the redistribution layer 152, which is disposed on the other side of the substrate 106.

[0076] In another aspect, a method for manufacturing an integrated capacitor on a substrate is disclosed, wherein the method may include the steps of: creating at least one trench in the substrate; arranging a multilayer stack on the substrate, the multilayer stack including at least three conductive layers and separated by an electrical isolation layer, wherein the multilayer stack includes a first set of odd-numbered layers and a second set of even-numbered layers, and wherein the multilayer stack is arranged in substantially vertical and substantially horizontal directions along a plurality of surfaces of the substrate; creating at least two trenches in the multilayer stack down to the lowest layer of the multilayer stack, thereby defining at least a first terminal trench and a second terminal trench; removing a majority of the first set of odd-numbered layers within the first terminal trench; removing a majority of the second set of even-numbered layers within the second terminal trench; arranging an auxiliary conductive layer on the multilayer stack, wherein the auxiliary conductive layer is further arranged within at least the first terminal trench and the second terminal trench and contacts the first set of odd-numbered layers and the second set of even-numbered layers; and removing a majority of the auxiliary conductive layer such that the first terminal is electrically isolated from the second terminal.

[0077] Advantageously, a large portion of either the first set of odd-numbered layers or the second set of even-numbered layers can be selectively etched. By selectively etching either the first set of odd-numbered layers or the second set of even-numbered layers in the same trench, the collapse of the metal layers creates isolation between the unetched metal layers and the trench. For example, by selectively etching the first set of odd-numbered layers within the first terminal trench, the second set of even-numbered layers will collapse due to weight, isolating the second set of even-numbered layers from the trench. Furthermore, advantageously, the dielectric material disposed between the first set of odd-numbered layers and the second set of even-numbered layers can be retained, allowing the first set of odd-numbered layers to remain electrically isolated from the second set of even-numbered layers.

[0078] Figure 3 An embodiment illustrating a schematic diagram of the steps of the method described in this disclosure is shown. A multilayer stack 120 is deposited on a substrate 106, wherein the multilayer stack includes an insulating layer 121 and eight conductive layers separated by electrically insulating layers 105, i.e., dielectric layers. The multilayer stack includes a first set of odd-numbered layers 103 and a second set of even-numbered layers 104, wherein the first set of odd-numbered layers has different characteristics from the second set of even-numbered layers. A photoresist layer 122 is disposed on top of the multilayer stack using a mask, which defines the pattern to be deposited for the photoresist layer. The photoresist layer is removed from the region where a first trench 131 is created. The first trench 131 is created by etching the multilayer stack down to the lowest layer of the multilayer stack. Alternatively, the first trench can be created down to the substrate. In this case, there will be no electrical isolation between the conductive layers and the substrate. This could potentially result in high coupling and potential leakage. Selective etching is performed, wherein selective etching removes a portion of the first set of odd-numbered layers in the multilayer stack from the first trench. Due to the mechanical structure of the multi-layered stack, this selective etching of most of the first set of odd-numbered layers causes the second set of even-numbered layers to collapse. This forms electrical isolation between the first set of odd-numbered layers within the first trench, while maintaining electrical isolation between the multi-layered stacked conductive layers. A photoresist layer 122 can be deposited on this structure, wherein the photoresist layer is removed at the location where the second trench 132 is created. Then, most of the second set of even-numbered layers can be selectively etched from the second trench. Due to the mechanical structure of the multi-layered stack, this selective etching of most of the second set of even-numbered layers causes the first set of odd-numbered layers to collapse. This forms electrical isolation between the second set of even-numbered layers within the second trench, while maintaining electrical isolation between the multi-layered stacked conductive layers. An auxiliary conductive layer 123 can be disposed on top of the structure comprising two trenches, wherein the auxiliary conductive layer has electrical contact with the second set of even-numbered layers in the first trench and the first set of odd-numbered layers in the second trench, thereby creating a first terminal 133 and a second terminal 134. A portion of the auxiliary conductive layer is then removed to electrically isolate the first terminal from the second terminal.

[0079] Figure 4An embodiment illustrating a schematic diagram of the steps of the method disclosed in this disclosure is shown. A multilayer stack 120 is deposited on a substrate 106, wherein the multilayer stack includes an insulating layer 121 and eight conductive layers separated by electrically insulating layers 105, i.e., dielectric layers. The multilayer stack includes a first set of odd-numbered layers 103 and a second set of even-numbered layers 104, wherein the first set of odd-numbered layers has different properties than the second set of even-numbered layers. A photoresist layer 122 is disposed on top of the multilayer stack using a mask, wherein the photoresist layer is removed from the region where the first trench 131 is created. The first trench is then created by etching the multilayer stack down to the lowest layer of the multilayer stack. Alternatively, the first trench can be created down to the substrate. In this case, there will be no electrical isolation between the conductive layers and the substrate. This could potentially result in high coupling and potential leakage. Selective etching is performed, wherein selective etching removes a portion of the first set of odd-numbered layers from the first trench in the multilayer stack. Due to the mechanical structure of the multilayer stack, this selective etching of the first set of odd-numbered layers does not cause the second set of even-numbered layers to collapse due to their thickness. Therefore, a dielectric layer is deposited within the first trench to electrically isolate the first set of odd-numbered layers from the first trench. Preferably, the dielectric layer can be deposited within the first trench using a deposition method capable of conformally depositing layers, such as atomic layer deposition (ALD). A photoresist layer can be deposited on this structure, wherein the photoresist layer is removed at the location where the second trench 132 is created. Then, most of the second set of even-numbered layers can be selectively etched from the second trench. Due to the mechanical structure of the multilayer stack, this selective etching of most of the second set of even-numbered layers does not cause the first set of odd-numbered layers to collapse. Therefore, a dielectric layer is deposited within the second trench to electrically isolate the second set of even-numbered layers from the second trench. Preferably, the dielectric layer can be deposited within the second trench using a deposition method capable of conformally depositing layers, such as atomic layer deposition (ALD). This forms electrical isolation of the second set of even-numbered layers within the second trench while maintaining electrical isolation between the multilayer stacked conductive layers. An auxiliary conductive layer 123 may be disposed on top of a structure comprising two trenches, wherein the auxiliary conductive layer has electrical contact with a second set of even-numbered layers in the first trench and a first set of odd-numbered layers in the second trench, thereby creating a first terminal 133 and a second terminal 134. A portion of the auxiliary conductive layer is then removed to electrically isolate the first terminal from the second terminal.

[0080] The integrated capacitor manufactured using the methods disclosed herein can be any integrated capacitor disclosed herein.

[0081] In another aspect, the present invention discloses a method for manufacturing a via connecting at least two layers in a multilayer stack of at least three layers disposed on a substrate. The method may include the following steps: disposing of a multilayer stack on a substrate, the multilayer stack comprising at least three conductive layers separated by an electrically insulating layer, wherein the multilayer stack comprises a first set of odd-numbered layers and a second set of even-numbered layers; creating at least one trench in the multilayer stack down to the lowest layer of the multilayer stack; removing a majority of the first set of odd-numbered layers or the second set of even-numbered layers through the at least one trench; disposing of an auxiliary conductive layer on the multilayer stack, wherein the auxiliary conductive layer is further disposed within the at least one trench and contacts the first set of odd-numbered layers or the second set of even-numbered layers.

[0082] Figure 3 or Figure 4 An embodiment of a method for fabricating a via is shown, illustrating steps of the via connecting at least two layers in a multilayer stack. The via can be fabricated according to some steps of the method previously described in this disclosure, which describes a method for fabricating an integrated capacitor on a substrate.

[0083] The multilayer stack and substrate can be any multilayer stack and any substrate described herein. The vias described in this method can be any vias described in this disclosure.

[0084] Figure 5 Schematic embodiments of two scenarios are shown, where the first scenario illustrates an embodiment with one terminal having an ohmic contact with the substrate, and the second scenario illustrates an embodiment where both terminals have substrate isolation. Scenario 1 shows a schematic of a first trench 133 being created down to the substrate 106, where the insulating layer 121 is also removed by an etching process that creates the first configuration 133. When the auxiliary conductive layer 123 is deposited in the first trench 133, electrical connection between the auxiliary conductive layer 123 and the substrate 106 is established via an ohmic contact. Scenario 2 shows a schematic of the first trench 133 being created down to the lowest layer of the substrate, where the insulating layer 121 is partially or not removed by an etching process that creates the first trench 133. This isolates the auxiliary conductive layer 123 from the substrate 106.

[0085] As described above and as Figure 5 Case 1 or the first case shown can be used in applications that require efficient decoupling between the first terminal and external devices connected to the first terminal.

[0086] On the other hand, an integrated capacitor device is disclosed. This integrated capacitor device may include the integrated capacitor described herein and at least two external terminals. The at least two external terminals may be connected to at least a first terminal and a second terminal of the integrated capacitor described herein. Preferably, the integrated capacitor device may be a surface mount (SMD) component. An SMD component is an electronic component that can be directly mounted onto the surface of a printed circuit board (PCB) or any other acceptable electronic component. SMD components are suitable for high-density circuit boards. SMD components can have various sizes, ranging from the relatively large 1206 size to the tiny 0201 size. The integrated capacitor device may be an SMD component with a size within the size range described herein.

[0087] Figure 6A An embodiment of an integrated capacitor with external terminals 500 is shown. External terminals 501, 502 are arranged on the top side of a substrate 106, where the integrated capacitor is also fabricated. The external terminals are in electrical contact with the first and second terminals of the integrated capacitor. Preferably, the external terminals may be thick enough to maintain mechanical constraints arising from bonding or any other method, such as soldering, when electrically connecting the external terminals to any external device, PCB, or die.

[0088] In another aspect, an integrated capacitor device is disclosed, wherein the integrated capacitor device may include at least one integrated capacitor disclosed herein; one or more through-holes, such as through-substrate vias, disposed in the substrate and connected to at least a first terminal and a second terminal of the at least one integrated capacitor, and wherein the through-substrate vias may provide a plurality of terminals on both sides of the substrate. Advantageously, the through-substrate vias may be disposed on the side of the integrated capacitor such that the through-substrate vias do not interfere with the structure of the integrated capacitor. Preferably, a redistribution layer may be disposed from at least the first terminal and the second terminal of the integrated capacitor such that the redistribution layer may connect at least the first terminal and the second terminal to the through-substrate via.

[0089] Figure 6B An embodiment of an integrated capacitor with external terminals 500 is shown, wherein external terminals 501 and 502 are arranged on both sides of a substrate 106 having through-holes 503. The through-holes 503 are arranged on both sides of the integrated capacitor such that they do not pass through the integrated capacitor, but preferably pass through the substrate on the side of the integrated capacitor. The through-holes are connected to a first terminal and a second terminal of the integrated capacitor, thereby establishing an electrical connection between the first and second terminals of the integrated capacitor and the through-holes.

[0090] In another aspect, an integrated circuit assembly is disclosed, wherein the integrated circuit assembly may include at least one integrated circuit; at least one integrated capacitor as described herein; wherein the at least one integrated circuit and at least one integrated capacitor may be integrated in a substrate and electrically connected, and wherein the integrated circuit assembly may further include at least two external terminals.

[0091] Figure 7A A schematic embodiment of an integrated capacitor 100 integrated with an integrated circuit 600 in a substrate 106 is shown. This embodiment illustrates two integrated capacitors 100, one of which is disposed on each side of the integrated circuit and both located on one side of the substrate 106. Terminals are disposed on the top of the substrate to electrically connect the integrated capacitors to the integrated circuit, or to provide the option to electrically connect different terminals to external devices, dies, or PCBs. By integrating the integrated capacitors on both sides of the integrated circuit and within the same substrate, efficient decoupling can be achieved without the need for large-volume capacitors, such as SMD capacitors with large capacitance values. The close proximity of the capacitors to the integrated circuit can reduce noise and improve electromagnetic compatibility.

[0092] In one aspect, an integrated circuit assembly may include at least one integrated circuit; at least one integrated capacitor as described herein; one or more through-holes, such as through-substrate vias, preferably disposed in the substrate and connected to at least first and second terminals of at least one integrated capacitor as defined herein and / or connected to at least one integrated circuit, wherein the through-substrate vias may provide a plurality of external terminals on both sides of the substrate.

[0093] Figures 7B-7C An embodiment of an integrated capacitor 100 integrated with an integrated circuit 600 in a substrate 106 is shown, wherein external terminals are part of a through-substrate via 503. The through-substrate via allows electrical connections on both sides of the substrate. Figure 6C shows an embodiment where the integrated capacitor is disposed on one side of the substrate, while the integrated circuit is disposed within the substrate but on the other side. This allows for a short connection between the integrated capacitor and the integrated circuit while reducing the substrate footprint.

[0094] Figures 8A-8B An example of a schematic diagram illustrating a possible application of integrated capacitors in stacked electronic components is shown. Figure 8A An embodiment is shown in the schematic diagram, in which an SMD component is stacked on top of an integrated capacitor 100 integrated with an integrated circuit 600 in a substrate 106. The SMD component is soldered to a through-hole in the substrate. Figure 8BAn embodiment is illustrated in the schematic diagram, in which an integrated capacitor 500 is stacked on top of a substrate 106 including an integrated circuit 600 and a through-hole. In this embodiment, the integrated capacitor 500 serves as an SMD component, wherein the external terminals of the integrated capacitor are soldered to the through-hole of the substrate including the integrated circuit, thereby electrically connecting the integrated capacitor device to the integrated circuit.

[0095] Figures 9A-9I An example of a schematic diagram illustrating a possible application of integrated capacitors in stacked electronic components is shown. Figure 9A An embodiment of an integrated capacitor device is illustrated, stacked on top of a laminate and an application PCB. The integrated capacitor device is soldered to through-substrate vias within the laminate via external terminals, which further connect to the application PCB on the other side of the laminate. Preferably, the application PCB provides internal electrical wiring to allow the integrated capacitor to be electrically connected to SMD components or integrated circuits, or both. Figure 9B It shows the relationship with Figure 9A The embodiment shown is similar to the schematic diagram shown, but in which the laminate is replaced by a silicon substrate. A silicon substrate allows for better heat dissipation than a laminate substrate. The advantage of a silicon substrate lies in its suitability for integrating dies or, more generally, integrating electronic components and / or devices within the substrate. Figure 9C An embodiment of a schematic diagram of an integrated circuit integrated within a silicon substrate is shown, wherein the silicon substrate includes through-holes that allow electrical connections between the two sides of the silicon substrate. Integrated capacitors are disposed on top of the silicon substrate, as close as possible to the integrated circuit, thereby significantly reducing the various parasitic effects that may arise from the long wiring length between the integrated circuit and the integrated capacitors. Figure 9D An embodiment of a stacked electronic assembly is shown, including an integrated circuit assembly with integrated capacitors stacked on top of a laminate substrate and further stacked on top of an application PCB. Figure 9E An embodiment of a stacked electronic assembly is shown, comprising an integrated circuit assembly with integrated capacitors and integrated circuits within a substrate stacked on top of an auxiliary silicon substrate, and further stacked on top of an application PCB. The silicon substrate is provided with through-holes to allow direct electrical connections from one side of the silicon substrate to the other. Figure 9F An embodiment of a stacked electronic assembly is shown, comprising an integrated circuit assembly including integrated capacitors and integrated circuits included within a substrate, stacked on top of an auxiliary silicon substrate, and further stacked on top of an application PCB. The auxiliary silicon substrate includes through-holes that allow electrical connections from one side of the auxiliary silicon substrate to the other. The auxiliary silicon substrate includes a magnetic core, such as a coil, integrated within it. Figure 9GAn embodiment of a stacked electronic assembly is shown, wherein integrated circuits and SMD components are stacked on a substrate including integrated capacitors, and wherein the substrate also includes through-holes to allow electrical connections from one side of the substrate to the other side, wherein a PCB connection is applied on the other side. Figure 9H An embodiment of a stacked electronic assembly is shown, wherein the integrated circuit assembly includes an integrated circuit and two integrated capacitors disposed within a substrate on each side of the integrated circuit. The substrate also includes through-holes allowing SMD components to be disposed on one side of the substrate, while an applied PCB is disposed on the other side. Figure 9I An embodiment of a stacked electronic assembly is illustrated, comprising an integrated circuit assembly, surface mount device (SMD) components, and an application PCB. The integrated circuit assembly includes an integrated circuit integrated within a substrate on one side, wherein the substrate includes a through-hole that electrically connects the integrated circuit to an integrated capacitor integrated within a substrate on the other side. The integrated circuit assembly is stacked on top of the application PCB, and the SMD components are stacked on top of the integrated circuit assembly. Example List

[0096] The following embodiments are disclosed in this article: 1. An integrated capacitor on a substrate, comprising: At least one trench within the substrate; A multilayer stack comprising at least three conductive layers deposited on a substrate and separated by an electrically insulating layer, wherein the multilayer stack comprises a first set of odd-numbered layers and a second set of even-numbered layers, and wherein the multilayer stack is arranged along multiple surfaces of the substrate in substantially vertical and substantially horizontal directions. At least a first terminal and a second terminal, wherein the first terminal contacts a first set of odd-numbered layers, and the second terminal contacts a second set of even-numbered layers.

[0097] 2. The integrated capacitor according to Project 1, wherein the substrate is a semiconductor substrate, a glass substrate, a sapphire substrate, or a polyamide substrate.

[0098] 3. The integrated capacitor according to any one of the preceding items, wherein the multilayer stack comprises at least four, preferably at least five, more preferably at least ten, even more preferably at least fifteen, and most preferably at least twenty conductive layers.

[0099] 4. The integrated capacitor according to any one of the preceding items, wherein the integrated capacitor includes at least two trenches in the substrate, preferably at least three trenches, more preferably at least four trenches.

[0100] 5. The integrated capacitor according to any one of the preceding items, wherein at least one trench has an opening width in the range of 0.1µm to 10µm.

[0101] 6. The integrated capacitor according to any one of the preceding items, wherein at least one trench has a depth in the range of 10µm to 725µm.

[0102] 7. The integrated capacitor according to any one of the preceding items, wherein the integrated capacitor comprises at least three terminals, preferably at least five terminals, more preferably at least ten terminals, and even more preferably at least twenty terminals.

[0103] 8. The integrated capacitor according to any one of the preceding items, wherein at least the first terminal and the second terminal are through holes.

[0104] 9. The integrated capacitor according to item 8, wherein the via has a redistribution layer.

[0105] 10. The integrated capacitor according to any one of items 8-9, wherein the redistribution layer is disposed on the upper surface of the via, and wherein the upper surface of the via is substantially disposed at the same height as the upper surface of the multilayer stack.

[0106] 11. The integrated capacitor according to any one of items 8-10, wherein the diameter of the through hole is in the range of 1 to 50 µm.

[0107] 12. The integrated capacitor according to any one of items 8-11, wherein the thickness of the redistribution layer is in the range of 1 to 30 µm.

[0108] 13. The integrated capacitor according to any one of items 8-12, wherein the through hole is a through-substrate through-hole.

[0109] 14. The integrated capacitor according to any one of the preceding items, wherein at least the first terminal and the second terminal are configured to have an auxiliary conductive layer deposited thereon.

[0110] 15. The integrated capacitor according to item 14, wherein the auxiliary conductive layer is made of copper (Cu).

[0111] 16. The integrated capacitor according to any one of items 14-15, wherein the auxiliary conductive layer is configured to be deposited with a seed layer comprising an adhesion layer and a seed metal layer, or configured to be deposited using an electroless nickel immersion gold (ENIG) method including a seed layer.

[0112] 17. The integrated capacitor according to any one of the preceding items, wherein the conductive layer is made of copper (Cu), gold (Au), chromium (Cr), titanium (Ti), platinum (Pt), aluminum (Al), tantalum (Ta), titanium carbide (TiC), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium-doped zinc oxide (TZO) and / or aluminum-doped zinc oxide (AZO).

[0113] 18. The integrated capacitor according to any one of the preceding items, wherein the conductive layer is configured to be deposited using a deposition method such as evaporation, sputtering or atomic layer deposition.

[0114] 19. The integrated capacitor according to any one of the preceding items, wherein the thickness of the conductive layer is in the range of 5 to 500 nm.

[0115] 20. The integrated capacitor according to any one of the preceding items, wherein one or more of the electrical isolation layers are dielectric layers.

[0116] 21. The integrated capacitor according to item 20, wherein the dielectric layer is made of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), hafnium oxide (HfO2) or titanium dioxide (TiO2).

[0117] 22. The integrated capacitor according to any one of the preceding items, wherein the thickness of the dielectric layer is in the range of 5 to 3000 nm.

[0118] 23. The integrated capacitor according to any one of the preceding items, wherein the integrated capacitor includes an auxiliary electrical isolation layer.

[0119] 24. The integrated capacitor according to item 23, wherein an auxiliary electrical isolation layer is disposed between the substrate and the multilayer stack.

[0120] 25. The integrated capacitor according to any one of the preceding items, wherein the auxiliary electrical isolation layer is an insulating layer.

[0121] 26. The integrated capacitor according to item 25, wherein the insulating layer is made of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3) or aluminum nitride (AlN).

[0122] 27. The integrated capacitor according to any one of the preceding items, wherein the thickness of the insulating layer is in the range of 5 to 3000 nm.

[0123] 28. The integrated capacitor according to any one of the preceding items, wherein the electrical isolation layer is configured to be deposited using an auxiliary deposition method, such as thermal oxidation, evaporation, sputtering, atomic layer deposition, or chemical vapor deposition.

[0124] 29. The integrated capacitor according to any one of the preceding items, wherein the semiconductor substrate is a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or a gallium arsenide (GaAs) substrate.

[0125] 30. The integrated capacitor according to any one of the preceding items, wherein the thickness of the substrate is in the range of 50 to 750 µm.

[0126] 31. The integrated capacitor according to any one of the preceding items further includes a diffusion barrier layer.

[0127] 32. The integrated capacitor according to item 31, wherein a diffusion barrier layer is disposed between an insulating layer and a multilayer stack.

[0128] 33. The integrated capacitor according to any one of items 31-32, wherein the diffusion barrier layer has a thickness in the range of 5 to 100 nm.

[0129] 34. The integrated capacitor according to any one of the preceding items, wherein at least one trench is at least one through-substrate trench, and wherein the through-substrate trench is configured to be etched through the substrate.

[0130] 35. The integrated capacitor according to any one of the preceding items, wherein the multilayer stack is configured to be deposited on a first side and a second side of a substrate.

[0131] 36. The integrated capacitor according to any one of the preceding items, wherein the first side and the second side of the substrate are opposite sides of the substrate.

[0132] 37. The integrated capacitor according to any one of the preceding items, wherein the multilayer stack is configured to be deposited on at least one side of a through-substrate trench, and, for example, the multilayer stack is configured to be connected from a first side to a second side through at least one through-substrate trench.

[0133] 38. The integrated capacitor according to item 37, wherein at least one side of the through-substrate trench is at least one inner side of the through-substrate trench.

[0134] 39. The integrated capacitor according to any one of the preceding items, wherein at least one through-substrate trench is configured to be filled with through-substrate via material, for example, the substrate includes at least one through-substrate via.

[0135] 40. The integrated capacitor according to any one of the preceding items, wherein at least one through-substrate via is configured to be connected to the redistribution layer.

[0136] 41. The integrated capacitor according to any one of the preceding items, wherein the redistribution layer comprises a first redistribution layer and a second redistribution layer.

[0137] 42. The integrated capacitor according to any one of the preceding items, wherein a first redistribution layer is disposed on a first side of the substrate and a second redistribution layer is disposed on a second side of the substrate.

[0138] 43. The integrated capacitor according to any one of the preceding items, wherein the redistribution layer includes at least a first terminal and / or a second terminal.

[0139] 44. A method for manufacturing an integrated capacitor on a substrate, comprising the following steps: Create at least one trench in the substrate; A multilayer stack is disposed on a substrate, the multilayer stack comprising at least three conductive layers separated by an electrically insulating layer, wherein the multilayer stack comprises a first set of odd-numbered layers and a second set of even-numbered layers, and wherein the multilayer stack is disposed along multiple surfaces of the substrate in substantially vertical and substantially horizontal directions. In a multilayer stack, at least two trenches are created down to the lowest layer of the multilayer stack, thereby defining at least a first terminal trench and a second terminal trench; Remove most of the first set of odd-numbered layers within the first terminal trench; Remove most of the second even-numbered layer within the second terminal trench; An auxiliary conductive layer is disposed on a multilayer stack, wherein the auxiliary conductive layer is further disposed in at least a first terminal trench and a second terminal trench and contacts a first set of odd-numbered layers and a second set of even-numbered layers. Most of the auxiliary conductive layer is removed, making the first terminal electrically isolated from the second terminal.

[0140] 45. The method according to item 44, wherein at least two trenches in the multilayer stack are created down to the substrate.

[0141] 46. ​​The method according to any one of items 44-45, wherein the integrated capacitor is the integrated capacitor according to any one of items 1-43.

[0142] 47. A method of manufacturing a through-hole connecting at least two layers, said at least two layers comprising a multilayer stack of at least three layers disposed on a substrate, the method comprising the steps of: A multilayer stack is disposed on a substrate, the multilayer stack including at least three conductive layers and separated by an electrically insulating layer, wherein the multilayer stack includes a first group of odd-numbered layers and a second group of even-numbered layers; Create at least one trench down to the lowest layer of the multi-layer stack; Remove most of the first set of odd-numbered layers or the second set of even-numbered layers by at least one trench; An auxiliary conductive layer is disposed on a multilayer stack, wherein the auxiliary conductive layer is further disposed within at least one trench and contacts a first set of odd-numbered layers or a second set of even-numbered layers.

[0143] 48. The method according to item 47, wherein at least one trench in the multilayer stack is created down to the substrate.

[0144] 49. The method according to any one of items 47-48, wherein the multilayer stack and substrate are multilayer stacks and substrates according to any one of items 1-43, and wherein the through-hole is a through-hole according to any one of items 8-13.

[0145] 50. An integrated capacitor device comprising an integrated capacitor according to any one of items 1-43 and at least two external terminals, wherein the at least two external terminals are connected to at least a first terminal and a second terminal of the integrated capacitor according to any one of items 1-43.

[0146] 51. An integrated capacitor device, comprising: At least one integrated capacitor as defined in any one of items 1-43; One or more through-holes, such as through-substrate through-holes, are arranged in the substrate and connected to at least a first terminal and a second terminal of an integrated capacitor defined in any one of items 1-43, wherein the through-substrate through-holes provide a plurality of terminals on both sides of the substrate.

[0147] 52. An integrated circuit component, comprising: At least one integrated circuit; At least one integrated capacitor as defined in any one of items 1-43; At least one integrated circuit and at least one integrated capacitor are integrated in the substrate and electrically connected, and the integrated circuit assembly further includes at least two external terminals.

[0148] 53. An integrated circuit component, comprising: At least one integrated circuit; At least one integrated capacitor as defined in any one of items 1-43; One or more through-holes, such as through-substrate through-holes, are arranged in the substrate and connected to at least the first and second terminals of at least one integrated capacitor defined in any one of items 1-43 and / or connected to at least one integrated circuit, wherein the through-substrate through-holes provide a plurality of external terminals on both sides of the substrate.

Claims

1. An integrated capacitor on a substrate, comprising: At least one trench within the substrate; A multilayer stack comprising at least three conductive layers deposited on the substrate and separated by an electrically insulating layer, wherein the multilayer stack comprises a first set of odd-numbered layers and a second set of even-numbered layers, and wherein the multilayer stack is arranged along a plurality of surfaces of the substrate in substantially vertical and substantially horizontal directions. At least a first terminal and a second terminal, wherein the first terminal contacts the first set of odd-numbered layers, and the second terminal contacts the second set of even-numbered layers.

2. The integrated capacitor according to claim 1, wherein, The substrate is a semiconductor substrate, a glass substrate, a sapphire substrate, or a polyamide substrate, wherein the semiconductor substrate is a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or a gallium arsenide (GaAs) substrate.

3. The integrated capacitor according to any one of the preceding claims, wherein, The multilayer stack includes at least four, preferably at least five, more preferably at least ten, even more preferably at least fifteen, and most preferably at least twenty conductive layers.

4. The integrated capacitor according to any one of the preceding claims, wherein, The integrated capacitor includes at least two trenches, preferably at least three trenches, and more preferably at least four trenches within the substrate.

5. The integrated capacitor according to any one of the preceding claims, wherein, The integrated capacitor includes at least three terminals, preferably at least five terminals, more preferably at least ten terminals, and even more preferably at least twenty terminals.

6. The integrated capacitor according to any one of the preceding claims, wherein, The at least first terminal and the second terminal are through holes, and the through holes are through-substrate through holes.

7. The integrated capacitor according to any one of the preceding claims, wherein, The at least first terminal and the second terminal are configured to have an auxiliary conductive layer deposited thereon, wherein the auxiliary conductive layer is made of copper (Cu).

8. The integrated capacitor according to any one of the preceding claims, wherein, The conductive layer is made of copper (Cu), gold (Au), chromium (Cr), titanium (Ti), platinum (Pt), aluminum (Al), tantalum (Ta), titanium carbide (TiC), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium-doped zinc oxide (TZO), and / or aluminum-doped zinc oxide (AZO), and wherein the conductive layer is configured to be deposited by a deposition method such as evaporation, sputtering, or atomic layer deposition.

9. The integrated capacitor according to any one of the preceding claims, wherein, One or more of the electrical isolation layers are dielectric layers, and the dielectric layers are made of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), hafnium oxide (HfO2) or titanium dioxide (TiO2).

10. The integrated capacitor according to any one of the preceding claims, wherein, The at least one trench is at least one through-substrate trench, and wherein the through-substrate trench is configured to be etched through the substrate.

11. The integrated capacitor according to any one of the preceding claims, wherein, The multilayer stack is configured to be deposited on a first side and a second side of the substrate, wherein the first side and the second side of the substrate are opposite sides of the substrate.

12. The integrated capacitor according to any one of the preceding claims, wherein, The multilayer stack is configured to be deposited on the side surface of the at least one through-substrate trench, and for example, the multilayer stack is configured to be connected from the first side to the second side through the at least one through-substrate trench, wherein the side surface of the at least one through-substrate trench is the inner side surface of the at least one through-substrate trench.

13. The integrated capacitor according to any one of the preceding claims, wherein, The at least one through-substrate trench is configured to be filled with through-substrate via material, for example, the substrate includes at least one through-substrate via.

14. The integrated capacitor according to any one of the preceding claims, wherein, The at least one through-substrate via is configured to connect to the redistribution layer.

15. The integrated capacitor according to any one of the preceding claims, wherein, The redistribution layer includes a first redistribution layer and a second redistribution layer, wherein the first redistribution layer is disposed on a first side of the substrate, and the second redistribution layer is disposed on a second side of the substrate.

16. The integrated capacitor according to any one of the preceding claims, wherein, The redistribution layer includes at least the first terminal and / or the second terminal.

17. A method for manufacturing an integrated capacitor on a substrate, comprising the following steps: At least one trench is created in the substrate; A multilayer stack is disposed on the substrate, the multilayer stack comprising at least three conductive layers separated by an electrically insulating layer, wherein the multilayer stack comprises a first group of odd-numbered layers and a second group of even-numbered layers, and wherein the multilayer stack is disposed along a plurality of surfaces of the substrate in substantially vertical and substantially horizontal directions. In the multilayer stack, at least two trenches are created down to the lowest layer of the multilayer stack, thereby defining at least a first terminal trench and a second terminal trench; Remove most of the first set of odd-numbered layers within the first terminal trench; Remove most of the second set of even-numbered layers within the second terminal trench; An auxiliary conductive layer is disposed on the multilayer stack, wherein the auxiliary conductive layer is further disposed within the at least first terminal trench and the second terminal trench, and contacts the first set of odd-numbered layers and the second set of even-numbered layers; Most of the auxiliary conductive layer is removed to electrically isolate the first terminal from the second terminal.

18. The method according to claim 17, wherein, The at least two trenches in the multilayer stack are created down to the substrate.

19. The method according to any one of claims 17-18, wherein, The integrated capacitor is the integrated capacitor according to any one of claims 1-16.

20. A method of manufacturing a through-hole, the through-hole connecting at least two layers, the at least two layers comprising a multilayer stack of at least three layers disposed on a substrate, the method comprising the steps of: A multilayer stack is disposed on the substrate, the multilayer stack comprising at least three conductive layers separated by an electrically insulating layer, wherein the multilayer stack comprises a first group of odd-numbered layers and a second group of even-numbered layers; In the multi-layer stack, at least one trench is created down to the lowest layer of the multi-layer stack; The majority of the first set of odd-numbered layers or the second set of even-numbered layers is removed by the at least one trench; An auxiliary conductive layer is disposed on the multilayer stack, wherein the auxiliary conductive layer is further disposed within the at least one trench and contacts the first set of odd-numbered layers or the second set of even-numbered layers.

21. The method according to claim 20, wherein, The at least one trench in the multilayer stack is created down to the substrate.

22. The method according to any one of claims 20-21, wherein, The multilayer stack, the substrate, and the via are as described in any one of claims 1-16.

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