FPGA-based 8Fs instruction receiving and IO control method in UART communication of array server

Abstract

The invention provides an 8Fs instruction receiving and IO control method in array server UART communication based on an FPGA, belongs to the technical field of array server hardware control, and is suitable for multi-node server cluster hardware management. According to the method, a purple light syncretic PGL50H-6FG484 FPGA is adopted as a main control unit, and a BMC sends a 0x8F single-byte 8Fs instruction through a UART (Universal Asynchronous Receiver / Transmitter); and after receiving the instruction, the FPGA analyzes the operation command through a frame header, an equipment address and additional data verification, matches 20 calculation modules, outputs an IO control signal, and simultaneously acquires the state of the module and returns the state to the BMC. The BMC is triggered to give an alarm through continuous three times of invalid instructions, and a flash enable signal and a power supply control signal are interlocked. According to the method, the UART control accuracy and reliability are improved, hardware resources are efficiently utilized, and the system security is enhanced.

Description

Technical Field

[0001] This invention relates to the field of array server hardware control technology, specifically to a method for receiving and controlling 8Fs instructions in UART communication of an FPGA-based array server. Background Technology

[0002] As server technology evolves towards multi-node clustering, array servers require sophisticated hardware management and I / O control for numerous computing modules. The core requirements focus on four dimensions: "large-scale I / O expansion," "precise instruction transmission," "real-time status monitoring," and "system stability and reliability." However, traditional array server I / O control schemes have significant shortcomings: 1. Hardware architecture redundancy: Traditional solutions often use multiple independent MCUs (microcontroller units) to control the computing modules, which not only leads to high hardware costs and large board space occupation, but also increases signal delay and failure risk due to the complex communication links between multiple devices. 2. Low instruction transmission efficiency: Traditional UART communication often uses multi-byte instructions (such as AT instructions), which have complex instruction structures and require cumbersome parsing logic from FPGA or MCU. The excessive length of instructions can easily lead to an increased transmission error rate, and the parsing time increases control delay. 3. Lack of effective fault tolerance and security mechanisms: Traditional solutions only handle instruction errors (such as frame header errors and address errors) by discarding them once, and cannot identify continuous errors, which can easily lead to loss of control of the computing module; at the same time, critical operations such as flashing lack linkage and interlock with the power status, which poses a risk of hardware damage or data writing errors caused by flashing while powered on. 4. Difficulty in status monitoring and maintenance: Traditional solutions are mostly one-way control of "instruction issuance-execution", lacking a real-time feedback mechanism for calculating module status. The BMC (Baseboard Management Controller) cannot grasp the module's operating status in real time, making it difficult to quickly trace the root cause after a fault occurs, resulting in low operation and maintenance efficiency. Summary of the Invention

[0003] This invention aims to solve the problems mentioned in the background art and provides a method for receiving 8Fs instructions and controlling IO in UART communication of an array server based on FPGA. It realizes large-scale IO expansion and instruction processing through a single FPGA and combines multi-dimensional verification, fault tolerance and status feedback design to solve the defects of traditional solutions.

[0004] The specific technical solution is as follows: A method for receiving and controlling 8Fs instructions in UART communication of an FPGA-based array server is characterized in that the method is used in an array server UART communication control system, the array server UART communication control system comprising: an FPGA main control unit, a BMC, and multiple computing modules; wherein, the BMC establishes bidirectional data communication with the FPGA main control unit through a UART communication interface, the FPGA main control unit integrates a GPIO expansion interface, and the GPIO expansion interface is electrically connected to each of the multiple computing modules in a one-to-one correspondence. The method includes the following steps: 1) The BMC generates 8Fs instructions and sends the 8Fs instructions to the FPGA main control unit through the UART communication interface; 2). After receiving the 8Fs instruction, the FPGA main control unit sequentially performs frame header verification, device address verification, and additional data verification; 3) If all the above checks pass, the FPGA main control unit parses the operation command in the 8Fs instruction and calls the preset channel mapping table to determine the computing module channel ID that matches the operation command; if any check fails, the FPGA main control unit records the corresponding error code and executes the preset fault tolerance operation. 4) The FPGA main control unit outputs IO control signals to the computing module corresponding to the channel ID through the GPIO expansion interface to realize the functional control of the computing module; 5) Simultaneously, the FPGA main control unit collects the real-time status data of the computing module, encapsulates the status data into response data in a preset format, and transmits it back to the BMC through the UART communication interface.

[0005] As a preferred embodiment of the present invention, the FPGA main control unit is model Ziguang Tongchuang PGL50H-6FG484. The FPGA main control unit expands 140 GPIO signals through internal logic resources, and the 140 GPIO signals constitute the GPIO expansion interface.

[0006] As a preferred embodiment of the present invention, the number of the plurality of computing modules is 20, the 140 GPIO signals are divided into 20 groups, each group of GPIO signals corresponds to one computing module, and each group of GPIO signals contains 7 independent GPIOs, which are used for power-on / off control, status reading and flashing operation of the computing module respectively.

[0007] As a preferred embodiment of the present invention, the communication parameters of the UART communication interface are: baud rate 115200bps, 8 data bits, no parity bit, and 1 stop bit; the 8Fs instruction is a single-byte hexadecimal instruction with instruction code 0x8F.

[0008] As a preferred embodiment of the present invention, the preset fault-tolerant operation in step 6) is as follows: when the FPGA main control unit receives 3 consecutive invalid instructions (the invalid instructions include frame header errors, device address errors, or operation instruction errors), an alarm trigger signal is generated and sent to the BMC through the UART communication interface, and the BMC activates an audible and visual alarm or a log alarm.

[0009] As a preferred embodiment of the present invention, the control response delay of the FPGA main control unit to the computing module is less than 1ms; the time for the UART communication interface to transmit a complete 8Fs instruction (including frame header, check field and additional data) does not exceed 87μs.

[0010] In a preferred embodiment of the present invention, the FPGA main control unit integrates a PLL clock module, a debounce module, a cmd_uart_tx module, and 20 CoreModules. The PLL clock module provides a stable 50MHz operating clock for the FPGA main control unit. The debounce module debounces the status signals fed back from the computing modules to eliminate signal jitter interference. The cmd_uart_tx module converts the encapsulated response data into UART protocol data and sends it to the BMC. Each of the 20 CoreModules corresponds one-to-one with one of the 20 computing modules, responsible for parsing the operation commands in the 8Fs instructions and generating corresponding IO control signals.

[0011] As a preferred embodiment of the present invention, the functions of each group of 7 GPIO signals are allocated as follows: 2 channels are used for power-on / off control of the computing module (1 channel is the power-on enable signal, and 1 channel is the power-off enable signal); 3 channels are used for status reading of the computing module (1 channel is the blade presence detection signal, 1 channel is the power-on status feedback signal, and 1 channel is the temperature sampling signal); and 2 channels are used for flashing operations of the computing module (1 channel is the flashing enable signal, and 1 channel is the flashing data transmission signal). Moreover, the flashing enable signal is interlocked with the power control signal of the computing module, and the flashing enable signal is only effective when the computing module is in a power-off state.

[0012] As a preferred embodiment of the present invention, the frame header verification in step 2) adopts the CRC16-CCITT verification algorithm to verify the frame header, number, additional data length, device address, control instructions and operation commands of the 8Fs instruction, totaling 6 bytes; the additional data verification adopts the CRC-32-IEEE802.3 verification algorithm to verify the additional data field of the 8Fs instruction; and the FPGA main control unit is also equipped with a status readback verification mechanism: after sending the IO control signal, the actual working status signal of the computing module is read back in real time and compared with the preset target control status. If the two are inconsistent, the IO control signal is resent until the status is consistent or the preset number of retries is reached (the number of retries does not exceed 3 times).

[0013] As a preferred embodiment of the present invention, the response data in step 5) is in 13-byte format, and the specific fields include: 1-byte slot address (identifying the corresponding computing module), 2-byte blade in-situ status data (bits 0 to 19 correspond to the in-situ status of 20 computing modules), 3-byte computing module power-on status data (bits 0 to 19 correspond to the power-on status of 20 computing modules), 4-byte first temperature data (corresponding to the core area temperature of the computing module), and 3-byte second temperature data (corresponding to the power supply area temperature of the computing module). After receiving the response data, the BMC matches the corresponding computing module based on the slot address, updates the status information of each computing module in real time, and stores it in the local log.

[0014] The present invention has the following beneficial effects: The present invention provides an FPGA-based UART communication method for 8Fs instruction reception and IO control in array servers. By constructing a bidirectional communication and control link between the BMC and the FPGA main control unit and the computing module, and combining a complete process of instruction verification, parsing, control, status feedback, and fault tolerance, the method achieves closed-loop management of array server UART instruction control. Multi-step verification (frame header, device address, and additional data verification) can filter invalid or erroneous instructions to avoid miscontrol. The channel mapping table ensures that operation commands accurately match the target computing module. Status feedback allows the BMC to monitor the computing module's operating status in real time. Fault-tolerant operation can trigger corresponding processing in case of anomalies. Furthermore, the integrated design of the FPGA main control unit eliminates the need for additional independent control or expansion chips, improving hardware resource utilization efficiency. Overall, the method significantly improves the accuracy, monitorability, and reliability of array server UART communication control. Attached Figure Description

[0015] Figure 1 A flowchart illustrating the method for receiving 8Fs instructions and controlling I / O in UART communication of an FPGA-based array server provided in this embodiment of the invention; Figure 2This is a schematic diagram of the physical connection of the BMC-FPGA-computing module in the FPGA-based array server UART communication receiving and IO control method provided in this embodiment of the invention. Figure 3 This is a protocol format diagram of the 8Fs instruction reception and IO control method in UART communication of an FPGA-based array server provided in an embodiment of the present invention. Detailed Implementation

[0016] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0017] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual images. They should not be construed as limiting the scope of this application. To better illustrate the embodiments of the present invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0018] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present application. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0019] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" or similar designation indicating a connection between components should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] Example This embodiment provides a method for receiving 8Fs instructions and controlling I / O in UART communication of an FPGA-based array server, such as... Figures 1-3As shown, this method is used in the UART communication control system of the array server. The UART communication control system of the array server includes: FPGA main control unit, BMC and multiple computing modules; wherein, the BMC establishes bidirectional data communication with the FPGA main control unit through the UART communication interface, the FPGA main control unit integrates GPIO expansion interface, and the GPIO expansion interface is electrically connected to multiple computing modules one by one. The method includes the following steps: 1) The BMC generates 8Fs instructions and sends them to the FPGA main control unit via the UART communication interface; 2) After receiving the 8Fs instruction, the FPGA main control unit sequentially performs frame header verification, device address verification, and additional data verification; 3) If all the above checks pass, the FPGA main control unit parses the operation command in the 8Fs instruction and calls the preset channel mapping table to determine the calculation module channel ID that matches the operation command; if any check fails, the FPGA main control unit records the corresponding error code and executes the preset fault tolerance operation. 4) The FPGA main control unit outputs IO control signals to the computing module corresponding to the channel ID through the GPIO expansion interface to realize the functional control of the computing module; 5) Simultaneously, the FPGA main control unit collects real-time status data from the computing module, encapsulates the status data into response data in a preset format, and transmits it back to the BMC via the UART communication interface; 6) The FPGA main control unit has a built-in dynamic verification threshold adjustment module: It counts the bit error rate of the UART communication link in real time. When the bit error rate is >0.5%, it automatically increases the threshold of "continuous invalid instruction trigger alarm" from 3 times to 5 times to avoid false alarms caused by link interference. When the bit error rate is ≤0.1%, the threshold drops back to 3 times to ensure timely response to anomalies. When the bit error rate is in the range of 0.1% to 0.5%, the threshold is maintained at 4 times to achieve a dynamic balance between fault tolerance sensitivity and anti-interference capability. The bit error rate is calculated by the ratio of the number of CRC check failures within 100ms to the total number of instructions.

[0021] This solution establishes a bidirectional communication and control link between the BMC (Browser Control Center) and the FPGA main control unit, and the computing module. Combined with a complete process of instruction verification, parsing, control, status feedback, and fault tolerance, it achieves closed-loop management of UART instruction control in the array server. Specifically, multi-step verification (frame header, device address, and additional data verification) filters invalid or erroneous instructions, preventing miscontrol; the channel mapping table ensures accurate matching of operation commands to the target computing module; status feedback allows the BMC to monitor the computing module's operating status in real time; and fault-tolerant operations trigger corresponding processing in case of anomalies. Overall, this significantly improves the accuracy, monitorability, and reliability of UART communication control in the array server.

[0022] Among them, the dynamic verification threshold adjustment module adaptively adjusts the "continuous invalid command trigger alarm" threshold by statistically analyzing the bit error rate of the UART communication link in real time (the ratio of the number of CRC check failures to the total number of commands within 100ms). The threshold is adjusted from 3 to 5 times when the bit error rate is >0.5%, from 5 to 3 times when it is ≤0.1%, and remains at 4 times when it is 0.1%~0.5%. This effectively balances fault tolerance sensitivity and anti-interference capability, avoids the problems of "link interference false alarm" or "continuous abnormal missed alarm" caused by traditional fixed thresholds, and improves the adaptability of the system's fault tolerance mechanism.

[0023] Specifically, in this embodiment, the FPGA main control unit is model PGL50H-6FG484 from Unisoc. This FPGA main control unit expands 140 GPIO signals through internal logic resources, and these 140 GPIO signals constitute a GPIO expansion interface. The FPGA main control unit also integrates an AI anomaly prediction module. This module is based on a lightweight decision tree model and collects three types of data in real time: historical instruction error rate, temperature fluctuation amplitude of the calculation module, and power-on state switching frequency. When the model outputs "fault risk probability > 80%", it generates a warning signal in advance and sends it back to the BMC. For example, if the temperature fluctuation of a certain calculation module exceeds 5°C within 10 minutes and the power-on switching occurs more than twice, it predicts that the power module of the module may be abnormal, and the BMC pushes an operation and maintenance reminder in advance, realizing the upgrade from "passive alarm" to "active prevention".

[0024] This solution designates the FPGA main control unit as the Ziguang Tongchuang PGL50H-6FG484 and utilizes its internal logic resources to expand 140 GPIO channels to form an expansion interface. On the one hand, it leverages the hardware resource advantages of this FPGA model to ensure the stability and sufficiency of GPIO expansion; on the other hand, it eliminates the need for additional independent GPIO expansion chips, simplifying the hardware architecture, reducing hardware costs and board space occupation. At the same time, the integrated design of the FPGA also reduces communication latency between multiple devices, providing reliable hardware support for the subsequent control of multiple computing modules.

[0025] Among them, the AI ​​anomaly prediction module, based on a lightweight decision tree model, collects three types of data in real time: historical instruction error rate, temperature fluctuation range of the computing module, and power-on state switching frequency. When the probability of failure risk is greater than 80% (such as a module with a temperature fluctuation of more than 5°C within 10 minutes and more than 2 power-on switching), it generates a warning signal in advance and sends it back to the BMC, realizing the upgrade from "passive alarm after failure occurs" to "proactive prevention before failure occurs", which buys maintenance personnel time to deal with the problem, reduces the probability of hardware damage to the computing module, and enhances system reliability.

[0026] Specifically, in this embodiment, there are 20 computing modules, and the 140 GPIO signals are divided into 20 groups. Each group of GPIO signals corresponds to one computing module, and each group of GPIO signals contains 7 independent GPIOs, which are used for power-on / off control, status reading, and flashing operations of the computing modules. The FPGA main control unit also integrates a dynamic GPIO power supply optimization module: it automatically adjusts the power supply voltage of the corresponding GPIO group according to the working mode of the computing module (run / standby / power off) - the GPIO power supply is 3.3V when the module is running (to ensure the driving capability of the control signals), it drops to 1.8V when in standby (to reduce static power consumption), and the GPIO power supply is cut off when the module is powered off (to avoid leakage current loss). The GPIO power supply status and the power status of the computing modules are linked through internal logic, without the need for additional control instructions. A single array server can save about 5~8Wh of energy per day, which meets the requirements of green computing.

[0027] This solution divides 140 GPIO channels into 20 groups based on 20 computing modules. Each group has 7 GPIO channels, corresponding to the multi-dimensional control needs of a single computing module (power on / off, status reading, flashing). This solution achieves precise allocation and efficient utilization of GPIO resources. On one hand, the dedicated allocation of each GPIO group avoids control signal interference between different computing modules; on the other hand, the 7 GPIO channels cover the core operational needs of the computing modules without the need for additional control interfaces, ensuring comprehensive and independent control of each computing module and meeting the needs of multi-node server clusters for fine-grained management of individual modules.

[0028] The dynamic GPIO power supply optimization module automatically adjusts the power supply voltage of the corresponding GPIO group according to the working mode of the computing module (run / standby / shutdown). The module operates at 3.3V to ensure driving capability, operates at 1.8V to reduce static power consumption, and shuts down the power supply to avoid leakage. Furthermore, the GPIO power supply is linked with the module power status without the need for additional instructions. A single array server can save 5-8Wh of energy per day, which meets the requirements of green computing and solves the energy waste problem of traditional GPIO constant voltage power supply.

[0029] Specifically, in this embodiment, the communication parameters of the UART communication interface are: baud rate 115200bps, 8 data bits, no parity bit, and 1 stop bit; the 8Fs instruction is a single-byte hexadecimal instruction with the instruction code 0x8F; the FPGA main control unit has a built-in configurable multi-protocol conversion module that supports dynamic switching between UART and I2C / SPI protocols: when the BMC issues a "protocol switching instruction (0x0A + target protocol identifier)", the module automatically adjusts the interface timing and data format. For example, when switching to the I2C protocol, the baud rate is adapted to 100kHz / 400kHz, and when switching to the SPI protocol, it supports four modes such as CPOL=0 / CPHA=0. This design makes the FPGA compatible with BMCs from different manufacturers (some manufacturers' BMCs only support I2C / SPI), expanding the applicable scenarios of the solution and allowing it to be adapted to multiple models of array servers without changing the hardware.

[0030] This solution ensures a unified communication protocol between the BMC and the FPGA main control unit by clearly defining the standardized parameters (baud rate, data bits, etc.) of the UART communication interface, reducing communication failures or data distortion caused by parameter mismatches. Furthermore, defining the 8Fs instruction as a single-byte hexadecimal instruction (0x8F) simplifies the FPGA's instruction parsing logic and shortens the parsing time compared to traditional multi-byte instructions (such as AT instructions). At the same time, the single-byte format also reduces the probability of bit errors during instruction transmission, improving the efficiency of instruction transmission and parsing.

[0031] Among them, the configurable multi-protocol conversion module supports dynamic switching between UART and I2C / SPI protocols (triggered by the BMC issuing the "0x0A + target protocol identifier" command; I2C is compatible with 100kHz / 400kHz baud rates, and SPI supports four timing modes). It is compatible with BMCs from different manufacturers (some manufacturers' BMCs only support I2C / SPI), and can be adapted to multiple array server models without changing hardware. This breaks the limitation of traditional solutions that "only support UART", expanding the applicable scenarios and market versatility of the solution.

[0032] Specifically, in this embodiment, the fault-tolerant operation preset in step 6) is as follows: when the FPGA main control unit receives 3 consecutive invalid instructions (invalid instructions include frame header errors, device address errors, or operation instruction errors), an alarm trigger signal is generated and sent to the BMC through the UART communication interface, and the BMC activates an audible and visual alarm or a log alarm.

[0033] This solution employs a fault-tolerant design that triggers a BMC alarm after three consecutive invalid commands. This avoids false alarms triggered by a single invalid command and allows for timely detection of continuous command anomalies (such as frame header errors or address errors). Once the alarm signal is fed back to the BMC, the BMC activates audible and visual alarms or log alerts, enabling maintenance personnel to quickly detect system communication or command anomalies and intervene promptly for troubleshooting (such as checking the UART link or the BMC command generation module). This prevents the accumulation of anomalies from causing the computing module to malfunction or the system to fail, thus improving the system's fault warning capabilities and maintainability.

[0034] Specifically, in this embodiment, the control response delay of the FPGA main control unit to the computing module is less than 1ms; the time for the UART communication interface to transmit a complete 8Fs instruction (including frame header, check field and additional data) does not exceed 87μs.

[0035] This solution optimizes the control logic of the FPGA main control unit and the UART communication link to achieve rapid response and command transmission to the computing module. Rapid response ensures that the computing module can promptly execute control commands issued by the BMC (such as power on / off and status adjustments), meeting the array server's real-time control requirements. Rapid command transmission reduces the latency of commands in the link, mitigating control asynchrony issues caused by transmission delays and further improving the real-time performance and coordination of the system control.

[0036] Specifically, in this embodiment, the FPGA main control unit integrates a PLL clock module, a debounce module, a cmd_uart_tx module (UART command transmission), and 20 CoreModules (core control modules). The PLL clock module provides a stable 50MHz operating clock for the FPGA main control unit; the debounce module debouncing the status signals fed back from the computing modules eliminates signal jitter interference; the cmd_uart_tx module converts the encapsulated response data into UART protocol data and sends it to the BMC; and the 20 CoreModules correspond one-to-one with the 20 computing modules, responsible for parsing 8FS commands. The CoreModule generates corresponding IO control signals based on the operation commands in the instruction. It also has an instruction priority scheduling logic: operation commands are divided into three categories: "urgent level (e.g., emergency shutdown, over-temperature protection)," "normal level (e.g., power-on, status query)," and "low priority (e.g., flashing, parameter configuration)." Urgent level instructions are preemptively executed (interrupting current normal / low priority instructions), while normal and low priority instructions are executed in a FIFO queue. For example, when the FPGA is flashing the computing module (low priority), if it receives an over-temperature protection instruction (urgent level), it immediately pauses the flashing and executes shutdown control, further reducing the response latency to less than 200μs, ensuring the hardware safety of the computing module.

[0037] This solution integrates a PLL clock module, a debounce module, a cmd_uart_tx module, and 20 CoreModules within the FPGA main control unit. Each module has a clear division of labor and works collaboratively: the PLL module provides a stable clock, ensuring the normal operation of all logic circuits within the FPGA and preventing instruction parsing errors or control signal anomalies caused by clock instability; the debounce module eliminates jitter interference from the computing module's status signals, ensuring accurate status readings; the cmd_uart_tx module ensures stable transmission of response data according to the UART protocol, preventing data loss; and the 20 CoreModules correspond one-to-one with the computing modules, enabling dedicated control of each module, improving control accuracy and processing efficiency, optimizing the overall signal processing and control flow within the FPGA, and enhancing system stability.

[0038] The instruction priority scheduling logic divides operation commands into "emergency level (emergency shutdown, over-temperature protection)", "normal level (power-on, status query)" and "low priority (flashing, parameter configuration)". Emergency level instructions preemptively interrupt the execution of normal / low priority instructions (e.g., if an over-temperature instruction is received during flashing, flashing can be paused immediately to execute shutdown). The response latency is shortened to less than 200μs, avoiding hardware security risks caused by low priority instructions occupying resources and ensuring the safety of the computing module in abnormal scenarios.

[0039] Specifically, in this embodiment, the functions of each group of 7 GPIO signals are allocated as follows: 2 channels are used for power-on / off control of the computing module (1 channel for power-on enable signal, 1 channel for power-off enable signal), 3 channels are used for reading the status of the computing module (1 channel for blade presence detection signal, 1 channel for power-on status feedback signal, 1 channel for temperature sampling signal), and 2 channels are used for flashing operations of the computing module (1 channel for flashing enable signal, 1 channel for flashing data transmission signal); and the flashing enable signal is interlocked with the power control signal of the computing module, and the flashing enable signal is only effective when the computing module is in a power-off state; FP The GA main control unit also supports a secure mechanism for remote firmware upgrade (FOTA): the firmware upgrade package issued by the BMC must carry a digital signature of the SM2 national cryptographic algorithm. After receiving it, the FPGA verifies the legality of the signature through the built-in national cryptographic verification module. After the verification is successful, the firmware integrity is verified by CRC-32. During the upgrade process, a "dual-partition backup" strategy is adopted - the FPGA is divided into two firmware storage partitions, primary and backup. During the upgrade, the firmware is first written to the backup partition. After verification, the firmware is switched to the backup partition to run, avoiding the FPGA from being bricked due to upgrade interruption. This solves the problem of traditional local flashing requiring on-site operation and high risk.

[0040] This solution assigns clear functions to each group of 7 GPIOs (power on / off, status reading, flashing), making the role of each GPIO clear and avoiding control errors caused by functional confusion. The interlock design between the flashing enable signal and the computing module power control signal prevents flashing operations from being performed while the computing module is powered on—avoiding potential hardware damage (such as chip burnout) or data writing errors (such as firmware flashing failure) that may be caused by power-on flashing. This ensures the safety of the flashing operation from the control logic level, while also ensuring the independence and accuracy of operations such as power on / off and status reading.

[0041] Among them, the remote FOTA security mechanism requires that the firmware upgrade package issued by BMC must carry the SM2 national cryptographic algorithm digital signature. After the FPGA verifies the legality through the built-in national cryptographic verification module, the firmware integrity is verified by CRC-32. The upgrade adopts a "dual partition backup" strategy (write to the backup partition first, and switch to run after verification). This enables convenient remote firmware upgrades while avoiding the risk of FPGA "bricking" due to upgrade interruption, and solves the problem of low security caused by traditional local flashing requiring on-site operation.

[0042] Specifically, in this embodiment, in step 2), the frame header verification uses the CRC16-CCITT verification algorithm to verify the 6 bytes of the 8Fs instruction, including the frame header, number, additional data length, device address, control instructions, and operation commands; the additional data verification uses the CRC-32-IEEE802.3 verification algorithm to verify the additional data field of the 8Fs instruction; and the FPGA main control unit also has a status readback verification mechanism: after sending the IO control signal, the actual working status signal of the calculation module is read back in real time and compared with the preset target control status. If the two are inconsistent, the IO control signal is resent until the status is consistent or the preset number of retries is reached (the number of retries does not exceed 3 times, and the interval between each retrieval is 100μs / time).

[0043] This scheme employs the CRC16-CCITT algorithm to verify key fields of the instruction frame and the CRC-32-IEEE802.3 algorithm to verify additional data. The two verification algorithms target different data segments respectively, which can comprehensively cover data errors (such as byte loss and bit flipping) during instruction transmission, greatly improving the integrity and accuracy of instruction data. The status readback verification mechanism compares the "target control status" with the "actual working status" to promptly detect deviations in the execution of control instructions (such as execution failure caused by abnormal GPIO signal transmission), and corrects the deviations through the retry mechanism to ensure that the control instructions can be executed accurately in the end, further reducing the risk of errors at the signal transmission or hardware execution level.

[0044] Specifically, in this embodiment, the response data in step 5) is in 13-byte format, with specific fields including: 1-byte slot address (identifying the corresponding computing module), 2-byte blade in-situ status data (bits 0-19 correspond to the in-situ status of 20 computing modules), 3-byte computing module power-on status data (bits 0-19 correspond to the power-on status of 20 computing modules), 4-byte first temperature data (corresponding to the core area temperature of the computing module), and 3-byte second temperature data (corresponding to the power supply area temperature of the computing module). After receiving the response data, the BMC matches the corresponding computing module based on the slot address. The status information of each computing module is updated in real time and stored in the local log; the response data adds a "health score field (1 byte, value 0~100)": the FPGA calculates the health score based on the computing module's temperature (40%), power-on stable time (30%), and historical error count (30%). For example, the health score is 100 when the temperature is 35℃ (full score), the power-on stable time is 24h (full score), and the historical error count is 0 (full score); when the temperature exceeds the threshold (e.g., 85℃), the health score drops below 20. The BMC can directly use this field to quickly filter high-risk modules without secondary calculation, thus improving operation and maintenance efficiency.

[0045] This solution designs the response data in a 13-byte format, including slot address, in-situ status, power-on status, and temperature data. This allows the BMC to quickly match the corresponding computing module through the slot address and simultaneously obtain multi-dimensional status information (hardware in-situ, power supply, temperature) of the module at one time, eliminating the need to send multiple status query commands and improving status acquisition efficiency. The BMC updates the status information in real time and stores logs, which not only facilitates real-time monitoring of the operating status of each computing module by maintenance personnel, but also provides data support for subsequent fault diagnosis (such as tracing the time point of abnormal temperature or power-on failure), enhancing the system's monitorability and fault tracing capabilities.

[0046] Among them, the response data health score field adds a 1-byte health score (0~100 points, with temperature accounting for 40%, power-on stability time for 30%, and historical error count for 30%) to the 13-byte response data. For example, a score of 100 is given when the temperature is 35℃+, the power-on stability time is 24h+, and the historical error count is 0. When the temperature exceeds 85℃, the score is below 20. BMC can directly use this field to quickly filter high-risk modules without the need for secondary integration of multi-dimensional status data, which greatly improves operation and maintenance efficiency and simplifies the fault location process.

[0047] In summary, the working principle of this invention is to construct a bidirectional closed-loop control link of "BMC-FPGA main control unit-computing module", relying on the integrated logic processing capabilities of the FPGA to achieve efficient reception, parsing, execution, and status feedback of 8Fs instructions. The specific process is as follows: 1. Command generation and transmission: The BMC generates 8Fs instructions (single-byte hexadecimal instructions, with the core identifier being 0x8F) based on the management requirements of the array server (such as power on / off, flashing, and status query of the computing module), and sends the instructions to the FPGA main control unit through the UART communication interface with preset parameters (a unified protocol ensures communication compatibility); 2. Multi-dimensional instruction verification: After receiving the 8Fs instruction, the FPGA main control unit first performs a three-level verification: 2.1 Frame header verification (using CRC16-CCITT algorithm): Verify the frame header, number, additional data length, device address, control instructions and operation command fields of the instruction to filter frame structure errors; 2.2 Device Address Verification: Verify whether the device address in the instruction matches the FPGA's own address (e.g., 0x01 corresponds to FPGA1) to avoid erroneous control across devices; 2.3 Additional Data Verification (using CRC-32-IEEE802.3 algorithm): Verify the additional data in the instruction (such as target module slot information) to ensure data integrity; 3. Instruction parsing and target matching: If all three levels of verification pass, the FPGA main control unit parses the operation command in the 8Fs instruction, calls the preset "channel mapping table" (pre-stores the correspondence between computing modules and GPIO channels), and determines the computing module channel ID that matches the operation command; During this process, the 20 CoreModules inside the FPGA (corresponding one-to-one with the 20 computing modules) are responsible for dedicated instruction parsing and control signal generation, avoiding control conflicts between multiple modules; 4. IO control signal output: The FPGA main control unit outputs IO control signals to the computing module corresponding to the target channel ID through its extended 140 GPIO interfaces (divided into 20 groups according to 20 computing modules, with 7 GPIOs in each group), realizing functions such as power on / off and flashing. The PLL clock module inside the FPGA provides a stable clock to ensure accurate timing of control signals; the debounce module performs debouncing on the status signals fed back by the calculation module to avoid misjudgments caused by signal jitter. 5. Status Acquisition and Response Feedback: While outputting control signals, the FPGA main control unit acquires real-time status data (such as on-state, power-on, and temperature data) from the computing module, encapsulates it into response data according to a preset format (including slot address and status field), and transmits it back to the BMC through the UART communication interface to realize the "control-status feedback" closed loop. 6. Fault tolerance: If any verification fails (such as frame header error or device address mismatch), the FPGA main control unit records the corresponding error code (such as a specific code value corresponding to a frame header verification error); when three invalid instructions are received consecutively, an alarm trigger signal is generated and sent back to the BMC, which then activates the alarm mechanism to prevent the accumulation of abnormalities from causing system failure.

[0048] How to use This method requires both hardware deployment and software configuration. The process is clear and easy to maintain. The specific steps are as follows: 1. Hardware deployment: Establish the physical connection of "BMC-FPGA-Computing Module": Connect the UART transmit / receive pins of the BMC to the UART interface pins of the FPGA main control unit (model: Ziguang Tongchuang PGL50H-6FG484) to achieve bidirectional communication; Divide the 140 GPIO interfaces of the FPGA into 20 groups, with each group of 7 GPIOs electrically connected to the control pins (power on / off, status detection, flashing interface) of one computing module, ensuring that each group of GPIOs corresponds to a single computing module. 2. Parameter configuration and logic preset: Configure UART communication parameters: Set the UART communication protocol (baud rate, data bits, parity bits, stop bits) in both BMC and FPGA to ensure protocol compatibility; The key logic is preset inside the FPGA: write the channel mapping table (to clarify the correspondence between the computing module ID and the GPIO channel), the verification algorithm (CRC16-CCITT, CRC-32-IEEE802.3), the fault tolerance rule (triggering an alarm after 3 consecutive invalid instructions) and the response data encapsulation format; 3. Command issuance and automatic control: Maintenance personnel can generate 8Fs instructions for the target operation (such as "Power on computing module 1" or "Read the temperature of computing module 5") through the BMC's management interface or control program. The BMC will automatically send the instructions to the FPGA via the UART interface. After receiving the command, the FPGA automatically performs multi-dimensional verification, command parsing, target module matching, and IO control signal output without manual intervention, thus completing the control of the computing module. 4. Status monitoring and data viewing: The BMC receives the response data transmitted back from the FPGA in real time, parses it, and displays information such as the presence status, power-on status, and temperature of each computing module on the management interface, allowing maintenance personnel to intuitively grasp the operating status of the array server. BMC automatically stores the received status data in the local log to form a historical record for easy tracing later. 5. Troubleshooting and Maintenance: When the BMC receives an alarm signal from the FPGA (such as a continuous invalid instruction alarm), the maintenance personnel can locate the abnormal link based on the alarm information: if it is an instruction error, check the BMC's 8Fs instruction generation logic; if it is a communication abnormality, check the UART link between the BMC and the FPGA (such as pin connection, cable integrity); if it is a module status abnormality, issue a status query command through the BMC to further locate the faulty module.

[0049] The overall technical effects of this invention are as follows: This invention addresses the pain points of traditional array server I / O control from multiple dimensions through "hardware integrated design + fine-grained instruction processing + closed-loop control implementation." The technical effects can be summarized in the following five points: 1. Improve control accuracy and precision The solution filters invalid or erroneous commands through "multi-dimensional verification (frame header, device address, and additional data)" to avoid miscontrol due to command anomalies; it ensures that operation commands are accurately matched to the target computing module through "channel mapping table + dedicated CoreModule" without cross-module interference; and it corrects signal transmission or execution deviations through "status readback verification" (reading back the actual status after sending the control signal and comparing it with the target status) to ensure that control commands are accurately implemented and significantly reduce the risk of misoperation.

[0050] 2. Enhance system reliability and stability A single FPGA main control unit replaces the traditional multi-MCU design, reducing the number of hardware components and communication link nodes, and lowering the latency and failure probability between multiple components. The FPGA integrates a PLL clock module and a debounce module to ensure clock stability and status signal jitter-free operation, respectively, avoiding control failures caused by timing abnormalities or signal interference. The fault-tolerant design of "continuous invalid instruction alarm" can promptly capture continuous abnormalities, preventing the accumulation of abnormalities from causing the computing module to go out of control or the system to fail, thus improving overall stability.

[0051] 3. Optimize hardware resource utilization efficiency Leveraging the 140-channel GPIO expansion capability of the Ziguang Tongchuang PGL50H-6FG484FPGA, the GPIOs are grouped and allocated according to the needs of 20 computing modules, achieving efficient utilization of GPIO resources without the need for additional independent GPIO expansion chips. A single FPGA undertakes multiple functions such as "instruction parsing, IO control, and status acquisition", simplifying the hardware architecture, reducing board space occupation and hardware costs, and is more resource-efficient than traditional multi-MCU solutions.

[0052] 4. Ensure the safety of critical operations The solution is designed with "interlocking between the flashing enable signal and the computing module power control signal". The flashing enable signal is only effective when the computing module is powered off, thus preventing hardware burnout or firmware writing errors caused by power-on flashing from the control logic level. Two verification algorithms (CRC16-CCITT and CRC-32-IEEE802.3) cover key fields of the instruction and additional data respectively, comprehensively preventing errors such as byte loss and bit flipping during data transmission, and ensuring the security of instruction and status data.

[0053] 5. Improve monitorability and maintainability The "real-time status feedback" mechanism enables the BMC to obtain multi-dimensional status information such as the presence, power-on, and temperature of the computing module in real time, with no monitoring blind spots; the BMC's log storage function provides data support for fault tracing, and maintenance personnel can locate the time and link of the fault through historical records; "abnormal alarms" can quickly trigger maintenance intervention without the need for continuous manual inspection, which greatly improves the efficiency of fault diagnosis and reduces maintenance costs.

[0054] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for receiving 8Fs instruction and IO control in FPGA-based array server UART communication, characterized in that, The method is used for an array server UART communication control system, and the array server UART communication control system comprises an FPGA master control unit, a BMC and a plurality of computing modules; wherein the BMC establishes bidirectional data communication with the FPGA master control unit through a UART communication interface, the FPGA master control unit is integrated with a GPIO expansion interface, and the GPIO expansion interface is electrically connected with the plurality of computing modules one by one; the method comprises the following steps: 1) The BMC generates an 8Fs instruction, and sends the 8Fs instruction to the FPGA master control unit through the UART communication interface; 2) After receiving the 8Fs instruction, the FPGA master control unit sequentially performs frame header verification, device address verification and additional data verification; 3) If all the verifications pass, the FPGA master control unit analyzes the operation command in the 8Fs instruction, calls a preset channel mapping table to determine the computing module channel ID matched with the operation command; if any verification fails, the FPGA master control unit records the corresponding error code and performs a preset fault-tolerant operation; 4) The FPGA master control unit outputs an IO control signal to the computing module corresponding to the channel ID through the GPIO expansion interface, so as to realize the function control of the computing module; 5) At the same time, the FPGA master control unit collects real-time state data of the computing module, encapsulates the state data into response data in a preset format, and returns the response data to the BMC through the UART communication interface.

2. The method of receiving 8Fs instruction in FPGA-based array server UART communication and IO control according to claim 1, characterized in that, The model of the FPGA master control unit is PGL50H-6FG484 of Zhejiang Zhihui Technology Co., Ltd., the FPGA master control unit expands 140 GPIO signals through internal logic resources, and the 140 GPIO signals constitute the GPIO expansion interface.

3. The method of receiving 8Fs instruction in FPGA-based array server UART communication and IO control according to claim 1, characterized in that, The number of the plurality of computing modules is 20, the 140 GPIO signals are divided into 20 groups, each group of GPIO signals corresponds to one computing module, and each group of GPIO signals comprises 7 independent GPIOs, which are respectively used for power-on / off control, state reading and flashing operation of the computing module.

4. The method of receiving 8Fs instruction in FPGA-based array server UART communication and IO control according to claim 1, characterized in that, The communication parameters of the UART communication interface are: baud rate 115200 bps, data bit 8 bits, no parity bit, and stop bit 1 bit; the 8Fs instruction is a single-byte hexadecimal instruction, and the instruction code is 0x8F.

5. The method of receiving 8Fs instruction in FPGA-based array server UART communication and IO control according to claim 1, characterized in that, The preset fault-tolerant operation in step 6) is that when the FPGA master control unit continuously receives 3 invalid instructions, an alarm trigger signal is generated and sent to the BMC through the UART communication interface, and the BMC starts audible and visual alarm or log alarm.

6. The method of receiving 8Fs instruction in FPGA-based array server UART communication and IO control according to claim 1, characterized in that, The control response delay of the FPGA master control unit to the computing module is less than 1 ms; and the time for the UART communication interface to transmit a complete 8Fs instruction is not more than 87 μs.

7. The method of receiving 8Fs instruction in FPGA-based array server UART communication and IO control according to claim 1, characterized in that, The FPGA master control unit is internally integrated with a PLL clock module, a debounce module, a cmd_uart_tx module and 20 CoreModules; wherein the PLL clock module provides a 50MHz stable working clock for the FPGA master control unit; the debounce module performs debouncing processing on the state signals fed back by the computing modules to eliminate signal jitter interference; the cmd_uart_tx module converts the encapsulated response data into UART protocol data and sends it to the BMC; the 20 CoreModules correspond to the 20 computing modules one by one, and are responsible for parsing the operation commands in the 8Fs instructions and generating corresponding IO control signals.

8. The method of receiving 8Fs instruction in FPGA-based array server UART communication and IO control according to claim 3, characterized in that, The function allocation of each group of 7-way GPIO signals is: 2-way for the on-off control of the computing module, 3-way for the state reading of the computing module, and 2-way for the flashing operation of the computing module; and the flashing enable signal and the power control signal of the computing module are interlocked, and the flashing enable signal can only be valid when the computing module is in a power-off state.

9. The method of receiving 8Fs instruction in FPGA-based array server UART communication and IO control according to claim 1, characterized in that, In step 2), the frame header check uses the CRC16-CCITT check algorithm to check the frame header, number, additional data length, device address, control instruction and operation command of the 8Fs instruction; the additional data check uses the CRC-32-IEEE802.3 check algorithm to check the additional data field of the 8Fs instruction; and the FPGA master control unit is also provided with a state read-back check mechanism: after sending the IO control signal, the actual working state signal of the computing module is read back in real time, compared with the preset target control state, and if they are inconsistent, the IO control signal is re-sent until the states are consistent or the preset retry number is reached.

10. The method for receiving 8Fs instruction and IO control in FPGA-based array server UART communication according to any one of claims 1-9, characterized in that, In step 5), the format of the response data is 13 bytes, and the specific fields include: 1 byte slot address, 2 bytes blade in-position state data, 3 bytes computing module power-on state data, 4 bytes first temperature data and 3 bytes second temperature data; after receiving the response data, the BMC matches the corresponding computing module based on the slot address, updates the state information of each computing module in real time and stores it to the local log.

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