FDIP-based novel instruction prefetching method and apparatus, and electronic device

Abstract

The invention provides a novel instruction prefetching method and device based on FDIP and electronic device.The method comprises the steps that after a target instruction block address enters a target instruction fetching queue, the target instruction block address is matched with a label array of instruction cache for the first time; when it is determined that an instruction block corresponding to the target instruction block address is in an instruction cache, locking a target cache line corresponding to the target instruction block address, and unlocking the target cache line after an instruction fetching process of the target instruction block address is completed; when the target instruction block becomes the first entry of the target fetch queue, the fetch unit obtains the target instruction block from the instruction cache. According to the scheme, after the branch predictor generates the target instruction block address, the target instruction block address only needs to be matched with the tag array once, so that access conflicts and dynamic power consumption caused by two times of matching can be avoided, additional area overhead is avoided, the performance of a CPU can be improved, and the power consumption of the CPU can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer architecture, and particularly relates to a new instruction prefetch method and device based on FDIP and electronic equipment. BACKGROUND

[0002] Fetch Directed Instruction Prefetch (FDIP) is based on decoupled Branch Predictor (BP) and Fetch. BP sends Fetch Block (FB) to Fetch Target Queue (FTQ), which is finally used by I-Cache. This decoupling operation enables BP to continue running in the case of Fetch Stall. FDIP initiates prefetch operation through FTQ, greatly reuses resources, and has relatively small additional overhead.

[0003] Figure 1 The existing FDIP prefetch scheme is shown in the schematic diagram. The decoupled Branch Predictor BP and Fetch unit, and FTQ are a FIFO queue that caches FB (Fetch Block) sent by Branch Predictor BP and then sends it to Fetch unit. FTQ is an intermediate component that links BP and Fetch unit. In the case that the current FB (Fetch Block) does not hit I-Cache, if the L2 bus is idle, PIQ (Prefetching Instruction Queue) is notified, and PIQ initiates a Cache Prefetch request to L2 cache. After the cache line returns data, it is placed in PREB (Prefetch Buffer). When the first FB (Fetch Block) in FTQ is processed, I-Cache is queried first. In the case that I-Cache does not hit, the first entry of PREB is queried. If PREB hits, data is obtained from PREB and written into I-Cache.

[0004] The existing FDIP prefetch scheme has the following two key shortcomings: 1. Accessing the TAG ARRAY twice will increase power consumption. Specifically, (1): When entering the FTQ, the TAG ARRAY needs to be read and it needs to be determined whether it is hit or miss. If it misses, it will enter the PIQ and wait for prefetching; (2): When the FB (Fetch Block) becomes the first FTQ entry, the TAG ARRAY also needs to be read and it needs to be determined whether it is hit or miss. If it misses, the PIQ will initiate a prefetch request to the L2Cache and wait for the prefetch result. If it hits, the instruction fetching operation will be performed normally.

[0005] 2. Using PREB incurs additional space overhead. The two accesses to TAGARAY mentioned above also cause access conflicts. Existing technologies have designed TAGARAY to address this issue, which, while resolving access conflicts, results in a significant increase in space overhead. Summary of the Invention

[0006] This specification provides a novel instruction prefetching method, apparatus, and electronic device based on FDIP to solve the problems of increased power consumption and additional area overhead caused by two accesses to the TAG ARRAY in existing FDIP prefetching schemes.

[0007] To address the aforementioned technical problems, this specification provides a novel instruction prefetching method based on FDIP, comprising: after a target instruction block address enters the target instruction fetch queue, first matching the target instruction block address with the tag array of the instruction cache; if it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, locking the target cache line corresponding to the target instruction block address, and unlocking the target cache line after completing the instruction fetch process for the target instruction block address; when the target instruction block becomes the first entry in the target instruction fetch queue, the instruction fetch unit retrieves the target instruction block from the instruction cache.

[0008] In some embodiments, determining that the instruction block corresponding to the target instruction block address is in the instruction cache includes: after the target instruction block address is first matched with the tag array of the instruction cache, if the target instruction block address hits the instruction cache, determining that the instruction block corresponding to the target instruction block address is in the instruction cache.

[0009] In some embodiments, when it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, locking the target cache line corresponding to the target instruction block address and unlocking the target cache line after completing the instruction fetch process of the target instruction block address includes: locking the target cache line corresponding to the target instruction block address when the target instruction block address hits the instruction cache, locking the target cache line after completing the instruction fetch process of the target instruction block address, and unlocking the target cache line after completing the instruction fetch process of the target instruction block address.

[0010] In some embodiments, determining that the instruction block corresponding to the target instruction block address is in the instruction cache includes: after initially matching the target instruction block address with the tag array of the instruction cache, if the target instruction block address does not hit the instruction cache, retrieving the target instruction block corresponding to the target instruction block address from the secondary cache through a prefetching process; and storing the target instruction block in a cache line to be purged in the instruction cache, wherein the cache line to be purged is a cache line allocated for the target instruction block address after it is determined that the target instruction block address does not hit the instruction cache.

[0011] In some embodiments, when it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, the target cache line corresponding to the target instruction block address is locked, and the target cache line is unlocked after the instruction fetch process for the target instruction block address is completed. This includes: when the target instruction block address does not hit the instruction cache, selecting and locking the cache line to be evicted, obtaining the target instruction block corresponding to the target instruction block address from the secondary cache through a prefetch process, storing the target instruction block in the locked cache line to be evicted, updating the label array of the instruction cache through the address of the cache line to be evicted, and unlocking the target cache line after the instruction fetch process for the target instruction block address is completed.

[0012] In some embodiments, the method further includes: if the selected cache line to be purgeed is locked by the address of another instruction block being processed, first pausing and waiting for the fetch process of the other instruction block address to end and the cache line to be purgeed to be released, and then initiating a prefetch process for the target instruction block address.

[0013] In some embodiments, the method further includes: if the instruction block corresponding to the target instruction block address is not cacheable, first pausing until there is no ongoing instruction block retrieval request, and then initiating a target retrieval request for the instruction block corresponding to the target instruction block address; after initiating the target retrieval request, blocking subsequent instruction block retrieval requests.

[0014] In some embodiments, the method further includes: after selecting the cache line to be evicted, performing conflict detection; the conflict detection determines whether the cache line to be evicted is an instruction block address that was hit by the matching process of other instruction block addresses; if so, the matching process of the other instruction block addresses is treated as a miss.

[0015] The second aspect of this specification provides a novel instruction prefetching apparatus based on FDIP, comprising: a matching module, configured to match the target instruction block address with a tag array of the instruction cache for the first time after the target instruction block address enters the target instruction fetch queue; a locking module, configured to lock the target cache line corresponding to the target instruction block address when it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, and to unlock the target cache line after the instruction fetching process of the target instruction block address is completed; and an instruction fetching module, configured to fetch the target instruction block from the instruction cache when the target instruction block becomes the first entry in the target instruction fetch queue.

[0016] In some embodiments, determining that the instruction block corresponding to the target instruction block address is in the instruction cache includes: after the target instruction block address is first matched with the tag array of the instruction cache, if the target instruction block address hits the instruction cache, determining that the instruction block corresponding to the target instruction block address is in the instruction cache.

[0017] In some embodiments, the locking module includes: a first locking module, configured to lock the target cache line corresponding to the target instruction block address when the target instruction block address hits the instruction cache, lock the target cache line after completing the instruction fetch process of the target instruction block address, and unlock the target cache line after completing the instruction fetch process of the target instruction block address.

[0018] In some embodiments, determining that the instruction block corresponding to the target instruction block address is in the instruction cache includes: after initially matching the target instruction block address with the tag array of the instruction cache, if the target instruction block address does not hit the instruction cache, then retrieving the target instruction block corresponding to the target instruction block address from the secondary cache through a prefetching process; storing the target instruction block in the cache line to be purged in the instruction cache, wherein the cache line to be purged is the cache line allocated for the target instruction block address after determining that the target instruction block address does not hit the instruction cache.

[0019] In some embodiments, the locking module includes: a second locking module, configured to select and lock a cache line to be evicted when the target instruction block address does not hit the instruction cache; retrieve the target instruction block corresponding to the target instruction block address from the secondary cache through a prefetch process; store the target instruction block in the locked cache line to be evicted; update the tag array of the instruction cache through the address of the cache line to be evicted; and unlock the target cache line after completing the instruction fetch process for the target instruction block address.

[0020] In some embodiments, the apparatus further includes: a second pausing module, configured to, when the selected cache line to be purged is locked by other instruction block addresses being processed, first pause and wait for the instruction fetch process of the other instruction block address to end and the cache line to be purged to be released, and then initiate a prefetch process for the target instruction block address.

[0021] In some embodiments, the apparatus further includes: a first pausing module, configured to pause until there is no ongoing instruction block retrieval request when the instruction block corresponding to the target instruction block address is not cacheable, and then initiate a target retrieval request for the instruction block corresponding to the target instruction block address; and a blocking module, configured to block subsequent instruction block retrieval requests after initiating the target retrieval request.

[0022] In some embodiments, the apparatus further includes: a conflict detection module, configured to perform conflict detection after selecting cache lines to be evicted; the conflict detection determines whether the cache line to be evicted is an instruction block address that has been hit by a matching process of other instruction block addresses; and a processing module, configured to treat the matching process of other instruction block addresses as a miss if the cache line is an instruction block address that has been hit by a matching process of other instruction block addresses.

[0023] A third aspect of this specification provides an electronic device, comprising: a memory and a processor, wherein the processor and the memory are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to implement the novel instruction prefetching method based on FDIP as described in the first aspect.

[0024] A fourth aspect of this specification provides a computer storage medium storing computer program instructions, which, when executed, implement the steps of the novel instruction prefetching method based on FDIP as described in the first aspect.

[0025] This specification provides a computer program product in a fifth aspect, comprising a computer program that, when executed by a processor, implements the steps of the novel instruction prefetching method based on FDIP as described in the first aspect.

[0026] The novel instruction prefetching method based on FDIP provided in this specification requires only one match between the target instruction block address and the instruction cache tag array after the branch predictor (BP) generates the target instruction block address. This avoids access conflicts and dynamic power consumption caused by two matches, avoids additional area overhead, and thus improves CPU performance and reduces CPU power consumption.

[0027] This solution is still based on the FDIP prefetch algorithm, but it breaks through its limitations by reducing the number of TAG ARRAY matching operations. This reduces access conflicts in the fetch unit, resulting in gains in both power consumption and performance, with almost no additional area overhead.

[0028] This scheme matches the TAG ARRAY only once. Before the target instruction block address FB is processed by the instruction fetch unit, its corresponding physical address (such as way & set) will be locked. The locked physical address cannot be evicted until the target instruction block address FB is processed by the instruction fetch unit.

[0029] When a TAG ARRAY is missing, this invention directly allocates a physical address (such as set&way) and fills the TAG ARRAY with the physical address PA. Subsequent accesses can directly hit this physical address (such as set&way) and cannot be evicted from this physical address (such as set&way), thus directly avoiding scenarios such as multi-hit. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 A schematic diagram of an existing FDIP prefetch scheme; Figure 2 This is a schematic diagram of a novel instruction prefetching scheme based on FDIP. Figure 3 This is a flowchart illustrating one method of the novel instruction prefetching method based on FDIP provided in this specification. Figure 4 This is a flowchart illustrating another method for the novel instruction prefetching method based on FDIP provided in this specification. Figure 5A schematic diagram illustrating the state changes during the prefetch process and the actual instruction fetch process for the target cache line corresponding to the target instruction block address FB. Figure 6 This is a flowchart illustrating another method of the novel instruction prefetching method based on FDIP provided in this specification. Figure 7 This is a schematic diagram of the entire instruction fetch process in one embodiment; Figure 8 A timing diagram illustrating server-level CPU access to the tag array; Figure 9 A schematic diagram of an embodiment that conforms to the relative distance limit of the prefetch pointer; Figure 10 A schematic block diagram of a novel instruction prefetching device based on FDIP provided in this specification; Figure 11 This is a schematic diagram of the electronic device provided in this specification. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0033] Modern CPU storage systems are divided into innermost, middle, and outermost layers based on speed and capacity, from fastest to slowest. The innermost layer, also known as the L1 cache, is closest to the CPU core, has the fastest speed, and the smallest capacity, ranging from a few KB to tens of KB. The L1 cache is typically divided into an instruction cache (I-Cache) and a data cache (D-Cache). The middle layer, also known as the L2 cache, is slightly slower than the L1 cache but has a larger capacity, typically ranging from hundreds of KB to several MB. The outermost layer includes the L3 cache and main memory; some CPUs have an L3 cache. The L3 cache has a larger capacity than both L1 and L2 caches, ranging from several MB to tens of MB, and is shared by multiple cores. Main memory has the largest capacity, typically ranging from several GB to tens of GB, but is the slowest. The L2 cache is the backup for the L1 cache. When the CPU cannot find the required data / instruction in the L1 cache (also known as an "L1 cache miss"), it will first look in the L2 cache instead of directly accessing main memory.

[0034] The core of FDIP is to decouple the branch predictor (BP) and the fetch unit, allowing them to work in parallel. It utilizes a fetch target queue (FTQ) to temporarily store prediction results, and finally, the instruction block is efficiently retrieved from the instruction cache (I-Cache). In traditional architectures, the branch predictor (BP) and the fetch unit are bound together. The fetch unit must wait for the branch predictor (BP) to predict the address of the next instruction before it can fetch from the I-Cache; this serial execution is inefficient. In FDIP, the branch predictor (BP) can work independently and in advance, continuously predicting potentially needed instruction blocks without waiting for the fetch unit to complete. The fetch unit focuses on reading instructions from the I-Cache and also doesn't need to wait for the real-time results from the branch predictor (BP). The parallel processing of the branch predictor (BP) and the fetch unit significantly improves overall speed.

[0035] Specifically, the complete workflow of FDIP can be divided into three core steps: 1. The branch predictor (BP) predicts and generates instruction block addresses (FBs) (usually virtual addresses, which correspond to physical addresses). Based on historical instruction execution patterns, the BP predicts the instruction paths that may be executed in the future and generates the corresponding instruction block addresses. The instruction block address (FB) is a continuous range of instruction addresses and is the fetch target address for the instruction fetch unit. 2. The instruction block address (FB) is temporarily stored in the instruction fetch target queue (FTQ). 3. The instruction cache (I-Cache) reads the instruction block addresses (FBs) sequentially from the FTQ, retrieves the corresponding instruction blocks from its own storage based on the address range in the instruction block address (FB), and returns them to the instruction fetch unit. The instruction fetch unit then passes the instruction blocks to the subsequent instruction decoding and execution units. In FDIP, the instruction cache (I-Cache) does not need to wait for the real-time prediction results of the branch predictor (BP) but directly reads the existing instruction block addresses from the FTQ, improving instruction fetch efficiency.

[0036] The instruction cache (I-Cache) uses a tag array (TAG ARRAY) and a data array (Data ARRAY). The TAG ARRAY stores the address tags (specifically, physical addresses, PAs) of each instruction block in the I-Cache, quickly determining whether the target instruction block address (FB) exists in the I-Cache. In the FDIP architecture's instruction cache, data is divided into multiple cache lines (instruction blocks, corresponding to Fetch Blocks) for storage. Each instruction block cache line corresponds to a tag, which records the address information of the instruction block cache line. The TAG ARRAY is the centralized storage area for these tags. The Data ARRAY is the structure within the instruction cache (I-Cache) that stores the actual instruction block cache lines, corresponding one-to-one with the TAG ARRAY (each tag corresponds to one instruction block).

[0037] The basic storage unit of a cache is a cache line. When the CPU accesses memory, it reads / writes in units of cache lines, rather than accessing individual bytes or instructions. A request initiated by the CPU (such as the instruction fetch unit or data access unit) to a cache (L1 / L2 / L3) or memory for a specific cache line is called a cache line request. The purpose of a cache line request is to retrieve or update the data or instructions in that cache line.

[0038] The branch predictor (BP) predicts and generates instruction block addresses (FB), which are temporarily stored in the fetch target queue (FTQ). Each entry in the FTQ (one entry, one FB) represents a predicted instruction block address. The FTQ follows a first-in, first-out (FIFO) principle. Internally, the FTQ contains multiple sub-logic units, each responsible for different tasks, enabling parallel processing of "fetch service" and "prefetch prediction". The fetch service unit specifically handles the first instruction block address (FB) of the FTQ. Its core tasks are: passing the first instruction block address (FB) to the fetch unit (Fetch) to trigger the fetch request (fetch req); and cooperating with the fetch unit (Fetch) to complete the I-Cache / PREB hit lookup to ensure that the first instruction block address (FB) is fetched first (because this is the instruction block most urgently needed by the current pipeline). The prefetching and prediction unit is independent of the instruction fetching service unit. It specifically scans the non-first instruction block addresses (FBs) in the FTQ (usually the last few instruction block addresses in the queue). Its core task is to initiate prefetch access to these instruction block addresses (FBs), query the TAGARRAY to determine whether the instruction block address (FB) is in the I-Cache. If the I-Cache misses and the L2 bus is idle, it notifies the PIQ (Prefetching Instruction Queue) to initiate a prefetch request, loading the instruction block cache line corresponding to these instruction block addresses (FBs) into the PREB (Prefetch Buffer) to prepare for future retrieval.

[0039] The Instruction Prefetch Queue (PIQ) is a high-speed cache structure located at the front end of the CPU, specifically used to store the addresses (FBs) of prefetched instruction blocks. The core function of the PIQ is to prefetch instructions that may be executed in the future, reducing fetch stalls caused by cache misses. An Entry is a single storage unit within the PIQ, used to store the address (FB) of a prefetched instruction block (typically corresponding to a cache line). Each Entry contains address information, status flags (such as "prefetched," "pending execution," etc.), and other fields. Requesting a PIQ entry means that the CPU's prefetcher requests an available Entry from the PIQ to store a new prefetched instruction block address (FB). This is the first step in prefetching instructions, similar to reserving a space in a queue.

[0040] like Figure 1As shown, the existing FDIP prefetch scheme is as follows: the branch predictor (BP) predicts and generates instruction block addresses (FB), which are temporarily stored in the instruction fetch target queue (FTQ). When an instruction block address (FB) enters the FTQ, the prefetch prediction unit of the FTQ initiates a prefetch access for that instruction block address (FB). Specifically, the prefetch access includes: matching the instruction block address (FB) with the tag array (TAG ARRAY) of the I-Cache to quickly determine whether the instruction block address (FB) corresponding to the instruction block address (FB) exists in the I-Cache (i.e., whether the instruction block address (FB) hits or misses the I-Cache). If it exists (i.e., hits the I-Cache), the prefetch process is not triggered; if it does not exist (i.e., misses the I-Cache), the prefetch process is triggered.

[0041] The prefetch process is as follows: FTQ sends the address FB of the instruction block that was missed to PIQ. PIQ prefetches the instruction block cache line corresponding to the address FB from the L2 cache and sends the prefetch result to the prefetch cache PREB.

[0042] When the instruction block address FB becomes the first entry in the FTQ, the fetch unit fetches the instruction block address FB of the first entry in the FTQ and initiates an actual fetch access for that instruction block address FB. Since there is a time difference (which may be several clock cycles) between the prefetch access and the actual fetch, the state of the I-Cache may have changed during this time. These changes include: 1. The prefetch request may have been completed, and the instruction block cache line corresponding to the instruction block address FB has been loaded from the L2 cache into the I-Cache (in this case, matching the instruction block address FB with the tag array TAGARRAY of the I-Cache will result in a hit); 2. Other instruction fetching processes may have written the instruction block cache line corresponding to the instruction block address FB into the I-Cache (in this case, matching the instruction block address FB with the tag array TAGARRAY of the I-Cache will result in a hit); 3. Prefetching may not have been completed or may have failed, and the instruction block cache line corresponding to the instruction block address FB is not in the I-Cache (in this case, matching the instruction block address FB with the tag array TAGARRAY of the I-Cache will result in a miss, and the instruction block cache line corresponding to the instruction block address FB needs to be retrieved from the prefetch cache PREB or the L2 cache).

[0043] Based on the possible changes in the I-Cache state, during actual instruction fetching, the fetch unit first matches the instruction block address FB with the I-Cache's tag array TAG ARRAY to quickly determine whether the instruction block cache line corresponding to the instruction block address FB exists in the I-Cache (i.e., whether the instruction block address FB hits or misses the I-Cache). If it exists (i.e., hits the I-Cache), the instruction block cache line corresponding to the instruction block address FB is directly retrieved from the I-Cache, which improves the efficiency of instruction block retrieval. If it does not exist (i.e., misses the I-Cache), the fetch unit retrieves the instruction block cache line corresponding to the instruction block address FB from the prefetch cache PREB, and the retrieved instruction block cache line needs to be written into the I-Cache's data array Data ARRAY so that it can be hit during subsequent matching. If the instruction block cache line corresponding to the instruction block address FB is not found in the prefetch cache (PREB), the instruction fetch unit (Fetch) needs to fetch the instruction block cache line from the L2 cache. In this case, the instruction block fetching efficiency is the lowest.

[0044] As can be seen from the description of the existing FDIP prefetch schemes above, since the state of the I-Cache may change between the prefetch access and the actual instruction fetch, fetching an instruction block address FB in the FTQ of an FDIP prefetch scheme requires accessing the TAG ARRAY twice. These two accesses to the TAG ARRAY may conflict, thus affecting performance. To resolve the impact of the two access conflicts, a prefetch cache PREB needs to be set up, which incurs additional area overhead.

[0045] To address the increased power consumption and additional area overhead caused by the existing FDIP prefetch scheme that requires two accesses to the tag array (TAG ARRAY), this specification provides an FDIP prefetch scheme that only requires one access to the TAG ARRAY. This reduces access conflicts and dynamic power consumption of the TAG ARRAY, thereby improving CPU performance and reducing power consumption.

[0046] like Figure 2 and Figure 3 As shown, this specification provides a novel instruction prefetching method based on FDIP, including the following S10 to S30.

[0047] S10: After the target instruction block address enters the target instruction fetch queue, the target instruction block address is matched with the label array of the instruction cache for the first time.

[0048] The target instruction fetch queue is the FTQ mentioned above, which can be referred to in the description above and will not be repeated in this manual.

[0049] Instruction cache refers to the first-level cache, namely the I-Cache mentioned above. The I-Cache and its tag array TAGARRAY can be referred to in the above description, and will not be repeated in this manual.

[0050] The branch predictor (BP) predicts the instruction paths that may be executed in the future based on the historical instruction execution patterns, and then generates the instruction block addresses (FBs) corresponding to these instructions.

[0051] The first match refers to the process where, after the instruction block address (FB) enters the FTQ (Instruction Prefetch Queue), the FTQ's prefetching and prediction unit initiates a prefetch access to that instruction block address (FB), checking the TAG ARRAY to determine if the instruction block address (FB) is in the I-Cache. If the result of the first match is an I-Cache miss and the L2 bus is idle, the PIQ (Prefetching Instruction Queue) will be notified to initiate a prefetch request. In other words, the "first match" here is actually the matching of the instruction block address (FB) with the TAG ARRAY during the instruction prefetching phase, as described above, and not the matching during the actual instruction fetching phase.

[0052] S20: If it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, the target cache line corresponding to the target instruction block address is locked, and the target cache line is unlocked after the instruction fetch process of the target instruction block address is completed.

[0053] When locked, the target cache line cannot be evicted; when unlocked, the target cache line can be evicted.

[0054] After the target instruction block address is initially matched against the instruction cache tag array, there are two possible matching results: 1. The target instruction block address hits the instruction cache (I-Cache); 2. The target instruction block address does not hit the instruction cache (I-Cache). Accordingly, S20 also includes two cases.

[0055] In some embodiments, determining that the instruction block corresponding to the target instruction block address is in the instruction cache includes: after the target instruction block address is first matched with the tag array of the instruction cache, if the target instruction block address hits the instruction cache, determining that the instruction block corresponding to the target instruction block address is in the instruction cache.

[0056] Accordingly, such as Figure 4As shown, S20 includes S21: when the target instruction block address hits the instruction cache, the target cache line corresponding to the target instruction block address is locked, and the target cache line is locked after the instruction fetch process of the target instruction block address is completed, and the target cache line is unlocked after the instruction fetch process of the target instruction block address is completed.

[0057] Therefore, it can be seen that when the target instruction block address hits the instruction cache, the target cache line corresponding to the target instruction block address is in a locked state from the time the prefetch process matches until the actual instruction fetch process ends. Figure 5 The diagram illustrates the state changes of the target cache line corresponding to the target instruction block address FB during the prefetch and actual fetch processes.

[0058] The aforementioned "locking the target cache line corresponding to the target instruction block address" can be achieved by locking the target cache line using its physical address. For example, locking the set&way corresponding to the target instruction block address.

[0059] In some embodiments, determining that the instruction block corresponding to the target instruction block address is in the instruction cache includes: after initially matching the target instruction block address with the tag array of the instruction cache, if the target instruction block address does not hit the instruction cache, retrieving the target instruction block corresponding to the target instruction block address from the secondary cache through a prefetching process; and storing the target instruction block in a cache line to be purged in the instruction cache, wherein the cache line to be purged is a cache line allocated for the target instruction block address after it is determined that the target instruction block address does not hit the instruction cache.

[0060] "Allocating a cache line" and "fetching the target instruction block from the L2 cache" can be performed simultaneously. After allocating a cache line, the cache line to be purged can be locked before or after the target instruction block is stored in the cache line to be purged.

[0061] Allocating cache lines for the target instruction block address can be achieved by retrieving empty cache lines from the data array and using these empty cache lines as cache lines to be allocated for the target instruction block address. In the initial stages of instruction prefetching, some empty cache lines may exist, and this method can be used to allocate cache lines for the target instruction block address. Once no empty cache lines remain, other methods can be used to periodically clear some cache lines from the data cache.

[0062] Alternatively, a cache line can be allocated to the target instruction block address, or a cache line to be evicted can be selected from the data array and used as the cache line allocated to the target instruction block address.

[0063] The cache line to be purged can be selected after a miss is determined; or it can be selected after the target instruction block corresponding to the address of the target instruction block is obtained from the L2 cache through the prefetch process. For example, it can be selected before the target instruction block obtained from the L2 cache is backfilled into the Data ARRAY array of the instruction cache. After the cache line to be purged is selected, the target instruction block is backfilled into the cache line to be purged.

[0064] Accordingly, such as Figure 6 As shown, S20 includes S22: when the target instruction block address does not hit the instruction cache, select the cache line to be evicted and lock it, obtain the target instruction block corresponding to the target instruction block address from the secondary cache through a prefetch procedure, store the target instruction block into the locked cache line to be evicted, update the tag array of the instruction cache through the address of the cache line to be evicted; and unlock the target cache line after completing the instruction fetch procedure for the target instruction block address.

[0065] In the above S22, "obtaining the target instruction block corresponding to the address of the target instruction block from the L2 cache through the prefetch process" and "selecting and locking the cache line to be purged" can be executed synchronously.

[0066] The aforementioned "updating the tag array of the instruction cache using the address of the cache line to be cached" refers to using the address of the cache line to be cached as the storage address of the cache line corresponding to the target instruction block address FB, and updating the tag array TAG ARRAY of the instruction cache I-Cache accordingly. This process of updating the tag array TAG ARRAY can also be called backfilling.

[0067] Therefore, when the target instruction address does not hit the instruction cache, a new cache line (i.e., the address of the cache line to be purged mentioned above) is allocated for the prefetched instruction to store the prefetched instruction block, and the address of the newly allocated cache line is backfilled into the tag array TAG ARRAY. From the time the prefetch process matches until the actual instruction fetch, the newly allocated cache line remains locked. Figure 5 It can also serve as a schematic diagram of the state changes of a newly allocated cache line during the prefetch and actual instruction fetch processes.

[0068] The aforementioned "selecting and locking the cache lines to be evicted" can be achieved by locking the cache lines using their physical addresses. For example, selecting set&way to be evicted and locking set&way. Existing eviction strategies can be used to select the cache lines to be evicted, and this application does not improve upon them.

[0069] Figure 4 and Figure 6The processing methods for the two branches (target instruction address hit, instruction cache miss) are illustrated respectively. In some embodiments, Figure 4 , Figure 6 They can each exist separately in one embodiment, for Figure 4 or Figure 6 For branches not mentioned, existing technologies or other novel methods may be employed. In some embodiments, this may also include... Figure 4 and Figure 6 The processing methods for the two branches are shown.

[0070] S30: When the target instruction block becomes the first entry in the target fetch queue, the fetch unit retrieves the target instruction block from the instruction cache.

[0071] The target instruction fetch queue (FTQ) follows a first-in, first-out (FIFO) principle. The fetch unit prioritizes processing the first entry (i.e., the head entry) of the target instruction block address in the FTQ. For the target instruction block address to become the first entry in the target instruction fetch queue (FTQ), it means that the target instruction block address is the address of the instruction block that most urgently needs to be fetched by the fetch unit.

[0072] In S30, "the fetch unit obtains the target instruction block from the instruction cache" means that in the actual fetch process of the target instruction block address, the fetch unit can obtain the target instruction block corresponding to the target instruction block address from the instruction cache without performing a secondary matching between the target instruction block address and the tag array of the instruction cache.

[0073] The novel instruction prefetching method based on FDIP provided in this specification requires only one match between the target instruction block address and the instruction cache tag array after the branch predictor (BP) generates the target instruction block address. This avoids access conflicts and dynamic power consumption caused by two matches, avoids additional area overhead, and thus improves CPU performance and reduces CPU power consumption.

[0074] This solution is still based on the FDIP prefetch algorithm, but it breaks through its limitations by reducing the number of TAG ARRAY matching operations. This reduces access conflicts in the fetch unit, resulting in gains in both power consumption and performance, with almost no additional area overhead.

[0075] This scheme matches the TAG ARRAY only once. Before the target instruction block address FB is processed by the instruction fetch unit, its corresponding physical address (such as way & set) will be locked. The locked physical address cannot be evicted until the target instruction block address FB is processed by the instruction fetch unit.

[0076] When a TAG ARRAY is missing, this invention directly allocates a physical address (such as set&way) and fills the TAG ARRAY with the physical address PA. Subsequent accesses can directly hit this physical address (such as set&way) and cannot be evicted from this physical address (such as set&way), thus directly avoiding scenarios such as multi-hit.

[0077] In some embodiments, if the selected cache line to be purgeed is locked by the address of another instruction block being processed, the process first pauses and waits for the fetch process of the other instruction block address to finish and for the cache line to be purgeed to be released before initiating a prefetch process for the target instruction block address.

[0078] The above statement, "The selected cache line to be purgeed is locked by the address of another instruction block to be processed," can also be described as "The selected cache line to be purgeed is locked by the address of the preceding instruction block in the target fetch queue (FTQ)." The address of the preceding instruction block in the target fetch queue (FTQ) (FB) refers to the address of the instruction block that is currently being processed with the highest priority in the target fetch queue (FTQ).

[0079] like Figure 7 As shown, after the fetch unit initiates the fetch procedure for a target instruction block address FB in the FTQ, it matches the target instruction block address FB with the tag array TAG ARRAY of the I-Cache. If the target instruction block address FB hits the instruction cache I-Cache, the set and way corresponding to the hit instruction block address FB is directly locked. The set and way are released after the target instruction block address FB becomes the first entry in the FTQ and the fetch unit completes the actual fetching of the target instruction block address FB. If the target instruction block address FB does not hit the instruction cache I-Cache, the set and way of the cache line to be purgeed is selected, and the set and way of the cache line to be purgeed is used as the address of the cache line corresponding to the target instruction block address FB to update the tag array TAG ARRAY of the I-Cache.

[0080] If the target instruction block address FB does not hit the instruction cache I-Cache, the selected cache line to be cached may be locked in the target instruction fetch queue (FTQ) preceding instruction block address FB. In this case, it is necessary to pause stall and wait for it to release the lock before requesting a PIQ entry and initiating a cache line request to the L2 cache. After the cache line is returned, it is backfilled into the I-Cache data array Data ARRAY, and the corresponding set & way data in the data array Data ARRAY is accessed for instruction processing. After the instruction at the target instruction block address FB is processed, the lock of the set & way is released.

[0081] It is important to note that because the tag array (TAG ARRAY) has been updated in advance, even if the instruction block corresponding to the target instruction block address (FB) fails to be fetched by the instruction fetch unit and sent to the subsequent pipeline (e.g., a pipeline refresh occurs), the set and way will still be locked until the cache line is backfilled to the data array (DATA ARRAY) to release the set and way.

[0082] In some embodiments, if the instruction block corresponding to the target instruction block address is not cacheable, the process is first paused until there is no ongoing instruction block retrieval request, and then a target retrieval request for the instruction block corresponding to the target instruction block address is initiated; and after the target retrieval request is initiated, subsequent instruction block retrieval requests are blocked.

[0083] Data in certain memory areas (such as I / O device registers and special system memory) is not allowed to be cached; the raw address must be accessed directly, and the access result cannot be stored in the cache. Since the novel instruction prefetching method based on FDIP provided in this specification does not provide a cache area for caching prefetched instruction blocks, if a non-cacheable cache line request occurs, stalling must be initiated until there are no ongoing cache line requests before a non-cacheable cache line request can be initiated. After initiating this cache line request, all subsequent cache line requests must also be blocked. This is because cache lines may be returned out of order, and there is no prefetch cache area; therefore, subsequent cache line requests can only be allowed after the address (FB) of the non-cacheable instruction block has been processed by the instruction fetch unit. During the processing of a non-cacheable instruction block address (FB), if a subsequent instruction block address (FB) hits the tag array (TAG ARRAY), this logic will not affect the process; if a subsequent instruction block address (FB) does not hit the tag array (TAG ARRAY), stall will be paused until the non-cacheable instruction block address (FB) has been processed.

[0084] Figure 8 This is a timing diagram for server-level CPU access to the tag array (TAG ARRAY). Cycle-0, Cycle-1, Cycle-2, and Cycle-3 represent the first, second, third, and fourth clock cycles, respectively, while FB-X and FB-Y represent the addresses of two specific instruction blocks (FB) in the instruction fetch target queue (FTQ).

[0085] In the first clock cycle (Cycle-0), the instruction block address FB-X is selected to determine if it exists in the instruction cache (I-Cache); in the second clock cycle (Cycle-1), the instruction block address FB-X is matched with the tag array (TAG ARRAY) of the I-Cache; at the same time, the instruction block address FB-Y is selected to determine if it exists in the instruction cache (I-Cache).

[0086] In the third clock cycle (Cycle-2), processing is performed based on the matching result of instruction block address FB-X, including: if there is a hit, instruction block address FB-X waits for the instruction fetch unit to fetch and decode; if there is a miss, an instruction prefetch queue (PIQ) entry is requested, the instruction block cache line corresponding to instruction block address FB-X is obtained from the L2 cache, and the set & way to be evicted from the data array (Data ARRAY) of instruction cache I-Cache is selected, and the physical address (known) of the obtained cache line is written into the tag array of instruction cache I-Cache.

[0087] In the third clock cycle, Cycle-2, the selected instruction block address FB-Y is matched with the tag array TAGARRAY of the I-Cache.

[0088] After selecting the set and way to be evicted, conflict detection is required. If the set and way to be evicted happens to be the set and way that the instruction block address FB-Y is matched, then a miss must be handled for the instruction block address FB-Y.

[0089] In the fourth clock cycle (Cycle-3), processing is performed based on the matching result of instruction block address FB-Y, including: if there is a hit, instruction block address FB-Y waits for the instruction fetch unit to fetch and decode; if there is a miss, an instruction prefetch queue (PIQ) entry is requested, the instruction block cache line corresponding to instruction block address FB-Y is obtained from the L2 cache, and the set & way to be evicted from the data array (Data ARRAY) of instruction cache I-Cache is selected, and the physical address (known) of the obtained cache line is written into the tag array of instruction cache I-Cache.

[0090] The novel instruction prefetching method based on FDIP provided in this specification can still be optimized by limiting the prefetch range of existing FDIP prefetching algorithms. Assuming that the fetch target queue FTQ is a FIFO queue with a depth of 16, prefetching can be limited to the entries from the first instruction block address FB to the twelfth instruction block address FB in the fetch target queue FTQ. By limiting the relative distance of the prefetch pointers, prefetching too early or too late can be prevented. Figure 9 A schematic diagram of one embodiment that conforms to the relative distance limit of the prefetch pointer.

[0091] This specification also provides a novel instruction prefetching device based on FDIP, which can be used to implement the aforementioned novel instruction prefetching method based on FDIP. For example... Figure 10 As shown, the device includes a matching module 10, a locking module 20, and an instruction fetching module 30.

[0092] The matching module 10 is used to match the target instruction block address with the tag array of the instruction cache for the first time after the target instruction block address enters the target instruction fetch queue.

[0093] The locking module 20 is used to lock the target cache line corresponding to the target instruction block address when it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, and to unlock the target cache line after the instruction fetch process of the target instruction block address is completed.

[0094] The instruction fetch module 30 is used to fetch the target instruction block from the instruction cache when the target instruction block becomes the first entry in the target instruction fetch queue.

[0095] In some embodiments, determining that the instruction block corresponding to the target instruction block address is in the instruction cache includes: after the target instruction block address is first matched with the tag array of the instruction cache, if the target instruction block address hits the instruction cache, determining that the instruction block corresponding to the target instruction block address is in the instruction cache.

[0096] In some embodiments, the locking module includes a first locking module, configured to lock the target cache line corresponding to the target instruction block address when the target instruction block address hits the instruction cache, lock the target cache line after completing the instruction fetch process of the target instruction block address, and unlock the target cache line after completing the instruction fetch process of the target instruction block address.

[0097] In some embodiments, determining that the instruction block corresponding to the target instruction block address is in the instruction cache includes: after the target instruction block address is matched with the tag array of the instruction cache for the first time, if the target instruction block address does not hit the instruction cache, the target instruction block corresponding to the target instruction block address is obtained from the second-level cache through a prefetching process; the target instruction block is stored in the cache line to be queued in the instruction cache, wherein the cache line to be queued is the cache line selected and locked after it is determined that the target instruction block address does not hit the instruction cache.

[0098] In some embodiments, the locking module includes a second locking module, configured to select and lock a cache line to be evicted when the target instruction block address does not hit the instruction cache, retrieve the target instruction block corresponding to the target instruction block address from the secondary cache through a prefetch process, store the target instruction block into the locked cache line to be evicted, update the tag array of the instruction cache through the address of the cache line to be evicted, and unlock the target cache line after completing the instruction fetch process for the target instruction block address.

[0099] In some embodiments, the apparatus further includes a second pausing module, configured to, when the selected cache line to be purged is locked by other instruction block addresses being processed, first pause and wait for the instruction fetch process of the other instruction block addresses to end and the cache line to be purged to be released, and then initiate a prefetch process for the target instruction block address.

[0100] In some embodiments, the device further includes a first stagnation module and a blocking module.

[0101] The first stall module is used to stall until there are no ongoing instruction block retrieval requests when the instruction block corresponding to the target instruction block address is not cacheable, and then initiate a target retrieval request for the instruction block corresponding to the target instruction block address. The blocking module is used to block subsequent instruction block retrieval requests after the target retrieval request is initiated.

[0102] In some embodiments, the apparatus further includes a collision detection module and a processing module.

[0103] The conflict detection module performs conflict detection after selecting cache lines to be evicted; the conflict detection determines whether the cache line to be evicted is an instruction block address that has been matched by the matching process of other instruction block addresses. The processing module treats the matching process of other instruction block addresses as a miss if the cache line is an instruction block address that has been matched by the matching process of other instruction block addresses.

[0104] The descriptions and functions of the above devices can be found in the section on novel instruction prefetching methods based on FDIP, and will not be repeated here.

[0105] This invention also provides an electronic device, such as...Figure 11 As shown, the electronic device may include a processor 1101 and a memory 1102, wherein the processor 1101 and the memory 1102 may be connected via a bus or other means. Figure 11 Taking the example of a connection between China and Israel via a bus.

[0106] Processor 1101 may be a central processing unit (CPU). Processor 1101 may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations thereof.

[0107] Memory 1102, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the novel instruction prefetching method based on FDIP in this embodiment of the invention (e.g., Figure 10 The matching module 10, locking module 20, and instruction fetch module 30 are shown. The processor 1101 executes various functional applications and data processing by running non-transitory software programs, instructions, and modules stored in the memory 1102, thereby implementing the novel instruction prefetching method based on FDIP in the above method embodiments.

[0108] The memory 1102 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor 1101, etc. Furthermore, the memory 1102 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1102 may optionally include memory remotely located relative to the processor 1101, and these remote memories may be connected to the processor 1101 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0109] The one or more modules are stored in the memory 1102, and when executed by the processor 1101, the novel instruction prefetching method based on FDIP is executed.

[0110] The specific details of the above-mentioned electronic device can be understood by referring to the relevant descriptions and effects in the method embodiments, and will not be repeated here.

[0111] This specification also provides a computer storage medium storing computer program instructions, which, when executed, implement the steps of the novel instruction prefetching method based on FDIP described above.

[0112] This specification also provides a computer program product comprising a computer program that, when executed by a processor, implements the steps of the novel instruction prefetching method based on FDIP described above.

[0113] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0114] The various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, please refer to each other. The focus of each embodiment is to describe the differences from other embodiments.

[0115] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions.

[0116] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0117] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute certain parts of the methods of various embodiments of this application.

[0118] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc.

[0119] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0120] Although this application has been described through embodiments, those skilled in the art will know that this application has many modifications and variations without departing from the spirit of this application, and it is intended that the appended claims cover such modifications and variations without departing from the spirit of this application.

Claims

1. A novel instruction prefetching method based on FDIP, characterized in that, include: After the target instruction block address enters the target instruction fetch queue, the target instruction block address is matched with the label array of the instruction cache for the first time; If it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, the target cache line corresponding to the target instruction block address is locked, and the target cache line is unlocked after the instruction fetch process of the target instruction block address is completed. When the target instruction block becomes the first entry in the target fetch queue, the fetch unit retrieves the target instruction block from the instruction cache.

2. The method according to claim 1, characterized in that, Determining whether the instruction block corresponding to the target instruction block address is in the instruction cache includes: After the target instruction block address is matched against the instruction cache tag array for the first time, if the target instruction block address hits the instruction cache, it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache.

3. The method according to claim 1, characterized in that, If it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, the target cache line corresponding to the target instruction block address is locked, and the target cache line is unlocked after the instruction fetch process for the target instruction block address is completed, including: If the target instruction block address hits the instruction cache, the target cache line corresponding to the target instruction block address is locked, and the target cache line is locked after the instruction fetch process of the target instruction block address is completed, and the target cache line is unlocked after the instruction fetch process of the target instruction block address is completed.

4. The method according to claim 1, characterized in that, Determining whether the instruction block corresponding to the target instruction block address is in the instruction cache includes: After the target instruction block address is matched with the tag array of the instruction cache for the first time, if the target instruction block address does not hit the instruction cache, the target instruction block corresponding to the target instruction block address is obtained from the second-level cache through a prefetch process; The target instruction block is stored in the cache line to be purged in the instruction cache. The cache line to be purged is the cache line allocated for the target instruction block address after it is determined that the target instruction block address has not been hit in the instruction cache.

5. The method according to claim 1, characterized in that, If it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, the target cache line corresponding to the target instruction block address is locked, and the target cache line is unlocked after the instruction fetch process for the target instruction block address is completed, including: If the target instruction block address is not hit in the instruction cache, select the cache line to be evicted and lock it. Obtain the target instruction block corresponding to the target instruction block address from the L2 cache through a prefetch procedure, and store the target instruction block into the cache line to be evicted. Update the label array of the instruction cache with the address of the cache line to be evicted. After the instruction fetch procedure for the target instruction block address is completed, unlock the target cache line.

6. The method according to claim 4 or 5, characterized in that, The method further includes: If the selected cache line to be purge is locked by the address of another instruction block, the process first pauses and waits for the fetch process of the other instruction block address to finish and for the cache line to be purge to be released before initiating a prefetch process for the target instruction block address.

7. The method according to claim 4 or 5, characterized in that, The method further includes: If the instruction block corresponding to the target instruction block address is not cacheable, pause until there is no ongoing instruction block retrieval request, and then initiate the target retrieval request for the instruction block corresponding to the target instruction block address. After initiating the target acquisition request, subsequent instruction block acquisition requests are blocked.

8. The method according to claim 4 or 5, characterized in that, The method further includes: After selecting the cache lines to be evicted, conflict detection is performed; the conflict detection determines whether the cache lines to be evicted are instruction block addresses that have been matched by the address matching process of other instruction blocks. If so, the matching process for the addresses of the other instruction blocks will be treated as a miss.

9. A novel instruction prefetching device based on FDIP, characterized in that, include: The matching module is used to match the target instruction block address with the tag array of the instruction cache for the first time after the target instruction block address enters the target instruction fetch queue; The locking module is used to lock the target cache line corresponding to the target instruction block address when it is determined that the instruction block corresponding to the target instruction block address is in the instruction cache, and to unlock the target cache line after the instruction fetch process of the target instruction block address is completed. The instruction fetch module is used to retrieve the target instruction block from the instruction cache when the target instruction block becomes the first entry in the target instruction fetch queue.

10. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to implement the novel instruction prefetching method based on FDIP as described in any one of claims 1 to 8.

11. A computer storage medium, characterized in that, The computer storage medium stores computer program instructions, which, when executed, implement the steps of the novel instruction prefetching method based on FDIP as described in any one of claims 1 to 8.

12. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the steps of the novel instruction prefetching method based on FDIP as described in any one of claims 1 to 8.

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