Method for capturing LPDDR5 digital signal based on logic analyzer

Abstract

The invention relates to the technical field of data storage, and discloses an LPDDR5 digital signal capturing method based on a logic analyzer, and the method comprises the steps: carrying out ball mounting welding on CA signals and CS signals of A / B channels of LPDDR5 and to-be-tested instruments on a test board, and selecting corresponding plots according to the actual connection condition, the number of the to-be-tested instruments being eight; during connection, Plot is distributed according to actually connected signal lines, sampling clocks of each group of Plot are uniformly connected to a CKt / c signal, impedance of an instrument to be tested is set according to input impedance matching of a logic analyzer, the LPDDR5 adopts a PODL level standard, and a voltage threshold value of the instrument to be tested is set as VDDQ / 2; and a special protocol decoder of the LPDDR5 is loaded in logic analyzer software. According to the invention, the problem of functional faults or performance bottlenecks existing in the final positioning digital system is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, in particular to a method for grabbing LPDDR5 digital signals based on a logic analyzer. BACKGROUND

[0002] In the early stage of research and development and in the daily need to solve the abnormal boards sent by customers, the related logic commands of soldering and grabbing LPDDR5 are grabbed to analyze the multi-channel digital signals in the digital circuit, verify the correctness of different combinations of signals and the related timing relationship, help engineers verify whether it meets the design specification or locates the timing exception; verify the correctness of the signal, troubleshoot the timing problem, but there is a functional failure or performance bottleneck in the final positioning of the digital system. SUMMARY

[0003] The present application provides a method for grabbing LPDDR5 digital signals based on a logic analyzer, which can solve the technical problem of functional failure or performance bottleneck in the final positioning of the digital system.

[0004] To solve the above technical problems, one technical solution adopted by the present application is to provide a method for grabbing LPDDR5 digital signals based on a logic analyzer, which comprises: The CA signal and the CS signal of the A / B channel of the LPDDR5 are soldered with the instrument under test on the test board, and the corresponding plot is selected according to the actual connection, wherein the instrument under test has 8 plots; When connecting, the plot is allocated according to the actual connection of the signal line, the sampling clock of each group of plots is uniformly connected to the CK_t / c signal, the impedance of the instrument under test is set according to the input impedance matching of the logic analyzer, the LPDDR5 adopts the PODB level standard, and the voltage threshold of the instrument under test is set to VDDQ / 2; Load the special protocol decoder of the LPDDR5 in the logic analyzer software, wherein the special protocol decoder of the LPDDR5 is built-in command truth table and timing rules defined by JEDEC standard, select Chip according to the CA signal and the CS signal of the A / B channel, and complete the correct association of the special protocol decoder of the LPDDR5 with the physical channel and the logic signal; Create a bus in the logic analyzer software, and map the CA signal and the CS signal to the corresponding bits of the bus, respectively; Set the sampling threshold, bit width and polarity, and observe whether the signal has a jump; If the signal has a jump, the signal is normal; If the signal has no jump, check the soldering, power supply and controller initialization state.

[0005] The beneficial effects of the present application are: the embodiment converts the "cycle-by-cycle command comparison" from manual line-by-line comparison to software automatic verification by establishing a JEDEC standard command encoding library - the logic analyzer can automatically identify illegal encoding (such as 0_001100 without corresponding standard command), cycle violation (such as MODE REG WRITE only 1 cycle), and mark the abnormal type in the table, which improves the efficiency compared with manual verification, and avoids human error and misjudgment. For key timing parameters such as tCSCA, tRP, tRCD, the scheme does not need manual marking of waveforms and calculation of time difference - the software can automatically locate the CS# falling edge and CA stable point, combine the CK cycle conversion interval time, and generate a timing report containing "measurement value - standard threshold - compliance", which can compress the original 1-2 hours of timing analysis to 10-15 minutes, greatly shortening the test cycle. Subdivide the illegal command encoding into "no corresponding encoding", "cycle violation", "CS# level conflict" three categories, and associate possible causes (such as control chip logic error, signal attenuation), avoiding the "no direction trial and error" in traditional troubleshooting; at the same time, through the synchronous linkage of state table and waveform, the original waveform of the corresponding cycle can be viewed by clicking the abnormal command line, realizing the rapid tracing of "abnormal phenomenon - original signal". BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a flowchart of a method for capturing LPDDR5 digital signals based on a logic analyzer according to the first embodiment of the present application. DETAILED DESCRIPTION

[0007] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0008] The terms "comprise" and "have" and any variations thereof in the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed or can optionally include other steps or units inherent to these processes, methods, products or devices.

[0009] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a single alternative embodiment. One of skill in the art will understand that embodiments described herein can be combined with other embodiments in various ways.

[0010] Figure 1 is a flowchart of a method for capturing LPDDR5 digital signals based on a logic analyzer according to a first embodiment of the application. As shown in Figure 1 , the method comprises: Step 1, ball-bonding the CA signal and the CS signal of the A / B channel of the LPDDR5 to the device under test on the test board, and selecting the corresponding plot according to the actual connection, wherein the device under test has 8 plots in total; Step 2, assigning the plot according to the actual connection of the signal line, connecting the sampling clock of each group of plots to the CK_t / c signal, setting the impedance of the device under test according to the input impedance matching of the logic analyzer, and setting the voltage threshold of the device under test to VDDQ / 2, wherein the LPDDR5 adopts the P0DL level standard; Step 3, loading the special protocol decoder of the LPDDR5 in the logic analyzer software, wherein the special protocol decoder of the LPDDR5 is built-in with the command truth table and timing rules defined by the JEDEC standard, selecting the Chip according to the CA signal and the CS signal of the A / B channel, and completing the correct association of the physical channel and the logic signal of the special protocol decoder of the LPDDR5; Step 4, creating a bus in the logic analyzer software, and mapping the CA signal and the CS signal to the corresponding bits of the bus, respectively; Step 5, setting the sampling threshold, bit width, and polarity, and observing whether the signal has a jump; Step 6, if the signal has a jump, it means that the signal is normal; Step 7, if the signal has no jump, check the bonding, power supply, and controller initialization state.

[0011] Step 1 is to establish a stable and low-interference signal path between LPDDR5 and the instrument under test. First, locate the A / B channel key signals of the LPDDR5 chip on the test board, where the CA signal is the address control signal responsible for transmitting key information such as memory operation addresses and commands, and the CS signal is the chip select signal used to select the memory chip to be operated. Both are core control signals for LPDDR5 protocol interaction. When soldering, use micro solder balls with an appropriate signal frequency. Clean the test board pads and the instrument interface before soldering to remove oxidation and impurities. Strictly control the temperature and time during soldering to avoid damaging the chip pins or causing the pads to fall off. The 8 Plots provided by the instrument under test are independent signal acquisition channels. Select them according to actual testing needs, for example, the A channel CA signal and CS signal can occupy Plots 1-4, and the B channel corresponds to Plots 5-8. This ensures that signals in the same channel are concentrated and allocated, facilitating subsequent signal correlation and analysis, while avoiding signal interference caused by Plot cross-use.

[0012] Preparation: Prepare the LPDDR5 test board, instrument under test (such as a high-performance logic analyzer), appropriate micro solder balls (it is recommended to use 0.3mm-0.5mm diameter tin-lead solder balls or lead-free solder balls that match the LPDDR5 chip pin pitch), constant temperature soldering station (temperature range 200℃-300℃), microscope (magnification ≥50 times), anhydrous ethanol, and anti-static brush. Wear an anti-static bracelet to avoid static damage to the chip.

[0013] Pad cleaning: Use an anti-static brush to dip anhydrous ethanol and gently wipe the pads corresponding to the A / B channel CA signal and CS signal on the test board, as well as the Plot interface pads of the instrument under test, to remove surface oxidation, dust, and residual flux. After wiping, let it air dry to ensure that the pads are free of stains.

[0014] Ball placement and soldering operation: Place the solder balls on the target pads of the test board and heat them with the hot air gun of the constant temperature soldering station. Set the hot air temperature to 250℃-280℃ and the air speed to medium-low to avoid blowing the solder balls away. After the solder balls melt and fully fuse with the pads, stop heating and let the solder joints cool naturally to room temperature. After soldering, use a microscope to check the solder joints to ensure that there are no problems such as incomplete soldering (solder joints are not full, with gaps), continuous soldering (adjacent solder joints are short-circuited), and soldering (solder balls fall off).

[0015] The 8 plots of the instrument under test are independent acquisition channels, and the allocation should meet the requirements of "channel separation and function concentration". The recommended allocation scheme one (single-chip dual-channel test): A channel CS#, CA0-CA5 occupies Plot1-Plot7, and Plot8 is reserved as a backup channel; allocation scheme two (dual-chip single-channel test): CS# of chip 1, CA0-CA5 occupies Plot1-Plot7, and key signals of chip 2 occupy Plot8. Record the correspondence table of Plot and signal after allocation to avoid subsequent confusion.

[0016] Step 2 solves the consistency and accuracy of signal acquisition. Plot allocation needs to follow the "same group and same function" principle, grouping CA signals and CS signals of the same channel, and each group of Plot must be uniformly connected to the CK_t / c differential clock signal of LPDDR5. CK_t / c clock is the synchronization reference of LPDDR5, and uniform clock can ensure that all signals are sampled under the same time reference, avoiding signal timing deviation caused by asynchronous clock. In terms of impedance matching, the input impedance of the logic analyzer needs to be consistent with the output impedance of LPDDR5 signal. Usually, the characteristic impedance of LPDDR5 signal transmission line is 50Ω or 60Ω, and the input impedance parameter needs to be adjusted through the hardware setting interface of the instrument under test. Poor matching will cause signal reflection and distortion, affecting the test results. Voltage threshold setting strictly follows the PODL level standard of LPDDR5, and PODL level is a special level specification for low-power memory. Setting the threshold to VDDQ / 2 can accurately distinguish the high and low levels of the signal, and VDDQ is the I / O supply voltage of LPDDR5. This setting can maximize the adaptation of the swing range of LPDDR5 signal and improve the accuracy of high and low level identification.

[0017] Group the signals of the same function into a group of Plot, and the clock interface of each group of Plot must be directly soldered to the CK_t / c differential clock signal pin of LPDDR5, and is prohibited to be connected through a patch line to reduce clock delay. For example, the clock terminals of A channel group Plot1-Plot4 are soldered to CK_t pin, and the clock terminals of B channel group Plot5-Plot8 are soldered to CK_c pin, to ensure the symmetry of differential clock.

[0018] First, measure the characteristic impedance of the LPDDR5 signal transmission line with an impedance tester. The impedance standard for LPDDR5 is typically 50Ω±5Ω or 60Ω±5Ω. In the hardware configuration interface of the instrument under test, find the input impedance setting option and adjust the impedance value of the Plot to the measured value. For example, if the transmission line impedance is 50Ω, set the Plot input impedance to 50Ω. After completing the impedance matching, send the test signal through the signal generator and verify that there is no reflected waveform.

[0019] Confirm the PODL level standard version adopted by LPDDR5 (refer to JEDEC JESD209-5 specification). Under this standard, the VDDQ voltage range is typically 0.5V-1.1V (specific values are subject to the chip datasheet). Measure the actual VDDQ voltage value through the voltage detection point of the test board using a multimeter, calculate the specific value of VDDQ / 2, for example, if VDDQ=1.0V, set the voltage threshold to 0.5V, input this value in the threshold setting interface of the instrument under test, and save the configuration.

[0020] In step 3, the protocol decoder is the core tool for implementing the analysis of physical signals to protocol content. The core advantage of the LPDDR5 dedicated protocol decoder is that it has a complete command truth table and timing rules defined by JEDEC standard built-in. JEDEC standard is the authoritative specification in the memory industry, ensuring the universality and accuracy of the decoding results. After loading the decoder, select the corresponding Chip based on the actual connection of A / B channel CA signal and CS signal, i.e., determine the LPDDR5 chip number and channel attribution of the current test. The key operation is to correctly associate the physical channel with the logical signal, i.e., map the physical signal collected by the Plot of the instrument under test (e.g., Plot 1 corresponds to CA0 signal) to the logical signal name recognized by the decoder. If the association is incorrect, the decoder will not be able to correctly parse the command and address information, resulting in complete failure of subsequent analysis. This step requires checking each physical channel corresponding to the logical signal one by one to ensure no mismatch or missing.

[0021] Open the logic analyzer software and select the "LPDDR5" dedicated decoder in the "Protocol Decode" module (ensure that the software version supports the latest JEDEC standard, if not, upgrade the software patch). After loading, the software will automatically import the command truth table of LPDDR5 (including the level combination of all standard commands such as activation, read, write, precharge) and timing rules (such as threshold range of key timing parameters such as tRCD, tRP).

[0022] In the decoder interface, click "Channel Configuration" and select the target Chip (such as Chip0, Chip1) according to the number of LPDDR5 chips on the test board and the channel attribution. Then perform one-to-one mapping of physical channels and logical signals, for example, map Plot1 to CS#, Plot2 to CA0, Plot3 to CA1, …, and Plot7 to CA5. When mapping, check the "Signal Validity Verification" option. The software will automatically verify whether the mapping conforms to the protocol specification. If an error is prompted, recheck the correspondence between Plot and signal. After loading, import the datasheet of the test LPDDR5 chip and update the timing parameter reference value of the decoder to the nominal value of the chip, for example, update the tRFC parameter to 260ns specified by the chip to ensure that the timing judgment standard during decoding is consistent with the actual characteristics of the chip.

[0023] In Step 4, the purpose of bus creation is to integrate scattered individual signals into a logical bus that conforms to the LPDDR5 protocol, facilitating batch analysis and command recognition. In the logic analyzer software, when creating a new bus, you need to name and set the bus properties, then map the CA signals (CA0-CA5) and CS signals (CS#) to the corresponding bits of the bus. Mapping must strictly follow the bit definition of the control bus in the LPDDR5 protocol, for example, mapping CS# to the 0th bit of the bus, and CA0-CA5 to bits 1-6, respectively, to form a complete 7-bit control bus. Through the bus form, scattered level changes can be integrated into complete bus data, intuitively presenting the control signal combination of each memory operation, greatly improving signal analysis efficiency and avoiding tedious operations of analyzing individual signals one by one.

[0024] In the "Bus Edit" function of the logic analyzer software, click "New Bus" and name it "LPDDR5_CTRL_BUS" (control bus). Select "Parallel Bus" as the bus type and set the bit width to 7 bits. Click Confirm to create. According to the bus bit definition of the LPDDR5 protocol, map the signals to the bus bits in order. The standard mapping rule is: Bus Bit0→CS# signal, Bit1→CA0 signal, Bit2→CA1 signal, Bit3→CA2 signal, Bit4→CA3 signal, Bit5→CA4 signal, Bit6→CA5 signal. After mapping, click "Bus Preview" to view the real-time display of the bus signals and ensure that each bit's signal state is normally refreshed without lag or loss. Save the configured bus properties as a template file (the suffix is recommended to be.lpd5bus) for easy direct invocation in subsequent similar tests, reducing repetitive configuration work.

[0025] In step 5, the setting of the sampling parameters directly determines the accuracy of signal capture. The sampling threshold is again confirmed to be VDDQ / 2, consistent with the voltage threshold setting in step 2, forming a double guarantee to ensure the uniformity of high and low level judgment standards; the bit width is set to 7 bits, fully matching the signal combination of CS#+CA0-CA5, covering the core bit width of LPDDR5 control signals; the polarity setting needs to match the effective logic of the signal, CS# is a low-active signal, which means that when the level is low, the chip is selected, and CA signal is a high-active signal, which means that when the level is high, the signal is effective, and correct setting of the polarity can avoid misjudgment of the signal state by the decoder. After the parameter setting is completed, the logic analyzer is started for signal acquisition, focusing on observing whether the bus signal has normal toggling. Toggling is a basic feature of signal transmission, and normal LPDDR5 will produce regular toggling of CA signals and CS signals when changing commands after initialization or executing operation commands.

[0026] The sampling threshold is again confirmed to be VDDQ / 2, consistent with step 2.3, to avoid threshold conflicts; the bit width is fixed at 7 bits, corresponding to the complete control signal combination of CS#+CA0-CA5; the polarity setting strictly follows the signal definition, CS# is set to "low active" (check the "low level active" option in the software), and CA0-CA5 is set to "high active" (default high level active, no additional adjustment is needed). Select the "continuous sampling" mode, set the sampling frequency to 5-10 times the working frequency of LPDDR5, for example, if the memory working frequency is 6400Mbps, set the sampling frequency to 32Gbps to ensure complete capture of signal toggling details. The sampling duration is set to 10ms-100ms, taking into account data volume and analysis efficiency, to avoid missing toggling due to too short sampling duration. After starting sampling, view the bus waveform on the software waveform display interface. Under normal circumstances, after LPDDR5 is powered on and initialized, CS# will appear as a low-level pulse, and CA signals will produce regular high-low toggling with initialization commands. If the waveform shows a straight line (no level change), it is determined that there is no toggling; if the waveform has obvious high-low level alternation, it is determined that there is toggling.

[0027] In step 6, when regular toggling of CA signals and CS signals is observed, it can be determined that the signals are normal. "Normal" here has two meanings, one is that the signal transmission is normal at the physical layer, indicating that the ball mounting is reliable, the signal path has no open circuit or short circuit, and the hardware connection meets the requirements; the other is that the signal interaction is normal at the protocol layer, the memory controller has started to send control signals to the LPDDR5, and the chip is not in a completely silent state. The regularity of signal toggling can be judged in combination with the memory operation scenario, for example, a series of command signal toggling will occur during power-on initialization, and address signals and chip selection signals will toggle together during read / write operation.

[0028] Observe whether there is a jump, verify the regularity and compliance of the jump. Combined with the analysis result of the decoder, view the protocol command corresponding to the jump, such as the pre-charge command (CS# low, CA signal specific combination) that should appear in the initialization stage, the activation command, etc., and the command timing conforms to the JEDEC standard. Through the "signal statistics" function of the software, view the jump times, high-level duration, low-level duration, etc. Parameters, compared with the typical values in the chip datasheet, the deviation within ±10% is normal. At the same time, measure the phase difference between the clock signal and the CA signal to ensure that the phase deviation is within the allowed range to avoid timing violations.

[0029] In step 7, if the signal has no jump, the problem needs to be diagnosed from easy to difficult according to the priority. First, check the soldering situation. You can observe whether there is a virtual soldering, soldering or continuous soldering phenomenon of the solder ball through a microscope, which is the most common fault point in hardware connection. Second, check the power supply, focusing on checking whether the VDDQ (I / O power supply) and VDD (core power supply) voltages of the LPDDR5 are within the range specified by the JEDEC standard. Abnormal power supply voltage will cause the chip to malfunction and thus have no signal output. Finally, check the controller initialization state. The memory controller needs to complete the initialization configuration after power-on, including clock configuration, timing parameter configuration, chip identification, etc. If the initialization fails, the controller cannot send control signals to the LPDDR5, and you need to read the controller status register through the debugging tool to check whether the initialization program is executed successfully and the configuration parameters are correct.

[0030] Recheck all solder joints under microscope, focus on the solder joints of Plot and signal pin, clock pin. If there is a loose solder, reheat and repair. If there is a continuous tin, use a thin copper wire dipped in flux to remove excess solder. At the same time, use a multimeter to measure the continuity of the signal path. Set the multimeter to the buzzer range, connect one end of the signal pin and the other end of the Plot interface. If the buzzer is on, the path is normal, otherwise there is a break. Use a multimeter to measure the key voltages of LPDDR5, such as core power supply VDD, I / O power supply VDDQ, auxiliary power supply VDD2, etc. Compare with the standard voltage range of chip datasheet, for example, VDD standard is 0.8V±0.05V. If the measured value exceeds the range, check if the output of the power management chip (PMIC) is normal, check if there is a short circuit or open circuit in the power supply circuit, replace the faulty power chip or fuse. Connect the memory controller (such as the built-in memory controller of the CPU) through the debugger, read the status register of the controller (such as the initialization status register, error status register). If the register shows that the initialization is not completed, check the firmware configuration file of the controller, confirm that the clock frequency, channel enable, chip quantity and other parameter settings are correct, reprogram the firmware and restart the controller. If the register shows that there is an error code, locate the problem according to the error code table (such as channel error, command error, etc.), and repair it accordingly.

[0031] After step 4, the method further comprises: Set the preset details of sampling, where the preset details can be time or event. If only the boot-up process is captured, time is selected. If the error point is found from the log, event is selected. Time trigger is suitable for capturing the complete startup process. Set the delay time after power-on to start capturing (or use the loop capture mode to capture the entire initialization sequence); Set event trigger for known error points (such as system log error address 0x8000_0000 write failure). Set the trigger condition as "WRITE command + specific address" on the bus to achieve precise positioning.

[0032] Time trigger does not rely on specific signal state, only through time dimension control sampling start-stop, suitable for capturing the complete process of "hardware reset→initialization configuration→command interaction" after power-on of LPDDR5, especially suitable for scenarios without explicit error log and troubleshooting of signal abnormality in startup phase. First, the trigger delay time setting needs to be based on the power-on timing of the test board, and the preparation time of "power stabilization→controller startup→LPDDR5 response" needs to be reserved to avoid invalid data caused by too early sampling or missing key stage caused by too late sampling. Setting rule: if the test board completes power stabilization (VDD / VDDQ voltage reaches nominal value) within 100ms after power-on, set the trigger delay to 120ms-150ms; if the timing control includes a complex power management chip (PMIC), measure the interval time (recorded as T) between "power-on startup signal→LPDDR5 CK_t / c clock start output" through an oscilloscope, and set the trigger delay to T+20ms to ensure that LPDDR5 has entered a responsive state when sampling starts. Operation path: logic analyzer software→"sampling control"→"time trigger"→"delay time", input specific value (unit supports ms / μs, needs to be selected according to actual timing accuracy).

[0033] The sampling duration preset covers the complete initialization sequence of LPDDR5. According to JEDEC JESD209-5 specification, LPDDR5 initialization includes steps such as "PRECHARGE ALL→MRW configuration→ZQ calibration→ACTIVATE", and the total time consumption is usually 50ms-200ms (depending on the number of chips and configuration complexity).

[0034] Set single-chip dual-channel scenario: set the sampling duration to 100ms-150ms to ensure that all initialization commands are covered; multi-chip (≥2) scenario: set the sampling duration to 150ms-200ms to reserve inter-chip synchronization time; if capturing the first read / write operation after startup, it can be extended to 300ms to avoid missing the first command interaction after initialization.

[0035] When the boot process signal anomaly is intermittent (such as sporadic initialization failure), it is difficult to capture a single time trigger. Enable the loop collection mode, continuously monitor and automatically save the sampling data that meets the conditions. Loop period and number of times setting: loop period: set to "trigger delay time + sampling duration + 100ms", for example, trigger delay 150ms, sampling duration 100ms, then loop period is set to 350ms, to avoid overlapping of adjacent two sampling data; The number of cycles is set according to the test requirements, usually 10-20 times for mass production test (covering multiple rounds of boot verification), and 50 times for R&D debugging (to improve the probability of capturing anomalies), or check "infinite loop" and set "storage full automatically cover", continuously monitor until the anomaly is captured. The data saving rule enables the "conditional saving" function, which only saves the sampling data containing signal jump (triggered by the software "signal activity detection" function), filters out invalid data without signal change, and reduces storage occupation. For example, set "when the number of bus signal jumps ≥5 times, automatically save", to ensure that the saved data contains valid initialization process.

[0036] Event trigger starts sampling based on "specific signal combination / protocol command", suitable for system log has clear error scenario (such as address 0x8000_0000 write failure, specific command timeout), can accurately capture the signal waveform before and after the error occurs, and locate the root cause (such as command error, address mismatch, timing violation).

[0037] LPDDR5 WRITE command needs to be realized through CS# (active low) + CA signal (specific combination) + address signal, and event trigger needs to meet the "command type" and "address value" two conditions at the same time, to ensure the positioning of specific error operation.

[0038] In the logic analyzer software "event trigger"→"protocol condition", select "command type = WRITE", the software will automatically associate the WRITE command truth table in the LPDDR5 decoder (such as CS#=0, CA5-CA0=010100, for reference only, the specific standard is JEDEC), only when the command combination is captured, the next address judgment is entered.

[0039] If the test board has mapped the address 0x8000_0000 to a specific Bank / Row / Column of the LPDDR5 through software configuration, add "address parameter = 0x8000_0000" to the trigger condition and select the "exact match" mode; if there is bit width splitting of the address (such as the Row address occupying 16 bits and the Column address occupying 10 bits), according to the LPDDR5 address mapping rule, 0x8000_0000 is split into Row = 0x20000 and Column = 0x000, and the trigger values of the Row address bit and the Column address bit are set respectively to avoid matching failure caused by address splitting. To analyze the "cause and effect" of the error, the "pre-trigger duration" and the "post-trigger duration" need to be set: the pre-trigger duration is set to 1-5 ms to capture the signal state before the error command is sent (such as whether there is an abnormal pre-charge command, whether the clock is stable); the post-trigger duration is set to 5-10 ms to capture the response signal after the error command is sent (such as whether the LPDDR5 returns ACK, whether there is a timeout retransmission), which helps to determine whether the error is caused by abnormal feedback from the LPDDR5.

[0040] In addition to "specific address write failure", the event trigger condition can be flexibly configured according to the system log error type, as shown in Table 1: Time trigger verification: manually restart the test board and observe whether the logic analyzer starts sampling after the set delay time and whether the sampling data contains the signal jump of the LPDDR5 initialization stage; event trigger verification: actively send a target error operation (such as writing data to 0x8000_0000) through the test board software, observe whether the analyzer triggers sampling immediately, and whether the target command and address are included in the sampling data to ensure that there is no missing or mismatching of the trigger condition.

[0041] Before step 5, the method further comprises: According to the Nyquist theorem, set the sampling rate to be at least 2.5 times the highest frequency of the signal.

[0042] The LPDDR5 signal includes three types of core signals: differential clock signal (CK_t / c), control signal (CA / CS#), and data signal (DQ / DQS). The highest frequencies of different signals differ, and the sampling rate needs to be calculated according to the actual working frequency. The core basis is: Minimum sampling rate (Fs_min) = signal maximum frequency (F_signal_max) x 2.5 Wherein "2.5 times" is the engineering adaptation value, that is, it meets the 2 times bottom line requirement of Nyquist law, and reserves 0.5 times redundancy to cope with signal edge jitter, high frequency noise and other interference, and ensures that the waveform is aliasing-free.

[0043] According to the JEDEC JESD209-5 specification, the common working frequency (data rate) of LPDDR5 and the corresponding signal maximum frequency, sampling rate configuration are shown in Table 2: Note: LPDDR5 data rate is "double data rate" (DDR), that is, the data signal frequency is 2 times the clock frequency, so when calculating the sampling rate, the data signal maximum frequency should be used as the reference to avoid insufficient sampling rate caused by only referring to the clock frequency.

[0044] If the test involves both control signals and data signals (such as capturing the complete process of "command sending → data transmission"), the sampling rate is calculated based on the highest frequency signal (data signal), for example, the control signal frequency of 6400Mbps LPDDR5 is 1600MHz, and the data signal frequency is 3200MHz. It needs to be set at 3200MHz x 2.5 = 8Gsps to ensure that there is no aliasing in both types of signals.

[0045] Signal overclocking test scenario: If the test board verifies the LPDDR5 overclocking performance (such as data rate exceeding 8533Mbps), first measure the actual signal maximum frequency (avoid relying only on theoretical values) through an oscilloscope, and then calculate the sampling rate according to "actual maximum frequency x 2.5", for example, the actual data signal frequency is 4500MHz, then the sampling rate needs to be ≥11.25Gsps.

[0046] In combination with the previous time trigger and event trigger scenarios, the cooperative configuration rules of sampling rate and trigger mode are supplemented to ensure that the sampling rate meets the Nyquist law and adapts to the test requirements of different scenarios. Time trigger covers the complete booting / initialization process, and the sampling rate needs to be cooperatively set with "sampling time length" to avoid data overflow caused by too high sampling rate, or waveform distortion caused by too low sampling rate: Single sampling data volume (Byte) = sampling rate (Gsps) x sampling time length (s) x channel number x bit width per channel (Bit) / 8; Take "6400Mbps LPDDR5, 8 channels Plot, 16Bit per channel, 100ms sampling duration" as an example: Data volume = 10Gsps × 0.1s × 8 × 16Bit / 8 = 16GB; Ensure the storage capacity of the logic analyzer ≥ 16GB, if the storage is insufficient, appropriately reduce the sampling rate (such as to 8Gsps) or shorten the sampling duration (such as to 50ms) under the premise of meeting "Fs≥2.5×F_signal_max", balance data integrity and storage requirements.

[0047] Cyclic acquisition needs to continue multiple rounds of sampling, which may lead to rapid storage full if set at the highest sampling rate. The "dynamic sampling rate" strategy can be used: initialization phase (no high-frequency data transmission): set the sampling rate at 2.5 times the control signal frequency (e.g. 4Gsps for 6400Mbps LPDDR5); data transmission phase (high-frequency data interaction): automatically switch to a sampling rate of 2.5 times the data signal frequency (e.g. 10Gsps); achieved through the "segmented sampling" function of the logic analyzer, which meets the Nyquist theorem and reduces the amount of invalid data.

[0048] Event-triggered focused precise positioning of error points requires that high-frequency signals (such as data transmission anomalies) before and after the error occur can be captured completely. The core configuration rules are as follows: The "pre-trigger duration" and "post-trigger duration" of event-triggered need to be adjusted in combination with the sampling rate to ensure that enough signal periods are captured: pre-trigger duration: needs to include "10-20 signal periods before the error", for example, data signal frequency 3200MHz (period ≈ 0.3125ns), then the pre-trigger duration needs to be ≥ 10 × 0.3125ns = 3.125ns, calculated by 10Gsps sampling rate (sampling interval 0.1ns), pre-trigger data points ≥ 31, pre-trigger duration can be set to 5ns; post-trigger duration: needs to include "20-30 signal periods after the error", similarly, it can be set to 10ns, to ensure complete observation of the signal response after the error.

[0049] After setting the sampling rate, verify whether it meets the Nyquist theorem by the following steps to avoid substandard sampling rate due to hardware limitations or configuration errors: Use the logic analyzer to collect the DQ data signal of LPDDR5, and view the "rising edge / falling edge" details of the waveform in the software: if the waveform edge is clear, without ladder-shaped distortion (aliasing phenomenon), and the signal high-low level transition time meets the chip datasheet (such as rise time ≤ 50ps), it means that the sampling rate meets the standard; if the waveform overlaps and the edge is blurred, the sampling rate needs to be increased (such as from 8Gsps to 10Gsps) until the waveform is complete.

[0050] Input a sine wave signal of known frequency (consistent with the highest frequency of the LPDDR5 data signal, such as 3200MHz) to the logic analyzer through the signal generator; after collecting the waveform, use the "frequency analysis" function of the software to calculate the signal frequency. If the measured frequency deviates from the input frequency by ≤1% and there is no additional noise frequency (aliasing product), the sampling rate meets the requirements; if the deviation is more than 5% or noise appears, check if the sampling rate setting is correct or if the logic analyzer supports the sampling rate (some low-end devices may have a virtual sampling rate).

[0051] In the normal working state of LPDDR5, collect the complete process of "WRITE command→data write": if the timing relationship of "CS# pull-down→CA signal sending command→DQ signal transmitting data" can be clearly observed, and each bit of the data signal can be accurately identified (without bit loss or misjudgment), it means that the sampling rate is suitable for the actual test scenario; if the data bits cannot be distinguished (such as adjacent bit waveforms overlapping), increase by a ratio of "current sampling rate ×1.2" until the data is correctly identified.

[0052] Before step 5, the method further comprises: Introduce segmented storage technology, and record data only when the signal jumps.

[0053] Based on the sampling rate configuration based on the Nyquist theorem, introduce segmented storage technology (only trigger data recording when the signal jumps, and do not store during the non-jumping period), combined with the LPDDR5 signal jumping characteristics, supplement the technical principles, configuration steps, and coordination rules with the existing sampling system, while ensuring signal integrity, significantly reduce data storage occupancy, and adapt to long-time testing requirements under high sampling rate.

[0054] LPDDR5 signals have "active periods" (such as high-frequency jumps during command sending and data transmission) and "silent periods" (such as initialization gaps and stable levels during no operation). The segmented storage technology triggers storage through jump detection, and only retains active period data. The core logic is as follows: preset a "jump threshold" (such as signal level change ≥100mV to determine as valid jump, suitable for PODL level swing of LPDDR5) in the logic analyzer, and monitor the signal level of all acquisition channels in real time; when any channel detects a valid jump, immediately start data storage for that segment, and set a "segment timeout time" (such as 500ns). If there is no new jump within the timeout, the current segment is automatically ended and the next jump detection is entered. All segmented data are automatically spliced in timestamp order to form a complete "silent period omitted, active period complete" sampling data chain, avoiding time sequence breakage caused by segmentation.

[0055] The adaptability of segment storage for different signal types of LPDDR5 is shown in Table 3: Segment storage has the most significant optimization effect on the storage of control signals, moderate optimization on data signals, and no effect on clock signals (no silent period), and the channel storage rules are configured accordingly. In combination with the previous "Nyquist sampling rate" and "time / event trigger" system, segment storage needs to be configured in the order of "first set the sampling rate → then configure the trigger mode → finally set the segment rule", and the specific steps are as follows: Taking "sampling rate 10Gsps (complying with Nyquist 2.5 times requirement), event trigger (positioning 0x8000_0000 write failure)" as an example, the segment storage configuration is as follows: Control signal (CA / CS#): The jump threshold is set to VDDQx10% (e.g. 100mV when VDDQ=1.0V), and segment storage is enabled; Data signal (DQ / DQS): The jump threshold is set to VDDQx8% (80mV), and segment storage is enabled; Clock signal (CK_t / c): Because of continuous jump, segment storage is disabled, and "reduced precision storage" (e.g. 16Bit bit width reduced to 8Bit) is used to balance storage occupancy; Based on the timing parameters of LPDDR5 (e.g. tRCD=18ns, minimum command gap 18ns), the segment timeout time is set to "maximum command gap x2" (e.g. 36ns), to ensure complete capture of the jump sequence of consecutive commands and avoid premature command truncation due to timeout; Time trigger scenario: Segment storage is started after "trigger delay time", and the sampling duration is set to "theoretical complete duration x1.5" (e.g. original 100ms extended to 150ms), to avoid effective data loss due to segment missing; Event trigger scenario: Segment storage is not enabled in the pre-trigger stage (e.g. 5ns) (the error signal before the error needs to be captured completely), and segment storage is enabled in the post-trigger stage (e.g. 10ns), to balance error positioning accuracy and storage optimization.

[0056] Take "6400Mbps LPDDR5, 8-channel Plot, sampling rate 10Gsps, event-triggered post-trigger 10ns" as an example, compare the data volume of ordinary storage and segmented storage: ordinary storage data volume: 10Gsps x 10ns x 8 x 16Bit / 8 = 200KB; segmented storage data volume: assuming that the active period of the data signal in the post-trigger stage accounts for 60%, the active period of the control signal accounts for 40%, and the clock signal is stored with reduced precision: data signal: 10Gsps x 10ns x 4 (data channel) x 16Bit / 8 x 60% = 48KB; control signal: 10Gsps x 10ns x 3 (control channel) x 16Bit / 8 x 40% = 24KB; clock signal: 10Gsps x 10ns x 1 (clock channel) x 8Bit / 8 = 10KB; total data volume: 48KB + 24KB + 10KB = 82KB, saving 59% compared with ordinary storage.

[0057] In combination with common test scenarios of LPDDR5, supplement the differentiated configuration rules of segmented storage to ensure adaptation to different test targets: capture the complete initialization sequence while avoiding long silent periods occupying storage; set the segmented timeout time to "maximum initialization gap x 1.2" (e.g., if the maximum initialization gap is 500ns as specified by JEDEC, set 600ns); enable "segmented pre-trigger" (e.g., 200ns), which means that the data 200ns before the transition is also included in the storage, avoiding missing the pre-signal of the initialization command; set the sampling duration to 300ms (ordinary storage requires more than 30GB, segmented storage can be reduced to within 10GB).

[0058] Capture the continuous transition of data transmission completely without missing any bit; set the segmented timeout time of the data signal to "1 data period" (e.g., 6400Mbps LPDDR5 data period 0.3125ns, set 0.5ns), ensuring that the continuous transition is classified as the same segment; disable the transition threshold of the data signal (store directly according to the sampling rate), and only enable segmentation for the control signal to avoid data bit loss due to transition detection delay; use "segmented compression" (e.g., LZ77 algorithm) to further reduce the storage occupancy of consecutive identical bits.

[0059] Long-term cyclic acquisition to capture sporadic fault transition signals; enable "segmented cyclic coverage" to automatically cover the earliest fault-free segment when the storage is full, retaining the latest fault segment; the fault trigger condition (e.g., CS# abnormally low) is linked with segmented storage, and once a fault is triggered, segmented coverage is immediately stopped, locking the segmented data before and after the fault; set the segmented timeout time to 1ms to balance the fault capture range and storage occupancy.

[0060] The introduction of the segment storage technology, only in the signal jump, through the segment storage technology record data after the step, the method further comprises: After the test board is powered on successfully, click RUN on the main interface to start collecting signals. At this time, the logic analyzer enters the pre-trigger state. When the trigger condition (such as CS# falling edge) is met, the instrument under test will capture the waveforms before and after the trigger point and store them in memory.

[0061] Powering on the test board is the prerequisite for entering the pre-trigger state. First, complete the hardware check and software configuration to avoid trigger failure due to insufficient preparation. First, confirm that the ball bonding of the LPDDR5 test board and the logic analyzer is not loose (focus on checking CA / CS# signals and CK_t / c clock pins). Use a multimeter to retest the signal path conduction; check if the test board power adapter output voltage matches the LPDDR5 VDD / VDDQ requirements (such as VDD=0.8V, VDDQ=1.0V), and if the power indicator lights normally; confirm that the logic analyzer has been connected to the computer via USB / Ethernet, and that the Plot channel of the instrument under test (logic analyzer) has been allocated as per the pre-set (such as CA signal on channel A corresponding to Plot1-Plot4).

[0062] Software configuration confirmation: open the logic analyzer software, load the saved "LPDDR5 sampling template" (including the pre-set parameters such as Nyquist sampling rate 10Gsps, segment storage rules, trigger conditions); check the LPDDR5 signals corresponding to each Plot in the "Channel Configuration" interface (such as Plot1=CS#, Plot2=CA0) to ensure no mismatch; enter the "Storage Settings" interface and confirm that the segment storage function is enabled (check "Store only when jumping"), and the storage path is the local disk of the computer (remaining space ≥20GB to avoid data loss due to full storage).

[0063] Powering on and starting the collection operation: turn on the test board power, observe the power indicator light (usually green) of the LPDDR5 chip on the test board, and after the light is always on (about 100-200ms, power stabilization time), confirm that the test board main interface displays normally (no hardware error prompt); click the "RUN" button on the test board main interface. At this time, the logic analyzer software status bar will display "entering pre-trigger state" (usually indicated by a yellow indicator light or text prompt), and the collection is officially started.

[0064] The pre-trigger state is a transition phase of "waiting for the trigger condition to be met", and the core role is to cache the key signals before triggering, providing the basis for subsequent positioning of the trigger point before and after the timing. The "sampling state" column of the logic analyzer software displays "Pre-Trigger", and the waveform display area is blank or only displays the real-time collected signal preview (not stored), and the sampling rate indicator light flashes at the preset 10Gsps frequency; The Plot channel indicator light (such as one LED for each Plot) of the logic analyzer is green and slowly flashes, indicating that the channel has been activated and is monitoring the signal, but the trigger condition has not been met; The pre-trigger stage temporarily caches the signal data of the recent period (cache duration = pre-trigger duration, such as 5ns), and the cache space is the built-in memory of the logic analyzer (not the local disk). If the trigger condition is not met for a long time (such as more than 10 minutes), the cache will automatically overwrite the oldest data to prevent memory overflow.

[0065] Cooperative logic with segmented storage: The pre-trigger stage does not enable "transition detection" of segmented storage, but caches all signal data at the full sampling rate (10Gsps). The reason is that pre-trigger data needs to fully reflect the signal state before triggering (such as the level change before the CS# falling edge), and if segmented storage is enabled, the pre-trigger condition may be missed. The format of the cached data is consistent with the subsequent storage format (such as 16Bit bit width), ensuring the time sequence continuity of the cached data after triggering and the data after triggering, and avoiding the fault caused by the format difference.

[0066] When the preset trigger condition (such as CS# falling edge) is monitored, the pre-trigger state ends, and the waveform capture stage is entered. This link needs to accurately respond to the trigger signal and cooperate with segmented storage to complete data storage. Taking the "CS# falling edge" trigger as an example, the logic analyzer will monitor the level change of Plot1 (CS# signal) in real time. When the signal falls from high level (such as VDDQ=1.0V) to low level (such as ≤0.2V), and the falling edge time ≤50ps (consistent with the LPDDR5 signal edge requirement), it is determined that the trigger condition is met. If the trigger condition is a combination condition (such as "CS# falling edge + CA0 high level"), both signal state requirements need to be met. The logic analyzer will determine through "and logic" to avoid single signal false triggering (such as only CS# falling edge but CA0 low level, not triggering).

[0067] At the moment when the trigger condition is met, the logic analyzer immediately locks the 5ns data (including the signal before the CS# falling edge) cached in the pre-trigger stage and marks it as the "pre-trigger data segment". This data segment is written to the temporary storage area first to prevent it from being overwritten. Then, the post-trigger data collection stage is entered, and the collection duration is performed according to the pre-set post-trigger duration (e.g., 10ns). This stage uses the segmentation storage technology: for the control signal (CS# / CA), only when a signal transition (e.g., CA0 changes from low to high) is detected, the data in this period is stored, and no transition period (e.g., CS# remains low) is stored; for the data signal (DQ / DQS), since the post-trigger may enter the data transmission stage (continuous high-frequency transition), the transition detection of the segmentation storage is disabled, and the complete sampling rate of 10Gsps is stored to ensure no bit loss; for the clock signal (CK_t / c), the reduced-precision storage (8Bit width) is performed continuously to provide a reference for data timing analysis.

[0068] After the post-trigger collection is completed, the software automatically adds timestamps (accurate to the ps level, e.g., trigger time = 123456789ps) to the "pre-trigger data segment" and "post-trigger data segment" and concatenates them in chronological order to form a complete waveform file (usually in.lwf format, supporting subsequent playback and analysis).

[0069] The post-trigger captured waveform needs to be correctly stored and traceable, and the data viewing method needs to be mastered to ensure that the trigger point and abnormal signals can be quickly located: storage trigger condition: when the post-trigger data collection is completed (e.g., 10ns later), the logic analyzer software will pop up a "data storage in progress" prompt (the progress bar displays the storage progress), and the storage path is the local disk pre-set earlier; segmented storage identification: in the stored waveform file, different colors are used to mark the segmented storage areas (e.g., red segment = complete storage before trigger, blue segment = transition storage after trigger, gray segment = reduced-precision clock storage), which facilitates subsequent differentiation of data types; storage completion feedback: after successful storage, the software status bar displays "storage complete" (green indicator light), and a storage report is generated (including file size, collection duration, trigger time, and transition number, etc., such as "file size = 82KB, trigger time = 123456789ps, transition number = 23 times").

[0070] In the software waveform display interface, click on the "trigger point marker" (usually a red vertical line) to quickly locate the trigger position of the CS# falling edge. Drag the time axis left and right to view the waveforms 5ns before the trigger (pre-trigger data) and 10ns after the trigger (post-trigger data). In the "data segment management" interface, you can view the detailed information of each segment (such as "Post-trigger segment 1: CA0 jump, duration = 0.5ns, data volume = 4KB"). Double-click on the segment to zoom in and view the waveform of that segment to verify whether there is signal distortion. Load the LPDDR5 dedicated protocol decoder to decode the stored waveform file. If the trigger condition is "CS# falling edge", the decoding result should be able to identify the corresponding LPDDR5 command (such as the activate command ACT) of the falling edge, and the command timing should comply with the JEDEC standard (such as tRCD=18ns).

[0071] Abnormal scenarios and troubleshooting methods: In the "power on → pre-trigger → trigger → storage" process, problems such as pre-trigger timeout, trigger non-response, and storage failure may occur. Targeted troubleshooting is as follows in Table 4: After step 4, the method further comprises: Display the CS / CA signal level (high / low) sampled at each CK edge in the form of timing waveform from the waveform display window, and check the signal quality by measuring the waveform, wherein the signal quality at least includes whether there is ringing and edge monotonicity.

[0072] Present the CS / CA signal level sampled at each CK edge. First, complete the parameter configuration of waveform display to ensure the timing alignment of CK clock and CS / CA signal. Open the "Waveform Display" interface of the logic analyzer software, select the "CK edge sampling" mode in the "Trigger and Sampling" menu, and specify the rising edge / falling edge of the LPDDR5 CK_t (or CK_c) differential clock as the sampling reference (LPDDR5 usually samples control signals at the CK rising edge, which needs to be consistent with the JEDEC standard). Enable the "Sampling Point Marker" function, and the software will automatically add a red dot marker (sampling point) at the position of the CS / CA signal corresponding to each CK edge, and label the level state of the sampling time (such as "high level (1)" "low level (0)") below the waveform, to intuitively present the sampling result of each clock cycle.

[0073] The waveforms of CK_t clock signal, CS signal, CA0-CA5 signal are arranged in a "time axis synchronization" manner, with the CK_t waveform at the top (as the timing reference), and the CS / CA waveforms arranged below in turn, to ensure that the time axis scales of all signals are consistent (e.g., the horizontal axis unit is set to ps, and each grid represents 100 ps); through the "waveform scaling" function, the waveform corresponding to the CK clock period is enlarged to be visible on the full screen (e.g., the CK period of 6400Mbps LPDDR5 is 625 ps, and after enlargement, the rising edge, high level, falling edge, and low level stages in a single period can be clearly seen), to avoid overlapping of sampling points due to improper scaling ratio.

[0074] In the "waveform style" setting, the high level waveform of the CS / CA signal is set to green, the low level is set to red, the sampling point marker is set to a red dot, and the rising edge of the CK clock is set to a yellow vertical line, to strengthen the timing correlation through color differentiation; the "level value labeling" is enabled, and the level value at this moment is automatically displayed below each sampling point (e.g., "VDDQ=1.0V" is labeled when the CS signal is at high level, and "0V" is labeled when it is at low level), to facilitate quick checking of whether the level meets the PODL standard.

[0075] The signal quality check focuses on "ringing" and "edge monotonicity", which are quantitatively analyzed through software measurement tools or manual labeling. Ringing is a high-frequency oscillation that occurs after the transition of a signal edge, usually caused by impedance mismatch. It is detected after the rising edge and the falling edge of the CS / CA signal: the rising edge (from low level to high level) and the falling edge (from high level to low level) of the CS / CA signal are located, and ringing usually occurs within 1-3 clock cycles after the completion of the edge transition (e.g., within 0-1.25 ns after the rising edge). Taking the rising edge of the CS signal as an example, the waveform without ringing should remain stable at high level (fluctuation ≤5% VDDQ) after the rising edge, and if there is an oscillation of "high level→low level→high level" (fluctuation >5% VDDQ), it is determined that there is ringing. Using the "voltage measurement tool" of the software, measurement points are added at the peak and valley positions of the ringing, and the peak voltage (V_peak) and the valley voltage (V_valley) are read; the ringing amplitude is calculated: ringing amplitude = V_peak - V_target (V_target is VDDQ for high level ringing, and V_target is 0V for low level ringing), and if the ringing amplitude >10% VDDQ (e.g., >0.1V when VDDQ=1.0V), it is determined that the ringing is out of specification; the ringing duration is recorded: the time from the completion of the edge transition to the oscillation amplitude ≤5% VDDQ, and if the duration >1 CK cycle (e.g., >625 ps in 6400Mbps LPDDR5), it may affect the accuracy of subsequent sampling.

[0076] Edge monotonicity refers to the absence of reverse fluctuations during the rising / falling edge of a signal (i.e., the rising edge only goes from low to high without any intermediate drop; the falling edge only goes from high to low without any intermediate rise), defining the starting point and ending point of the signal edge: the starting point of the rising edge is the time when the level reaches 10% VDDQ, and the ending point is the time when the level reaches 90% VDDQ; the starting point of the falling edge is the time when the level reaches 90% VDDQ, and the ending point is the time when the level reaches 10% VDDQ (consistent with JEDEC's definition of edge time); the starting point and ending point of the edge are marked on the waveform with a blue dashed line, forming an "edge analysis interval".

[0077] Using the "edge monotonicity analysis" function of the software, automatically detect the level change trend in the edge interval: if the rising edge appears "the level rises from 10% VDDQ to 50% VDDQ, then drops to 40% VDDQ, and then rises to 90% VDDQ", it is determined as "non-monotonic rising edge"; if the falling edge appears "the level drops from 90% VDDQ to 50% VDDQ, then rises to 60% VDDQ, and then drops to 10% VDDQ", it is determined as "non-monotonic falling edge"; manual verification: if the software has no automatic analysis function, 5-8 measurement points can be added uniformly in the edge interval, and the level value of each point is recorded; if the level value continuously increases (rising edge) or continuously decreases (falling edge), it is determined as monotonic, otherwise it is non-monotonic.

[0078] After completing the signal quality check, export the waveform data and generate a report for subsequent traceability and problem review: Waveform data export: In the logic analyzer software, select "File → Export Waveform Data", the format can be selected as "CSV" (contains timestamp, CK level, CS level, CA0-CA5 level) or "PNG" (waveform screenshot, annotated sampling points and quality problems); When exporting, include "signal quality measurement results" (ring amplitude, duration, edge monotonicity determination) to ensure complete and traceable data.

[0079] Quality report generation: The report template should include: test board information (LPDDR5 model, VDDQ voltage), sampling parameters (sampling rate 10Gsps, CK edge sampling), waveform screenshot (annotated out-of-specification location), quality determination result (compliant / non-compliant items), optimization suggestions; For out-of-specification items, detailed analysis is required: such as "CS signal rising edge ring amplitude 0.15V (out of specification), suspected to be caused by transmission line impedance 60Ω and analyzer input impedance 50Ω mismatch, suggest adjusting the analyzer impedance to 60Ω".

[0080] The CS / CA signal level (high / low) sampled by each CK edge is displayed in the form of a time waveform by the waveform display window, and the signal quality is checked by measuring the waveform, wherein the signal quality at least includes whether there is a ring and the step of edge monotonicity, and the method further comprises: Comparing the command truth table specified by LPDDR5 JEDEC with the digital logic of the waveform display window, if there is a functional failure in the system, comparing the timing waveforms in the normal and abnormal states to find the difference in the timing waveform; According to the search results, combined with circuit design, determine whether there is a logic error; If there is a logic error, change the related register configuration at the software level.

[0081] The JEDEC JESD209-5 specification defines the truth table of all standard commands of LPDDR5 (CS# and CA0-CA5 level combination), and the digital logic of the waveform display window (CS / CA level sampled by CK edge) is compared with the truth table one by one to verify the correctness of command parsing: first extract the truth table of LPDDR5 commonly used core commands (based on CS# low active, CA signal high active) to clearly define the correspondence of "command - level combination", as shown in Table 5: Note: "X" in the table means that the level is irrelevant (any high / low), all commands need to be sampled on the CK rising edge, and the level combination needs to last at least 1 CK period.

[0082] In the waveform display window of the logic analyzer software, locate the CK rising edge sampling point (red dot mark), extract the "CS#+CA0-CA5" level combination of each sampling point in time sequence, and form a "timestamp - level combination" list, for example: timestamp 123456789ps: CS#=0, CA5=0, CA4=0, CA3=0, CA2=0, CA1=1, CA0=0 → level combination [0,0,0,0,0,1,0]; timestamp 123457414ps (next CK period): CS#=0, CA5=0, CA1=0, CA0=1 → level combination [0,0,1,0,1,0,1].

[0083] The extracted level combination is compared with the above truth table to determine the command type corresponding to each sampling point: if the level combination [0, 0, 0, 0, 0, 1, 0] completely matches the truth table of the “ACTIVATE command”, and the level combination lasts for 1 CK period (625 ps), it is determined that the command analysis is correct; if there is “no corresponding command for the level combination” (such as CS#=0, CA5=1, CA4=0, and other CA signals are arbitrary), or “the level combination does not match the command” (such as [0, 0, 1, 0, 1, 0, 0] should be a WRITE command, but is analyzed as a READ command), it is determined that there is a “command analysis exception”, which needs to be further investigated.

[0084] In addition to the level combination, it is necessary to verify whether the command timing conforms to the sequence specified by JEDEC, for example: normal flow: PRECHARGE command → interval tRP (minimum time from precharge to activation, such as 18 ns) → ACTIVATE command → interval tRCD (minimum time from activation to read / write, such as 16 ns) → WRITE / READ command; if “ACTIVATE command is followed by WRITE command without interval tRCD”, or “PRECHARGE command is not executed directly to send ACTIVATE command”, even if the level combination matches, it is determined as “timing violation fault”.

[0085] When the system has a functional fault (such as read / write failure, initialization error), the timing waveforms of normal and faulty board cards need to be collected, and differences are found by multi-dimensional comparison: to ensure the accuracy of difference finding, the test conditions of normal and abnormal board cards need to be completely consistent: hardware conditions: same LPDDR5 model, same test board design, same ball mounting and soldering process, same power voltage (VDD=0.8V, VDDQ=1.0V); sampling parameters: same sampling rate (10Gsps), same trigger condition (CS# falling edge), same pre / post-trigger duration (5ns / 10ns), same waveform display configuration (time axis unit ps, level labeling method).

[0086] Extract the "command sequence" (commands arranged in chronological order) of normal and faulty boards, and compare whether there are missing, redundant or out-of-order commands: normal sequence: NOP → PRECHARGE → NOP (tRP interval) → ACTIVATE → NOP (tRCD interval) → WRITE →...; abnormal sequence: NOP → ACTIVATE (missing PRECHARGE) → NOP → WRITE (tRCD not met) →... → Here, "missing PRECHARGE command" and "tRCD violation" are key differences; use the software "sequence comparison tool" to automatically mark the difference position and generate a difference report (e.g. "at timestamp 123456789ps, the normal board has a PRECHARGE command, and the faulty board has an ACTIVATE command").

[0087] Signal level and timing parameter difference comparison: For the same command (e.g. ACTIVATE), compare the level values and timing parameters of normal and abnormal waveforms, as shown in Table 6: Clock and signal phase difference comparison: LPDDR5 requires that the CS / CA signal and CK clock maintain a specific phase difference (usually 0°±30°), and the phase difference between the falling edge of the CS signal and the rising edge of the CK in the normal waveform is about 15°; if the phase difference in the faulty waveform reaches 90°, it will cause the CS / CA signal to be unstable (e.g. in the edge transition stage) when the CK rising edge is sampled, resulting in "level sampling error" (e.g. high level mis-sampling as low level), which needs to be marked as a key clue for failure.

[0088] According to the waveform difference finding results, combined with the circuit design (schematic diagram, PCB layout) of the LPDDR5 test board, determine whether there is a logic error, and the core troubleshooting direction is as follows: If the CA0 signal is always high (regardless of command type), check the connection path of the CA0 signal according to the schematic diagram: if the CA0 signal is mistakenly connected to the VDDQ power supply terminal (instead of the CA0 pin of LPDDR5) in the schematic diagram, it will cause CA0 to be always high, which is a "schematic diagram logic error"; if the schematic diagram is connected correctly, but the CA0 signal is short-circuited with the VDDQ copper in the PCB layout, it is a "PCB manufacturing logic error", which needs to be measured with a multimeter to measure the conductivity of the CA0 pin and VDDQ (short-circuit if the buzzer is on).

[0089] The CS / CA signals of LPDDR5 are usually generated by a memory controller (such as a CPU built-in controller) or a dedicated control chip. If the waveform display command sequence is disordered (such as ACTIVATE without PRECHARGE), the logic function of the control chip needs to be checked: check the datasheet of the control chip to confirm whether the supported LPDDR5 command timing meets the JEDEC standard; read the "command sending state register" of the control chip through the debugging tool. If the register shows that the "PRECHARGE command has not been sent", but there is no such command in the waveform, it is determined that the "control chip logic error" (the command is not sent as configured).

[0090] If the phase difference between the CS / CA signal and the CK clock exceeds the standard (such as 90°), the clock synchronization circuit needs to be checked in combination with the circuit design: if the path length of the CS / CA signal (such as 15cm) is much longer than that of the CK clock (such as 5cm) in the PCB layout, it will cause a difference in signal transmission delay, which is a "PCB timing logic error" and needs to be adjusted to be consistent (error ≤ 1cm); if the CS / CA signal does not pass through a timing compensation chip (such as a delay line chip) in the schematic diagram, while the CK clock does, it will cause a phase difference, which is a "schematic timing logic error".

[0091] If the tRCD interval in the waveform display is only 10ns (lower than the JEDEC specified 16ns), the timing configuration of the control chip needs to be checked: read the "tRCD configuration register" of the control chip. If the register value is set to 10ns (not 16ns), it is a "software configuration error" (not a circuit logic error) and the register needs to be modified; if the register value is correct (16ns), but the actual interval in the waveform is 10ns, it is a "control chip timing logic error" (the timing is not output as configured by the register) and needs to be checked in hardware.

[0092] Waveform differences (such as missing commands, abnormal levels, and excessive phase differences) can be found by circuit design (schematic diagram / PCB) to find corresponding design problems; the design problem conflicts with the requirements of JEDEC standard or LPDDR5 chip datasheet; exclude non-design factors such as soldering quality, power noise, instrument error (such as the difference still exists after re-soldering).

[0093] If the logic error is caused by "inappropriate software register configuration" (such as incorrect timing parameter register value, command enable register not turned on), the register configuration can be modified through software tools without hardware modification. The specific process is as follows: According to the type of logical error, locate the corresponding configuration register, for example: timing parameter error (tRCD = 10 ns) -> target register: tRCD configuration register (address such as 0x1204); command enable error (PRECHARGE command not sent) -> target register: command enable register (address such as 0x1301); refer to the register manual of the LPDDR5 memory controller or control chip to determine the register address, bit definition, and read-write permission (such as read-only / writable).

[0094] Connect the test board using a debugging tool (such as a JTAG debugger, serial port tool), and obtain the current value through a register read command: example (JTAG command): read_reg 0x1204 -> return value: 0x000A (hexadecimal, corresponding to 10 ns, not meeting the requirement of 16 ns); record the current value for comparison and verification after modification.

[0095] According to the JEDEC standard and chip requirements, calculate the correct value of the target register: tRCD needs to be set to 16 ns, and if each bit of the register corresponds to 1 ns, the correct value is 0x0010 (hexadecimal); in the command enable register, the PRECHARGE command enable bit (Bit2) is set to 1 (on), and if the current Bit2 = 0, the correct value is the current value | 0x0004.

[0096] Perform modification operation: send register write command through debugging tool to write correct value: example (JTAG command): write_reg 0x1204 0x0010 -> prompt "Write success"; some registers need to be "written and restarted to take effect", and need to send a restart command (such as reset_controller) to restart the memory controller or control chip.

[0097] Re-read the target register to confirm that the value has been updated to the correct value (such as 0x1204 register value changes to 0x0010); re-collect timing waveforms to verify whether the logical error is repaired: timing parameter error: check whether the tRCD interval changes to 16 ns, and whether the command sequence meets the normal process; command enable error: check whether the PRECHARGE command is sent normally, and whether the corresponding level combination appears in the waveform; if the waveform shows that the error is repaired and the system function (such as read-write operation) returns to normal, it is determined that the modification is successful; if there is still an error, the register configuration needs to be checked again or other logical problems need to be checked.

[0098] After step 4, the method further comprises: The waveform is digitized into a time-ordered CS / CA state table by the list display window, with each row showing the signal combination of a clock cycle, and the evolution of the command sequence is observed.

[0099] The list display window is the core tool for digitizing waveform signals by time period. The window parameters need to be configured first to ensure that the table data is accurately aligned with the CK clock period: In the logic analyzer software interface, click "View -> List Display" to enable table display function; if the software supports multi-window linkage, check the "Waveform - List Synchronization" option to ensure that the selected row in the list is highlighted synchronously with the corresponding clock period waveform in the waveform display window, facilitating cross-validation.

[0100] In the "Configuration" menu of the list window, select "Time Reference -> CK Clock Period" to set the "Row Unit" of the table to 1 CK clock period (e.g. 6400Mbps LPDDR5 CK period is 625ps), ensuring that each row accurately corresponds to the signal state of one clock period; if there is a CK_t / c differential clock, specify the "CK_t rising edge" as the period starting point (consistent with the LPDDR5 sampling reference) to avoid data deviation caused by period starting misalignment.

[0101] In the "Column Selection" interface of the list window, check the following key columns to ensure coverage of time, signal state, and command analysis results, as shown in Table 7: Hide irrelevant columns (such as other signal channels and redundant time parameters) to avoid table redundancy and interfere with observation.

[0102] Sort by "Timestamp" column in "Ascending" order to ensure that the table data strictly follows the time sequence and corresponds to the natural evolution of the command sequence; if you need to focus on a specific command stage (such as the initialization stage), you can use the "Timestamp Filter" function to set the time range (e.g. 123456789ps-123466789ps) to display only the CK period data within that time period, reducing irrelevant information interference.

[0103] Table data needs to be strictly based on waveform sampling results, ensuring that the signal state of each CK cycle and command analysis is accurate, and the core generation rules are as follows: the CS / CA signal state of each CK cycle is determined by the level value of the rising edge sampling point in the cycle (consistent with the LPDDR5 protocol sampling mechanism); the level determination threshold strictly follows the POLDL standard, that is: high level (1): sampling value ≥80% VDDQ (such as VDDQ=1.0V, ≥0.8V); low level (0): sampling value ≤20% VDDQ (such as ≤0.2V); if the sampling value is between 20%-80% VDDQ (such as 0.3V-0.7V), it is determined as "uncertain state", marked as "X" in the table, and the sampling point is marked as "abnormal" in the waveform window, which needs to be checked for level instability later.

[0104] In-cycle level stability check: if the CS / CA signal in a CK cycle appears multiple level jumps (non-stable state), mark "in-cycle jump" in the "remark" column of the table and record the number of jumps (such as "2 jumps"); the command analysis result of such unstable cycle needs to be marked as "Invalid" (invalid) to avoid incorrect commands into the sequence, for example: the CS# in a CK cycle is low first and then high, the level combination is not fixed, and it cannot be matched with the truth table, the command column shows "Invalid".

[0105] The generation of "command analysis" column in the table strictly follows the JEDEC command truth table, and the matching process is as follows: extract the "level combination" of the current row (such as CS#=0, CA5-CA0=000010); compare it with the preset truth table (such as the ACTIVATE command corresponding combination [0,0,0,0,0,1,0]); completely match to fill in the corresponding command name, partially match or no match, respectively display "Partial Match" (partial match) or "Unknown" (unknown); for example: if the level combination is [0,0,0,0,0,1,0], it is completely consistent with the ACTIVATE command truth table, and the command column shows "ACTIVATE"; if the combination is [0,0,0,0,0,1,X] (CA0 is uncertain state), it shows "Partial Match (ACTIVATE)".

[0106] Taking the command sequence of the LPDDR5 initialization phase as an example, the actual form of the state table is shown, and how to observe the evolution process of the command sequence and locate the sequence anomaly through the table is explained.

[0107] Initialization phase state table instance (6400Mbps LPDDR5, VDDQ=1.0V), as shown in Table 8: Normal sequence evolution observation: From table row 1-9, the command sequence evolution in initialization phase can be clearly seen: NOP (cycle 1) -> PRECHARGE (cycle 2) -> NOP (cycle 3-4, tRP interval) -> ACTIVATE (cycle 5) -> NOP (cycle 6-7, tRCD interval) -> ZQ CAL (cycle 8) -> NOP (cycle 9, calibration waiting); Key observation: the number of NOP cycles between each command (e.g. 2 CK cycles interval between PRECHARGE to ACTIVATE, corresponding to 1250ps=1.25ns, Note: 6400Mbps LPDDR5's CK cycle is 625ps, 2 cycles is 1.25ns, actual tRP needs 18ns, needs to interval 29 CK cycles (18ns / 625ps≈28.8), the table example is a simplified display, actual needs to adjust the number of cycles accordingly), ensure that the timing interval meets the JEDEC standard, the sequence evolution logic is coherent.

[0108] Abnormal sequence evolution positioning (taking missing PRECHARGE as an example): If the fault board's state table is as follows (part of the rows), as shown in Table 9: Sequence evolution abnormal point: Cycle 2 directly jumps from NOP to ACTIVATE, missing the PRECHARGE command, compared with the normal sequence (NOP->PRECHARGE->NOP->ACTIVATE), the "command missing" problem can be quickly located; combined with the "remark" column of the table without PRECHARGE related records, further confirm the sequence evolution logic error, need to check the control chip command sending logic or register configuration according to the fault positioning scheme in the previous section.

[0109] Timing violation sequence positioning (taking tRCD insufficient as an example): Abnormal table fragment, as shown in Table 10: Sequence evolution problem: ACTIVATE (cycle 5) is followed by only 1 CK cycle (625ps) interval to send WRITE command, which does not meet tRCD=16ns (needs 29 CK cycles), the dense jump in the "command analysis" column of the table (ACTIVATE->WRITE without NOP interval) directly reflects the timing violation, combined with the interval calculated by "timestamp", can quantify the violation duration (625ps vs 16ns), provides data basis for subsequent register modification (such as adjusting tRCD configuration register).

[0110] For subsequent analysis and problem review, export the CS / CA status table and generate a command sequence evolution report: In the list display window, click "File→Export Table", and the following formats are supported: CSV format: can be opened with Excel for editing and data filtering (such as filtering rows with "Command Analysis = Unknown" to locate unknown command periods), and all column data (timestamp, level state, command, etc.) are retained; Excel format: with data format settings (such as command column color annotation, level state 0 / 1 bold), no secondary editing is needed, and it is suitable for direct use in reports; TXT format: plain text table, strong compatibility, suitable for importing into other analysis tools (such as MATLAB) for command sequence timing analysis.

[0111] If only a specific stage (such as initialization, read / write stage) needs to be analyzed, the "Filter" function in the list window can be used to filter data by "Timestamp Range" or "Command Type" first, then export the filtered table to reduce the amount of invalid data; when exporting, check the "Include Waveform Screenshot Link" option, each row in the table can be associated with the waveform screenshot path of the corresponding CK period, and clicking it can jump to view the original waveform of that period, realizing cross verification of table and waveform.

[0112] Test board information (LPDDR5 model, CK frequency), sampling parameters (sampling rate, time range), table data statistics (total CK period number, command type and number, such as NOP: 50 times, ACTIVATE: 3 times, WRITE: 10 times); use flowchart to show standard command sequence (such as initialization stage flowchart: NOP→PRECHARGE→[tRP]→ACTIVATE→[tRCD]→ZQ CAL→NOP), mark the function and timing requirements of each command; if there is an exception, include a "normal table fragment - abnormal table fragment" comparison chart, mark the difference points (such as command missing, timing violation) with a red box, and calculate the impact of the exception (such as the number of command misjudgments caused by insufficient tRCD); summarize whether the command sequence meets the JEDEC standard, the positioning results of the abnormal points (such as software configuration error, hardware logic problem) and subsequent repair suggestions (such as modifying the tRCD value of register address 0x1204).

[0113] In the report, insert the "command sequence timeline chart" with the timestamp as the horizontal axis and the command type as the vertical axis, and use different color bars to represent the duration of each command (such as PRECHARGE for 1 cycle and NOP for 29 cycles), which intuitively presents the time distribution of sequence evolution; for key commands (such as ACTIVATE and WRITE), add the corresponding relationship between table row number and waveform screenshot to facilitate readers to quickly trace back and view the original signal.

[0114] After step 4, the method further comprises: Comparing the decoded command sequence with the JEDEC standard, it is found that the command encoding is illegal; Using the timing analysis function of the logic analyzer, measure the delay from CS active to CA stable, the interval period number between commands, and check whether it meets the chip timing parameters; When an abnormal command is found, trace back the system state before the abnormal command to analyze the root cause.

[0115] Decoding the command sequence needs to be strictly compared with the command encoding and sequence logic in JEDEC JESD209-5 specification to accurately identify illegal command encoding. The specific operation is as follows: establish a JEDEC standard command encoding library, first sort out the standard encoding of LPDDR5 core commands (CS# low active, CA0-CA5 level combination), form a comparison reference library, and the key command encoding is shown in Table 11: Note: JEDEC standard clearly stipulates that "CS#_CA5-CA0 combination other than Table 11 is illegal command", and some commands (such as MODE REG WRITE) need to last for 2 CK cycles, and single-cycle encoding is invalid.

[0116] Extract the "level combination" column data (such as 0_001100) from the CS / CA state table and compare it with the above standard encoding library one by one: if the encoding completely matches a standard command (such as 0_000010 matches ACTIVATE) and the duration meets the requirements (such as 1 CK cycle), it is determined as "compliant command"; If the encoding has no matching item (such as 0_001100), the encoding matches but the duration is not consistent (such as MODE REG WRITE only lasts for 1 cycle), or the CS# level conflicts with the encoding requirements (such as PRECHARGE encoding requires CS#=0, but the actual CS#=1), it is determined as "illegal command encoding", and the "remark" column in the table is marked as "illegal encoding: 0_001100, no corresponding standard command".

[0117] In addition to single command encoding, the logical order between commands needs to be verified to meet JEDEC standards, for example: normal logic: PRECHARGE → [tRP interval] → ACTIVATE → [tRCD interval] → WRITE / READ; illegal logic: ACTIVATE → PRECHARGE (no tRAS interval, JEDEC requires a tRAS interval after activation before precharging), WRITE → ACTIVATE (no precharge prefix). For illegal logic sequences, mark "sequence violation: ACTIVATE followed by PRECHARGE, missing tRAS interval" in the table and associate the corresponding JEDEC clause (e.g. JESD209-5 7.3.2 section).

[0118] According to the comparison results, the illegal command encoding is divided into three categories for subsequent targeted analysis, as shown in Table 12: Using the timing analysis function of the logic analyzer, measure the delay from CS active to CA stable, the command interval period, and verify whether it meets the chip timing parameter requirements. The specific operation is as follows: in the logic analyzer software, click "Analysis → Timing Analysis → New Timing Measurement Task", select the "LPDDR5 CS / CA Timing" template, and automatically load the JEDEC standard timing parameter threshold (which can be adjusted according to the chip datasheet).

[0119] Measurement parameter configuration: check the key timing parameters to be measured, and specify the measurement reference and unit, as shown in Table 13: CS active to CA stable delay (tCSCA) measurement: locate the CS# signal falling edge (active start point): in the waveform display window, use the "Edge Marker Tool" to mark the time when CS# changes from high to low (e.g. T1=123457414ps); locate the CA signal stable point: observe the CA0-CA5 signals, and wait for all CA signals to stop jumping (stabilize at the target level) (e.g. T2=123457564ps); calculate the delay: tCSCA = T2 - T1 = 150ps, compared with the chip threshold (≤180ps), if ≤180ps, it is determined to be compliant, otherwise, mark "tCSCA out of specification: 150ps≤180ps (compliant)" or "tCSCA out of specification: 200ps>180ps (violation)".

[0120] Command interval period number (tCMD) measurement: In the CS / CA state table, extract the CK cycle number of the previous command (e.g., PRECHARGE, cycle 2) and the CK cycle number of the next command (e.g., ACTIVATE, cycle 5); calculate the interval period number: 5 - 2 = 3 CK cycles, if ≥1 cycle, determine compliance; for critical intervals (e.g., tRP, tRCD), convert to time by combining CK cycles: 3 cycles x 625ps / cycle = 1875ps = 1.875ns, compared to JEDEC standard tRP≥18ns, if 1.875ns<18ns, determine "tRP interval violation: 1.875ns<18ns".

[0121] Timing report generation: The logic analyzer software automatically generates a "timing measurement report" containing the measured value of each parameter, the standard threshold, and the compliance determination, as shown in Table 14: In the waveform display window, mark the timing parameter measurement points with different colored lines: red line: CS# falling edge (tCSCA start point); blue line: CA signal stable point (tCSCA end point); green arrow: command interval period range (e.g., PRECHARGE cycle 2 to ACTIVATE cycle 5); exceed the standard parameters marked with red font beside the waveform (e.g., "tRP=1.875ns<18ns, violation").

[0122] When illegal command encoding or timing violation is found, the system state before the abnormal command needs to be traced back to locate the root cause: In the CS / CA state table, find the row marked "illegal command" or "timing violation" (e.g., cycle 10, command encoding 0_001100), record its timestamp (e.g., T_abnormal=123462414ps); set the reverse tracking time range: take T_abnormal as the endpoint, trace back 20 CK cycles (about 20x625ps=12.5ns), covering the system initialization, register configuration, and signal interaction process before the abnormal command.

[0123] Read the key register values of the control chip within the first 20 CK cycles before the abnormal command through the JTAG debugging tool, and focus on: command sending register (such as address 0x1301): check if there is a preset value of error command code (such as 0_001100), if there is, it is determined that "register configuration error causes illegal command"; timing configuration register (such as tRP configuration register 0x1204): if the tRP configuration value is 1.875ns (not 18ns), it is determined that "timing register configuration error causes tRP violation"; status register (such as 0x1400): check if there is a "signal error" "timeout" and other state marks, if there is, it is associated with the cause of the abnormal command.

[0124] Call the power supply waveform (VDD, VDDQ) and clock waveform (CK_t / c) stored by the logic analyzer before the abnormal command: power supply state: if VDDQ voltage drop occurs before the abnormality (such as from 1.0V to 0.7V), it is determined that "unstable power supply causes CA signal level abnormality, generates illegal code"; clock state: if the frequency fluctuation (such as from 1600MHz to 1500MHz) or phase jump occurs in CK_t / c, it is determined that "clock abnormality causes command cycle count error, timing violation occurs".

[0125] Analyze the CS / CA signal interaction sequence before the abnormal command, for example: if "CA3 signal continuously high (should be low)" occurs before the abnormal command (0_001100), trace back the start time of the CA3 signal abnormality (such as cycle 8 starts CA3 constant high), check if there is external interference (such as other signal crosstalk) or soldering fault (such as CA3 pin virtual soldering) at that time; if "CS# signal is triggered multiple times (falling edge without command)", it is determined that "CS# signal noise causes the control chip to misidentify the command and generate illegal code".

[0126] According to the reverse tracking result, the abnormal root cause is divided into four categories, and the corresponding solutions are provided, as shown in Table 15: After completing the abnormal source tracing, generate an "abnormal command reverse tracking report", including the following contents: abnormal command basic information: code, time stamp, compliance determination; reverse tracking range and method: time range (such as T 12.5ns before the abnormality), use tool (JTAG debugging, power supply monitoring); key tracking result: register value, power supply clock state, signal interaction abnormal point; root cause positioning conclusion: clearly define the abnormal root cause type (such as register configuration error); solution and verification result: implemented repair measures and compliance verification data after repair.

[0127] This embodiment converts the "cycle-by-cycle command comparison" from manual line-by-line checking to software automated verification by establishing a JEDEC standard command encoding library. The logic analyzer can automatically identify illegal encodings (such as 0_001100 without a corresponding standard command) and cycle violations (such as MODE REG WRITE for only one cycle), and mark the abnormal types in the table. Compared with manual verification, the efficiency is improved, and human errors are avoided.

[0128] For key timing parameters such as tCSCA, tRP, tRCD, the scheme does not require manual marking of waveforms and calculation of time difference. The software can automatically locate the CS# falling edge and CA stable point, combine the CK cycle conversion interval time, and generate a timing report containing "measurement value - standard threshold - compliance". The original timing analysis of 1-2 hours can be compressed to 10-15 minutes, greatly shortening the test cycle.

[0129] Illegal command encodings are subdivided into "no corresponding encoding", "cycle violation", and "CS# level conflict", and associated with possible causes (such as control chip logic error, signal attenuation), avoiding the "no direction trial and error" in traditional troubleshooting. At the same time, through the synchronous linkage of state table and waveform, the original waveform of the corresponding cycle can be viewed by clicking the abnormal command line, realizing the rapid tracing of "abnormal phenomenon - original signal".

[0130] For abnormal commands, the scheme not only stops at "finding illegal encodings", but also through the process of "locking time range → tracking register / power / clock state → classifying root cause", locates deep-seated problems (such as tRP violation is not simply a timing problem, but a register configuration error). For example, when ACTIVATE is directly followed by PRECHARGE, the tRAS configuration register can be read through JTAG to confirm whether the sequence violation is caused by too small register value setting, avoiding fixing the appearance while ignoring the root cause.

[0131] Distinguish between "software configuration error" (such as improper register value) and "hardware failure" (such as pin virtual welding) - for the former, the register can be modified through JTAG (such as changing the tRP configuration from 1.875ns to 18ns) to achieve repair, without the need to disassemble the board and re-solder, saving more than 80% of time and material costs compared with hardware rework. Only when it is confirmed through reverse tracking that it is a hardware problem (such as CA3 virtual welding), targeted hardware operation is performed, avoiding blind disassembly and modification.

[0132] The generated CS / CA state table (CSV / Excel format), timing report, and backtracking report all contain complete timestamps, waveform screenshot links, and subsequent comparisons of historical data if similar abnormalities occur, eliminating the need to repeatedly collect waveforms and measure parameters, reducing the occupation of test resources (such as logic analyzers and test boards).

[0133] Not only does it check the command encoding compliance, but it also verifies the command sequence logic (such as the sequence of PRECHARGE→ACTIVATE→WRITE) and timing intervals (such as tRP≥18ns), ensuring that the system from "command generation" to "signal interaction" meets the JEDEC standards and chip datasheet requirements, avoiding risks such as read / write errors and system crashes due to implicit timing violations (such as insufficient tRCD) in long-term operation.

[0134] All repair measures correspond to specific verification standards — for example, after modifying the register, tRP needs to be re-measured to confirm ≥18ns; after re-soldering, CA3 signals need to be collected to confirm normal level switching, rather than "subjectively judging that the repair is complete". This quantitative verification ensures that the problem is completely solved, avoiding subsequent system failures due to incomplete repairs.

[0135] In several embodiments provided by the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only illustrative, and for example, the division of units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed units can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0136] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0137] The above is only an embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for capturing LPDDR5 digital signals based on a logic analyzer, characterized in that, The method comprises: The CA signal and the CS signal of the A / B channel of the LPDDR5 are ball welded with the instrument under test on the test board, and the corresponding plot is selected according to the actual connection, wherein the instrument under test has a total of 8 plots; When connecting, the plot is allocated according to the actual connected signal line, the sampling clock of each group of plots is uniformly connected to the CK_t / c signal, the impedance of the instrument under test is set according to the input impedance matching of the logic analyzer, the LPDDR5 adopts the PODB level standard, and the voltage threshold of the instrument under test is set to VDDQ / 2. The special protocol decoder of the LPDDR5 is loaded in the logic analyzer software, wherein the special protocol decoder of the LPDDR5 is built-in command truth table and timing rules defined by JEDEC standard, the Chip is selected according to the CA signal and the CS signal of the A / B channel, and the special protocol decoder of the LPDDR5 correctly associates the physical channel and the logic signal. A bus is created in the logic analyzer software, and the CA signal and the CS signal are respectively mapped to the corresponding bit of the bus. The sampling threshold, bit width and polarity are set, and whether the signal has a jump is observed. If the signal has a jump, the signal is normal. If the signal has no jump, check the welding, power supply and controller initialization state.

2. The method for grabbing LPDDR5 digital signal based on logic analyzer according to claim 1, wherein, After the step of creating a bus in the logic analyzer software and mapping the CA signal and the CS signal to the corresponding bit of the bus, the method further comprises: Set the preset details of sampling, wherein the preset details can be time or event, if only the boot process is captured, select time, if the error is found from the log, select event, time trigger is suitable for capturing the complete startup process; Set to start capturing after a certain time delay after power-on; Set the event trigger to the known error point, set the trigger condition as "WRITE command + specific address" appearing on the bus, and realize accurate positioning.

3. The method for grabbing LPDDR5 digital signal based on logic analyzer according to claim 1, wherein, Before the step of setting the sampling threshold, bit width, polarity, and observing whether the signal has a jump, the method further comprises: According to the Nyquist theorem, set the sampling rate to be at least 2.5 times the highest frequency of the signal.

4. The method for grabbing LPDDR5 digital signal based on logic analyzer according to claim 1, wherein, Before the step of setting the sampling threshold, bit width, polarity, and observing whether the signal has a jump, the method further comprises: Introduce segmented storage technology, and record data only when the signal jumps through segmented storage technology.

5. The method for grabbing LPDDR5 digital signal based on logic analyzer according to claim 4, wherein, After the step of introducing segmented storage technology and recording data only when the signal jumps through segmented storage technology, the method further comprises: After the test board is successfully powered on, click RUN on the main interface to start collecting signals, at this time the logic analyzer enters the pre-trigger state; When the set trigger condition is met, the instrument under test will capture the waveforms before and after the trigger point and store them in the memory.

6. The method for grabbing LPDDR5 digital signal based on logic analyzer according to claim 1, wherein, After the step of creating a bus in the logic analyzer software and mapping the CA signal and the CS signal to the corresponding bit of the bus, the method further comprises: The CS / CA signal level sampled at each CK edge is displayed in the waveform display window in the form of a timing waveform, and the signal quality is checked by measuring the waveform, wherein the signal quality at least includes whether there is a ringing and edge monotonicity.

7. The method for grabbing LPDDR5 digital signal based on logic analyzer according to claim 6, wherein, The CS / CA signal level sampled by each CK edge is displayed in the form of a timing waveform by the waveform display window, and the signal quality is checked by measuring the waveform, wherein the signal quality at least includes whether there is a ring and the step of edge monotonicity, and the method further comprises: Comparing the command truth table specified by LPDDR5 JEDEC with the digital logic of the waveform display window, if there is a functional failure in the system, comparing the timing waveforms in the normal and abnormal states to find the difference timing waveforms; According to the finding result, it is determined whether there is a logic error according to the circuit design positioning problem; If there is a logic error, the related register configuration is changed at the software level.

8. The method for grabbing LPDDR5 digital signal based on logic analyzer according to claim 1, wherein, After the step of creating a bus in the logic analyzer software and mapping the CA signal and the CS signal to the corresponding bit of the bus, the method further comprises: The waveform is digitized into a CS / CA state table sorted by time by the list display window, and each row displays the signal combination of one clock cycle, and the evolution process of the command sequence is observed.

9. The method for grabbing LPDDR5 digital signal based on logic analyzer according to claim 1, wherein, After the step of creating a bus in the logic analyzer software and mapping the CA signal and the CS signal to the corresponding bit of the bus, the method further comprises: Comparing the decoded command sequence with the JEDEC standard to find illegal command encoding; Using the timing analysis function of the logic analyzer, the delay from CS active to CA stable and the interval period number between commands are measured to check whether the chip timing parameters are met; When an abnormal command is found, the system state before the abnormal command is traced back to analyze the root cause of the abnormality.

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