Multi-mode robust terminal peripheral latency measurement system and method

Abstract

This invention relates to the field of computer measurement and performance testing technology. To address the problems of large end-to-end latency measurement errors and the inability to quantify and decompose the latency of each component in existing technologies, a multi-mode, highly adaptive terminal peripheral latency measurement system and method are disclosed. The system hardware includes a hardware measurement terminal and a host computer; the hardware measurement terminal includes a central control module, a physical trigger module, and a photoelectric feedback module. The method integrates multiple test modes to measure the latency of peripherals, displays, and the overall interaction. It accurately determines screen brightness jumps through a dynamic window calibration algorithm; it uses an RTT latency compensation module built into the host computer to eliminate system errors; and it utilizes an end-to-end latency decomposition module built into the central control module to quantify the total latency into independent components for peripherals, displays, system processing, and the game engine, enabling error tracing and performance bottleneck location. This achieves multi-dimensional, high-precision, and adaptive measurement of terminal interaction latency under complex environments.

Description

Technical Field

[0001] This invention belongs to the field of computer measurement and performance testing technology, specifically relating to a multi-mode, highly adaptable terminal peripheral latency measurement system and method. Background Technology

[0002] With the development of esports and high-performance applications, users are paying increasing attention to the response latency of computer peripherals (including keyboards, mice, gamepads, etc.) and the overall response latency of terminal systems. Existing latency measurement technologies mainly suffer from the following shortcomings:

[0003] Lack of systematic approach: Existing solutions mostly only measure the total latency from "key press to screen light up", or measure keyboard and mouse latency and monitor latency separately. The start and end points of timing are not defined in a unified way and overlap with each other. It is impossible to distinguish the contributions of each link such as peripheral internal processing, USB bus polling, operating system input stack (Hook / Raw input, also known as host input stack), application rendering submission and monitor refresh phase, making it difficult to locate bottlenecks.

[0004] Operating system-level measurement blind spots: Open source tools often struggle to isolate operating system input processing latency, easily misrepresenting it as peripheral hardware latency, leading to overestimation of results; or ignoring this component in tests outside the system environment, resulting in underestimation of results.

[0005] Poor environmental adaptability: Traditional photoelectric detection solutions mostly use fixed voltage thresholds, which are prone to false triggering or missed detection when faced with different brightness panels, changes in ambient light, or PWM dimming flicker; even slight displacement of the sensor position may cause calibration failure.

[0006] Uncorrected communication latency error: In the host computer-slave computer interaction architecture, USB CDC virtual serial port communication suffers from transmission and buffer queue latency. Existing solutions often fail to deduct this communication time and directly include it in the measurement results, resulting in inflated and unstable data.

[0007] Lack of statistical stability analysis: The measurement jitter of some tools (e.g., standard deviation can reach 2.5 ms) is significantly greater than the physical jitter of high-return peripherals themselves (the theoretical standard deviation of 1000 Hz return rate is about 0.29 ms). The test system error masks the true fluctuation of the tested object, making it difficult to assess the stability of the device. Summary of the Invention

[0008] To address the aforementioned technical problems, this invention proposes a multi-mode, highly adaptable terminal peripheral delay measurement system and method. It utilizes a dynamic window calibration algorithm to enhance adaptability to ambient light and different screen dimming methods, eliminates system errors introduced by USB CDC virtual serial communication through RTT round-trip delay compensation, measures the system input stack delay using a reference loop (ideal peripheral), and employs a full-link delay decomposition module to achieve precise definition, measurement, and combined calculation of delays at each stage from peripheral physical triggering to screen photoelectric feedback.

[0009] This invention provides a multi-mode, highly adaptable terminal peripheral delay measurement system, the system comprising at least a hardware measurement terminal and a host computer;

[0010] The host computer has a built-in mode selection and configuration module, an RTT delay compensation module, and a full-link delay breakdown and analysis module.

[0011] The mode selection and configuration module is used to provide a test mode selection interface and configure test parameters; the start and end times of the test mode are determined and recorded based on events of different measurement principles; the measurement principles include screen brightness change detection, command feedback and external triggering;

[0012] The RTT delay compensation module is used to estimate the one-way communication delay by means of the round-trip time of the command, and to compensate for the original delay measurement value involving command interaction.

[0013] The end-to-end latency decomposition and analysis module is used to calculate and decompose at least two of the following measurement results from peripheral hardware latency, display latency, system processing latency, and application additional latency, based on the latency data to be analyzed obtained from at least two test modes with different measurement principles;

[0014] The hardware measurement terminal includes a physical trigger module, a central control module, and a photoelectric feedback module;

[0015] The physical trigger module is used to generate a trigger signal when the peripheral device under test is operated;

[0016] The photoelectric feedback module is used to collect the brightness signal of the display screen of the main control terminal device;

[0017] The central control module is bidirectionally connected to the physical trigger module, photoelectric feedback module, and host computer, and is used to record the start time, send test commands, record the end time, and receive measurement data according to the selected test mode; the central control module has a built-in dynamic window calibration logic module and a reference loop measurement module.

[0018] Preferably, the test modes include at least: display latency test, end-to-end latency test, peripheral latency test, response speed test, and grayscale latency test;

[0019] The screen brightness change detection includes screen brightness jump detection and screen brightness gradual change detection;

[0020] The start time of the display latency test is determined based on the event fed back by the instruction, and the end time is determined based on the detection of screen brightness jump.

[0021] The start time of the end-to-end latency test is determined based on an externally triggered event, and the end time is determined based on the detection of screen brightness jumps.

[0022] The peripheral latency test includes both real peripheral path measurement and ideal peripheral path measurement;

[0023] In the actual peripheral path measurement, the starting time is determined based on externally triggered events, and the ending time is determined based on events fed back from instructions.

[0024] In the ideal peripheral path measurement, the starting time is determined by the simulation generated internally by the central control module based on externally triggered events, and the ending time is determined based on the events fed back by the instruction.

[0025] The start and end times of the reaction speed test are determined based on externally triggered events.

[0026] The starting time of the grayscale delay test is determined based on the event fed back by the instruction, and the ending time is determined based on the screen brightness gradient detection.

[0027] Preferably, the central control module employs a microcontroller with microsecond-level timing capability;

[0028] The microcontroller is configured as a composite USB device, capable of being simultaneously enumerated as an HID device for simulating peripheral input and a virtual serial port device for communicating with a host computer.

[0029] The microcontroller detects the digital signal of the physical trigger module in a polling manner through GPIO pins, and acquires the brightness signal simulated by the photoelectric feedback module through the analog-to-digital converter interface built into the microcontroller.

[0030] The dynamic window calibration logic module is used to adaptively determine the screen brightness jump based on the brightness signal and record it as the endpoint time.

[0031] The reference loop measurement module is used to measure the system input stack delay of the main control terminal device from responding to a hardware interrupt to the system kernel capturing the input message.

[0032] On the other hand, the present invention also provides a multi-mode highly adaptive terminal peripheral latency measurement method, which utilizes the aforementioned multi-mode highly adaptive terminal peripheral latency measurement system to implement the method steps, the method comprising:

[0033] Step 100: Use the built-in mode selection and configuration module of the host computer to select the test mode and configure the test parameters, and send the test mode command and the configured test parameters to the hardware measurement terminal.

[0034] Step 110: According to the selected test mode, the central control module determines and records the start time based on the event judgment of different measurement principles, and starts the corresponding signal acquisition.

[0035] Step 120: Based on the selected test mode, use the central control module to determine and record the endpoint time;

[0036] Step 130: The host computer and the central control module engage in bidirectional communication to obtain the original delay measurement value corresponding to the test mode.

[0037] Step 140: Using the RTT delay compensation module built into the host computer, estimate the one-way communication delay by means of the round-trip time of the command, and compensate the original delay measurement value involving command interaction to obtain the delay data to be analyzed.

[0038] Step 150: Obtain the latency data to be analyzed under at least two test modes with different measurement principles, and use the full-link latency decomposition and analysis module built into the host computer to decompose and calculate it, and output at least two of the measurement results of peripheral hardware latency, display latency, system processing latency and application additional latency.

[0039] Preferably, when it is necessary to calculate the peripheral hardware latency, the central control module uses the built-in reference loop measurement module, based on the kernel latency measurement mechanism of self-simulation loopback, to calculate the system input stack latency of the main control terminal device from responding to the hardware interrupt to the system kernel capturing the input message;

[0040] The self-simulated loopback kernel latency measurement mechanism includes:

[0041] The central control module is set to simulate peripheral working mode. It generates a trigger signal for the simulated button by pulling down its own GPIO pin or triggering the internal logic. The timing starts from the starting point, and the HID input message is sent to the host computer through the USB HID interface.

[0042] When the host computer captures the HID input message through the system hook based on signal loopback logic, it immediately sends an acknowledgment command to the central control module through the virtual serial port.

[0043] Upon receiving the confirmation command, the central control module stops timing, obtains the total hardware interrupt loopback duration, and uploads it to the host computer.

[0044] The host computer compensates for the total time of the hardware interrupt loopback based on the one-way communication delay measured by the built-in RTT delay compensation module, removes the influence of one-way communication delay and average USB polling waiting time, and obtains the system input stack delay from the main control terminal device responding to the hardware interrupt to the system kernel capturing the HID input message.

[0045] Preferably, the peripheral hardware latency is represented by the latency data to be analyzed measured from the actual peripheral path in the peripheral latency test, the system input stack latency, and the average waiting time of the USB polling interval.

[0046] The display latency is directly represented by the latency data to be analyzed in the display latency test;

[0047] The system processes latency by breaking down and representing the latency data to be analyzed using the latency data measured under ideal load in the end-to-end latency test, the latency data to be analyzed using the actual peripheral path measured in the peripheral latency test, and the latency data to be analyzed using the display latency test.

[0048] The additional latency of the application is represented by decomposing the latency data to be analyzed, which was measured under actual application conditions in the end-to-end latency test and the latency data to be analyzed, which was measured under ideal load conditions in the end-to-end latency test.

[0049] Compared with existing technologies, this invention achieves high-precision and high-reliability delay measurement at extremely low cost, while also possessing broad equipment compatibility and strong environmental adaptability. Specific beneficial effects include:

[0050] (1) Accurately locate performance bottlenecks by multi-mode combined measurement and full-link delay decomposition analysis: Decompose the total delay into independent components such as peripheral hardware, system input stack, application program, display circuit and refresh phase; quantify the delay of each link by measuring with M1–M5 and reference circuit, and achieve a breakthrough from measurement to diagnosis.

[0051] (2) Adopting dynamic window calibration algorithm and error compensation mechanism to achieve high-precision anti-interference measurement: Adaptively judge screen brightness jump, adapt to complex light and screen content, and achieve sub-millisecond accuracy; by RTT delay compensation and USB phase analysis to remove system error, the real hardware delay is measured, the standard deviation of keyboard and mouse delay test is close to the physical limit, and the monitor delay test conforms to the theoretical refresh phase.

[0052] (3) It has broad compatibility and high versatility: It is compatible with various input devices such as keyboards, mice, gamepads, and graphics tablets; it supports LCD, OLED and DC dimming displays; it integrates five test modes: display latency, peripheral latency, end-to-end latency, response speed and grayscale latency, and works stably under different ambient light conditions to meet the needs of diverse scenarios.

[0053] (4) Achieve low cost and high reproducibility: Compatible with general development boards (such as Raspberry Pi Pico) and common photosensitive sensors, no special boards or soldering required; built based on general components and standard interfaces, the hardware cost is extremely low, and it has high reproducibility and ease of use. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0055] Figure 1 This is a schematic diagram of the structural framework of a multi-mode highly adaptable terminal peripheral delay measurement system in one embodiment of the present invention;

[0056] Figure 2 This is a schematic diagram of the structure and workflow of the physical triggering module in one embodiment of the present invention;

[0057] Figure 3 This is a schematic diagram of the structure and workflow of the RTT delay compensation module in one embodiment of the present invention;

[0058] Figure 4 This is a flowchart illustrating a multi-mode, highly adaptable terminal peripheral latency measurement method in one embodiment of the present invention.

[0059] Figure 5 This is a schematic diagram of the kernel latency measurement mechanism with self-simulated loopback in one embodiment of the present invention. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] This invention employs clear definitions and formulas to express the system structure, test modes, algorithms, and data output. It reproduces consistent measurement calibers and decomposition relationships across different embodiments, and facilitates implementation and direct application in industrial settings by combining multiple measurement modes. Furthermore, the embodiments further demonstrate hardware connection details, microcontroller firmware flow, host computer data processing scripts, and recommended parameter values ​​to support engineering implementation and large-scale application. The terminal peripheral latency measurement system provided by this invention is used to measure the latency of peripherals (keyboards / mice / gamepads, etc.) connected to a main control terminal device. The system mainly consists of a hardware measurement terminal and a host computer, and covers multiple test modes.

[0062] In one embodiment, such as Figure 1 As shown, the present invention provides a multi-mode highly adaptable terminal peripheral delay measurement system, which includes at least a hardware measurement terminal and a host computer;

[0063] The host computer has a built-in mode selection and configuration module, an RTT delay compensation module, and a full-link delay breakdown and analysis module.

[0064] The mode selection and configuration module is used to provide a test mode selection interface and configure test parameters; the start and end times of the test mode are determined and recorded based on events of different measurement principles; the measurement principles include screen brightness change detection, command feedback and external triggering;

[0065] The RTT delay compensation module is used to estimate the one-way communication delay by means of the round-trip time (RTT) of the command, and to compensate for the original delay measurement value involved in command interaction.

[0066] The end-to-end latency decomposition and analysis module is used to calculate and decompose at least two of the following measurement results from peripheral hardware latency, display latency, system processing latency, and application additional latency, based on the latency data to be analyzed obtained from at least two test modes with different measurement principles;

[0067] The hardware measurement terminal includes a physical trigger module, a central control module, and a photoelectric feedback module;

[0068] The physical trigger module is used to generate a trigger signal when the peripheral device under test is operated;

[0069] The photoelectric feedback module is used to collect the brightness signal of the display screen of the main control terminal device;

[0070] The central control module is bidirectionally connected to the physical trigger module, photoelectric feedback module, and host computer, and is used to record the start time, send test commands, record the end time, and receive measurement data according to the selected test mode; the central control module has a built-in dynamic window calibration logic module and a reference loop measurement module.

[0071] Specifically, the peripheral device under test is connected to the main control terminal device, which is the test target, through a standard interface; the display screen is connected to the main control terminal device through a video cable, or is directly integrated into the main control terminal device; the main control terminal device outputs the processed image signal to the display screen.

[0072] The hardware measurement terminal is connected to the main control terminal device via a USB interface to send analog input signals to the main control terminal device; the main control terminal device runs the application under test and outputs image signals.

[0073] The central control module is connected to the main control terminal device via a USB interface, physically reusing the same transmission line, and logically divided into a Human Interface Device (HID) channel and a virtual serial port channel.

[0074] The photoelectric feedback module is attached to the display screen and converts changes in screen brightness into electrical signals.

[0075] In one embodiment, the central control module employs a microcontroller with microsecond-level timing capabilities, such as a Raspberry Pi Pico, RP2040, RP2350, or STM32F411.

[0076] The microcontroller is configured as a composite USB device, having at least a USB HID device interface and a USB Communication Device Class (CDC) virtual serial port interface, and can be simultaneously enumerated as an HID device for simulating peripheral input (e.g., a USB HID keyboard / mouse device) and a virtual serial port device for communicating with a host computer.

[0077] The microcontroller detects the digital signal of the physical trigger module in a polling manner through GPIO pins, and acquires the brightness signal simulated by the photoelectric feedback module through the microcontroller's built-in analog-to-digital converter interface.

[0078] The central control module has a built-in dynamic window calibration logic module, which is used to adaptively determine screen brightness jumps based on the brightness signal and record them as the endpoint time. The dynamic window calibration logic module specifically executes a dynamic window calibration algorithm, including: continuously sampling the brightness signal during the waiting trigger phase to update the brightness extreme value window in real time, and generating an adaptive threshold range based on the brightness extreme value window and a preset safety margin; when the brightness value of the real-time brightness signal collected after the start time exceeds the adaptive threshold range, the central control module determines it as a screen brightness jump and records it as the endpoint time. The dynamic window calibration algorithm adapts to changes in ambient light, changes in global screen brightness, and periodic fluctuations caused by PWM dimming, significantly reducing false triggers and missed detections compared to the fixed threshold method.

[0079] The central control module has a built-in reference loop measurement module for measuring the system input stack delay from the time the main control terminal device responds to a hardware interrupt to the time the system kernel captures the input message. Specifically, the reference loop measurement module uses a self-simulated loop-based kernel delay measurement mechanism to control the hardware measurement terminal to conduct simulated physical button triggers through internal circuitry and send a standard input message to the system through the USB HID interface. The central control module records the sending time. After capturing the input message, the host computer sends back an acknowledgment command through the USB CDC virtual serial port. The system uses this round-trip process to measure and separate the pure electrical delay (excluding peripheral physical mechanical structures) from the host system kernel processing delay as the system input stack delay, which is used as the reference value for constructing a delay decomposition model.

[0080] In one embodiment, such as Figure 2 As shown, the physical trigger module includes at least a conductive trigger medium and a signal connection circuit. The signal connection circuit is used to construct a closed-loop trigger structure, including at least a signal line and a ground loop. The conductive trigger medium is attached to the surface of an operable component (e.g., a button) of the peripheral under test. The signal connection circuit includes at least a signal line, a pull-up resistor, and a debouncing circuit. One end of the signal connection circuit is connected to the conductive trigger medium via a signal line, and the other end is connected to a GPIO pin of the MCU, configuring the GPIO pin in pull-up input mode. The debouncing circuit is used to eliminate the influence of mechanical jitter caused by physical contact on the trigger signal, ensuring the accuracy of the start time.

[0081] In practice, the user / operator holds the alligator clip and connects it to the system ground potential or a preset low potential point; at the instant the peripheral device under test is operated, the conductive trigger medium forms a closed loop with the system ground, causing the GPIO of the central control module to be pulled from the pull-up input state to the low level; the central control module records the trigger signal corresponding to the low-level transition as the starting time T0 of the delay timer.

[0082] In one embodiment, the debounce time threshold of the debounce circuit is set to 10µs to ensure sufficient filtering of typical mechanical jitter noise generated when a human hand touches the conductive trigger medium, while ensuring a high response speed to real physical trigger events. The debounce function of the debounce circuit can be implemented through an internal digital filter of the MCU, programmable logic, or an external RC circuit (a circuit composed of resistors and capacitors).

[0083] In one embodiment, the conductive triggering medium is a soft conductive material, such as copper foil tape.

[0084] In one embodiment, the photoelectric feedback module uses a high-sensitivity photosensitive sensor (such as TEMT6000 or a high-speed photodiode) attached to the surface of the display screen to convert the screen light signal into an analog voltage output to the ADC interface of the MCU for capturing the endpoint time T1.

[0085] In one embodiment, the test mode includes at least: display latency test (M1), end-to-end latency test (M2), peripheral latency test (M3), response speed test (M4), and grayscale latency test (M5).

[0086] The screen brightness change detection includes screen brightness jump detection and screen brightness gradual change detection;

[0087] The start time of the display latency test is determined based on the event fed back by the instruction, and the end time is determined based on the detection of screen brightness jump.

[0088] The start time of the end-to-end latency test is determined based on an externally triggered event, and the end time is determined based on the detection of screen brightness jumps.

[0089] The peripheral latency test includes both real peripheral path measurement and ideal peripheral path measurement;

[0090] In the actual peripheral path measurement, the starting time is determined based on externally triggered events, and the ending time is determined based on events fed back from instructions.

[0091] In the ideal peripheral path measurement, the starting time is determined by the simulation generated internally by the central control module based on externally triggered events, and the ending time is determined based on the events fed back by the instruction.

[0092] The start and end times of the reaction speed test are determined based on externally triggered events.

[0093] The starting time of the grayscale delay test is determined based on the event fed back by the instruction, and the ending time is determined based on the screen brightness gradient detection.

[0094] The central control module establishes a bidirectional communication connection with the physical trigger module, the photoelectric feedback module, and the host computer (e.g., a bidirectional communication link via a USB CDC virtual serial port).

[0095] Specifically, the host computer and the central control module establish a bidirectional communication link through a USB CDC virtual serial port to send test commands and receive measurement data.

[0096] In one embodiment, the RTT delay compensation module built into the host computer, such as Figure 3 As shown, the method is used to obtain the RTT value by measuring the round-trip time of a specific instruction and to estimate the one-way communication delay t_serial = RTT / 2, and to perform delay compensation on the original delay measurement value involving instruction interaction; the host computer further captures the HID input message time point on the peripheral data path of the host operating system through system hooks based on signal loopback logic, so as to support the measurement of the delay between the peripheral path and the system input stack.

[0097] The host computer also has a built-in end-to-end delay breakdown and analysis module, which is used to combine and differentially calculate measurement data based on different test modes, and output sub-delay indicators and derived results.

[0098] The end-to-end delay breakdown and analysis module defines and calculates multiple delay data to be analyzed based on multi-test mode measurement data:

[0099] The display circuit delay t_disp_circ is defined as the minimum measured value of the original delay after RTT delay compensation in the display delay test (M1):

[0100] t_disp_circ=min(M1_raw)+t_serial;

[0101] Where M1_raw is the raw delay measurement value of M1 mode, that is, from the moment the central control module receives the start command from the host computer to the moment the photoelectric sensor detects the screen brightness jump; min() is the minimum value function;

[0102] The average display latency t_disp_avg is defined as the mean of the original latency measurements after RTT latency compensation in the display latency test:

[0103] t_disp_avg = mean(M1_raw) + t_serial;

[0104] Where mean() is the average value function; and the average display delay and the display circuit delay satisfy t_disp_avg = t_disp_circ + T_refresh / 2;

[0105] The display refresh interval T_refresh is 2×(t_disp_avg) t_disp_circ) yields:

[0106] T_refresh = 2 × (t_disp_avg) t_disp_circ)= 2 × [mean(M1_raw) min(M1_raw)];

[0107] The ideal end-to-end latency L_ref is defined as the raw latency measurement value of the end-to-end latency test under ideal graphics load;

[0108] The actual application end-total latency L_total is defined as the raw latency measurement value of the end-to-end latency test under real application load;

[0109] Ideal peripheral latency L_periph_ideal is defined as the measurement metric of the raw latency measurement M3_ideal_raw of the ideal peripheral path after RTT latency compensation:

[0110] L_periph_ideal = M3_ideal_raw t_serial;

[0111] Real peripheral latency L_periph_real is defined as the measurement metric of the raw latency measurement M3_real_raw of the real peripheral path after RTT latency compensation:

[0112] L_periph_real = M3_real_raw t_serial;

[0113] The system input stack delay t_host_input is defined as: t_host_input = L_periph_ideal T_poll / 2, where T_poll is the USB polling interval; t_usb_half = T_poll / 2 is the average waiting time of the USB polling interval (or the half-interval of the USB polling).

[0114] Application processing and rendering submission latency L_sys represents the latency between receiving an input message from the host terminal device and submitting the rendering command to the display pipeline (input event → application logic processing → rendering engine processing → image API call → driver processing → submission). Specifically:

[0115] Defined as the ideal end-to-end latency under ideal load (e.g., pyglet). L_periph_ real t_disp_avg, that is:

[0116] L_sys=L_ref L_periph_ real t_disp_avg;

[0117] Defined as the end-to-end latency under actual load. L_periph_real t_disp_avg, that is:

[0118] L_sys=L_total L_periph_real t_disp_avg;

[0119] The refresh phase contribution t_vsync_phase is defined as:

[0120] t_vsync_phase=t_disp_avg t_disp_circ = T_refresh / 2;

[0121] The grayscale 10%→90% response matrix uses the 8×8 pixel response time GtG output from the grayscale test mode as matrix elements;

[0122] Pixel completion delay, under ideal / real-world load conditions, is defined as the sum of the ideal end-to-end delay / actual application end-to-end delay and the pixel response time in the grayscale 10%→90% response matrix, respectively:

[0123] Ideal pixel completion delay: L_full_pixel_ideal = L_ref + GtG;

[0124] Actual pixel completion delay in practical applications: L_full_pixel_actual = L_total + GtG;

[0125] Average pixel completion delay: t_pixel_avg = t_disp_avg + GtG;

[0126] Minimum pixel completion delay: t_pixel_min = t_disp_circ + GtG_min.

[0127] Using these metrics, and latency data obtained from at least two test modes with different measurement principles, calculate and decompose at least two of the following measurements: peripheral hardware latency, display latency, system processing latency, and application-related latency. Specifically:

[0128] Peripheral hardware latency L_hardware is calculated by breaking it down using latency data measured from the actual peripheral path in peripheral latency testing (real peripheral latency L_periph_real), system input stack latency t_host_input, and average waiting time of USB polling interval.

[0129] L_hardware = L_periph_real t_host_input t_usb_half;

[0130] Display latency is directly represented by the latency data to be analyzed in the display latency test, that is, the average display latency t_disp_avg in the display test;

[0131] The system processing latency (application processing and rendering submission latency L_sys under ideal load) is calculated by breaking it down using the latency data to be analyzed measured under ideal load in the end-to-end latency test (ideal end-to-end latency L_ref), the latency data to be analyzed measured on the actual peripheral path in the peripheral latency test (real peripheral latency L_periph_real), and the latency data to be analyzed in the display latency test (display average latency t_disp_avg), and is given by the following formula:

[0132] L_sys=L_ref L_periph_real t_disp_avg;

[0133] The additional latency of the application is calculated by breaking it down using the latency data to be analyzed under actual application conditions in the end-to-end latency test (actual application end-to-end latency L_total) and the latency data to be analyzed under ideal load conditions in the end-to-end latency test (ideal end-to-end latency L_ref), and is given by the following formula:

[0134] L_engine = L_total L_ref.

[0135] In one embodiment, such as Figure 4 As shown, the present invention also provides a multi-mode highly adaptive terminal peripheral latency measurement method, which utilizes the aforementioned multi-mode highly adaptive terminal peripheral latency measurement system to implement the method steps, the method comprising:

[0136] Step 100: Use the built-in mode selection and configuration module of the host computer to select the test mode and configure the test parameters, and send the test mode command and the configured test parameters to the hardware measurement terminal.

[0137] Step 110: According to the selected test mode, the central control module determines and records the start time based on the event judgment of different measurement principles, and starts the corresponding signal acquisition.

[0138] Step 120: Based on the selected test mode, use the central control module to determine and record the endpoint time;

[0139] Step 130: The host computer and the central control module engage in bidirectional communication to obtain the original delay measurement value corresponding to the test mode.

[0140] Step 140: Using the RTT delay compensation module built into the host computer, estimate the one-way communication delay by means of the round-trip time of the command, and compensate the original delay measurement value involving command interaction to obtain the delay data to be analyzed.

[0141] Step 150: Obtain the latency data to be analyzed under at least two test modes with different measurement principles, and use the full-link latency decomposition and analysis module built into the host computer to decompose and calculate it, and output at least two of the measurement results of peripheral hardware latency, display latency, system processing latency and application additional latency.

[0142] The method supports multiple test modes:

[0143] The display latency test mode is used when the host computer is running an ideal graphical window with high-frequency screen switching. At the same time that the window switches from white to black, a start command is sent to the central control module. The central control module starts timing after receiving the command and stops timing when the photoelectric feedback module detects a change in screen brightness. The original measurement value of the display latency test mode has a small measurement deviation because the timing start is later than the screen switching. The compensation value is obtained through RTT compensation. The minimum value after compensation corresponds to the display circuit latency, and the average value after compensation corresponds to the display average latency. Neither of them contains grayscale latency.

[0144] The end-to-end latency test mode is used to start from the physical trigger module detecting that the copper foil is connected to the system ground and end with the photoelectric feedback module determining the screen brightness jump. When the host computer is running an ideal graphics load, the ideal end-to-end latency is output. When the host computer is running a real application or game load, the actual application end-to-end latency is output. The results do not include grayscale latency.

[0145] Peripheral latency testing includes two measurement paths: real peripherals and ideal peripherals.

[0146] The actual peripheral path measurement starts with the physical trigger module causing the GPIO to be pulled low. After the host computer captures the HID input message of the peripheral on the host terminal device through the underlying system hook, it immediately notifies the central control module to stop timing through the USB CDC virtual serial port to obtain the original delay measurement value of the actual peripheral path measurement. After t_serial compensation, the actual peripheral delay is output.

[0147] The ideal peripheral path measurement is performed by the central control module, which enumerates a USB HID dummy keyboard. At the instant the copper foil is grounded, a HID message is automatically sent. The host computer picks up this message and sends a stop command back via the USB CDC virtual serial port, obtaining the total hardware interrupt loopback time. This is used as the raw delay measurement value for the ideal peripheral path measurement. After t_serial compensation, the ideal peripheral delay is output. The ideal peripheral delay, combined with the USB HID device descriptor, can estimate the USB polling interval T_poll. T_poll / 2 is used as the average phase wait term to deduct polling phase uncertainty, thereby evaluating the system input stack delay.

[0148] The reaction speed test mode is an additional function in the embodiment. For example, it starts with the contact of a conductive trigger medium (such as copper foil). After the central control module of the system waits randomly, the indicator light is lit. The operator releases the copper foil, and the system records the human-machine reaction time.

[0149] The grayscale delay test mode is used to select eight preset grayscale values ​​for calibration, and switch between the grayscale values ​​in pairs to calculate the response time from 10% to 90% change, and output an 8×8 grayscale response matrix. The grayscale response can be superimposed with the display circuit delay or the display average delay to obtain the minimum or average delay of pixel completion.

[0150] The host computer performs batch statistical processing on the raw data of each test mode, and outputs indicators such as minimum value, mean, and standard deviation; the host computer applies t_serial compensation to the display latency test and peripheral latency test involving serial port interaction; the peripheral latency distribution is used to estimate the USB polling interval T_poll and its half interval; the end-to-end latency breakdown and analysis module supports outputting and naming the following indicators: t_disp_circ, t_disp_avg, T_refresh, ideal end-to-end latency, actual application end-to-end latency, L_periph_ideal, L_periph_real, t_host_input, t_app_submit_ideal, t_app_submit_actual, t_vsync_phase, grayscale 10%→90% response matrix (elements are pixel response time GtG), and pixel completion latency (including ideal / actual indicators: ideal pixel completion latency L_full_pixel_ideal, actual application pixel completion latency L_full_pixel_actual).

[0151] Therefore, the key points and parameter configurations of this embodiment include at least the following: the physical trigger module adopts a structure with conductive trigger medium (such as copper foil) attachment and alligator clip grounding; the GPIO is configured as a pull-up input to detect low-level transitions caused by conduction; the photoelectric feedback module is fixed to a designated area of ​​the screen by adsorption or adhesive, and performs brightness sampling synchronously with the timing reference of the central control module; the dynamic window calibration algorithm constructs an adaptive threshold with a brightness extreme value window and a safety margin to resist ambient light and PWM flicker; the USB composite device provides both HID and CDC channels, with the CDC channel used for mode control, start / stop commands, and data feedback; the host computer periodically performs RTT measurements to update t_serial; the ideal graphics load uses high-frequency screen switching (10,000-frame window white / black switching), and the actual load uses typical high frame rate applications or games; the calibration and compensation rules include t_serial compensation for the starting deviation of M1 and M3, average deduction of the USB phase uncertainty of the peripheral path using T_poll / 2, and superimposing grayscale response time when necessary for pixel completion requirements.

[0152] Specifically, step 110 includes:

[0153] For display latency testing or grayscale latency testing, the central control module waits for and receives instructions sent by the host computer, and records the time when the instruction arrives as the starting time.

[0154] For end-to-end latency testing, peripheral latency testing, real peripheral path measurement, or response speed testing, the physical trigger module is enabled to generate a trigger signal when the peripheral under test is operated, which is recorded as the starting moment.

[0155] For ideal peripheral path measurement in peripheral latency testing, a simulated trigger signal is directly generated internally by the central control module and recorded as the starting moment.

[0156] Furthermore, step 120 includes:

[0157] For display latency testing or end-to-end latency testing, the central control module, based on the brightness signal collected by the photoelectric feedback module, uses a built-in dynamic window calibration logic module to execute a dynamic window calibration algorithm to adaptively determine screen brightness jumps and records them as the endpoint time. The dynamic window calibration algorithm includes: continuously sampling the brightness signal during the waiting trigger phase, updating and recording the minimum and maximum brightness values ​​within the sampling window in real time to obtain a dynamically changing brightness extreme value window; generating an adaptive threshold range based on the brightness extreme value window and a safety margin; when the real-time brightness signal collected after the starting time exceeds the range of the adaptive threshold range, it is determined as a screen brightness jump and recorded as the endpoint time.

[0158] For the actual peripheral path measurement or ideal peripheral path measurement of peripheral latency testing, the central control module waits for the host computer to send a stop command through the bidirectional communication link, and records the time of receiving the stop command as the end time.

[0159] For the reaction speed test, the central control module detects the recovery of the trigger signal of the physical trigger module and records the signal recovery time as the endpoint time;

[0160] For grayscale delay testing, the central control module determines the completion of screen brightness gradation based on the brightness signal collected by the photoelectric feedback module, and records the determination time of the completion of screen brightness gradation as the endpoint time.

[0161] In one embodiment, when (multiple test mode combinations) it is necessary to calculate peripheral hardware latency, the central control module uses the built-in reference loop measurement module, based on the kernel latency measurement mechanism of self-simulated loopback, to execute the system input stack latency of the main control terminal device from responding to hardware interrupt to the system kernel capturing the input message;

[0162] The self-simulated loopback kernel latency measurement mechanism, such as Figure 5 As shown, it includes:

[0163] The central control module is set to simulate peripheral working mode. It generates a trigger signal for the simulated button by pulling down its own GPIO pin or triggering the internal logic. The timing starts from the starting point, and the HID input message is sent to the host computer through the USB HID interface.

[0164] When the host computer captures the HID input message through the system hook based on signal loopback logic, it immediately sends an acknowledgment command to the central control module through the virtual serial port.

[0165] Upon receiving the confirmation command, the central control module stops timing, obtains the total hardware interrupt loopback duration, and uploads it to the host computer.

[0166] The host computer compensates for the total time of the hardware interrupt loopback based on the one-way communication delay measured by the built-in RTT delay compensation module, removes the influence of one-way communication delay and average waiting time of USB polling interval, and obtains the system input stack delay from the main control terminal device responding to the hardware interrupt to the system kernel capturing the HID input message.

[0167] The combination of multiple test modes that requires calculation of peripheral hardware latency actually refers to a combination of multiple test modes that includes actual peripheral path measurements for peripheral latency testing.

[0168] Further, in step 150, the end-to-end latency decomposition and analysis module built into the host computer calculates and decomposes at least two measurement results from the peripheral hardware latency, display latency, system processing latency, and application additional latency based on the latency data obtained from at least two test modes with different measurement principles. These include:

[0169] The peripheral hardware latency is represented by the latency data measured in the actual peripheral path during peripheral latency testing, the system input stack latency, and the average waiting time of the USB polling interval.

[0170] L_hardware = L_periph_real t_host_input t_usb_half;

[0171] The display latency is directly represented by the latency data to be analyzed in the display latency test: the average display latency t_disp_avg in the display test;

[0172] The system processes latency by breaking it down and representing it using latency data measured under ideal load in end-to-end latency testing, latency data measured on the actual peripheral path in peripheral latency testing, and latency data to be analyzed in display latency testing:

[0173] L_sys=L_ref L_periph_real t_disp_avg;

[0174] Additional application latency is represented by decomposing the latency data to be analyzed from both real-world application latency data and ideal load latency data measured in end-to-end latency testing:

[0175] L_engine = L_total L_ref.

[0176] In one embodiment, the core measurement capability of the multi-mode highly adaptive terminal peripheral latency measurement method is achieved through three basic test modes. Each mode measures different links in the latency chain, and the data, after compensation, can be used for subsequent collaborative analysis.

[0177] (a) Monitor Latency Test Mode (M1)

[0178] This mode is designed to measure the latency characteristics of the main control terminal device's display independently.

[0179] Operation: The host computer runs an ideal graphics test window capable of rendering at extremely high frame rates (e.g., a full-screen "10,000-frame window" created using the Pyglet library) on the main control terminal device. This window periodically switches between pure white and pure black. At the same time as issuing the screen switching control command, the host computer sends a "start timing" command to the central control module through a virtual serial port.

[0180] Measurement: The central control module takes the moment of receiving the "start timing" command as the starting point (T0) and then continuously monitors the screen brightness; once the expected brightness jump (such as white to black) is detected by the dynamic window calibration algorithm, the end time (T1) is recorded, and the raw delay measurement value M1_raw = T1 - T0 is obtained.

[0181] Compensation and Calculation: Due to the one-way delay t_serial in instruction transmission, M1_raw is systematically less than the actual delay, which requires compensation.

[0182] The display circuit delay t_disp_circ = min(M1_raw) + t_serial represents the shortest time for a signal to reach the display driver circuit, excluding refresh wait.

[0183] The average display latency t_disp_avg = mean(M1_raw) + t_serial, which includes the average waiting time due to the randomness of the display refresh cycle phase;

[0184] The display refresh interval T_refresh = 2 × (mean(M1_raw)) min(M1_raw)). Theoretically, t_disp_avg = t_disp_circ + T_refresh / 2.

[0185] (ii) End-to-end latency test mode (M2)

[0186] This mode measures the total end-to-end latency from physical operation of a peripheral device to visual feedback generated on the screen.

[0187] Operation: Correctly connect the physical trigger module (copper foil attached to the peripheral device under test) and the photoelectric feedback module (attached to the screen); the host computer controls the main control terminal device to run a specific graphics load.

[0188] Measurement: Starting from the physical trigger module detecting the peripheral operation (GPIO falling edge) as the starting point (T0), and ending from the photoelectric feedback module determining the screen brightness jump as the endpoint (T1), the original delay measurement value is obtained.

[0189] Classification:

[0190] Ideal end-to-end latency (L_ref): Measured when the master terminal device is running an ideal graphics load with extremely simple, extremely high frame rates (e.g., >6000 FPS) and limitations such as vertical synchronization (V-Sync) are disabled. The graphics processing pipeline latency is extremely low under this environment.

[0191] Real-world end-total latency (L_total): Measured when the main control terminal device is running a real application or game. This value includes additional latency introduced by application logic, complex rendering, graphics API overhead, etc.

[0192] (III) Peripheral Delay Test Mode (M3)

[0193] This mode is used to separate the measurement of the peripheral's own hardware latency and the operating system's input stack latency, and includes two measurement paths.

[0194] Real peripheral path (used to obtain L_periph_real):

[0195] Operation: Use a real keyboard or mouse under test as the test object, with conductive copper foil attached to its buttons / microswitches.

[0196] Measurement: Starting with the operation of the peripheral device (GPIO of the physical trigger module being pulled low); at the same time, the real peripheral device will send an HID message to the host terminal device through its own USB / BT connection; the system hook module of the host computer immediately sends a "stop timing" command to the central control module through the virtual serial port the moment it captures this HID message; when the central control module receives the command, it records the endpoint; and obtains the raw delay measurement value M3_real_raw.

[0197] Compensation: Real peripheral latency L_periph_real = M3_real_raw - t_serial, which includes the total time for peripheral internal scanning, debouncing, encoding / decoding, wireless transmission (if any), USB polling wait, and host operating system input stack processing.

[0198] Ideal peripheral path / reference loop measurement (used to obtain L_periph_ideal and t_host_input):

[0199] Operation: The central control module enumerates its USB HID interface as a virtual keyboard (dummy keyboard); the conductive medium of the physical trigger module is connected to another GPIO of the MCU that can be controlled to a low level by the program through a short wire, forming an internal "reference loop".

[0200] Measurement: When the test begins, the central control module performs two actions the instant it detects that the GPIO of the physical trigger module is pulled low (simulating a button press): a) Record the start time (T0); b) Immediately trigger a simulated button press event through its HID interface.

[0201] Loopback: After the host computer hook captures this spontaneous HID event, it immediately sends back a "stop timing" command through the virtual serial port; after receiving the command, the central control module records the endpoint (T1); and obtains the raw delay measurement value of the end-to-end delay test M3_ideal_raw = T1 - T0.

[0202] Compensation and decomposition:

[0203] The ideal peripheral latency L_periph_ideal = M3_ideal_raw - t_serial; since this path completely bypasses the physical and internal firmware processing of the real peripheral, L_periph_ideal mainly consists of two parts: the average waiting time for USB communication polling t_usb_half (i.e., T_poll / 2), and the latency t_host_input for the host operating system input stack to process the event.

[0204] The system input stack latency t_host_input = L_periph_ideal - t_usb_half. The USB polling interval T_poll can be obtained from the bInterval field of the HID device descriptor, or cross-validated by analyzing the distribution of multiple L_periph_ideal measurements (the difference between the maximum and minimum values).

[0205] In one embodiment, the multi-mode adaptive terminal peripheral latency measurement method also supports the following extended test modes:

[0206] Reaction Speed ​​Test Mode (M4): This mode is used to measure human-machine reaction time and does not participate in system delay analysis. Starting with the user touching the copper foil (GPIO pulled low), the central control module illuminates an indicator light after a random delay. The endpoint is when the user immediately releases the copper foil (GPIO returns to high level) after seeing the indicator light. The measured time primarily reflects the user's perception and motor nerve reaction time.

[0207] Gray-scale delay test mode (M5): This mode is specifically designed to measure the pixel response time (GtG) of displays such as LCDs and OLEDs. First, calibration is performed: the host computer control screen sequentially displays a set of preset gray-scale values ​​(e.g., 8). The central control module records the stable brightness value corresponding to each gray-scale through a photoelectric feedback module, establishing a gray-scale-brightness lookup table. Subsequently, the host computer control screen switches between all gray-scale pairs. For each switch, the central control module calculates the time required for the brightness to change from 10% to 90% according to the calibration table; this is the response time GtG (10%->90%) for that gray-scale pair. Finally, an 8x8 gray-scale response matrix is ​​output. This data can be superimposed with the results of M1 or M2 to obtain the pixel completion delay (e.g., L_total + GtG), more realistically reflecting visual motion blur in dynamic scenes.

[0208] In one embodiment, based on the compensated baseline index obtained from modes M1, M2, and M3, the end-to-end delay decomposition and analysis module decomposes the total delay into independent components with clear physical meaning according to the following mathematical model:

[0209] Peripheral hardware latency: L_hardware = L_periph_real - t_host_input - t_usb_half.

[0210] The above formula can be understood as follows: by deducting the input stack processing time (t_host_input) and the inherent waiting time of USB communication (t_usb_half) belonging to the system side from the total experience latency of the actual peripheral, the latency purely introduced by the peripheral itself (including sensors, mechanical structure, internal MCU, wireless module, etc.) can be separated.

[0211] System processing latency: L_sys = L_ref - L_periph_real - t_disp_avg.

[0212] The above formula can be understood as follows: under ideal graphics load, the ideal end-to-end latency, after deducting the latency from peripherals to the system and the average latency of the display, is the remaining part of the time consumed by the operating system's graphics subsystem (drivers, graphics APIs, compositors) and the process of submitting rendering commands to the GPU.

[0213] Additional application latency: L_engine = L_total - L_ref.

[0214] The above formula can be understood as the difference between the total latency of actual application and the total latency of ideal load, which directly quantifies the additional overhead brought by application logic such as game engine, complex scene rendering, physics simulation, and network synchronization.

[0215] Implementation parameters and accuracy verification

[0216] Example of key parameter configuration:

[0217] Firmware parameters: Dynamic window update cycle: 100 ms; Safety margin Delta: set according to sensor noise (typical value 5-20 ADC counts); ADC sampling rate: ≥10 kHz.

[0218] Host computer parameters: Number of RTT measurements: 600 (average); Ideal graphics load settings: borderless full screen, V-Sync off, presentation mode set to "Immediate".

[0219] Physical connection: Ensure that the conductive copper foil is in close contact with the moving parts of the peripheral device under test and that there is no looseness; ensure that the photoelectric sensor is firmly attached and that there is no ambient light leakage.

[0220] In one embodiment, the software interface and workflow of the host computer are as follows:

[0221] To enable flexible mode combinations and convenient operation, the host computer software provides an intuitive graphical user interface (GUI) and supporting workflows.

[0222] Main control panel: The pattern repository displays all available test patterns (M1, M2, M3, M4, L_sys) in the form of icon cards.

[0223] Dynamic parameter panel: When the user selects one or more modes, the interface automatically displays relevant, configurable parameter controls (such as sampling rate, debouncing time, USB polling preset value, load selection, etc.).

[0224] Test flow orchestrator:

[0225] Visual orchestration: Users can drag and drop pattern icons from the "Pattern Repository" to the "Test Sequence Track" on the right, freely combine and sort them to build custom test processes.

[0226] Preset templates: The software has built-in commonly used templates such as "Quick Evaluation of Peripherals" and "Complete System Analysis", which can be loaded with one click.

[0227] Logic control: Supports inserting "conditional judgment" (e.g., if M1 measures t_disp_avg>10ms, then M5 will be automatically executed for grayscale testing) and "loop" into the sequence.

[0228] Real-time monitoring and data dashboards:

[0229] During test execution, the interface displays real-time curves, including brightness sampling waveforms, adaptive threshold lines, and trigger markers, enabling users to monitor measurement quality in real time.

[0230] The raw data list is updated in real time and includes simple statistics (current value, mean, standard deviation).

[0231] Intelligent Reporting System:

[0232] The results view is adaptive: the software automatically switches to the most suitable results display view based on the final combination of execution modes. For example, if only M1 and M3 are executed, the hardware metrics dashboard is mainly displayed; if the complete combination is executed, the Sankey diagram of the entire chain decomposition is displayed.

[0233] Report generation: Generate a comprehensive report (HTML / PDF format) containing all data, charts, and analysis conclusions with one click, and export the raw data for further analysis.

[0234] Workflow Example: If a user wants to perform a complete system analysis, they only need to load the "Complete System Analysis" template on the interface and click Start; the software will automatically execute: RTT Calibration → M1 Monitor Test → M3 Ideal Path Test → M3 Real Path Test → M2 Ideal Load Test → M2 Actual Game Test; after all tests are completed, a professional report containing a full-link breakdown diagram and detailed data for each stage will automatically pop up.

[0235] The real-time key points of an application should include at least:

[0236] Graphics load: Ideally, V-Sync should be turned off, full screen should be exclusively used, the synchronization mode should be set to Immediate, and the frame rate should be increased to several thousand FPS to suppress graphics pipeline queue latency.

[0237] USB descriptor: Readable bInterval can estimate T_poll; if the platform driver has an aggregation scheduling mechanism, it can be determined through the ideal peripheral latency distribution (mean). Minimum value cross-validation.

[0238] Gray-scale calibration: First, the brightness values ​​of 8 gray-scale points are acquired and mapped in M5, and then GtG measurements are performed in pairs; overshoot records are used to characterize the impact of panel driving strategy on dynamic response.

[0239] Platform compatibility: The host computer software can be implemented on platforms such as Windows, Linux, and Android, with the core concept remaining unchanged; the choice of Hook / Raw Input interface needs to be adjusted according to the platform API.

[0240] In summary, this invention provides a multi-mode, highly adaptable terminal peripheral latency measurement system and method. Through hardware and software co-design, it solves the core problems of large errors and lack of traceability in terminal interaction latency measurement, achieving multi-dimensional, high-precision, and decomposable measurement capabilities, while also possessing excellent practicality and economy. Specifically, the following beneficial effects are achieved:

[0241] (1) Accurately locate performance bottlenecks by combining multi-mode measurement and full-link delay decomposition analysis: By integrating test modes based on multiple measurement principles (such as full-link, peripheral, and display tests) and using the full-link delay decomposition analysis module for joint calculation, a fine decomposition of total delay is realized for the first time; it can quantify and decompose independent components such as peripheral hardware delay, system input stack delay, application additional delay, and display delay (including circuit and refresh phase), enabling users to accurately locate performance bottlenecks and perform targeted optimization;

[0242] (2) High-precision anti-interference measurement is achieved by adopting dynamic window calibration algorithm and error compensation mechanism: By adopting dynamic window calibration algorithm to adaptively determine screen brightness jump, it effectively resists the interference of ambient light changes, screen content and animation switching, and improves the measurement stability in complex environments; by using RTT delay compensation and USB phase analysis, the error introduced by communication link and system polling is significantly removed, and more realistic hardware delay data is obtained, so as to achieve high-precision measurement in PC and other scenarios. The standard deviation of keyboard and mouse delay test is close to the physical limit, and the monitor delay test conforms to the theoretical refresh phase.

[0243] (3) It has broad compatibility and high versatility: The system is compatible with various input devices such as keyboards, mice, and gamepads, and supports various displays such as LCD, OLED and DC dimming, covering multiple platforms from PC to common host; multi-mode integration provides five test modes: display latency, peripheral latency, end-to-end latency, response speed and grayscale latency, to meet the diverse needs of various scenarios from hardware evaluation to application optimization; it has strong environmental adaptability and can work stably under different ambient light conditions;

[0244] (4) Achieve low cost and high reproducibility: The hardware is compatible with general development boards (such as Raspberry Pi Pico) and common electronic components, without the need for special boards and soldering, resulting in extremely low hardware costs; it is built based on general components and standard interfaces, has high reproducibility and ease of use, which is conducive to the rapid popularization and application of the technology.

[0245] The present invention also obtained delay measurement results through experiments and verified accuracy and robustness. In actual tests, the system demonstrated high accuracy and strong robustness.

[0246] Measurements were taken on an 8000 Hz polling rate composite USB device developed using Teensy 4.0: HID-side latency was approximately 0.3 ms, with a standard deviation of approximately 0.05 ms (this value is a composite of the average wait time for 8000 Hz polling and the system input stack latency t_host_input; the system term can be subtracted as needed to obtain the pure peripheral hardware latency). Measurements included:

[0247] Measuring an 8000 Hz mouse: standard deviation approximately 0.08–0.10 ms, close to the theoretical limit for the Windows platform;

[0248] 1000 Hz mouse: theoretical standard deviation approximately 0.29 ms, actual standard deviation approximately 0.30–0.34 ms;

[0249] Magnetic axis keyboards (such as the CK75, actuation distance 0.04 mm, 8000 Hz): peripheral latency approximately 2.3 ms, standard deviation approximately 0.08 ms;

[0250] 300 Hz gaming monitor: Theoretical refresh rate phase standard deviation is approximately 0.963 ms, actual measurement is 0.91~0.94 ms;

[0251] 60 Hz monitor: Theoretical refresh phase standard deviation is about 4.82 ms, actual measurement is 4.6~4.9 ms.

[0252] Robustness and compatibility performance:

[0253] The dynamic window algorithm is adapted to OLED dimming and various DC dimming displays with a dimming range of up to 80%.

[0254] The physical trigger module is compatible with various input devices and touch screens, including mechanical, magnetic axis, and optical axis keyboards, gamepads, graphics tablets, and touchpads.

[0255] In keyboard and mouse latency and end-to-end latency tests, the garbage data rate was less than 5%, the monitor latency test success rate was approximately 99%, and the grayscale test success rate was over 95%.

[0256] The test does not require preset specific screen brightness or ambient light conditions.

[0257] The core advantage of this invention lies in the flexible combination of test modes and data collaboration. Users can select at least two modes for combined testing based on specific evaluation objectives, and the system will automatically complete data fusion and in-depth analysis. Several typical application scenarios are listed below:

[0258] Scenario A: Quick Guide to Selecting Peripherals and Monitors (Combination: M1 + M3);

[0259] Suitable for: General users to quickly assess the basic performance of a newly purchased keyboard, mouse, or monitor.

[0260] Operation: Execute "Display Latency Test (M1)" and "Peripheral Latency Test (M3, including real path)" in sequence.

[0261] Output: The system directly reports two core hardware metrics, t_disp_avg (average display latency) and L_hardware (peripheral hardware latency), to help users intuitively compare the response speed of different products.

[0262] Scenario B: In-depth performance tuning of e-sports system (combination: M1 + M2 + M3).

[0263] Suitable for: esports players, hardware enthusiasts, or system administrators to perform end-to-end bottleneck analysis and optimization;

[0264] Operation: Execute M1, M3 (ideal + real), M2 (ideal load), and M2 (actual game load) in sequence. The software supports a "one-click test suite" to automatically complete the entire sequence.

[0265] Output: The system generates a complete latency breakdown report, including all five sub-indicators: L_hardware, t_host_input, t_disp_avg, L_sys, and L_engine, visualized as a latency chain waterfall chart. Users can clearly pinpoint system bottlenecks, such as whether the issue is slow peripherals, insufficient system input optimization, improper graphics settings, or a slow monitor.

[0266] Scenario C: Display dynamic sharpness assessment (combination: M1 + M5 or M2 + M5);

[0267] Suitable for: Gamers or monitor reviewers who are concerned about the clarity of dynamic game visuals;

[0268] Operation: Execute M1 to obtain the basic display latency, and execute M5 to obtain the grayscale response matrix (GtG). If a more intuitive operation is desired, M2 can be added.

[0269] Output: In addition to the standard latency, pixel completion latency (t_disp_avg + GtG or L_total + GtG) is provided. This metric combines signal latency and pixel flip time and is a key indicator for evaluating whether a display produces "ghosting" or "blurring" in fast-moving scenes.

[0270] Scenario D: Operating System / Driver Input Performance Evaluation (Combination: M3 Ideal Path);

[0271] Applicable to: Developers or tech enthusiasts evaluating the impact of different operating system versions, driver versions, or system configurations on input response;

[0272] Operation: Repeat the "ideal peripheral path" in M3 mode only;

[0273] Output: The system outputs a detailed statistical report of t_host_input (system input stack latency), including the mean, standard deviation, distribution histogram, and percentiles. By comparing t_host_input under different system environments, the optimization effect on input response speed at the system level can be quantitatively evaluated.

[0274] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0275] On the other hand, the present invention provides a computer device including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the multi-mode highly adaptive terminal peripheral latency measurement method provided in any of the above embodiments. The computer device may be a server. The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device stores sample data. The network interface of the computer device is used for communication with an external PC via a network connection.

[0276] On the other hand, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements the steps of the multi-mode highly adaptive terminal peripheral delay measurement method provided in any of the above embodiments.

[0277] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by hardware related to computer program instructions. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0278] Matters not covered in this invention are common knowledge.

[0279] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0280] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

[0281] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-mode robust terminal peripheral latency measurement system, comprising: The system includes at least a hardware measurement terminal and a host computer; The host computer has a built-in mode selection and configuration module, an RTT delay compensation module, and a full-link delay breakdown and analysis module. The mode selection and configuration module is used to provide a test mode selection interface and configure test parameters; the start time and end time of the test mode are determined and recorded based on events of different measurement principles. The measurement principle includes screen brightness change detection, command feedback, and external triggering; The test modes include at least: display latency test, end-to-end latency test, peripheral latency test, response speed test, and grayscale latency test; The screen brightness change detection includes screen brightness jump detection and screen brightness gradual change detection; The start time of the display latency test is determined based on the event fed back by the instruction, and the end time is determined based on the detection of screen brightness jump. The start time of the end-to-end latency test is determined based on an externally triggered event, and the end time is determined based on the detection of screen brightness jumps. The peripheral latency test includes both real peripheral path measurement and ideal peripheral path measurement; In the actual peripheral path measurement, the starting time is determined based on externally triggered events, and the ending time is determined based on events fed back from instructions. In the ideal peripheral path measurement, the starting time is generated internally by the central control module and determined based on externally triggered events, while the ending time is determined based on events fed back from the instruction. The start and end times of the reaction speed test are determined based on externally triggered events. The starting time of the grayscale delay test is determined based on the event fed back by the instruction, and the ending time is determined based on the screen brightness gradient detection. The RTT delay compensation module is used to estimate the one-way communication delay by means of the round-trip time of the command, and to compensate for the original delay measurement value involving command interaction. The end-to-end latency decomposition and analysis module is used to calculate and decompose at least two of the following measurement results from peripheral hardware latency, display latency, system processing latency, and application additional latency, based on the latency data to be analyzed obtained from at least two test modes with different measurement principles; The hardware measurement terminal includes a physical trigger module, a central control module, and a photoelectric feedback module; The physical trigger module is used to generate a trigger signal when the peripheral device under test is operated; The photoelectric feedback module is used to collect the brightness signal of the display screen of the main control terminal device; The central control module is bidirectionally connected to the physical trigger module, photoelectric feedback module, and host computer, and is used to record the start time, send test commands, record the end time, and receive measurement data according to the selected test mode; the central control module has a built-in dynamic window calibration logic module and a reference loop measurement module.

2. The multi-mode strongly adaptive terminal peripheral delay measurement system of claim 1, wherein, The peripheral device under test is connected to the main control terminal device, which is the test target, through a standard interface; the display screen is connected to the main control terminal device through a video cable, or is directly integrated into the main control terminal device; the main control terminal device outputs the processed image signal to the display screen; The hardware measurement terminal is connected to the main control terminal device via a USB interface to send analog input signals to the main control terminal device; the main control terminal device runs the application under test and outputs image signals. The central control module is connected to the main control terminal device via a USB interface, physically reusing the same transmission line and logically divided into an HID channel and a virtual serial port channel. The photoelectric feedback module is attached to the display screen and converts changes in screen brightness into electrical signals.

3. The multi-mode strongly adaptive terminal peripheral delay measurement system of claim 2, wherein, The central control module uses a microcontroller with microsecond-level timing capability; The microcontroller is configured as a composite USB device, capable of being simultaneously enumerated as an HID device for simulating peripheral input and a virtual serial port device for communicating with a host computer. The microcontroller detects the digital signal of the physical trigger module in a polling manner through GPIO pins, and acquires the brightness signal simulated by the photoelectric feedback module through the analog-to-digital converter interface built into the microcontroller. The dynamic window calibration logic module is used to adaptively determine the screen brightness jump based on the brightness signal and record it as the endpoint time. The reference loop measurement module is used to measure the system input stack delay of the main control terminal device from responding to a hardware interrupt to the system kernel capturing the input message.

4. The multi-mode strongly adaptive terminal peripheral delay measurement system of claim 3, wherein, The physical triggering module includes at least a conductive triggering medium and a signal connection circuit; The conductive triggering medium is attached to the surface of the operable component of the peripheral device under test; The signal connection circuit is used to construct a closed-loop trigger structure, and includes at least a signal line and a ground loop; One end of the signal line is connected to the conductive trigger medium, and the other end is connected to a GPIO pin of the microcontroller, and the GPIO pin is configured as a pull-up input mode; When the operable component of the peripheral under test is operated, the conductive trigger medium is connected to the system ground potential or a preset low potential point to generate a level transition on the GPIO pin.

5. A multi-mode highly adaptive terminal peripheral delay measurement method, comprising the steps of the multi-mode highly adaptive terminal peripheral delay measurement system as described in any one of claims 1-4, characterized in that, The method includes: Step 100: Use the built-in mode selection and configuration module of the host computer to select the test mode and configure the test parameters, and send the test mode command and the configured test parameters to the hardware measurement terminal. Step 110: According to the selected test mode, the central control module determines and records the start time based on the event judgment of different measurement principles, and starts the corresponding signal acquisition. Step 120: Based on the selected test mode, use the central control module to determine and record the endpoint time; Step 130: The host computer and the central control module engage in bidirectional communication to obtain the original delay measurement value corresponding to the test mode. Step 140: Using the RTT delay compensation module built into the host computer, the one-way communication delay is estimated by the round-trip time of the command, and the original delay measurement value involving command interaction is compensated to obtain the delay data to be analyzed. Step 150: Obtain the latency data to be analyzed under at least two test modes with different measurement principles, and use the full-link latency decomposition and analysis module built into the host computer to decompose and calculate, and output at least two of the measurement results of peripheral hardware latency, display latency, system processing latency and application additional latency.

6. The multi-mode strongly adaptive terminal peripheral delay measurement method of claim 5, wherein, The test modes include at least: display latency test, end-to-end latency test, peripheral latency test, response speed test, and grayscale latency test; the peripheral latency test includes actual peripheral path measurement and ideal peripheral path measurement. Step 110 includes: For display latency testing or grayscale latency testing, the central control module waits for and receives instructions sent by the host computer, and records the time when the instruction arrives as the starting time. For end-to-end latency testing, peripheral latency testing, real peripheral path measurement, or response speed testing, the physical trigger module is enabled to generate a trigger signal when the peripheral under test is operated, which is recorded as the starting moment. For ideal peripheral path measurement in peripheral latency testing, a simulated trigger signal is directly generated internally by the central control module and recorded as the starting moment.

7. The multi-mode strongly adaptive terminal peripheral delay measurement method of claim 6, wherein, Step 120 includes: For display latency testing or end-to-end latency testing, the central control module uses the built-in dynamic window calibration logic module to execute a dynamic window calibration algorithm based on the brightness signal collected by the photoelectric feedback module to adaptively determine the screen brightness jump and record it as the endpoint time. The dynamic window calibration algorithm includes: continuously sampling the brightness signal during the waiting trigger phase, updating and recording the minimum and maximum brightness values ​​within the sampling window in real time to obtain a dynamically changing extreme brightness window; generating an adaptive threshold range based on the extreme brightness window and a safety margin; and determining a screen brightness jump when the real-time brightness signal collected after the starting time exceeds the range of the adaptive threshold range, and recording it as the ending time. For the actual peripheral path measurement or ideal peripheral path measurement of peripheral latency testing, the central control module waits for the host computer to send a stop command through the bidirectional communication link, and records the time of receiving the stop command as the end time. For the reaction speed test, the central control module detects the recovery of the trigger signal of the physical trigger module and records the signal recovery time as the endpoint time; For grayscale delay testing, the central control module determines the completion of screen brightness gradation based on the brightness signal collected by the photoelectric feedback module, and records the determination time of the completion of screen brightness gradation as the endpoint time.

8. The multi-mode strongly adaptive terminal peripheral delay measurement method of claim 7, wherein, When it is necessary to calculate the peripheral hardware latency, the central control module uses the built-in reference loop measurement module and the kernel latency measurement mechanism based on the self-simulated loopback to calculate the system input stack latency of the main control terminal device from responding to the hardware interrupt to the system kernel capturing the input message. The self-simulated loopback kernel latency measurement mechanism includes: The central control module is set to simulate peripheral working mode. It generates a trigger signal for the simulated button by pulling down its own GPIO pin or triggering the internal logic. The timing starts from the starting point, and the HID input message is sent to the host computer through the USB HID interface. When the host computer captures the HID input message through the system hook based on signal loopback logic, it immediately sends an acknowledgment command to the central control module through the virtual serial port. Upon receiving the confirmation command, the central control module stops timing, obtains the total hardware interrupt loopback duration, and uploads it to the host computer. The host computer compensates for the total time of the hardware interrupt loopback based on the one-way communication delay measured by the built-in RTT delay compensation module, removes the influence of one-way communication delay and average waiting time of USB polling interval, and obtains the system input stack delay from the main control terminal device responding to the hardware interrupt to the system kernel capturing the HID input message.

9. The multi-mode strongly adaptive terminal peripheral delay measurement method of claim 8, wherein, The breakdown calculation of peripheral hardware latency, display latency, system processing latency, and additional application latency includes: The peripheral hardware latency is represented by the latency data to be analyzed, measured from the actual peripheral path in the peripheral latency test, the system input stack latency, and the average waiting time of the USB polling interval. The display latency is directly represented by the latency data to be analyzed in the display latency test; The system processes latency by breaking down and representing the latency data to be analyzed using the latency data measured under ideal load in the end-to-end latency test, the latency data to be analyzed using the actual peripheral path measured in the peripheral latency test, and the latency data to be analyzed using the display latency test. The additional latency of the application is represented by decomposing the latency data to be analyzed, which was measured under actual application conditions in the end-to-end latency test and the latency data to be analyzed, which was measured under ideal load conditions in the end-to-end latency test.

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