Bus driver, chip and electronic device

Abstract

A bus driver, a chip and an electronic device belong to the technical field of electronic circuits, a three-level input signal is accessed through a slope control circuit, and slope control is performed on the three-level input signal to output a first three-level signal; the driving circuit amplifies a first three-level signal based on an AB-type power amplifier and a B-type power amplifier, and amplifies a three-level input signal based on a G-type power amplifier so as to output a bus output signal; therefore, the influence of the temperature on the output slope can be reduced without configuring a reference band-gap current source module, and the stability of the output signal parameter of the bus driver is improved; meanwhile, the output signal swing of the bus driver is increased, and the driving capability of the bus driver is enhanced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic circuits, and particularly relates to a bus driver, a chip and an electronic device. BACKGROUND

[0002] In a complex electronic system, signals need to be transmitted between different devices or chips through a cable, but long-distance or heavy-load signal transmission can cause signal delay, attenuation or distortion. The bus driver ensures the integrity and reliability of the signal under the premise of meeting the protocol standard in different temperature environment applications by amplifying, shaping and increasing the signal. The bus driver is increasingly tending to be low-power and integrated. In mobile devices and embedded systems, the bus driver needs to optimize power consumption to prolong the device battery life. In the field of automotive electronics and industrial control, the drive circuit needs to have anti-interference ability, integrate the drive and protection functions, and improve the reliability and design flexibility of the system. Therefore, the parameter temperature stability, driving ability and power consumption of the drive circuit are increasingly important.

[0003] However, the related bus driver only amplifies the input signal based on the AB class power amplifier and the B class power amplifier, resulting in a small output signal swing and weak driving ability. In addition, the output signal of the bus driver needs to meet the corresponding protocol electrical characteristics and specifications, such as rise and fall time and transmission delay. The bus driver not only needs a drive circuit module, but also needs a slope control module to provide an input signal for the drive circuit, so as to control the slope of the output signal of the bus driver and determine the rise and fall time and other parameters. In order to save chip area and reduce circuit complexity, some bus drivers do not contain a reference bandgap module, and the device characteristics are affected by temperature and cannot provide a stable bias current. Therefore, the output slope of the slope controller is easily changed with temperature. If the slope is fast, the output overshoot is large. If the slope is slow, the delay is slow, so the output signal slope of the bus driver is greatly affected by temperature, and the parameter consistency is unstable.

[0004] Therefore, the related bus driver has poor parameter temperature stability, weak driving ability and large power consumption. SUMMARY

[0005] The application aims to provide a bus driver, a chip and an electronic device, and aims to solve the problems of poor parameter temperature stability, weak driving ability and large power consumption of the related bus driver.

[0006] The application embodiment provides a bus driver, which comprises: a slope control circuit, configured to access a three-level input signal and perform slope control on the three-level input signal to output a first three-level signal; The driving circuit is connected with the slope control circuit, and is configured to amplify the first three-level signal based on an AB class power amplifier and a B class power amplifier, and amplify the three-level input signal based on a G class power amplifier, so as to output a bus output signal.

[0007] The embodiment of the present application also provides a chip comprising the bus driver.

[0008] The embodiment of the present application also provides an electronic device comprising the bus driver.

[0009] Compared with the prior art, the embodiment of the present application has the beneficial effects that: since the slope control circuit is connected with the three-level input signal and performs slope control on the three-level input signal to output the first three-level signal, the reference band-gap current source module is not required to be configured, the output slope is reduced to be affected by temperature, and the stability of the output signal parameter of the bus driver is improved; meanwhile, the driving circuit is configured to amplify the first three-level signal based on the AB class power amplifier and the B class power amplifier, and amplify the three-level input signal based on the G class power amplifier to output the bus output signal, so that the output signal swing of the bus driver is increased, and the driving capability of the bus driver is enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0011] Figure 1 A structural schematic diagram of the bus driver provided by an embodiment of the present application is shown in FIG. 1. Figure 2 A structural schematic diagram of the slope control circuit in the bus driver provided by an embodiment of the present application is shown in FIG. 2. Figure 3 A structural schematic diagram of the driving circuit in the bus driver provided by an embodiment of the present application is shown in FIG. 3. Figure 4 Another structural schematic diagram of the bus driver provided by an embodiment of the present application is shown in FIG. 4. Figure 5 Another structural schematic diagram of the bus driver provided by an embodiment of the present application is shown in FIG. 5. Figure 6 A partial example circuit schematic diagram of the slope control unit in the bus driver provided by an embodiment of the present application is shown in FIG. 6. Figure 7A partial example circuit schematic diagram of a driving unit in a bus driver provided by an embodiment of the present application is provided; Figure 8 A partial example circuit schematic diagram of a first operational amplifier in a bus driver provided by an embodiment of the present application is provided; Figure 9 A partial example circuit schematic diagram of a second operational amplifier in a bus driver provided by an embodiment of the present application is provided; Figure 10 A partial example circuit schematic diagram of a first inverter in a bus driver provided by an embodiment of the present application is provided; Figure 11 A partial example circuit schematic diagram of a second inverter in a bus driver provided by an embodiment of the present application is provided; Figure 12 A schematic diagram of a push-pull structure of a class AB power amplifier with offset; Figure 13 A main signal waveform diagram of a bus driver provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0012] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0013] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0014] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0015] In addition, the terms "first", "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0016] Figure 1 The structure diagram of the bus driver provided by the preferred embodiment of the present application is shown, only the parts related to the embodiment are shown for the convenience of description, and the details are described as follows: The bus driver includes a slope control circuit 10 and a driving circuit 20.

[0017] The slope control circuit 10 is configured to access a three-level input signal and perform slope control on the three-level input signal to output a first three-level signal. The driving circuit 20 is connected with the slope control circuit 10 and configured to amplify the first three-level signal based on an AB class power amplifier and a B class power amplifier and amplify the three-level input signal based on a G class power amplifier to output a bus output signal.

[0018] The three-level input signal is accessed by the slope control circuit 10 and the slope control is performed on the three-level input signal to output the first three-level signal, so that the driving circuit 20 amplifies the first three-level signal based on the AB class power amplifier and the B class power amplifier and amplifies the three-level input signal based on the G class power amplifier to output the bus output signal; therefore, without configuring a reference bandgap current source module, the influence of temperature on the output slope can be reduced, the stability of the output signal parameters of the bus driver is improved; at the same time, the driving circuit 20 amplifies the three-level input signal based on the G class power amplifier, so that the output signal swing of the bus driver is increased and the driving capability of the bus driver is enhanced.

[0019] As shown in Figure 2 The three-level input signal includes a positive three-level input signal and a negative three-level input signal, and the first three-level signal includes a first positive three-level signal and a first negative three-level signal; the slope control circuit 10 includes a positive slope control module 11 and a negative slope control module 12.

[0020] The positive slope control module 11 is configured to access the positive three-level input signal and perform slope control on the positive three-level input signal to output the first positive three-level signal. The negative slope control module 12 is configured to access the negative three-level input signal and perform slope control on the negative three-level input signal to output the first negative three-level signal.

[0021] Through the above technical features, the slope control is performed on the differential three-level input signal, and the application scenarios of the bus driver are expanded.

[0022] As shown in Figure 3 The bus output signal includes a positive output signal and a negative output signal; and the driving circuit 20 includes a positive driving module 21 and a negative driving module 22.

[0023] The positive electrode driving module 21 is connected with the positive electrode slope control module 11, and is configured to amplify the first positive electrode three-level signal based on the AB class power amplifier and the B class power amplifier, and amplify the positive electrode three-level input signal based on the G class power amplifier, so as to output the positive electrode output signal. The negative electrode driving module 22 is connected with the negative electrode slope control module 12, and is configured to amplify the first negative electrode three-level signal based on the AB class power amplifier and the B class power amplifier, and amplify the negative electrode three-level input signal based on the G class power amplifier, so as to output the negative electrode output signal.

[0024] Through the above technical features, the differential three-level input signal and the differential first three-level signal are amplified to output the differential bus output signal, and the application scenarios of the bus driver are expanded.

[0025] As shown in Figure 4 The bus driver further includes a protection circuit 40.

[0026] The protection circuit 40 is connected with the driving circuit 20, and is configured to perform impedance matching and surge protection on the bus output signal, so as to output the bus output signal after impedance matching and surge protection.

[0027] In actual application, the bus driver will encounter bus surges, which mainly come from induced lightning high voltage, transient voltage or current generated by power switch switching, etc. In order to ensure safety, the influence of surges on the chip is suppressed by using external components or circuits such as discrete TVS diodes and surge protectors. However, using discrete devices to realize the surge protection function increases the complexity of system design, and the scattered external components are more easily affected by environmental factors. At the same time, the external protection circuit 30 usually occupies more space due to the large number of components, which is not conducive to the miniaturization of equipment. Therefore, the protection circuit 40 can be integrated on the chip including the bus driver, thereby improving the reliability of the bus driver and the chip.

[0028] Through the above technical solution, the reliability and safety of the bus driver are improved.

[0029] As shown in Figure 5 The bus driver further includes a protection circuit 30.

[0030] The protection circuit 30 is connected with the slope control circuit 10 and the driving circuit 20, and is configured to perform anti-reverse connection protection on the positive electrode supply voltage and the negative electrode supply voltage, so that the slope control circuit 10 and the driving circuit 20 are powered by the anti-reverse connection positive electrode supply voltage and the anti-reverse connection negative electrode supply voltage.

[0031] Different application scenarios may appear various pulse types on the power line, such as sudden closing of high-power load, starting, abnormal connection of wire harness and reverse connection of power polarity when jumper, which will cause overshoot, drop, negative voltage pulse and long time reverse connection of power voltage, therefore, the bus driver needs to add reverse connection protection circuit 30, such as diode and field effect tube, to prevent damage caused by abnormal power voltage.

[0032] By the above technical solution, the reliability and safety of the bus driver are improved.

[0033] Figure 6 A partial example circuit structure of the slope control unit in the bus driver provided by the embodiment of the application is shown, and the structure only shows the part related to the embodiment of the application for the convenience of description, and the details are as follows: The positive slope control module 11 and the negative slope control module 12 both include a slope control unit, and the slope control unit includes a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, a first capacitor C1, a first resistor R1 and a second resistor R2. The source of the first PMOS P1, the source of the second PMOS P2, the source of the third PMOS P3, the source of the fourth PMOS P4 and the source of the fifth PMOS P5 are connected to the positive power supply VCC_C; the source of the first NMOS N1, the source of the fourth NMOS N4, the source of the fifth NMOS N5, the source of the sixth NMOS N6 and the source of the seventh NMOS N7 are connected to the negative power supply VEE_C; the gate of the first PMOS P1 is connected to the drain of the first PMOS P1, the first end of the first resistor R1 and the gate of the fifth PMOS P5, the second end of the first resistor R1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the drain of the first NMOS N1, the gate of the first NMOS N1 and the gate of the fourth NMOS N4; the gate of the second PMOS P2 is connected to the drain of the second PMOS P2 and the drain of the second NMOS N2, the source of the second NMOS N2 is connected to the source of the third NMOS N3 and the drain of the fourth NMOS N4; the gate of the third PMOS P3 is connected to the gate of the fourth PMOS P4, the drain of the third PMOS P3 and the drain of the third NMOS N3; the drain of the fifth PMOS P5 is connected to the source of the sixth PMOS P6 and the source of the seventh PMOS P7, the drain of the sixth PMOS P6 is connected to the drain of the fifth NMOS N5 and the gate of the fifth NMOS N5, the drain of the seventh PMOS P7 is connected to the drain of the sixth NMOS N6, the gate of the sixth NMOS N6 and the gate of the seventh NMOS N7; the gate of the third NMOS N3 and the gate of the seventh PMOS P7 are connected and together form the input end of the slope control unit to input the positive three-level input signal or the negative three-level input signal; the gate of the second NMOS N2, the gate of the sixth NMOS N6, the drain of the fourth PMOS P4, the drain of the seventh NMOS N7 and the first end of the first capacitor C1 are connected and together form the output end of the slope control unit, which is connected to the driving circuit 20 to output the first positive three-level signal or the first negative three-level signal; the second end of the first capacitor C1 is connected to the power ground.

[0034] In an embodiment, the first resistor R1 and the second resistor R2 are positive temperature coefficient resistor and negative temperature coefficient resistor respectively.

[0035] The working principle is further explained as follows: Figure 6 ​It should be noted that the slope control module includes a rail-to-rail differential amplifier, a current bias circuit (including a first PMOS tube P1, a first NMOS tube N1, a first resistor R1 and a second resistor R2) and a first capacitor C1, the rail-to-rail differential amplifier is connected in the form of a unit buffer, the input signal (input three-level signal) is a three-phase level signal, and the direction of the jump determines the direction of the output current. The rise and fall time of the output signal (first three-level signal) depends on the size of the current. Since the input three-level signal jumps quickly and is approximately a step signal, the charging and discharging period of the first capacitor C1 is in a large signal state, and the rise and fall time depends on the slew rate SR of the rail-to-rail differential amplifier and the first capacitor value C1. The pull-up current IPU is equal to the product of the current IB, the size ratio of the fourth NMOS tube N4 and the first NMOS tube N1, and the size ratio of the fourth PMOS tube P4 and the third PMOS tube P3. The pull-down current IPD is equal to the product of the current IB, the size ratio of the fifth PMOS tube P5 and the first PMOS tube P1, and the size ratio of the seventh NMOS tube N7 and the sixth NMOS tube N6. The voltage relationship of the current IB path can be calculated as follows:

[0036] Where IB is the current flowing through the current bias circuit, VCC_C is the voltage of the positive power supply, VEE_C is the voltage of the negative power supply, V TH_P1 is the threshold voltage of the first PMOS tube P1, V TH_N1 is the threshold voltage of the first NMOS tube N1. It can be seen that IB is related to R1, R2, the voltage of the power supply and the threshold voltage.

[0037] The relationship between IPU and IPD and IB is as follows:

[0038]

[0039] Where MOS includes PMOS and NMOS, W is the gate width of MOS, and L is the gate length of MOS. The rise time trx and the fall time tfx refer to the rise or fall time between 10% and 90% of the output signal amplitude VOUT1 (i.e. (|VCC_C|+|VEE_C|) / 2). According to the first capacitor charging and discharging formula, the following can be obtained:

[0040]

[0041] According to the derived formula, the device parameters affected by temperature are R, the threshold voltage of the MOS tube and C1, wherein C1 is less affected by temperature, so the temperature relationship of (R1+R2) and the threshold voltage, i.e. the relationship of IB with temperature change, is directly analyzed, and IB is derived with respect to T as follows:

[0042] wherein,

[0043] The temperature expressions of various device parameters are as follows:

[0044]

[0045] Substituting the above formula can obtain:

[0046] wherein, TC （R1+R2） is the temperature coefficient of (R1+R2), C VTH is the threshold voltage temperature coefficient of the MOS tube, C VTHP is the threshold voltage temperature coefficient of the PMOS tube, and C VTHN is the threshold voltage temperature coefficient of the NMOS tube.

[0047] It is worth emphasizing that in the related art, the first resistance R1 and the second resistance R2 in the circuit structure are both polysilicon resistances, and the temperature coefficients are negative numbers, and the threshold voltage temperature coefficients of the MOS tubes are also negative numbers, so IB is a positive temperature coefficient, when VCC_C=-VEE_C=5V, the parameters are substituted into the above formula, and the temperature coefficient of IB is 5.78e-8. In theory, the temperature coefficient of IB is approximately 0, which can reduce the influence of temperature on the rising and falling time.

[0048] Therefore, the defect of the related art is that the threshold voltage temperature coefficient of the MOS tube is not adjustable, and to solve the above defect, the embodiment of the present application adjusts the temperature coefficient of (R1+R2) to achieve the purpose of changing the temperature coefficient of IB, and adjusts ΔIB / ΔT from a positive number to about 0, and in the specific implementation, TC （R1+R2） is adjusted from a negative number to a positive number, a positive temperature coefficient resistance R2 and a negative temperature coefficient resistance R1 are used, and the ratio of R1 and R2 is adjusted, so that the rising time and the falling time are designed to be within the index range, the influence of temperature on the rising time and the falling time of the output signal is reduced, and the stability of the driving output signal parameters is ensured without increasing additional circuits.

[0049] Figure 7 A partial example circuit structure of a driving unit in a bus driver provided by an embodiment of the present application is shown,Figure 8 This invention illustrates a partial example circuit structure of a first operational amplifier in a bus driver according to an embodiment of the present invention. Figure 9 This invention illustrates a partial example circuit structure of a second operational amplifier in a bus driver according to an embodiment of the present invention. Figure 10 This invention illustrates a partial example circuit structure of a first inverter in a bus driver according to an embodiment of the present invention. Figure 11 The present invention illustrates a partial example circuit structure of a second inverter in a bus driver according to an embodiment of the present invention. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below: like Figure 7 As shown, both the positive drive module 21 and the negative drive module 22 include a drive unit. The drive unit includes a first operational amplifier U1, a second operational amplifier U2, a first inverter U3, a second inverter U4, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The positive power supply end of the first operational amplifier U1, the positive power supply end of the second operational amplifier U2, the source of the eighth PMOS P8, the first end of the fifth resistor R5, the source of the ninth PMOS P9 and the drain of the eleventh NMOS N11 are connected to the positive power supply VCC_C; the negative power supply end of the first operational amplifier U1, the negative power supply end of the second operational amplifier U2, the source of the eighth NMOS N8, the second end of the sixth resistor R6, the source of the ninth NMOS N9 and the drain of the eleventh PMOS P11 are connected to the negative power supply VEE_C; the reverse input end of the first operational amplifier U1 and the reverse input end of the second operational amplifier U2 are connected and jointly constitute the first input end of the driving unit, and are connected with the slope control circuit 10 to input the first positive three-level signal or the first negative three-level signal; the output end of the first operational amplifier U1 is connected with the gate of the eighth PMOS P8, the gate of the tenth PMOS P10 and the first end of the third capacitor C3; the output end of the second operational amplifier U2 is connected with the gate of the eighth NMOS N8, the gate of the tenth NMOS N10 and the second end of the fourth capacitor C4; the drain of the eighth PMOS P8 is connected with the gate of the eleventh NMOS N11 and the first end of the third resistor R3, the second end of the third resistor R3 and the first end of the fourth resistor R4 and the first end of the second capacitor C2 are connected, the second end of the fourth resistor R4 is connected with the drain of the eighth NMOS N8 and the gate of the eleventh PMOS P11; the second end of the fifth resistor R5 is connected with the drain of the ninth PMOS P9 and the source of the tenth PMOS P10, the source of the tenth NMOS N10 is connected with the drain of the ninth NMOS N9 and the first end of the sixth resistor R6; the positive input end of the first operational amplifier U1 and the positive input end of the second operational amplifier U2, the drain of the tenth PMOS P10, the drain of the tenth NMOS N10, the source of the eleventh NMOS N11, the source of the eleventh PMOS P11, the second end of the second capacitor C2, the second end of the third capacitor C3 and the first end of the fourth capacitor C4 are connected and jointly constitute the output end of the driving unit to output the positive output signal or the negative output signal; the input end of the first inverter U3 and the input end of the second inverter U4 are connected and jointly constitute the second input end of the driving unit, and are connected with the slope control circuit 10 to input the positive three-level input signal or the negative three-level input signal.

[0050] As Figure 8As shown, the first operational amplifier U1 includes a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10; The first terminal of the seventh resistor R7, the source of the twelfth PMOS transistor P12, the source of the thirteenth PMOS transistor P13, the first terminal of the ninth resistor R9, and the first terminal of the tenth resistor R10 are all connected to the positive power supply VCC_C; the second terminal of the eighth resistor R8, the source of the twelfth NMOS transistor N12, and the source of the thirteenth NMOS transistor N13 are all connected to the negative power supply VEE_C; the gate of the first transistor Q1 forms the inverting input terminal of the first operational amplifier U1; the gate of the second transistor Q2 forms the non-inverting input terminal of the first operational amplifier U1; the second terminal of the seventh resistor R7 is connected to the emitter of the first transistor Q1 and the base of the third transistor Q3; the collector of the first transistor Q1 and the first terminal of the eighth resistor R8 and the first terminal of the tenth resistor Q3 are connected to the positive power supply VCC_C. The collector of transistor 2 is connected; the gate and drain of the twelfth PMOS transistor P12 and the collector of the third transistor Q3 are connected and together form the output terminal of the first operational amplifier U1; the emitter of the third transistor Q3 is connected to the emitter of the fourth transistor Q4 and the drain of the twelfth NMOS transistor N12; the gate of the thirteenth PMOS transistor P13 is connected to the drain of the thirteenth PMOS transistor P13 and the collector of the fourth transistor Q4; the base of the fourth transistor Q4 is connected to the second segment of the ninth resistor R9 and the emitter of the second transistor Q2; the second end of the tenth resistor R10 is connected to the drain of the thirteenth NMOS transistor N13, the gate of the twelfth NMOS transistor N12 and the gate of the thirteenth NMOS transistor N13.

[0051] like Figure 9 As shown, the second operational amplifier U2 includes the fourteenth PMOS transistor P14, the fifteenth PMOS transistor P15, the fourteenth NMOS transistor N14, the fifteenth NMOS transistor N15, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14; The first terminal of the eleventh resistor R11, the source of the fourteenth PMOS transistor P14, and the source of the fifteenth PMOS transistor P15 are all connected to the positive power supply VCC_C; the sources of the fourteenth NMOS transistor N14 and the fifteenth NMOS transistor N15, the second terminal of the twelfth resistor R12, the second terminal of the thirteenth resistor R13, and the second terminal of the fourteenth resistor R14 are all connected to the negative power supply VEE_C; the second terminal of the eleventh resistor R11 is connected to the collector of the fifth transistor Q5 and the collector of the sixth transistor Q6; the base of the fifth transistor Q5 forms the inverting input terminal of the second operational amplifier U2; the base of the sixth transistor Q6 forms the positive input terminal of the second operational amplifier U2. Phase input terminals; the emitter of the fifth transistor Q5 is connected to the base of the seventh transistor Q7 and the first end of the twelfth resistor R12; the gate of the fourteenth PMOS transistor P14 is connected to the gate of the fifteenth PMOS transistor P15, the drain of the fifteenth PMOS transistor P15, and the first end of the fourteenth resistor R14; the drain of the fourteenth PMOS transistor P14 is connected to the emitter of the seventh transistor Q7 and the emitter of the eighth transistor Q8; the collector of the eighth transistor Q8 is connected to the drain of the fifteenth NMOS transistor N15 and the gate of the fifteenth NMOS transistor N15; the emitter of the sixth transistor Q6 is connected to the base of the eighth transistor Q8 and the first end of the thirteenth resistor R13.

[0052] like Figure 10 The first inverter U3 shown includes a sixteenth PMOS transistor P16, a sixteenth NMOS transistor N16, a fifth capacitor C5, and a fifteenth resistor R15. The gates of the sixteenth PMOS transistor P16 and the sixteenth NMOS transistor N16 are connected and together form the input terminal of the first inverter U3. The source of the sixteenth PMOS transistor P16 is connected to the positive power supply VCC_C. The drain of the sixteenth PMOS transistor P16 is connected to the drain of the sixteenth NMOS transistor N16 and the first terminal of the fifteenth resistor R15. The second terminal of the fifteenth resistor R15 and the first terminal of the fifth capacitor C5 are connected and together form the output terminal of the first inverter U3. The second terminal of the fifth capacitor C5 is connected to the power supply terminal.

[0053] like Figure 11 As shown, the second inverter U4 includes the seventeenth PMOS transistor P17, the seventeenth NMOS transistor N17, the sixth capacitor C6, and the sixteenth resistor R16; The gate of the seventeenth PMOS P17 and the gate of the seventeenth NMOS N17 are connected and jointly constitute the input end of the second inverter U4; the source of the seventeenth PMOS P17 is connected with the positive power supply VCC_C, the drain of the seventeenth PMOS P17 is connected with the drain of the seventeenth NMOS N17 and the first end of the sixteenth resistor R16, the second end of the sixteenth resistor R16 and the first end of the sixth capacitor C6 are connected and jointly constitute the output end of the second inverter U4; the second end of the sixth capacitor C6 is connected with the power supply end.

[0054] The working principle is further described below in combination with the drawings: Figures 7 to 11 The related bus driver is designed based on an AB class power amplifier and a B class power amplifier, so that the bus driver has the disadvantage of large static power consumption, and the static power consumption is easily affected by device mismatch. During normal operation, the static current of the output tube is provided by the AB class power amplifier auxiliary drive tube. Since the main drive tube and the auxiliary drive tube both belong to common source tubes, device mismatch easily causes the main drive tube to deviate from the expected design operating point at the output intermediate level (i.e. near the 0V level), thereby generating static current and increasing the static power consumption of the overall drive circuit 20. When the chip is in standby state, it is not conducive to prolong the endurance time of the equipment.

[0055] In the present application, the first input signal (the first positive three-level signal or the first negative three-level signal) of the drive unit is generated by the slope control unit and is connected to the reverse input end of the two operational amplifiers. The output end VP1 of the OP_P sub-module is connected to the gate of P28 and P10, and the output end VN1 of the OP_N sub-module is connected to the gate of N8 and N10. The drive unit has two types of power output tubes, which are G class power amplifier push-pull tubes (P10 and N10) based on AB class power amplifiers and B class power amplifier push-pull tubes (P11 and N11). The source stage of P10 is connected in series between the positive power supply VCC_C and the drain of P10, and the source stage of N10 is connected in series between the drain of N10 and the positive power supply VCC_C. ​The source level of N10 and the negative power supply VEE_C are connected in series with R6 and the parallel structure of switch tube N9. The gate signals of P9 and N9 are obtained by inverting and RC filtering the positive three-level input signal or the negative three-level input signal. The high level and low level of the inverter corresponding to the gate signal of P9 are VCC_C and GND respectively, and the high level and low level of the inverter corresponding to the gate signal of N9 are GND and VEE_C respectively. The gate of N11 is connected to the drain of P8, and R2_1 and C2 are connected in parallel between the gate and the source level of N11. The gate of P11 is connected to the drain of N8, and R4 and C2 are connected in parallel between the gate and the source level of P11. Capacitor C3 is connected across the gate and the source level of P10, and capacitor C4 is connected across the gate and the source level of N10. The output end of the driving unit is connected to the non-inverting input end of the two operational amplifiers to form a buffer function in the form of negative feedback, so that the positive output signal completely follows the first positive three-level signal and the negative output signal completely follows the first negative three-level signal.

[0056] The driving unit adopts the topology structure of superposition of AB class power amplifier, B class power amplifier and G class power amplifier. The structure separates large signals and small signals, in which the B class power amplifier is the main output stage and is responsible for large signal establishment, and the AB class power amplifier is the auxiliary output stage, is responsible for small signal establishment, provides static current and improves output swing. The large signal establishment is mainly responsible by the output stage of the B class power amplifier, and the auxiliary output is by the output stage of the AB class power amplifier. Since the AB class power amplifier is a common-source push-pull output, its output amplitude is greater than that of the output stage of the B class power amplifier. When the output voltage gradually rises, the overdrive voltage output by the B class power amplifier decreases, the establishment of the large signal is mainly responsible by the output stage of the AB class power amplifier, and the driving of the B class power amplifier gradually decreases. When the output voltage finally exceeds the maximum output voltage of the B class power amplifier, the B class power amplifier enters the cutoff region. The output stage of the B class power amplifier has no static power consumption because one side is always cut off, while the output stage of the AB class power amplifier has static current. When the size is large or there is device mismatch, it will cause the overall power consumption to be large or to change greatly, so the low-power design needs to be made for the AB class power amplifier.

[0057] It should be noted that, as shown in Figure 12 In the topology structure of superposition of the AB class power amplifier and the B class power amplifier, the AB class power amplifier adopts a common-source push-pull output, and two amplifiers with a gain of A drive the push-pull tube, and the output is fed back to the amplifier.

[0058] Taking the NMOS tube as an example (the PMOS tube is the same), the static current generated at this time is

[0059] When the input signal is 0, the negative feedback makes Vout≈0, and the static current is Similarly, the static current of the PMOS transistor is .

[0060] As can be seen from the above formula, the static current of the NMOS transistor is affected by the gain A of the operational amplifier and the input offset voltage Vos. Since Vos is determined by the process and its direction is random, it cannot be controlled. When the gain A is larger, the static current is more affected by the process. In the embodiment of the application, a low-gain first operational amplifier U1 (i.e., A1 of Figure 12 ) and a second operational amplifier U2 (i.e., A2 of Figure 12 ) are used, and an input offset is artificially introduced to reduce the static current.

[0061] The structure of the operational amplifier is shown in Figure 8 and Figure 9 . Taking the first operational amplifier U1 as an example, the main body of the operational amplifier (R10, N12, N13, Q3, Q4, P12, and P13) adopts a full-symmetrical structure, and the input pair uses a BJT to reduce mismatch. The remaining devices consist of a level shifting circuit (R7, R8, Q1, Q2, and R9), which actively generates an offset voltage by artificially designing an asymmetric structure, so that V OS is offset in the expected direction. For example, the size ratio of Q1:Q2 is designed to be 10:1, and the resistance ratio of R7:R9 is designed to be 3:1.

[0062]

[0063]

[0064] Since there is negative feedback, when , R7:R9=3:1 is substituted into the above formula to obtain

[0065] Since

[0066]

[0067] , the input offset voltage of the main body of the operational amplifier is , and the static current is , which can stably reduce the static current. The second operational amplifier U2 has the same number of BJTs and the same resistance ratio as the first operational amplifier U1, i.e., Q5:Q6=10:1 and R12:R13=3:1.

[0068] Since the AB class power amplifier needs a low-gain operational amplifier to suppress the power consumption increase due to the imbalance of the band, and the B class power amplifier needs a high-gain operational amplifier to suppress the crossover distortion, the common source amplifiers P8 and N8 are cascaded at the output of the first operational amplifier U1 and the output of the second operational amplifier U2 to drive the B class power amplifier output push-pull tubes N11 and P11.

[0069] The embodiment of the application reduces the power consumption based on the AB class power amplifier by simultaneously using the AB class power amplifier principle and the G class power amplifier principle in addition to reducing the static power consumption by artificially introducing imbalance. Figure 13 As shown in the figure, the positive power voltage driving the push-pull tube is switched between VCC and VCC_L, and the negative power voltage driving the push-pull tube is switched between VEE_L and VEE by switching control. When the output is 0V, the switching tube is closed, the positive and negative power voltages of the output driving tube of the AB class power amplifier are VCC_L and VEE_L respectively, and the static current is reduced by reducing the overdrive voltage V OV When VCC_L and VEE_L cannot meet the output requirement, the switching tube is opened, and the positive and negative power of the driving tube are switched to VCC and VEE respectively, thereby improving the output swing and driving capability.

[0070] In the embodiment of the application, VCC and VEE can be supplied by an external power supply under the protection of the protection circuit 30, and VCC_L and VEE_L are generated by the voltage drop of the static current of the AB class power amplifier through resistors R5 and R6 respectively. Figure 13 The control signals SWP and SWN of the switching tube are slow ramp signals, which are three-level input signals first converted in level by different high and low level inverters and then generated by resistor-capacitor filtering. It is worth emphasizing that the positive and negative power levels of the push-pull tube of the AB class power amplifier should be switched to the highest level or the lowest level during the second half of the signal conversion period to achieve the purpose of rail-to-rail output and low static power consumption of the driving unit. In addition, Figure 6 The functions of R3, R4, C2, C3 and C4 in the figure are to perform Miller compensation and zero point compensation on the driving loop to ensure the stability of the loop.

[0071] The embodiment of the application uses the above two superposition methods to form the topology circuit of the driving unit in the application, which takes into account the characteristics and requirements of rail-to-rail output amplitude and static power consumption.

[0072] The embodiment of the application also provides a chip, which comprises the bus driver.

[0073] The embodiment of the application also provides an electronic device, which comprises the bus driver.

[0074] It should be understood that the size of the serial number of each step in the above-mentioned embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0075] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A bus driver, characterized in that, include: A slope control circuit is used to receive a three-level input signal and to control the slope of the three-level input signal to output a first three-level signal; The driving circuit, connected to the slope control circuit, is used to amplify the first three-level signal based on the Class AB power amplifier and the Class B power amplifier, and to amplify the three-level input signal based on the Class G power amplifier, so as to output a bus output signal.

2. The bus driver as described in claim 1, characterized in that, The three-level input signal includes a positive three-level input signal and a negative three-level input signal, and the first three-level signal includes a first positive three-level signal and a first negative three-level signal; The slope control circuit includes: A positive pole slope control module is used to receive the positive pole three-level input signal and control the slope of the positive pole three-level input signal to output the first positive pole three-level signal; The negative pole slope control module is used to receive the negative pole three-level input signal and control the slope of the negative pole three-level input signal to output the first negative pole three-level signal.

3. The bus driver as described in claim 2, characterized in that, Both the positive electrode slope control module and the negative electrode slope control module include a slope control unit. The slope control unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first capacitor, a first resistor, and a second resistor. The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are all connected to a positive power supply. The source of the first NMOS transistor, the source of the fourth NMOS transistor, the source of the fifth NMOS transistor, the source of the sixth NMOS transistor, and the source of the seventh NMOS transistor are all connected to the negative power supply. The gate of the first PMOS transistor is connected to the drain of the first PMOS transistor, the first end of the first resistor and the gate of the fifth PMOS transistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor and the gate of the fourth NMOS transistor. The gate of the second PMOS transistor is connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to the source of the third NMOS transistor and the drain of the fourth NMOS transistor. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, the drain of the third PMOS transistor, and the drain of the third NMOS transistor. The drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor and the source of the seventh PMOS transistor. The drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the fifth NMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor, and the gate of the seventh NMOS transistor. The gate of the third NMOS transistor and the gate of the seventh PMOS transistor are connected and together form the input terminal of the slope control unit, so as to receive the positive three-level input signal or the negative three-level input signal; The gate of the second NMOS transistor, the gate of the sixth NMOS transistor, the drain of the fourth PMOS transistor, the drain of the seventh NMOS transistor, and the first terminal of the first capacitor are connected and together form the output terminal of the slope control unit, which is connected to the driving circuit to output the first positive three-level signal or the first negative three-level signal. The second terminal of the first capacitor is connected to the power supply ground.

4. The bus driver as described in claim 2, characterized in that, The bus output signal includes a positive output signal and a negative output signal; The driving circuit includes: A positive drive module, connected to the positive slope control module, is used to amplify the first positive three-level signal based on a Class AB power amplifier and a Class B power amplifier, and to amplify the positive three-level input signal based on a Class G power amplifier, so as to output a positive output signal. The negative drive module, connected to the negative slope control module, is used to amplify the first negative three-level signal based on the AB class power amplifier and the B class power amplifier, and to amplify the negative three-level input signal based on the G class power amplifier, so as to output a negative output signal.

5. The bus driver as described in claim 4, characterized in that, Both the positive drive module and the negative drive module include a drive unit, which includes a first operational amplifier, a second operational amplifier, a first inverter, a second inverter, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a second capacitor, a third capacitor, a fourth capacitor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor. The positive power supply terminal of the first operational amplifier, the positive power supply terminal of the second operational amplifier, the source of the eighth PMOS transistor, the first terminal of the fifth resistor, the source of the ninth PMOS transistor, and the drain of the eleventh NMOS transistor are all connected to the positive power supply. The negative power supply terminal of the first operational amplifier, the negative power supply terminal of the second operational amplifier, the source of the eighth NMOS transistor, the second terminal of the sixth resistor, the source of the ninth NMOS transistor, and the drain of the eleventh PMOS transistor are all connected to the negative power supply. The inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are connected and together form the first input terminal of the driving unit, which is connected to the slope control circuit to receive the first positive three-level signal or the first negative three-level signal. The output terminal of the first operational amplifier is connected to the gate of the eighth PMOS transistor, the gate of the tenth PMOS transistor, and the first terminal of the third capacitor. The output terminal of the second operational amplifier is connected to the gate of the eighth NMOS transistor, the gate of the tenth NMOS transistor, and the second terminal of the fourth capacitor; The drain of the eighth PMOS transistor is connected to the gate of the eleventh NMOS transistor and the first end of the third resistor. The second end of the third resistor, the first end of the fourth resistor, and the first end of the second capacitor are connected. The second end of the fourth resistor is connected to the drain of the eighth NMOS transistor and the gate of the eleventh PMOS transistor. The second end of the fifth resistor R5 is connected to the drain of the ninth PMOS transistor P9 and the source of the tenth PMOS transistor P10, and the source of the tenth NMOS transistor N10 is connected to the drain of the ninth NMOS transistor N9 and the first end of the sixth resistor R6. The output terminal of the first inverter is connected to the gate of the ninth PMOS transistor, and the output terminal of the second inverter is connected to the gate of the ninth NMOS transistor. The positive inverting input terminal of the first operational amplifier and the positive input terminal of the second operational amplifier, the drain of the tenth PMOS transistor, the drain of the tenth NMOS transistor, the source of the eleventh NMOS transistor, the source of the eleventh PMOS transistor, the second terminal of the second capacitor, the second terminal of the third capacitor, and the first terminal of the fourth capacitor are connected together to form the output terminal of the driving unit to output the positive output signal or the negative output signal. The input terminals of the first inverter and the second inverter are connected and together form the second input terminal of the driving unit, which is connected to the slope control circuit to receive the positive three-level input signal or the negative three-level input signal.

6. The bus driver as described in claim 5, characterized in that, The first operational amplifier includes a twelfth PMOS transistor, a thirteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor; The first terminal of the seventh resistor, the source of the twelfth PMOS transistor, the source of the thirteenth PMOS transistor, the first terminal of the ninth resistor, and the first terminal of the tenth resistor are all connected to the positive power supply. The second terminal of the eighth resistor, the source of the twelfth NMOS transistor, and the source of the thirteenth NMOS transistor are all connected to the negative power supply. The gate of the first transistor forms the inverting input terminal of the first operational amplifier; The gate of the second transistor forms the positive input terminal of the first operational amplifier; The second end of the seventh resistor is connected to the emitter of the first transistor and the base of the third transistor, and the collector of the first transistor and the first end of the eighth resistor are connected to the collector of the second transistor. The gate of the twelfth PMOS transistor, the drain of the twelfth PMOS transistor, and the collector of the third transistor are connected and together form the output terminal of the first operational amplifier. The emitter of the third transistor is connected to the emitter of the fourth transistor and the drain of the twelfth NMOS transistor. The gate of the thirteenth PMOS transistor is connected to the drain of the thirteenth PMOS transistor and the collector of the fourth transistor. The base of the fourth transistor is connected to the second segment of the ninth resistor and the emitter of the second transistor. The second end of the tenth resistor is connected to the drain of the thirteenth NMOS transistor, the gate of the twelfth NMOS transistor, and the gate of the thirteenth NMOS transistor.

7. The bus driver as claimed in claim 5, characterized in that, The second operational amplifier includes a fourteenth PMOS transistor, a fifteenth PMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor; The first terminal of the eleventh resistor, the source of the fourteenth PMOS transistor, and the source of the fifteenth PMOS transistor are all connected to the positive power supply. The source of the fourteenth NMOS transistor, the source of the fifteenth NMOS transistor, the second terminal of the twelfth resistor, the second terminal of the thirteenth resistor, and the second terminal of the fourteenth resistor are all connected to the negative power supply. The second end of the eleventh resistor is connected to the collector of the fifth transistor and the collector of the sixth transistor; The base of the fifth transistor forms the inverting input terminal of the second operational amplifier; The base of the sixth transistor forms the non-inverting input terminal of the second operational amplifier; The emitter of the fifth transistor is connected to the base of the seventh transistor and the first end of the twelfth resistor. The gate of the fourteenth PMOS transistor is connected to the gate of the fifteenth PMOS transistor, the drain of the fifteenth PMOS transistor, and the first end of the fourteenth resistor. The drain of the fourteenth PMOS transistor is connected to the emitter of the seventh transistor and the emitter of the eighth transistor. The collector of the eighth transistor is connected to the drain of the fifteenth NMOS transistor and the gate of the fifteenth NMOS transistor. The emitter of the sixth transistor is connected to the base of the eighth transistor and the first end of the thirteenth resistor.

8. The bus driver as claimed in claim 1, characterized in that, Also includes: A protection circuit, connected to the drive circuit, is configured to perform impedance matching and surge protection on the bus output signal, so as to output the bus output signal after impedance matching and surge protection.

9. The bus driver as claimed in claim 1, characterized in that, Also includes: A protection circuit, connected to the slope control circuit and the drive circuit, is configured to provide reverse connection protection for the positive and negative power supply voltages, so that both the slope control circuit and the drive circuit operate under the power supply voltages provided after reverse connection protection.

10. A chip, characterized in that, The chip includes a bus driver as described in any one of claims 1 to 9.

11. An electronic device, characterized in that, The electronic device includes a bus driver as described in any one of claims 1 to 9.

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