Multi-instruction storage and calculation integrated chip architecture based on memristor array

Abstract

The invention discloses a multi-instruction storage and calculation integrated chip architecture based on a memristor array, and relates to the technical field of storage and calculation fusion. The chip architecture comprises a memristor array module, a calculation module, a core control module, an input cache module and an output cache module, and the core control module interacts with an external interface, analyzes instruction signals and controls a memristor array and related modules to execute tasks. According to the method, six working modes of writing, in-memory calculation, accumulation, emptying, reading and peak power calculation are realized, a plurality of memristor arrays are scheduled by customizing a control module, and flexible scheduling of matrix vector multiplication is realized; the input cache module provides parallel data supply to meet the bandwidth requirement of a peak computing power mode, and the output cache module supports result storage and accumulation. The data migration is effectively reduced while the universality is ensured, the overall energy efficiency of the chip is improved, the external interface is simple, the expansibility is good, the chip is easy to use, and the method is suitable for the fields of artificial intelligence, high-performance calculation and the like.

Description

Technical Field

[0001] This invention relates to the field of computer chip and memory technology, and in particular to a multi-instruction in-memory computing chip architecture based on memristor arrays. Background Technology

[0002] With the development of artificial intelligence, big data, and high-performance computing, matrix-vector multiplication has become a core operation in applications such as deep learning and scientific computing. Existing storage-compute separation architectures suffer from frequent data migration between storage and computation in large-scale matrix operations, making it difficult to balance energy efficiency and performance.

[0003] Memristors, due to their non-volatility and good analog / digital computing capabilities, are gradually becoming an important candidate for new in-memory computing architectures. However, existing memristor-based in-memory computing chips generally suffer from the following problems: 1) Fixed functionality, lack of versatility, and difficulty in supporting multiple tasks; 2) Input and output are limited, making it unable to flexibly adapt to matrix operations of different sizes; 3) The working mode is simple and it is difficult to realize diverse functions such as writing, calculation, reading and accumulation.

[0004] Therefore, there is an urgent need for a memristor-based in-memory computing chip architecture that can be flexibly configured via instructions and simultaneously possesses high energy efficiency and high versatility. The purpose of this invention is to propose an in-memory computing chip based on a memristor array, which, by introducing an instruction set to control data organization, input / output, in-memory computation, and accumulation operations, achieves efficient and flexible matrix-vector multiplication operations, significantly improving computational energy efficiency. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-instruction in-memory computing chip architecture based on memristor arrays to solve the problems of insufficient versatility, single computing mode, complex interface control and limited energy efficiency of existing in-memory computing architectures.

[0006] To achieve the above objectives, this invention proposes a novel chip architecture. This architecture tightly integrates multiple high-capacity memristor arrays with on-chip control circuitry, supporting parallel in-memory computation across the arrays while also enabling flexible control of five instruction sets. Within a memristor computing framework, this circuit, through a customized control module, can schedule multiple memristor arrays to perform matrix-vector multiplication operations of varying scales. Furthermore, the circuit's external interface is very simple and easy to use, and it also supports directly activating all arrays to complete multiplication-accumulation calculations, achieving peak computing power.

[0007] The technical solution of the present invention is as follows: A multi-instruction in-memory computing chip architecture based on a memristor array, characterized in that it includes: 1) Memristor array module, used for in-memory computation, performs multiplication and accumulation operations. It includes multiple memristor arrays and a multiplexer. The memristor arrays store weight data and perform in-memory computation. The multiplexer selects the computation results from multiple memristor arrays and outputs them to the subsequent computation module for accumulation. The trigger input for this module comes from outside the chip or the core control module, triggering the memristor arrays to complete in-memory computation. Once triggered, it continuously and automatically retrieves data from the input buffer and outputs the final multiplication and accumulation result to the computation module. In addition, this module can be directly controlled by external signals to perform peak computing power mode of full array in-memory computation and output the computation result directly to the outside of the chip. 2) The calculation module is used to collect the partial sums calculated by the memristor array and further sum them. It is also used for residual calculation in the cumulative calculation mode. It includes a multi-level addition tree. The input is the output of the memristor array module or the output buffer module. The output is the accumulated result, which is output to the output buffer module. Whether residual calculation is needed is controlled by the core control module. Finally, a 2-to-1 data selector selects whether to accumulate residuals and outputs the final result. 3) The core control module interacts with external interfaces to parse instruction signals and control the memristor array and related modules to perform tasks, realizing six working modes of the chip, including write mode, in-memory calculation mode, accumulation calculation mode, clear mode, read mode, and peak computing power mode. 4) The input buffer module stores the external input vector through the storage unit, and rearranges and stores the input data to ensure that it can output bit by bit according to the peak bandwidth. Its input comes from the core control module, and its output can output each parameter to be calculated to the memristor array module bit by bit. 5) Output buffer module: Stores the calculation results output by the calculation module through the storage unit, and outputs the stored content to the calculation module for residual calculation or directly to the core control module for output outside the chip; The output of the stored content to the calculation module for residual calculation needs to be completed by a multiplexer, and the data output outside the chip needs to be intercepted by the output interception module to extract specific segments, and then handed over to the core control module for external transmission.

[0008] Furthermore, each of the memristor arrays has multiple rows and columns of storage cells, supporting weighted representations with different bit widths.

[0009] Furthermore, in the interaction between the core control module and the external interface, the signals input through the external interface include: a valid signal (representing an external request to use this module); an instruction signal (cfgin, representing the instruction used by the external party, valid simultaneously with valid); and input data (datain, representing the data required by the external party for this task; if not needed, this signal is invalid for this task). The signals output to the external interface include: a ready signal (indicating the module's idle / busy state); and output data (dataout, representing the data output after the task is completed; if no data is needed, this signal is invalid for this task). The core control module and the external interface use a handshake mechanism to complete task interaction. When both the valid signal and the ready signal are high, the handshake is successful. After a successful handshake, the ready signal is pulled low, the chip enters the working state, and executes instructions. When the task is completed, the ready signal is pulled high, and the dataout result is output as valid. In peak computing power mode, the peak computing power trigger signal (trigger) activates all memristor arrays for parallel computation. After the computation is completed, the computation result is directly output to the external chip via the array output signal (maxdataout).

[0010] Furthermore, the core control module controls and implements six operating modes of the chip, which are as follows: 1) Write mode, used to write input data to the input buffer; 2) In-memory computation mode, used to trigger the memristor array to perform in-memory computation and write the result to the output buffer; 3) Accumulation calculation mode, used to perform additional accumulation on the in-memory calculation result and the existing data in the output buffer; 4) Clear mode, used to clear all input buffers; 5) Read mode, used to output the data content in the cache through an external interface; 6) Peak computing power mode, used to simultaneously activate multiple memristor arrays to complete large-scale computations in parallel.

[0011] Furthermore, the input buffer module organizes the input data in the following way: when writing data, it needs to be reorganized according to the principle of "fastest retrieval first" to ensure that the output can provide parallel input to multiple memristor arrays at the same time, so as to support the high bandwidth data supply in peak computing power mode.

[0012] Furthermore, the storage unit of the output cache module is a register, and the calculation results are written into the register in sequence and padded with zeros when the data is insufficient.

[0013] Furthermore, the instruction signals parsed by the core control module include the following fields: 1) Data organization mode field, used to indicate how input data is distributed among multiple memristor arrays; 2) Input / output indicator field, used to indicate whether the task requires input or output; 3) Array activation field, used to control whether the memristor array is triggered to perform in-memory calculations; 4) Clear field, used to control the state of the input cache, clear all input cache or keep the input cache state; 5) The accumulation enable field is used to control whether to perform additional accumulation operations; 6) The cache selection field indicates the output cache number to be accumulated; 7) Data length field, used to indicate the amount of data involved in in-memory calculation / accumulation; 8) The array index field and the starting row and column number field are used to indicate the number of the memristor array involved and the data access location.

[0014] Compared with the prior art, the present invention has the following significant advantages: 1) High versatility: Through a unified multi-instruction system, it can support matrix-vector multiplication tasks of different scales and different splitting methods, taking into account both flexibility and adaptability.

[0015] 2) Superior energy efficiency: By utilizing in-memory computing, data transfer between memory and computing units is reduced, significantly improving the energy efficiency ratio.

[0016] 3) Simple interface: Task control and data exchange can be completed with only a few standardized signals, reducing the difficulty of integrating with external systems.

[0017] 4) Multiple modes: It provides six working modes, which can meet the needs of regular computing tasks and also bring out the hardware's maximum performance in peak computing power mode.

[0018] 5) Good scalability: By setting parameter fields in the instructions, the chip can flexibly configure the array sequence number, data range and cache sequence number, thus having good scalability and upgradeability.

[0019] In summary, this invention, by introducing a unified instruction set, input / output cache coordination mechanism, and peak computing power triggering mode into an in-memory computing architecture, realizes a multi-instruction in-memory computing chip that combines versatility and high energy efficiency, and has broad application prospects. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall chip architecture of the present invention; Figure 2 This is a schematic diagram of the chip module architecture in an embodiment of the present invention; Figure 3This is a schematic diagram of the external interface signal interaction timing in an embodiment of the present invention; Figure 4 This is a schematic diagram of SRAM writing and reading in an embodiment of the present invention. Detailed Implementation

[0021] The present invention will be further clearly and completely described below with reference to the accompanying drawings and specific embodiments.

[0022] This invention discloses a multi-instruction in-memory computing chip architecture based on a memristor array. The overall chip structure is as follows: Figure 1 As shown, it includes: 1) Memristor array module, used for in-memory calculations, to complete multiplication and accumulation operations.

[0023] 2) The calculation module is used to collect the partial sums calculated by the memristor array and further sum them, and it is also used for residual calculation in the accumulation mode.

[0024] 3) The core control module is used to parse command signals and control the memristor array and related modules to perform tasks, and supports multiple working modes.

[0025] 4) Input buffer module, used to store external input vectors. The input comes from the core control module, and the input data is rearranged and stored to ensure that it can be output bit by bit according to the peak bandwidth. Its output will output each parameter to be calculated bit by bit to the memristor array module. 5) Output cache module, used to store the calculation task results output by the calculation module, and output the stored content to the calculation module for residual calculation or directly to the core control module for off-chip output.

[0026] Figure 2 This is a schematic diagram showing the detailed structure of each module in the multi-instruction in-memory computing chip architecture based on a memristor array according to an embodiment of the present invention. As shown in the figure, the chip architecture includes: 1) The memristor array module includes 64 memristor arrays (memristor_0 ~ memristor_63) and a 64-channel -4-channel data selector. Each array has 512 rows × 4096 columns of storage cells, which can store weight data and perform in-memory calculations. The weight bit width is configurable; if set to 8 bits, each row can store 512 weights. The selector is used to select up to 4 arrays to complete subsequent accumulation calculations. The trigger input for this module comes from external sources or the core control module, which can trigger the memristor arrays to complete in-memory calculations. Once triggered, it will continuously and automatically retrieve data from the input buffer and output the final multiplication and accumulation result to the calculation module. Simultaneously, this module can be directly controlled by external signals (trigger) to perform peak computing power mode for full array in-memory calculations and directly output the calculation results to external sources (maxdataout).

[0027] 2) The calculation module mainly consists of an addition tree (adder0~adder4, etc.). The output of the parallel in-memory calculations performed by the 64 memristor array is output to the multi-level addition tree for summation (sum0~sum2) via a 64-4mux data selector. It can also be used to perform residual summation with previous results (sum3). Whether residual summation is needed is controlled by the core control module, and finally, a 2-to-1 data selector (2-1mux) selects whether to accumulate the residuals and outputs the final result. The input of the calculation module comes from the memristor array or the output buffer, and the accumulated result is output to the output buffer.

[0028] 3) The core control module is used to parse instruction signals and control the memristor array and related modules to perform tasks. It supports six working modes, including five working modes of the module to parse instruction signals and control the chip: realizing the coordinated work of chip writing, in-memory calculation, accumulation calculation, clearing and reading; and the sixth peak computing power mode.

[0029] The core control module receives input from external sources, including the external request signal `valid`, the external instruction signal `cfgin`, and external input data `datain`. At the start of each task, the output signal `ready` is set to 0 and remains set to 1 until the task is completed. Each task first parses `cfgin`. If data needs to be written to the array, the input data, including the data content and array address (`data&addr`), is output to the input buffer module. It also receives output from the output buffer module (`dataout`) and packages it for output to the external `dataout`. Furthermore, it needs to output all on-chip control signals to all other modules. These on-chip control signals include: a) Memristor trigger signal (pcm_ena): This signal is given to the memristor array module to trigger the memristor array that needs to be calculated.

[0030] b) Calculation selection signal (pcm_mux): Provides the memristor array module with the option to select up to 4 arrays to participate in subsequent calculations in both calculation and accumulation modes.

[0031] c) Accumulation enable signal (accum_ena): given to the calculation module to indicate whether the current result needs to be accumulated with the previous output in the output buffer.

[0032] d) Output Accumulation Selection Signal (accum_mux): Provided to the output buffer module to indicate which position of data in the output buffer is selected for accumulation in accumulation mode.

[0033] e) Output enable signal (output_ena): This signal is given to the output buffer module. The core control module parses the cfgin information, selects specific data and offsets in the output buffer, and obtains the final data to be output.

[0034] 4) Input buffer module, used to store external input vectors for on-demand output; its input comes from the core control module, and it rearranges the input data and stores it bit by bit to ensure that it can be output bit by bit according to the peak bandwidth. Its output will output each parameter to be calculated bit by bit to the memristor array module; in this example, 8192×64 SRAM is selected as the input buffer module.

[0035] 5) The output buffer module stores the computation results from the computation module in storage units and outputs the stored content to the computation module for residual calculation or directly to the core control module for off-chip output. Extracting the output data requires a 4-to-1 data selector. Data output to the off-chip needs to be truncated into specific segments by the output truncation module before being sent to the off-chip by the core control module. In this example, four 512×29-bit registers form four buffer units. Output data is written to these four output buffer units and selected by a 4-to-1 mux multiplexer, combined with the output truncation module to obtain the required data.

[0036] In the interaction between the core control module and external interfaces, the signals input through these interfaces include: a valid signal (request for use of the module from the outside); a cfgin signal (instruction signal for the current use of the module, valid simultaneously with valid); datain (data required for the current use; if not needed, this signal is invalid for this task); and a peak computing power trigger signal (trigger, the trigger signal for all arrays to be triggered by the outside). The signals output to the external interfaces include: a ready signal (indicating the module's idle state); dataout (data output after the current task is completed; if not needed, this signal is invalid for this task); and a maxdataout (peak computing power output signal, used in conjunction with trigger, directly outputting the peak computing power in full-array activated peak computing power mode, skipping subsequent accumulation calculations). Thus, by using a small number of standardized external interfaces, the complexity of using this circuit is significantly reduced, facilitating system integration.

[0037] In this example, the signals input to the external interface include: a 1-bit valid signal (valid), a 122-bit instruction signal (cfgin), 64×8-bit input data (datain), and a 1-bit peak computing power trigger signal (trigger); the signals output to the external interface include: a 1-bit ready signal (ready), 64×29-bit output data (dataout), and a 16-bit peak computing power output signal (maxdataout). like Figure 3 As shown, the external interface signal interaction timing is as follows: When an external task arrives, the external device pulls the valid signal high, and simultaneously provides the instruction signal cfgin and input data datain. The gray area in the figure represents the valid signal. If the chip is idle, the ready signal is high. At this time, both valid and ready are high, indicating a successful handshake. After a successful handshake, ready is pulled low, and the chip enters the working state to execute instructions. When the task is completed, the ready signal is pulled high, and the result is output as valid. In peak computing power mode, the external interface can send a high-level pulse to the trigger when ready=1 (indicating the chip is idle), thereby activating parallel computation of the entire memristor array. At this time, ready is set to 0 to indicate that the chip is busy. After the computation is completed, the result is not entered into the output buffer, but is directly output sequentially through maxdataout, requiring 64×512×29 / 16 clock cycles. After the computation is completed, ready is set back to 1 to indicate that the chip is idle.

[0038] The core control module controls the chip to operate in six modes, including five modes based on the parsing of the cfgin signal and a peak computing power mode, specifically: 1) Write mode, used to write input data into the input buffer; 2) In-memory computation mode, used to trigger a specified memristor array to perform in-memory computation and store the result in the output buffer; 3) Accumulation calculation mode, used to perform additional accumulation on the in-memory calculation result and the existing data in the output buffer; 4) Clear mode, used to clear all input buffers; 5) Read mode, used to output the data in the output buffer via dataout; 6) Peak computing power mode: Independent of the cfgin signal, the data to be calculated needs to be written into the input buffer in advance. Under the activation of the trigger, all memristor arrays work simultaneously to complete large-scale calculations in parallel, and the results are output through maxdataout.

[0039] The input buffer is organized as follows: The memristor array employs digital in-memory computation, requiring 1 bit of input to be applied to the array word line each time. In peak computing power mode, each of the 64 arrays requires 1 bit of input simultaneously, totaling 64 bits. To ensure bandwidth, the input cache SRAM outputs 64 bits per cycle, ensuring that each bit corresponds to a different array. Therefore, data must be reorganized according to the "fastest fetch first" principle during writing to guarantee parallel supply. The output mode of the input cache module can simultaneously provide parallel input to multiple memristor arrays to support high-bandwidth data supply in peak computing power mode. Figure 4 As shown, the SRAM width is 64 bits, and 64 bits can be read in parallel at one time to drive 64 arrays of WL simultaneously. Therefore, when writing a 4-bit value, it needs to be written according to the arrangement of the dark gray area in the figure, which requires the use of 4 SRAM addresses.

[0040] The output caching and result management methods are as follows: The output buffer is written to in a cyclical manner according to register numbers 0-3, for a total of 4 groups. Each group can store a maximum of 512 results, and zeros are added if there are insufficient results. When writing a new result, the old result is completely overwritten. The output data width is 29 bits: the 8-bit input is multiplied and accumulated with the 8-bit weight, requiring 26 bits for 512 rows of operations; considering a maximum of 4 groups for splitting and accumulating, 28 bits are needed; in the additional accumulation mode, it is accumulated with the buffer result, ultimately requiring 29 bits to ensure lossless precision.

[0041] The instruction signal structure definition includes the following fields for the 122-bit instruction signal cfgin: 1) The [1:0] field is the data organization mode bit: 2'b00 indicates that the 64 input data are not split (only 1 memristor array is effective), 2'b01 indicates that the 64 input data are divided into two equal parts (2 memristor arrays are effective), 2'b10 indicates that the 64 input data are divided into four equal parts (4 memristor arrays are effective), and 2'b11 is the reserved mode; this field has a profound impact on the write mode, in-memory calculation mode, and accumulation calculation mode; 2) [2] Fields are input / output indicator bits: 1'b0 indicates no input for the task, and 1'b1 indicates no output for the task; 3) [3] Field is the array activation bit: 1'b1 indicates that the memristor array required for the activation task has completed the in-memory calculation and summation and stored in the output buffer, 1'b0 indicates that the array is not working; 4) [4] Field is the clear bit: 1'b1 means clear all input buffers, 1'b0 means keep the input buffer state; 5) [5] Field is the accumulation enable bit: 1'b1 means that the operation result is accumulated with the data in the specified output buffer and then stored in the new output buffer, 1'b0 means that the operation result is directly stored in the output buffer; 6) [7:6] field is the cache selection bit: when the accumulation enable bit is 1'b1, it indicates the output buffer number (0-3) to be accumulated; 7) [17:8] Fields are data length bits: indicating the number of data points calculated / accumulated in memory (maximum value 512); 8) The [45:18] field is the array index: it contains four 7-bit data, which indicate the sequence number (0~63) of the four memristor arrays respectively. The validity varies with the data organization mode. That is, if [1:0]=2'b00, it means that the task is not split and only one memristor array is involved. Therefore, only [24:18] is valid, which means the sequence number of the memristor array involved. If [1:0]=2'b01, it means that the task is divided into two equal parts and two memristor arrays are involved. Therefore, only [31:18] is valid, which means the sequence number of the two memristor arrays involved. If [1:0]=2'b10, it means that the task is divided into four equal parts and four memristor arrays are involved. Then all of them are valid, which means the sequence number of the four memristor arrays involved. 9) The [85:46] field is the starting row number: it contains four 10-bit data, which respectively indicate the starting row number (0~511) of the input for the four memristor arrays. The validity varies with the data organization mode. That is, if [1:0]=2'b00, it means that the task is not split and only one memristor array is involved. Therefore, only [55:46] is valid, which represents the sequence number of the memristor array involved. If [1:0]=2'b01, it means that the task is divided into two equal parts and two memristor arrays are involved. Therefore, only [65:46] is valid, which represents the sequence numbers of the two memristor arrays involved. If [1:0]=2'b10, it means that the task is divided into four equal parts and four memristor arrays are involved. Then all of them are valid, which represents the sequence numbers of the four memristor arrays involved. 10) The [121:86] field is the starting column number: it contains four 9-bit data entries, each indicating the starting column group number of the output of one of the four memristor arrays, corresponding to the weight number (0-511). Its validity varies depending on the data organization mode. For example, if [1:0] = 2'b00, it means the task is not split, and only one memristor array participates; therefore, only [94:86] is valid, representing the sequence number of the participating memristor array. If [1:0] = 2'b01, it means the task is divided into two equal parts, and two memristor arrays participate; therefore, only [103:86] is valid, representing the sequence numbers of the two participating memristor arrays. If [1:0] = 2'b10, it means the task is divided into four equal parts, and four memristor arrays participate; therefore, all entries are valid, representing the sequence numbers of the four participating memristor arrays. Only the first data entry in the read task is valid, indicating the starting sequence number of the output buffer.

[0042] Each field of the cfgin command signal can be flexibly configured to achieve various functions.

[0043] Through the above-described working modes, the chip of this invention can flexibly adapt to different application requirements, significantly improving energy efficiency and computing performance while ensuring versatility, and is suitable for application scenarios such as artificial intelligence inference acceleration, signal processing and high-performance computing.

[0044] This invention introduces a multi-instruction control mechanism. By setting a unified instruction format, the chip can flexibly support multiple operating modes, including write, in-memory computation, accumulation computation, clear, read, and peak computing power mode. Except for the peak computing power mode, the other modes are directly configured and triggered by instructions, thereby enabling the chip to maintain versatility and flexibility for diverse computing tasks.

[0045] This invention employs a collaborative design of input / output buffers and array operations. The input buffer stores external input vectors, while the output buffer stores accumulation and calculation results; both are uniformly scheduled by the control module. This buffer design not only ensures high-parallelity array access but also allows for flexible accumulation and overwriting of results through different instruction combinations.

[0046] In this invention, the peak computing power mode uses simplified control signals to directly trigger all memristor arrays to run simultaneously, which can give full play to the parallelism of the hardware and output the maximum computing throughput in a very short time, thereby meeting the needs of high-performance scenarios.

[0047] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A multi-instruction in-memory computing chip architecture based on a memristor array, characterized in that, include: 1) Memristor array module, used for in-memory calculations, to perform multiplication and accumulation operations; It includes multiple memristor arrays and a multiplexer. The memristor arrays store weight data and perform in-memory calculations. The multiplexer selects the calculation results of multiple memristor arrays and outputs them to the subsequent calculation module for cumulative calculation. The module is triggered by inputs from outside the chip or the core control module, which triggers the memristor array to complete in-memory calculations. Once triggered, it continuously and automatically retrieves data from the input buffer and outputs the final multiplication and accumulation result to the calculation module. In addition, the module can be directly controlled by external signals to perform peak computing power mode of full array in-memory calculations and output the calculation results directly to the outside of the chip. 2) The calculation module is used to collect the partial sums calculated by the memristor array and further sum them, and it is also used for residual calculation in the cumulative calculation mode. It includes a multi-level addition tree. The input is the output of the memristor array module or the output of the output buffer module, and the output is the accumulated result, which is output to the output buffer module. Whether residual calculation is required is controlled by the core control module, and finally a 2-to-1 data selector selects whether to accumulate residuals and outputs the final result; 3) The core control module interacts with external interfaces to parse instruction signals and control the memristor array and related modules to perform tasks, realizing the chip's six working modes, including write mode, in-memory calculation mode, accumulation calculation mode, clear mode, read mode and peak computing power mode. 4) The input buffer module stores the external input vector through the storage unit, and rearranges and stores the input data to ensure that it can be output bit by bit according to the peak bandwidth. Its input comes from the core control module, and the output outputs each parameter to be calculated to the memristor array module bit by bit. 5) Output buffer module: Stores the calculation results output by the calculation module through the storage unit, and outputs the stored content to the calculation module for residual calculation or directly to the core control module for output outside the chip; The output of the stored content to the calculation module for residual calculation needs to be completed by a multiplexer, and the data output outside the chip needs to be intercepted by the output interception module to extract specific segments, and then handed over to the core control module for external transmission.

2. The chip architecture according to claim 1, characterized in that, The memristor array, each array having multiple rows and columns of storage cells, supports weighted representations with different bit widths.

3. The chip architecture according to claim 1, characterized in that, In the interaction between the core control module and the external interface, the signals input through the external interface include: a valid signal (request for use of this module from the outside); an instruction signal (cfgin) (instruction used by the outside in this operation, valid simultaneously with valid); and input data (datain) (data required for this operation; if not needed, this signal is invalid for this task). The signals output to the external interface include: a ready signal (indicating the idle / busy state of this module); and output data (dataout) (data output after the completion of this task; if not needed, this signal is invalid for this task). The core control module and the external interface use a handshake mechanism to complete task interaction. When the valid signal and the ready signal are both high, the handshake is successful. After a successful handshake, the ready signal is pulled low, the chip enters the working state, and executes instructions. When the task is completed, the ready signal is pulled high, and the dataout result is output as valid. In peak computing power mode, the peak computing power trigger signal (trigger) activates all memristor arrays for parallel computation. After the computation is completed, the computation result is directly output to the external chip via the array output signal (maxdataout).

4. The chip architecture according to claim 1, characterized in that, The core control module controls and implements six operating modes of the chip, specifically: 1) Write mode, used to write input data to the input buffer; 2) In-memory computation mode, used to trigger the memristor array to perform in-memory computation and write the result to the output buffer; 3) Accumulation calculation mode, used to perform additional accumulation on the in-memory calculation result and the existing data in the output buffer; 4) Clear mode, used to clear all input buffers; 5) Read mode, used to output the data content in the cache through an external interface; 6) Peak computing power mode, used to simultaneously activate multiple memristor arrays to complete large-scale computations in parallel.

5. The chip architecture according to claim 1, characterized in that, The input buffer module organizes the input data in the following way: when writing data, it reorganizes the data according to the principle of fastest retrieval priority, so as to ensure that the output can provide parallel input to multiple memristor arrays at the same time, in order to support high bandwidth data supply in peak computing power mode.

6. The chip architecture according to claim 1, characterized in that, The storage unit of the output buffer module is a register. The calculation results are written to the register in sequence and padded with zeros when the data is insufficient.

7. The chip architecture according to claim 1, characterized in that, The instruction signals parsed by the core control module include the following fields: 1) Data organization mode field, used to indicate how input data is distributed among multiple memristor arrays; 2) Input / output indicator field, used to indicate whether the task requires input or output; 3) Array activation field, used to control whether the memristor array is triggered to perform in-memory calculations; 4) Clear field, used to control the state of the input cache, clear all input cache or keep the input cache state; 5) The accumulation enable field is used to control whether to perform additional accumulation operations; 6) The cache selection field indicates the output cache number to be accumulated; 7) Data length field, used to indicate the amount of data involved in in-memory calculation / accumulation; 8) The array index field and the starting row and column number field are used to indicate the number of the memristor array involved and the data access location.

8. The chip architecture according to claim 1, characterized in that, The core control module first parses the instruction signal for each task. If it needs to write data to the array, it outputs the input data, including the data content and the array address, to the input buffer module. The core control module also receives the output stored in the output buffer module and packages it for output to the off-chip. The core control module outputs full-chip control signals to the corresponding modules. These full-chip control signals include: a) Memristor trigger signal: given to the memristor array module to trigger the memristor array that needs to be calculated; b) Calculation selection signal: Provide the memristor array module with a maximum of 4 arrays to participate in the subsequent calculation in both calculation mode and accumulation mode; c) Accumulation enable signal: given to the calculation module to indicate whether the current result needs to be accumulated with the previous output in the output buffer; d) Output accumulation selection signal: Provided to the output buffer module to indicate which position of data in the output buffer will be used for accumulation in accumulation mode; e) Output enable signal: The output buffer module is given the instruction signal information through the core control module. The module selects specific data and offset in the output buffer to obtain the final output data.

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