Equivalent road rapid simulation method compatible with SPICE

Abstract

The invention provides an equivalent road rapid simulation method compatible with SPICE (simulation program with integrated circuit emphasis). The method comprises the following steps: (1) based on a three-dimensional geometric structure and material characteristics of a target integrated circuit, constructing an equivalent path which comprises a direct current source, a resistor and a voltage-controlled current source, and coupling equivalent path solving networks in three directions by introducing the voltage-controlled current source; (2) according to a preset working load condition, calculating a parameter value of each circuit element in the equivalent circuit; (3) constructing a boundary condition of an equivalent path based on the three-dimensional geometric structure of the target integrated circuit; and (4) solving the constructed equivalent path. The method can be deployed on an SPICE platform, and the calculation speed of the method is far higher than that of an existing equivalent road simulation method.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation (EDA) and relates to a fast simulation method for equivalent circuits compatible with SPICE. Background Technology

[0002] As circuit feature sizes continue to shrink and integration density increases exponentially, the power density of advanced integrated circuits increases dramatically, leading to a significant rise in circuit temperature. Simultaneously, because advanced integrated circuits are composed of multiple layers of heterogeneous materials, temperature gradients induce significant thermal stress within the circuit.

[0003] Electrothermal coupling effects have a significant impact on the performance of devices and circuits. High temperatures can lead to degraded device performance (such as reduced carrier mobility and threshold voltage drift), further affecting circuit performance. Thermal stress can alter the electrical characteristics of devices (such as on-state current, threshold voltage, and interconnect lifetime), and may even induce microcracks and interface debonding in the circuit structure. Therefore, accurate and rapid modeling of electrothermal coupling effects is crucial for assessing their impact on circuit performance and reliability.

[0004] Because the equivalent thermal circuit method is compatible with circuit simulation platforms and has high computational efficiency, it has become a widely adopted method for integrated circuit thermal analysis. Furthermore, researchers have developed an equivalent multiphysics circuit framework compatible with circuit simulation platforms by developing an equivalent mechanical circuit method (Y. Liu, L. Tian, ​​Y. Niu, Y. Xia and W. Chen, "An Equivalent Multiphysics Circuit Framework for Electro-Thermal-Mechanical Coupling Simulation in Integrated Circuits by Proposing a SPICE Compatible Equivalent Mechanical Circuit Method," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025). Therefore, researchers can simulate electrothermal-mechanical coupling effects on circuit simulation platforms, thereby significantly improving circuit design efficiency.

[0005] However, the computation speed of the equivalent mechanical circuits (EMCs) previously proposed by the inventors based on the self-consistent iterative method is relatively slow. The simulation time for EMCs and the finite element method (FEM) is... Figure 1 A comparison was made in the middle. Figure 1The inserted section shows the simulation structure. With the same number of nodes, the simulation time for EMCs is approximately 10 times longer than that for FEMs, which significantly reduces circuit design efficiency.

[0006] Based on this, this invention proposes a fast simulation method for equivalent circuits compatible with SPICE, used to improve the simulation speed of equivalent mechanical circuits. In this invention, the newly constructed equivalent circuit is abbreviated as EMCc. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a fast simulation method for equivalent circuits that is compatible with SPICE.

[0008] The technical solution adopted in this invention is as follows:

[0009] A fast simulation method for equivalent circuits compatible with SPICE includes the following steps:

[0010] 1) Based on the three-dimensional geometry and material properties of the target integrated circuit, an equivalent circuit is constructed. During the construction process, a voltage-controlled current source is introduced to couple the equivalent circuit solution network in three directions.

[0011] 2) Calculate the parameter values ​​of each circuit element in the equivalent circuit according to the preset working load conditions;

[0012] 3) Based on the three-dimensional geometric structure of the target integrated circuit, construct the boundary conditions of the equivalent circuit;

[0013] 4) Solve for the constructed equivalent path.

[0014] In the above technical solution, further, in step 1), the equivalent circuit is constructed based on the three-dimensional geometric structure and material properties of the target integrated circuit, specifically following the following steps: (1) setting the circuit node to be determined; (2) connecting adjacent nodes; (3) adding resistors between circuit nodes; (4) adding DC current sources on the circuit nodes; (5) adding voltage-controlled current sources on the circuit nodes.

[0015] Furthermore, in step (5), four voltage-controlled current sources are added to each circuit node. Specifically, in the equivalent circuit used to calculate displacement u, the control voltage of the four voltage-controlled current sources added to each node is taken from the displacements v and w of adjacent nodes in the positive and negative x-axis directions, respectively; in the equivalent circuit used to calculate displacement v, the control voltage of the four voltage-controlled current sources added to each node is taken from the displacements u and w of adjacent nodes in the positive and negative y-axis directions, respectively; in the equivalent circuit used to calculate displacement w, the control voltage of the four voltage-controlled current sources added to each node is taken from the displacements u and v of adjacent nodes in the positive and negative z-axis directions, respectively. Thus, the three equivalent circuits used to calculate displacements u, v, and w are coupled and connected by voltage-controlled current sources. The three displacement variables u, v, and w can be obtained by solving them once. Compared with the scheme of adding only DC current sources in the equivalent circuits without adding voltage-controlled current sources, the simulation speed can be greatly improved.

[0016] Furthermore, in step 2), the expressions for the electrical components in the equivalent circuit are as follows: For the equivalent circuit used to calculate displacement u, the resistors are:

[0017] The resistance in the x-direction is:

[0018]

[0019] The resistance in the y-direction is:

[0020]

[0021] The resistance in the z-direction is:

[0022]

[0023] The DC current source is:

[0024]

[0025] The voltage-controlled current source is:

[0026]

[0027] Where: Δx is the distance between the two nodes of the resistor in the x-direction, Δy is the distance between the two nodes of the resistor in the y-direction, Δz is the distance between the two nodes of the resistor in the z-direction, λ and μ are Lamé coefficients, v represents the displacement in the y-direction, w represents the displacement in the z-direction, T represents the temperature, and α... xx Indicates the coefficient of thermal expansion;

[0028] The same applies to the equivalent path used to calculate displacement v and the equivalent path used to calculate displacement w.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] This invention provides a fast equivalent path simulation method compatible with SPICE, which can be deployed on the SPICE platform and has a calculation speed that is much higher than existing equivalent path simulation methods. Attached Figure Description

[0031] Figure 1 The simulation time is for EMCs and FEMs, with the inset showing the simulation structure. For simulation time of EMCs. t FEM The simulation time is for the finite element method.

[0032] Figure 2 This is a cube structure to be simulated in one embodiment of the present invention.

[0033] Figure 3 (a) Equivalent path (EMCc-x) used to calculate displacement u; (b) Equivalent path (EMCc-y) used to calculate displacement v; (c) Equivalent path (EMCc-z) used to calculate displacement w.

[0034] Figure 4 (a) Gate All-Around Nanosheet Transistor (GAA-NSFET); (b) xz cross section of GAA-NSFET; (c) Schematic diagram of simulation boundary condition settings.

[0035] Figure 5 A comparison of displacement distribution results calculated based on EMCc and FEM numerical simulations.

[0036] Figure 6 A comparison of stress distribution results calculated based on EMCc and FEM numerical simulations. Figure 7 Comparison of simulation time (a) and simulation time (b) results for EMCs, EMCc and FEM. Detailed Implementation

[0037] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0038] In the following examples, a typical three-dimensional nanoscale semiconductor electronic device is selected, taking the gate all-around nanosheet transistor structure (GAA-NSFET) as an example, to describe in detail the SPICE-compatible fast simulation method of the present invention. However, the SPICE-compatible fast simulation method of the present invention is not only applicable to GAA-NSFET, but also applicable to the modeling and analysis of electrothermal-mechanical coupling effects in most structures.

[0039] According to a specific embodiment of the present invention, an EMCc is established for the above structure, specifically including the following:

[0040] 1. Build EMCc:

[0041] by Figure 2 The method of constructing an EMCc is illustrated using a cubic structure as an example. The method of constructing an EMCc should follow these steps: (1) Set the nodes of the circuit to be determined; (2) Connect adjacent nodes; (3) Add resistors between adjacent circuit nodes; (4) Add a DC current source to each circuit node; (5) Add four voltage-controlled current sources to each circuit node.

[0042] 2. Expressions for electrical components in EMCc:

[0043] use Figure 3 In equation (a), when calculating the displacement u using EMC-x, the resistances are calculated using the following expressions.

[0044]

[0045] DC current sources are calculated using the following expression.

[0046]

[0047] The four voltage-controlled current sources are calculated using the following expression.

[0048]

[0049] Where Δx is the distance between the two nodes of the resistor in the x-direction, Δy is the distance between the two nodes of the resistor in the y-direction, Δz is the distance between the two nodes of the resistor in the z-direction, λ and μ are the Lamé coefficients, and α... xx The variable represents the coefficient of thermal expansion, v represents displacement in the y-direction, w represents displacement in the z-direction, and T represents temperature; the numbers in the variable subscripts correspond to... Figure 2 The node number in the data.

[0050] use Figure 3 When calculating v in EMC-y in (b), each resistor is calculated using the following expression.

[0051]

[0052] DC current sources are calculated using the following expression.

[0053]

[0054] The four voltage-controlled current sources are calculated using the following expression.

[0055]

[0056] use Figure 3 When calculating w in EMC-z in (c), each resistor is calculated using the following expression.

[0057]

[0058] DC current sources are calculated using the following expression.

[0059]

[0060] The four voltage-controlled current sources are calculated using the following expression.

[0061]

[0062]

[0063] The GAA-NSFET structure and the simulated configuration of electrothermal coupling effect are as follows: Figure 4 As shown. The GAA-NSFET structure is as follows. Figure 4 As shown in (a). The xz cross section and materials used in the GAA-NSFET are as follows. Figure 4 As shown in (b). The simulation configuration is as follows. Figure 4 As shown in (c), the power of the GAA-NSFET was simulated using the unbalanced Green's function (NEGF). The boundary of the GAA-NSFET was set to 300K. The top / bottom boundaries were fixed, and the side boundaries were set as periodic boundaries.

[0064] 3. Construct boundary conditions:

[0065] Based on the actual operating conditions of the integrated circuit to be simulated, equivalent path boundary conditions are constructed, specifically:

[0066] For fixed boundary conditions, the fixed boundary conditions can be constructed by setting the nodes in the corresponding equivalent path to ground.

[0067] For an equivalent circuit structure with periodic boundaries, the displacements at the two boundary nodes can be made to satisfy the periodic boundary by connecting the two boundary nodes with a wire.

[0068] For free boundary conditions, the free boundary can be constructed by building the resistance of the absorption layer in the equivalent circuit.

[0069] 4. Finally, solve for the constructed equivalent path.

[0070] The cross-sectional distributions of u, v, and w calculated by the EMCc of this invention are as follows: Figure 5 As shown in (a1), (b1), and (c1), the cross-sectional distributions of u, v, and w obtained by the finite element method are as follows. Figure 5 As shown in (a2), (b2), and (c2), the w(y = 30nm & x = 22, 26, 31nm) calculated by FEM and EMCc is as follows: Figure 5 As shown in (a3). The u (z = 38 nm & y = 25, 27, 30 nm) calculated by FEM and EMCc is as follows: Figure 5 As shown in (b3). The v(z=38nm&x=22, 26, 31nm) calculated by FEM and EMCc are as follows: Figure 5 As shown in (c3). According to Figure 5 The comparison results verified the correctness of the displacement results calculated by EMCc.

[0071] σ calculated from EMCc xx σ yy and σ zz The cross-sectional distribution is as follows Figure 6 As shown in (a1), (b1), and (c1), σ is calculated using the finite element method. xx σ yy and σ zz The cross-sectional distribution is as follows Figure 6 As shown in (a2), (b2), and (c2), σ is calculated using FEM and EMCc. xx (z = 38nm & y = 25, 27, 30nm) For example Figure 6 As shown in (a3). σ calculated by FEM and EMCc yy (z = 38nm & x = 22, 26, 31nm) For example Figure 6 As shown in (b3). σ calculated by FEM and EMCc zz (z = 38nm & y = 25, 27, 30nm) For example Figure 6 As shown in (c3). According to Figure 6 The comparison results verified the correctness of the stress results calculated by EMCc.

[0072] The simulation times for FEM, EMCc, and EMCs (where the EMCs method differs from the EMCc method in that it only adds DC current sources to the circuit nodes, without adding voltage-controlled current sources) are as follows: Figure 7 As shown in (a). With t FEM The simulation times are for EMCs, EMCc, and FEM, respectively. With tFEM The comparison results are as follows Figure 7 As shown in (b). With the same number of nodes, Compare 10 times shorter, and with t FEM The computational efficiency of the EMCc proposed in this invention is approximately 10 times faster than that of existing equivalent path structures.

[0073] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A SPICE-compatible equivalent circuit fast simulation method, characterized in that, The method comprises the following steps: 1) constructing equivalent force paths based on the three-dimensional geometric structure and material properties of the target integrated circuit, and introducing voltage-controlled current sources to couple the networks of the equivalent force paths in three directions during the construction process; 2) calculating the parameter values of each circuit element in the equivalent force paths according to a preset working load condition; 3) constructing the boundary conditions of the equivalent force paths based on the three-dimensional geometric structure of the target integrated circuit; 4) solving the constructed equivalent force paths.

2. The SPICE-compatible equivalent circuit fast simulation method of claim 1, wherein, In step 1), the equivalent force paths are constructed based on the three-dimensional geometric structure and material properties of the target integrated circuit, and the following steps are followed: (1) setting the circuit nodes to be solved; (2) connecting adjacent nodes; (3) adding resistors between the circuit nodes; (4) adding direct current sources to the circuit nodes; and (5) adding voltage-controlled current sources to the circuit nodes.

3. The SPICE-compatible equivalent circuit fast simulation method of claim 2, wherein, In step 5), four voltage-controlled current sources are added to each circuit node, specifically: in the equivalent force path for calculating displacement u, the control voltages of the four voltage-controlled current sources added to each node are taken from the displacements v and w of the adjacent nodes in the x-axis positive / negative direction; in the equivalent force path for calculating displacement v, the control voltages of the four voltage-controlled current sources added to each node are taken from the displacements u and w of the adjacent nodes in the y-axis positive / negative direction; and in the equivalent force path for calculating displacement w, the control voltages of the four voltage-controlled current sources added to each node are taken from the displacements u and v of the adjacent nodes in the z-axis positive / negative direction; thus, the three equivalent force paths for calculating displacements u, v and w are coupled and connected by voltage-controlled current sources, and the three displacement variables u, v and w can be obtained by solving once, thereby improving the simulation speed.

4. The SPICE-compatible equivalent circuit fast simulation method of claim 1, wherein, In step 2), the expressions of the electrical elements in the equivalent force paths are as follows: for the equivalent force path for calculating displacement u, the resistors are: the x-direction resistors are: the y-direction resistors are: the z-direction resistors are: the direct current sources are: the voltage-controlled current sources are: where: Δx is the distance between nodes at the ends of the resistor in the x direction, Δy is the distance between nodes at the ends of the resistor in the y direction, Δz is the distance between nodes at the ends of the resistor in the z direction, λ and μ are Lame's coefficients, v represents displacement in the y direction, w represents displacement in the z direction, T represents temperature, α xx represents the coefficient of thermal expansion; The same applies to the equivalent force paths for calculating displacements v and w.

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