Inverter synchronization method, inverter and storage medium

Abstract

The invention provides an inverter synchronization method, an inverter and a storage medium, and the inverter synchronization method is applied to a first inverter, and comprises the steps: responding to a timer of the first inverter, completing the counting of a preset timing period, sending a synchronization instruction to at least one second inverter, and executing first synchronization processing; wherein the synchronization instruction is used for indicating the at least one second inverter to execute second synchronization processing, and the first synchronization processing and the second synchronization processing are used for realizing synchronization between the first inverter and the at least one second inverter. According to the technical scheme of the invention, the synchronization of the inverter triggering synchronization processing is realized based on the timer of the first inverter, so that the at least one second inverter accurately enters the synchronization process, and the synchronization precision and efficiency between the first inverter and the at least one second inverter are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of inverters, in particular to an inverter synchronization method, an inverter and a storage medium. BACKGROUND

[0002] With the continuous improvement of the functions of smart terminals such as mobile phones and tablets, they have gradually become one of the tools commonly used in people's daily life and work.

[0003] In the process of conceiving and implementing the present application, the inventors have found that at least the following problems exist: when the existing inverters are connected in parallel, the synchronization accuracy is poor and the efficiency is low, and the high-precision cooperative operation requirement cannot be met.

[0004] The foregoing narrative is intended to provide general background information and does not necessarily constitute the prior art. SUMMARY

[0005] To solve the above technical problems, the present application provides an inverter synchronization method, an inverter and a storage medium, so that at least one second inverter accurately enters the synchronization process, and the accuracy and efficiency of the synchronization between the first inverter and the at least one second inverter are improved.

[0006] The present application provides an inverter synchronization method applied to a first inverter, comprising: in response to the completion of the counting of a preset time period by a timer of the first inverter, sending a synchronization instruction to at least one second inverter, and performing first synchronization processing; wherein the synchronization instruction is used to instruct the at least one second inverter to perform second synchronization processing, and the first synchronization processing and the second synchronization processing are used to realize synchronization between the first inverter and the at least one second inverter.

[0007] Optionally, the preset time period is configured according to the output frequency of the first inverter.

[0008] Optionally, the first synchronization processing comprises at least one of the following: timer synchronization compensation based on the preset time period; drive counter synchronization compensation based on a preset drive count value; determining the output phase of the first inverter based on the preset time period.

[0009] Optionally, the timer synchronization compensation based on the preset time period comprises: assigning the preset time period to the current count value of the timer, determining a first count compensation value according to the current count value of the timer and the preset time period, and compensating the timer according to the first count compensation value; And / or, the driving counter synchronization compensation based on the preset driving count value comprises: determining a second count compensation value according to the current driving count value of the driving counter of the first inverter and the preset driving count value, and compensating the driving counter of the first inverter according to the second count compensation value; And / or, the output phase of the first inverter determined based on the preset timing period comprises: determining a first angle step value according to the preset timing period, and determining the output phase of the first inverter according to the preset timing period and the first angle step value.

[0010] In a second aspect, the embodiments of the present application provide an inverter synchronization method applied to a second inverter, comprising: performing a second synchronization process in response to receiving a synchronization instruction; The synchronization instruction is sent by the first inverter after the timer of the first inverter completes the count of the preset timing period, and the second synchronization process is used to synchronize the at least one second inverter with the first inverter.

[0011] Optionally, the second synchronization process comprises at least one of the following: timer synchronization compensation based on a preset timing period, the preset timing period being configured according to the output frequency of the first inverter; driving counter synchronization compensation based on a preset driving count value; determining the output phase of the second inverter based on the preset timing period.

[0012] Optionally, the timer synchronization compensation based on the preset timing period comprises: determining a third count compensation value according to the current count value of the timer of the second inverter and the preset timing period, and compensating the timer of the second inverter according to the third count compensation value; And / or, the driving counter synchronization compensation based on the preset driving count value comprises: determining a fourth count compensation value according to the current driving count value of the driving counter of the second inverter and the preset driving count value, and compensating the driving counter of the second inverter according to the fourth count compensation value; And / or, determining the output phase of the second inverter based on the preset timing period comprises: determining a second angle step value according to the preset timing period, and determining the output phase of the second inverter according to the preset timing period and the second angle step value.

[0013] In a third aspect, the embodiments of the present application provide an inverter synchronization method, characterized in that comprising: The first inverter sends a synchronization instruction to at least one second inverter after the timer completes the preset time period counting, and performs a first synchronization processing; The at least one second inverter performs a second synchronization processing after receiving the synchronization instruction; The first synchronization processing and the second synchronization processing are used to synchronize the first inverter and the at least one second inverter.

[0014] In a fourth aspect, the embodiments of the present application further provide an inverter, comprising a memory and a processor, wherein the memory stores a processing program, and the processing program is executed by the processor to implement the steps of the inverter synchronization method according to any one of the above.

[0015] The embodiments of the present application further provide a storage medium, wherein the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the inverter synchronization method according to any one of the above.

[0016] The technical solution of the present application realizes the synchronization of the inverter trigger synchronization processing based on the timer of the first inverter, so that the at least one second inverter accurately enters the synchronization process, and the accuracy and efficiency of the synchronization between the first inverter and the at least one second inverter are improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0018] Figure 1 A hardware structure schematic diagram of a mobile terminal for implementing various embodiments of the present application.

[0019] Figure 2 A communication network system architecture diagram is provided for the embodiments of the present application.

[0020] Figure 3 A flowchart of the inverter synchronization method according to the first embodiment is shown.

[0021] Figure 4 A flowchart of the inverter synchronization method according to the second embodiment is shown.

[0022] Figure 5is a flowchart of the inverter synchronization method according to the third embodiment.

[0023] Figure 6 is a detailed flowchart of the inverter synchronization method according to the third embodiment.

[0024] Figure 7 is a strategy overview of the inverter synchronization method according to the third embodiment.

[0025] Figure 8 is a simulation comparison of the inverter synchronization method according to the third embodiment Figure 1 .

[0026] Figure 9 is a simulation comparison of the inverter synchronization method according to the third embodiment Figure 2 .

[0027] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments, with reference to the accompanying drawings. The above-described drawings have shown the explicit embodiments of the present application, and will be described in more detail hereinafter. These drawings and the written description are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0028] The exemplary embodiments will be described in detail herein with reference to the accompanying drawings. The following description is presented with reference to the accompanying drawings, in which a similar reference can indicate similar elements or features. The embodiments described in the following exemplary embodiments are not meant to represent all implementations in accordance with the present application. Rather, they are merely examples in accordance with some aspects of the present application as detailed in the appended claims.

[0029] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. Also, the use of "including", "comprising", "having" and "with" adding "one" or "some" to a list of elements in the context of any goods, methods, and apparatuses that collectively "comprise" the elements, are intended to preserve the option to additionally include other integers to the recited elements. The same applies to the use of "consisting essentially of" and "consisting of" in the context of any goods, methods, and apparatuses that collectively "consist of" the recited elements.

[0030] It should be understood that, although terms, first, second, third, etc. can be used herein to describe various information, these terms are not intended to denote a particular order or hierarchy among the information. These terms are used only to distinguish one category of information from another category of information. For example, a first information can be termed a second information, and similarly, a second information can be termed a first information without departing from the scope hereof. The word "if' as used herein, depending on the context in which it is used, can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Also, the word "comprise" or "comprising" as used herein, can be interpreted as meaning "comprising but not limited to." It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, and / or groups but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, items, and / or groups thereof. As used herein, the terms "or," "and / or," "and," "at least one of," and the like are to be interpreted as inclusive, unless the context of their use indicates otherwise. For example, "A, B, or C" or "A, B, and / or C" or "at least one of A and B" can be interpreted to mean "A; B; C; A and B; A and C; B and C; A, B, and C," or the like. Such clauses are also to be interpreted to mean "A, or B, or C, or any combination of the items A, B, and C" or the like.

[0031] It should be understood that, although various steps in the flowcharts of the embodiments of the present application are shown in a sequential order, these steps are not necessarily performed in the order shown. Unless explicitly stated, the steps of the embodiments of the present application are not necessarily performed in the order shown. Moreover, at least some of the steps can include multiple sub-steps or multiple stages, which are not necessarily performed in the order shown. For example, the steps of the flowcharts can be performed in parallel or in any order.

[0032] The word "if' as used herein, depending on the context in which it is used, can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrase "if determined" or "if detecting (a stated condition or event)" can be interpreted to mean "when determined" or "in response to determining" or "when detecting (a stated condition or event)" or "in response to detecting (a stated condition or event)," depending on the context in which it is used.

[0033] It should be noted that, in the present document, step codes such as S1, S2, etc. are used for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation in order. Those skilled in the art may, in specific implementation, perform S2 before S1, etc., but these should be within the scope of protection of the present application.

[0034] It should be understood that the specific embodiments described herein are merely illustrative of the present application and do not limit the present application.

[0035] In the following description, the suffixes used for elements, such as "module", "part", or "unit", are used only for convenience of explanation of the present application, and do not have a specific meaning by themselves. Thus, "module", "part", or "unit" can be mixedly used.

[0036] The smart terminal can be implemented in various forms. For example, the smart terminal described in the present application can include a smart terminal such as a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a smart watch, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a navigation device, a wearable device, a smart band, a pedometer, and the like, and a fixed terminal such as a digital TV, a desktop computer, and the like.

[0037] In the following description, a mobile terminal will be exemplarily described, and those skilled in the art will understand that the configuration according to the embodiments of the present application can be applied to a terminal of a fixed type, except for elements particularly used for mobile purposes.

[0038] Referring to Figure 1 , which is a hardware structure diagram of a mobile terminal according to an embodiment of the present application, the mobile terminal 100 can include an RF (Radio Frequency) unit 101, a WiFi module 102, an audio output unit 103, an A / V (audio / video) input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a storage 109, a processor 110, and a power supply 111, etc. Those skilled in the art can understand that the mobile terminal structure shown in Figure 1 The mobile terminal structure shown in

[0039] Hereinafter, the components of the mobile terminal will be described in detail with reference to Figure 1 The components of the mobile terminal will be described in detail as follows: The radio frequency unit 101 can be used for receiving and transmitting signals in the process of information or communication. Specifically, the radio frequency unit 101 receives the downlink information of the base station and provides the received information to the processor 110 for processing. In addition, the radio frequency unit 101 transmits the uplink data to the base station. Generally, the radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, etc. In addition, the radio frequency unit 101 can also communicate with the network and other devices through wireless communication. The above wireless communication can use any communication standard or protocol, including but not limited to GSM (Global System of Mobile communication), GPRS (General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division Duplexing-Long Term Evolution), TDD-LTE (Time Division Duplexing-Long Term Evolution), 5G and 6G, etc.

[0040] The WiFi belongs to a short-range wireless transmission technology. The WiFi module 102 can help the user to send and receive e-mails, browse web pages, and access streaming media, etc. It provides the user with wireless broadband Internet access. Although Figure 1 The WiFi module 102 is shown, but it can be understood that it does not belong to the necessary components of the mobile terminal, and can be omitted as needed without changing the essence of the application.

[0041] The audio output unit 103 can convert audio data, which is received by the radio frequency unit 101 or the WiFi module 102 or stored in the memory 109, into an audio signal and output the audio signal as sound when the mobile terminal 100 is in a call signal receiving mode, a call mode, a recording mode, a voice recognition mode, a broadcast reception mode, etc. Moreover, the audio output unit 103 can provide audio output related to a particular function performed by the mobile terminal 100 (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit 103 can include a speaker, a buzzer, etc.

[0042] The A / V input unit 104 is configured to receive audio or video signals. The A / V input unit 104 can include a graphics processor (GPU) 1041 and a microphone 1042. The graphics processor 1041 processes image data of a still picture or a video obtained by an image capture device (e.g., a camera) in a video capture mode or an image capture mode. Processed image frames can be displayed on the display unit 106. Processed image frames can be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the WiFi module 102. The microphone 1042 can receive sound (audio data) via the microphone 1042 in a telephone call mode, a recording mode, a voice recognition mode, or the like, and can process such sound into audio data. Processed audio (voice) data can be converted into a format that can be transmitted to a mobile communication base station via the radio frequency unit 101 in the case of the telephone call mode. The microphone 1042 can implement various types of noise cancellation (or suppression) algorithms to cancel (or suppress) noise or interference generated in the process of receiving and transmitting audio signals.

[0043] The mobile terminal 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors. The light sensor includes an ambient light sensor and a proximity sensor, which can optionally adjust the brightness of the display panel 1061 according to the brightness of ambient light, and turn off the display panel 1061 and / or the backlight when the mobile terminal 100 is moved to the ear. As one of the motion sensors, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally three axes), and detect the magnitude and direction of gravity when at rest, which can be used for applications that recognize the posture of the mobile terminal (such as switching between landscape and portrait screens, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometers, tapping), and the like. The mobile terminal can also be configured with a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, and other sensors, which will not be described here.

[0044] The display unit 106 is configured to display information input by a user or information provided to the user. The display unit 106 can include a display panel 1061, which can be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0045] The user input unit 107 can be used to receive input numerals or character information, and to generate key signal inputs related to user settings of the mobile terminal and control of functions. Optionally, the user input unit 107 can include a touch panel 1071 and other input devices 1072. The touch panel 1071, also called a touch screen, can collect touch operations of a user on or proximity thereto (e.g., operations by the user using a finger, a touch pen, or any suitable object or accessory on or in proximity to the touch panel 1071) and drive corresponding connection devices according to a pre-set program. The touch panel 1071 can include two parts, a touch detecting device and a touch controller. The touch detecting device detects the user's touch position and detects a signal resulting from the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detecting device and converts it into touch coordinates, which are then transmitted to the processor 110, and can receive commands from the processor 110 and execute them. In addition, the touch panel 1071 can be implemented in various types such as a resistive type, a capacitive type, an infrared type, and a surface acoustic wave type. In addition to the touch panel 1071, the user input unit 107 can include other input devices 1072. Optionally, the other input devices 1072 can include one or more of, but are not limited to, a physical keyboard, a function key (e.g., a volume control key, a switch key, etc.), a trackball, a mouse, a joystick, etc.

[0046] Optionally, the touch panel 1071 can cover the display panel 1061, and when the touch panel 1071 detects a touch operation on or in proximity thereto, it transmits the information to the processor 110 to determine the type of touch event, and then the processor 110 provides a corresponding visual output on the display panel 1061 according to the type of touch event. Although in the above description, the touch panel 1071 and the display panel 1061 are implemented as two separate components to achieve the input and output functions of the mobile terminal, in some embodiments, the touch panel 1071 and the display panel 1061 can be integrated to achieve the input and output functions of the mobile terminal, without being limited in this regard. Figure 1

[0047] The interface unit 108 serves as an interface through which at least one external device can be connected with the mobile terminal 100. For example, the external device can include a wired or wireless headset port, an external power (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input / output (I / O) port, a video I / O port, an earphone port, etc. The interface unit 108 can be used to receive input (e.g., data information, power, etc.) from an external device and to transmit the received input to one or more elements within the mobile terminal 100, or can be used to transmit data between the mobile terminal 100 and the external device. ​

[0048] The memory 109 can be used to store software programs and various data. The memory 109 can mainly include a program storage area and a data storage area, and the program storage area can store an operating system, application programs required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; and the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), and the like. In addition, the memory 109 can include a high-speed random access memory, and can also include a nonvolatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state memory device.

[0049] The processor 110 is the control center of the mobile terminal, connects all parts of the mobile terminal through various interfaces and lines, executes various functions of the mobile terminal and processes data by running or executing software programs and / or modules stored in the memory 109 and calling data stored in the memory 109, and thus monitors the mobile terminal as a whole. The processor 110 can include one or more processing units; preferably, the processor 110 can integrate an application processor and a modem processor, and the application processor can mainly process an operating system, a user interface, and application programs, and the like, and the modem processor can mainly process wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 110.

[0050] The mobile terminal 100 can also include a power supply 111 (such as a battery) for supplying power to various components; preferably, the power supply 111 can be logically connected to the processor 110 through a power management system, so as to realize the functions of managing charging, discharging, and power consumption management, and the like through the power management system.

[0051] Although Figure 2 The mobile terminal 100 can also include a Bluetooth module and the like, which are not described here.

[0052] In order to facilitate the understanding of the embodiments of the present application, the communication network system based on the mobile terminal of the present application is described below.

[0053] Please refer to Figure 2 , Figure 3 A communication network system architecture diagram provided by the embodiments of the present application, the communication network system is the LTE system of the general mobile communication technology, the LTE system includes the UE (User Equipment, user equipment) 201, E-UTRAN (Evolved UMTS Terrestrial Radio Access Network, evolved UMTS terrestrial radio access network) 202, EPC (Evolved Packet Core, evolved packet core network) 203 and operator's IP service 204 which are sequentially connected in communication.

[0054] Optionally, the UE 201 can be the terminal 100 described above, which will not be repeated here.

[0055] The E-UTRAN 202 includes eNode B 2021 and other eNode Bs 2022. Optionally, the eNode B 2021 can be connected with the other eNode Bs 2022 through backhaul (for example, X2 interface), the eNode B 2021 is connected to the EPC 203, and the eNode B 2021 can provide access for the UE 201 to the EPC 203.

[0056] The EPC 203 can include MME (Mobility Management Entity) 2031, HSS (Home Subscriber Server) 2032, other MMEs 2033, SGW (Serving GateWay) 2034, PGW (PDN Gate Way) 2035, and PCRF (Policy and Charging Rules Function) 2036. Optionally, the MME 2031 is a control node for processing signaling between the UE 201 and the EPC 203, and provides bearer and connection management. The HSS 2032 is used to provide some registers to manage functions such as a home location register (not shown in the figure), and to save some user-specific information about service features, data rates, etc. All user data can be transmitted through the SGW 2034, the PGW 2035 can provide IP address allocation for the UE 201 and other functions, and the PCRF 2036 is a policy and charging control policy decision point for service data flow and IP bearer resources, which selects and provides available policy and charging control decisions for policy and charging enforcement function units (not shown in the figure).

[0057] The IP service 204 can include the Internet, an intranet, an IMS (IP Multimedia Subsystem), or other IP services.

[0058] Although the above describes the LTE system as an example, those skilled in the art should know that the present application is not only applicable to the LTE system, but also applicable to other wireless communication systems, such as GSM, CDMA2000, WCDMA, TD-SCDMA, 5G, and future new network systems (such as 6G), etc., which are not limited here.

[0059] Based on the above mobile terminal hardware structure and communication network system, various embodiments of the present application are proposed.

[0060] First embodiment Reference Figure 3 , Figure 4 is a flowchart of the inverter synchronization method according to the first embodiment. The inverter synchronization method of the present embodiment can be applied to a first inverter and includes the following steps: S1: in response to a timer of the first inverter completing counting of a preset time period, sending a synchronization instruction to at least one second inverter and performing first synchronization processing; wherein the synchronization instruction is used to instruct the at least one second inverter to perform second synchronization processing, and the first synchronization processing and the second synchronization processing are used to synchronize the first inverter with the at least one second inverter.

[0061] Optionally, the first inverter is the core inverter (i.e. the master) that initiates the synchronization instruction. A timer inside the DSP (Digital Signal Processor) of the first inverter can be selected to count the preset time period, and is responsible for triggering the synchronization process and maintaining global timing consistency. Optionally, the second inverter is the slave inverter (i.e. the slave) that receives and responds to the synchronization instruction. The timer inside the DSP of the second inverter needs to be calibrated according to the preset time period of the first inverter, to ensure that the timing rhythm is consistent with that of the first inverter.

[0062] Optionally, when the timer of the first inverter completes counting of the preset time period, a synchronization signal is output through the IO interface of the DSP. All second inverters only receive the IO signal and do not need to send it back, and synchronization is achieved through the one-way interaction mode of “master sending and slave receiving”, simplifying the communication logic and hardware design. Here, the IO interface is the “channel” for transmitting signals between the first inverter and the second inverters, which can both receive external signals and send signals to the outside. Optionally, the first inverter outputs the synchronization signal through the IO interface as a digital level pulse signal.

[0063] Optionally, the inverter synchronization method proposed in the present application is applicable to a scenario where multiple DSP-based inverters work together. The core timing unit of each inverter directly reuses the hardware timer inside the DSP (such as Timer0 / Timer1 of TI C2000 series, TIM timer of STM32, etc.), without the need for additional external timing modules. The timer of the first inverter is taken as the event reference, and a synchronization instruction is broadcast to the slaves through the IO signal; the second inverter only needs to receive the signal through the IO interface of its own DSP and perform synchronization calibration.

[0064] Optionally, after the first inverter sends the synchronization instruction to the at least one second inverter, the timer count can be cleared or reloaded with the preset time period, to start the next round of period counting and maintain the continuity of the timing.

[0065] In this way, taking the timer of the first inverter as a unified reference, at least one second inverter is triggered to perform synchronization processing through a one-way synchronization instruction, which not only ensures accurate alignment of multiple inverters, avoids circulating current and uneven power, but also simplifies software and hardware design, reduces communication and hardware costs, and can adapt to multi-slave expansion scenarios.

[0066] Optionally, the preset timing period is configured according to the output frequency of the first inverter.

[0067] Optionally, the preset conversion relationship configuration can ensure that the synchronization instruction is consistent with the core working rhythm of the inverter, for example, it can be expressed as: period = 1 / frequency, so that the synchronization trigger rhythm matches the output waveform period of the inverter. In this way, when the output frequency of the first inverter is 50HZ, the corresponding preset timing period needs to be configured as a period of 20ms.

[0068] Optionally, the preset conversion relationship configuration can also be determined based on different use scenarios or user preferences, or in multiples.

[0069] Optionally, the first synchronization processing includes at least one of the following: timer synchronization compensation based on the preset timing period; drive counter synchronization compensation based on the preset drive count value; determining the output phase of the first inverter based on the preset timing period.

[0070] Optionally, by performing the first synchronization processing, the problems of "synchronization accuracy can only be tens of microseconds" and "it is difficult to synchronize the drive signal" in the prior art can be solved, the synchronization accuracy between the first inverter and at least one second inverter is improved, the inverter output waveform is strictly aligned in time, the phase synchronization between inverters is more accurate, the high-frequency circulating current caused by the carrier phase difference is eliminated, and the system loss and electromagnetic interference are greatly reduced.

[0071] Optionally, after sending the synchronization instruction to at least one second inverter, the first synchronization processing is performed, which can ensure that the first inverter and at least one second inverter perform compensation operations synchronously under the same time reference, thereby avoiding new deviations caused by asynchronous compensation opportunities, and significantly improving the synchronization accuracy and stability between the first inverter and at least one second inverter.

[0072] Optionally, the timer synchronization compensation based on the preset timing period includes: assigning the preset timing period to the current count value of the timer, determining a first count compensation value according to the current count value of the timer and the preset timing period, and compensating the timer according to the first count compensation value.

[0073] Optionally, the determined preset time period is directly assigned to the current count value of the timer. In this way, according to the difference between the current count value and the preset time period, the first count compensation value is determined, which can be specifically expressed by the formula: first count compensation value = preset time period - current count value. It can be understood that, for the first inverter, after the preset time period is assigned to the current count value of the timer, the preset time period is consistent with the current count value, and the first count compensation value corresponding to the calculation thereof should be equal to 0.

[0074] Optionally, when the timer is corrected according to the first count compensation value, the count deviation can be corrected in real time, and it is ensured that the timing rhythm of the master and the slave is completely aligned. For example, the first count compensation value (Err_timer) is compensated into the drive counter register, which can be expressed as: CpuTimer0Regs.TIM.all += Err_timer, that is, the first count compensation value (Err_timer) is superimposed into the count value full register (CpuTimer0Regs.TIM.all) of the CPU timer, the timer count is calibrated, and the synchronization of the timers between the first inverter and the second inverter is achieved. It can be understood that, for the first inverter, when the first count compensation value should be equal to 0, the compensation of the timer based on the first count compensation value is actually to maintain the current timer synchronization state, to confirm that the timing rhythm between the first inverter and at least one second inverter has been aligned, and adjustment is not required.

[0075] Optionally, by actively compensating the timer count deviation of the first inverter, the timing error is controlled, the synchronous period drift caused by the temperature drift of the crystal oscillator and electromagnetic interference is avoided, and it is ensured that the first inverter always provides a stable and consistent time reference for the second inverter.

[0076] Optionally, the drive counter synchronization compensation based on the preset drive count value comprises: According to the current drive count value of the drive counter of the first inverter and the preset drive count value, a second count compensation value is determined, and the drive counter of the first inverter is compensated according to the second count compensation value.

[0077] Optionally, the preset drive count value can be set based on user requirements, and can generally be set to 0 to unify the "phase starting point" of the drive counter of the first inverter (such as the 0 phase moment of the pulse width modulation carrier (PWM)), avoiding phase offset of the drive signal caused by deviation of the count starting point. Optionally, by calculating the actual deviation of the current drive count value of the drive counter of the first inverter from the preset drive count value, a second count compensation value is determined, and the drive counter of the first inverter is accurately calibrated based on the second count compensation value, ensuring that the drive signal timing is compliant, the carrier of the first inverter and the second inverter is synchronized, the timing of the drive signal (PWM wave) of the power switch (such as IGBT) of the first inverter is consistent with the preset standard, and the phase offset of the drive signal does not affect the output power quality.

[0078] Specifically, the calculation method of the second count compensation value can be represented by a formula: second count compensation value (Err_pwm) = preset drive count value (0) - current drive count value (PWM_TBCTR). Optionally, the drive counter of the first inverter is compensated by the second count compensation value, so that the drive counter of the first inverter strictly adheres to the preset drive count value, and the output moment, duty cycle, and phase of the IGBT drive signal (PWM wave) generated by the drive counter of the first inverter are completely consistent with the preset standard. Specifically, the compensation of the drive counter of the first inverter by the second count compensation value can be specifically represented by a formula: EPwm1Regs.TBCTR += Err_pwm. Wherein, EPwm1Regs.TBCTR represents the drive counter of the first inverter, and Err_pwm represents the second count compensation value. In this way, the drive counter of the first inverter is compensated by the second count compensation value, solving the problem of carrier asynchronization between the first inverter and the second inverter caused by clock deviation, hardware delay, load disturbance, etc., reducing the superposition of switching noise during multi-machine parallel operation, and reducing the risk of electromagnetic interference.

[0079] Optionally, the output phase of the first inverter is determined based on the preset timing period, including: The first angle step value is determined based on the preset timing period, and the output phase of the first inverter is determined based on the preset timing period and the first angle step value.

[0080] Optionally, the first angle step value refers to a fixed radian value of the electrical angle of the output voltage of the first inverter increasing / decreasing after a preset timing period. The output phase of the first inverter refers to the real-time electrical angle phase of the output voltage of the first inverter, which directly determines the waveform phase state of the output voltage.

[0081] Optionally, the first angle step value determined according to the preset time period can be expressed by a formula as: Wt_Step = 2π / T_period. Wherein, Wt_Step represents the first angle step value; T_period represents the preset time period.

[0082] Optionally, the output phase of the first inverter determined according to the preset time period and the first angle step value can be expressed by a formula as: Wt = Wt_Step * T_period. Wherein, Wt represents the output phase of the first inverter; Wt_Step represents the first angle step value; T_period represents the preset time period. In this way, the time count of the timer is bound with the angle of the inverter output voltage, and the precise control of the output phase is realized.

[0083] Optionally, the actual output phase of the first inverter can be expressed as: Vref = V_Set * sin(Wt), wherein Vref represents the actual output phase of the first inverter; V_Set represents the target voltage value set by the user. In this way, the output phase is precisely calculated by fixing the angle step value, the output phase of the first inverter is ensured to be stable and predictable, the second inverter can directly realize errorless following based on the phase reference, and the circulating current caused by the phase difference during parallel connection of multiple inverters is completely avoided.

[0084] In summary, the inverter synchronization method provided by the above embodiment realizes the synchronization of the inverter trigger synchronization processing based on the timer of the first inverter, so that at least one second inverter accurately enters the synchronization process, and the precision and efficiency of the synchronization between the first inverter and the at least one second inverter are improved. Here, taking the first inverter as a reference, the master-slave machine efficient synchronization is realized through one-way IO synchronization instruction trigger, combined with timer, drive counter compensation and output phase precise calculation. Both the circulating current and electromagnetic interference caused by crystal oscillator temperature drift and phase deviation are avoided, and the power quality is ensured, and the hardware and software design is simplified, and the cost is reduced.

[0085] Second embodiment Referring to Figure 4 , Figure 5 is a flowchart of the inverter synchronization method according to the first embodiment, and the inverter synchronization method of the embodiment of the application can be applied to the second inverter, including the steps of: S2, in response to receiving the synchronization instruction, performing the second synchronization processing; wherein the synchronization instruction is sent by the first inverter after the timer of the first inverter completes the count of the preset time period, and the second synchronization processing is used to realize the synchronization between the at least one second inverter and the first inverter.

[0086] Optionally, the second inverter takes the synchronization instruction sent by the first inverter as a trigger signal, and through performing the second synchronization processing, quickly aligns the timing, driving and output parameters of itself with the host reference, and finally realizes the accurate synchronization of the master-slave inverters, and guarantees the stability of the multi-machine parallel operation.

[0087] Optionally, the second synchronization processing includes at least one of the following: The timer synchronization compensation is performed based on a preset timing period, and the preset timing period is configured according to the output frequency of the first inverter. The driving counter synchronization compensation is performed based on a preset driving count value. The output phase of the second inverter is determined based on the preset timing period.

[0088] Optionally, after the second inverter receives the synchronization instruction of the first inverter, the current count value of the timer of the second inverter is read, and the timer synchronization compensation is performed based on the deviation of the current count value from the preset timing period, so that the timer of the second inverter is strictly aligned with the reference of the first inverter, avoiding the circulating current caused by the timing drift and the frequency difference, and guaranteeing the consistency of the multi-machine output.

[0089] Optionally, by performing the second synchronization operation, the single synchronization IO signal is used to simplify the software and hardware design, the timer and the driving signal are accurately synchronized, the circulating current phenomenon is significantly inhibited, the power consumption and heat are reduced, and at the same time, the synchronization accuracy between the first inverter and the at least one second inverter is improved, and the active power and the reactive power are evenly divided.

[0090] Optionally, after receiving the synchronization instruction sent by the first inverter, the second synchronization operation is immediately performed, which can ensure that the first inverter and the at least one second inverter perform the compensation operation synchronously under the same time reference, thereby avoiding the new deviation caused by the asynchronization of the compensation time, and significantly improving the synchronization accuracy and stability between the first inverter and the at least one second inverter.

[0091] Optionally, the timer synchronization compensation based on the preset timing period includes: According to the current count value of the timer of the second inverter and the preset timing period, a third count compensation value is determined, and the timer of the second inverter is compensated according to the third count compensation value.

[0092] Optionally, the preset time period should be consistent with the preset time period of the first inverter. Optionally, after the second inverter receives the synchronization instruction sent by the first inverter through the IO interface, the current count value of the timer of the second inverter is immediately read. The deviation, i.e. the third count compensation value, is calculated with the preset time period as the target reference. The calculation formula can be expressed as: third count compensation value (Err_timer_Slave) = preset time period (T_period) - current count value of the timer of the second inverter (Timer_Curr). For example, when the host period is 20ms and the current count of the slave is 18ms, the compensation value is calculated as 20ms-18ms=2ms, which is used to compensate for the deviation of the timer of the second inverter.

[0093] Optionally, the third count compensation value is directly superimposed into the current count value register of the timer, and the count deviation is corrected in real time to ensure that the timing rhythm of the master and the slave timers is completely aligned. For example, the third count compensation value (code represented as Err_timer) is compensated into the drive counter register, which can be expressed as: CpuTimer0Regs.TIM.all +=Err_timer, i.e. the third count compensation value (Err_timer) is superimposed into the count value full register (CpuTimer0Regs.TIM.all) of the CPU timer, which realizes the count calibration of the timer and achieves synchronization alignment with the timer of the first inverter.

[0094] Optionally, the drive counter synchronization compensation based on the preset drive count value includes: According to the current drive count value of the drive counter of the second inverter and the preset drive count value, a fourth count compensation value is determined, and the drive counter of the second inverter is compensated according to the fourth count compensation value.

[0095] Optionally, the preset drive count value can be set based on user requirements, and can generally be set to 0 to avoid phase shift of the drive signal due to deviation of the count starting point. Optionally, by calculating the actual deviation of the current drive count value of the drive counter of the second inverter from the preset drive count value, a fourth count compensation value is determined, and the drive counter of the first inverter is accurately calibrated based on the fourth count compensation value, ensuring that the drive signal timing is compliant and synchronized with the first inverter carrier, ensuring that the timing of the drive signal (PWM wave) of the power switch (such as IGBT) of the second inverter is consistent with the preset standard, avoiding the influence of phase shift of the drive signal on the output power quality. Specifically, the calculation method of the fourth count compensation value can be represented by the formula: fourth count compensation value (Err_pwm) = preset drive count value (0) - current drive count value (PWM_TBCTR). Optionally, the drive counter of the second inverter is compensated by the fourth count compensation value, so that the drive counter of the second inverter strictly adheres to the preset drive count value, and the output time, duty cycle, and phase of the IGBT drive signal generated by the drive counter are completely consistent with the preset standard. Specifically, the compensation of the drive counter of the second inverter by the fourth count compensation value can be specifically represented by the formula: EPwm1Regs.TBCTR += Err_pwm. Wherein, EPwm1Regs.TBCTR represents the drive counter of the second inverter, and Err_pwm represents the fourth count compensation value.

[0096] Optionally, the output phase of the second inverter is determined based on the preset timing period, including: The second angle step value is determined based on the preset timing period and the second angle step value, and the output phase of the second inverter is determined based on the preset timing period and the second angle step value.

[0097] Optionally, the second angle step value refers to a fixed radian value of the electrical angle of the output voltage of the second inverter increasing / decreasing after a preset timing period. The output phase of the second inverter refers to the real-time electrical angle phase of the output voltage of the second inverter, which directly determines the waveform phase state of the output voltage.

[0098] Optionally, the second angle step value can be represented by the formula: Wt_Step = 2π / T_period. Wherein, Wt_Step represents the second angle step value; T_period represents the preset timing period.

[0099] Optionally, the output phase of the second inverter determined according to the preset time period and the second angle step value can be expressed by a formula as follows: Wt = Wt_Step * T_period. Wherein, Wt represents the output phase of the second inverter; Wt_Step represents the second angle step value; and T_period represents the preset time period. In this way, the time count of the timer is bound to the electrical angle of the inverter output voltage, and accurate control of the output phase is achieved.

[0100] Optionally, the actual output phase of the second inverter can be expressed as: Vref = V_Set * sin(Wt), wherein Vref represents the actual output phase of the second inverter; and V_Set represents the target voltage value set by the user. In this way, the output phase is accurately calculated by fixing the angle step value, the output phase of the second inverter is stable and predictable, the second inverter can directly realize errorless following based on the phase reference, and circulating current caused by phase difference during parallel connection of multiple machines is completely avoided.

[0101] In summary, the inverter synchronization method provided in the above embodiment enables at least one second inverter to accurately enter the synchronization process, and improves the accuracy and efficiency of synchronization between the first inverter and the at least one second inverter. Here, taking the second inverter as a reference, after the second inverter receives the master synchronization instruction, the master reference is quickly aligned through the timer, the drive counter compensation and the accurate calculation of the output phase.

[0102] Third embodiment Reference Figure 5 , Figure 6 is a flowchart of the inverter synchronization method according to the first embodiment, and the inverter synchronization method of the embodiment of the application comprises the following steps: S3, the first inverter sends a synchronization instruction to the at least one second inverter after the timer completes the count of the preset time period, and performs the first synchronization processing.

[0103] Optionally, the timer of the first inverter continuously counts according to the preset time period, and when the count reaches a preset threshold, a "timer overflow interrupt" is triggered, indicating that a synchronization period ends, and a synchronization process is immediately started to send a synchronization instruction to the at least one second inverter. Optionally, in the interrupt service function, the first inverter outputs a preset synchronization instruction through the GPIO pin of the DSP, and the instruction is sent to all connected second inverters through a shielding transmission line as a synchronization trigger signal. Optionally, the instruction sending of the first inverter is strictly synchronized with the timer overflow, so as to ensure that the instruction is sent only once in each synchronization period, and repeated triggering of the slave machine is avoided.

[0104] Optionally, the first synchronization processing comprises at least one of the following: timer synchronization compensation based on a preset timing period; drive counter synchronization compensation based on a preset drive counter value; and determination of an output phase of the first inverter based on the preset timing period.

[0105] S4, after receiving the synchronization instruction, the at least one second inverter performs second synchronization processing; wherein the first synchronization processing and the second synchronization processing are used to synchronize the first inverter and the at least one second inverter.

[0106] Optionally, after receiving the synchronization instruction, the at least one second inverter performs second synchronization processing, and the second synchronization processing comprises at least one of the following: timer synchronization compensation based on a preset timing period, the preset timing period being configured according to an output frequency of the first inverter; drive counter synchronization compensation based on a preset drive counter value; and determination of an output phase of the second inverter based on the preset timing period.

[0107] Referring to Figure 7 A specific processing flow of a synchronization method of an inverter is provided, and the first synchronization processing performed by the first inverter and the second synchronization processing performed by the second inverter are specifically disclosed, comprising the steps of: S201, configuring a preset timing period; determining a first angle step value; and synchronizing IO configuration.

[0108] Optionally, the preset timing period is a basic time unit of the entire timing control mechanism, and determines the frequency of timing operation. The preset timing period can be configured according to the output frequency of the first inverter. The IO configuration refers to the configuration of the input / output port. The synchronized IO configuration refers to the unified setting and coordination of the input / output ports between various devices or modules in the system, so as to ensure accurate and orderly transmission of data between different devices.

[0109] S202, timing interrupt triggering.

[0110] Optionally, the timing interrupt is triggered when the timer of the first inverter completes preset timing period counting. As shown in FIG. 2, the interrupt is triggered at time a, and step S203 is performed at this time. Figure 8

[0111] S203, synchronization of the first inverter IO signal.

[0112] Optionally, the first inverter needs to keep synchronization with the IO signal of the at least one second inverter, so as to ensure that the input / output operation is consistent with other devices.

[0113] S204, synchronization IO interrupt triggering.

[0114] ​Step S205, the first inverter assigns the preset time period to the current count value of the timer; the second inverter acquires the current count value of the timer.

[0115] Optionally, the first inverter can directly write the determined preset time period into the "current count value register" of the timer, and the second inverter reads the current count value of its own timer after receiving the synchronization instruction of the first inverter.

[0116] Step S206, determining the compensation value for the timer.

[0117] Optionally, the compensation value for the timer includes the first count compensation value corresponding to the first inverter and the third count compensation value corresponding to the second inverter.

[0118] Optionally, the current count value of the timer is assigned to the preset time period, and the first count compensation value is determined according to the current count value of the timer and the preset time period. The determined preset time period is directly written into the "current count value register" of the timer. In this way, the first count compensation value is determined according to the difference between the current count value and the preset time period, which can be specifically expressed by the formula: first count compensation value = preset time period - current count value.

[0119] Optionally, the third count compensation value is determined according to the current count value of the timer of the second inverter and the preset time period. The preset time period should be consistent with the preset time period of the first inverter. Optionally, the second inverter reads the current count value of its own timer immediately after receiving the synchronization instruction sent by the first inverter through the IO interface. The deviation, i.e. the third count compensation value, is calculated with the preset time period as the target reference, and the calculation formula can be expressed as: third count compensation value (Err_timer_Slave) = preset time period (T_period) - current count value of the timer of the second inverter (Timer_Curr).

[0120] Step S207, determining the compensation value for the drive counter.

[0121] Optionally, the compensation value for the drive counter includes the second count compensation value corresponding to the first inverter and the fourth count compensation value corresponding to the second inverter.

[0122] Optionally, the second count compensation value is determined according to the current drive count value of the drive counter of the second inverter and a preset drive count value. The preset drive count value can be set based on user demand, and can be generally set to 0, so as to avoid phase offset of the drive signal caused by the deviation of the count start point. Optionally, the second count compensation value is determined by calculating the actual deviation of the current drive count value of the drive counter of the second inverter from the preset drive count value.

[0123] Optionally, the fourth count compensation value is determined according to the current drive count value of the drive counter of the second inverter and a preset drive count value. The preset drive count value can be set based on user demand, and can be generally set to 0, so as to avoid phase offset of the drive signal caused by the deviation of the count start point. Optionally, the fourth count compensation value is determined by calculating the actual deviation of the current drive count value of the drive counter of the second inverter from the preset drive count value.

[0124] In step S208, the timers of the first inverter and the second inverter are compensated, the drive counters of the first inverter and the second inverter are compensated, and the output phases of the first inverter and the second inverter are determined.

[0125] Optionally, the timer of the first inverter is compensated according to the first count compensation value. The timer of the second inverter is compensated according to the third count compensation value.

[0126] Optionally, the drive counter of the first inverter is compensated according to the second count compensation value. The drive counter of the second inverter is compensated according to the fourth count compensation value.

[0127] Optionally, the first angle step value is determined according to the preset timing period, the output phase of the first inverter is determined according to the preset timing period and the first angle step value, the second angle step value is determined according to the preset timing period, and the output phase of the second inverter is determined according to the preset timing period and the second angle step value.

[0128] Optionally, when the first inverter performs the first synchronization processing and the second inverter performs the second synchronization processing, the specific synchronization processing process can refer to the first and second embodiments. That is, the first and second embodiments have detailed descriptions of similar synchronization processing, and the specific operations, logics and the like related to the synchronization processing of the inverter in this process can be referred to for clear processing details and flow.

[0129] Optionally, the first synchronization processing is performed by the first inverter, and the second synchronization processing is performed by the second inverter, which can effectively improve the parallel connection situation. As can be seen from the simulation diagram of FIG. 8, the yellow curve represents the voltage, the blue curve represents the total current, the red curve represents the first inverter current, and the green curve represents the second inverter current. Figure 8 As can be seen from the simulation diagram of FIG. 8, the yellow curve represents the voltage, the blue curve represents the total current, the red curve represents the first inverter current, and the green curve represents the second inverter current. Figure 9 As can be seen from the simulation diagram of FIG. 8, the yellow curve represents the voltage, the blue curve represents the total current, the red curve represents the first inverter current, and the green curve represents the second inverter current.

[0130] Optionally, the first synchronization processing is performed by the first inverter, and the second synchronization processing is performed by the second inverter, which can optimize the active and reactive power sharing of the inverters. As can be seen from the simulation diagram of FIG. 9, the yellow curve represents the active power of the first inverter, the blue curve represents the reactive power of the first inverter, the red curve represents the active power of the second inverter, and the green curve represents the reactive power of the second inverter. Figure 9 As can be seen from the simulation diagram of FIG. 9, the yellow curve represents the active power of the first inverter, the blue curve represents the reactive power of the first inverter, the red curve represents the active power of the second inverter, and the green curve represents the reactive power of the second inverter. Figure 9 As can be seen from the simulation diagram of FIG. 9, the yellow curve represents the active power of the first inverter, the blue curve represents the reactive power of the first inverter, the red curve represents the active power of the second inverter, and the green curve represents the reactive power of the second inverter. ​ As can be seen from the simulation diagram of FIG. 9, the yellow curve represents the active power of the first inverter, the blue curve represents the reactive power of the first inverter, the red curve represents the active power of the second inverter, and the green curve represents the reactive power of the second inverter.

[0131] Meanwhile, in an actual application scenario, when the main frequency of the main control chip is set to 120MHz, the switching frequency of the inverter is 20kHz, and the output frequency of the inverter is 50Hz, the synchronization precision of the synchronization scheme proposed in the present application can be calculated as 50Hz / 120MHz = 416ns; while the synchronization precision of the traditional synchronization scheme based on the number of switching frequencies is only 1 / 20kHz = 50μs. As can be seen from the data comparison, the synchronization precision of the inverter synchronization method of the present application is significantly improved compared with the traditional scheme.

[0132] The embodiment of the present application also provides an inverter, which comprises a memory and a processor, and the memory stores a processing program which, when executed by the processor, implements the steps of the inverter synchronization method in any of the above embodiments.

[0133] The embodiment of the present application further provides a storage medium, and the storage medium stores a processing program. The processing program is executed by a processor to implement the steps of the inverter synchronization method in any of the above embodiments.

[0134] In the embodiments of the inverter and the storage medium provided in the present application, all the technical features of any of the above inverter synchronization method embodiments can be included, and the description and explanation content is basically the same as that of the above method embodiments, which will not be repeated here.

[0135] The embodiment of the present application further provides a computer program product, which comprises computer program code, and when the computer program code is run on a computer, the computer is caused to execute the method in various possible embodiments as above.

[0136] The embodiment of the present application further provides a chip, which comprises a memory and a processor. The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the device installed with the chip executes the method in various possible embodiments as above.

[0137] It can be understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of the present application. The technical solutions provided in the embodiments of the present application are also applicable to other scenarios. For example, those skilled in the art can know that, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0138] The above sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0139] The steps in the method of the embodiments of the present application can be adjusted in sequence, combined and reduced according to actual needs.

[0140] The units in the device of the embodiments of the present application can be combined, divided and reduced according to actual needs.

[0141] In the present application, for the same or similar term concept, technical solution and / or application scenario description, generally only the first time is described in detail, and for the sake of brevity, the repeated description is generally not repeated. When understanding the technical solutions and the like of the present application, the same or similar term concept, technical solution and / or application scenario description and the like which are not described in detail can be referred to the relevant description before.

[0142] In the present application, the description of each embodiment has its own emphasis, and the part not described or recorded in a certain embodiment can be referred to the relevant description of other embodiments.

[0143] The technical features of the technical solutions of the present application can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered as falling within the scope of the present application.

[0144] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and a necessary general hardware platform, and of course, can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk) as described above, and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, a controlled terminal, or a network device) to execute the method of each embodiment of the present application.

[0145] In the above-described embodiments, all or part can be realized by software, hardware, firmware, or any combination thereof. When realized by software, all or part can be realized in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a storage medium or transferred from one storage medium to another, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) mode. The storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be a magnetic medium (such as a floppy disk, a storage disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state storage disk (SSD)), etc.

[0146] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included within the patent protection scope of the present application.

Claims

1. An inverter synchronization method, characterized in that, Applied to the first inverter, including: In response to the timer of the first inverter completing the counting of the preset timing period, a synchronization command is sent to at least one second inverter, and the first synchronization process is executed; The synchronization instruction is used to instruct the at least one second inverter to perform a second synchronization process, and the first synchronization process and the second synchronization process are used to synchronize the first inverter with the at least one second inverter.

2. The method according to claim 1, characterized in that, The preset timing period is configured according to the output frequency of the first inverter.

3. The method according to claim 1, characterized in that, The first synchronization process includes at least one of the following: Timer synchronization compensation is performed based on the preset timing period; Drive counter synchronization compensation is performed based on preset drive count values; The output phase of the first inverter is determined based on the preset timing period.

4. The method according to claim 3, characterized in that, The timer synchronization compensation based on the preset timing period includes: The preset timing period is assigned to the current count value of the timer. Based on the current count value of the timer and the preset timing period, a first count compensation value is determined, and the timer is compensated based on the first count compensation value. And / or, the drive counter synchronization compensation based on a preset drive count value includes: Based on the current drive count value of the drive counter of the first inverter and the preset drive count value, a second count compensation value is determined, and the drive counter of the first inverter is compensated according to the second count compensation value. And / or, determining the output phase of the first inverter based on the preset timing period includes: The first angle step value is determined according to the preset timing period, and the output phase of the first inverter is determined according to the preset timing period and the first angle step value.

5. An inverter synchronization method, characterized in that, Applied to the second inverter, including: Upon receiving a synchronization command, a second synchronization process is executed; The synchronization command is sent by the first inverter after its timer completes a preset timing period count, and the second synchronization process is used to enable synchronization between the at least one second inverter and the first inverter.

6. The method according to claim 5, characterized in that, The second synchronization process includes at least one of the following: Timer synchronization compensation is performed based on a preset timing period, which is configured according to the output frequency of the first inverter. Drive counter synchronization compensation is performed based on preset drive count values; The output phase of the second inverter is determined based on the preset timing period.

7. The method according to claim 6, characterized in that, The timer synchronization compensation based on the preset timing period includes: Based on the current count value of the timer of the second inverter and the preset timing period, a third count compensation value is determined, and the timer of the second inverter is compensated according to the third count compensation value; And / or, the drive counter synchronization compensation based on a preset drive count value includes: Based on the current drive count value of the drive counter of the second inverter and the preset drive count value, a fourth count compensation value is determined, and the drive counter of the second inverter is compensated according to the fourth count compensation value. And / or, determining the output phase of the second inverter based on the preset timing period includes: The second angle step value is determined according to the preset timing period, and the output phase of the second inverter is determined according to the preset timing period and the second angle step value.

8. An inverter synchronization method, characterized in that, include: After the timer completes the counting of the preset timing period, the first inverter sends a synchronization command to at least one second inverter and performs the first synchronization process. Upon receiving the synchronization command, the at least one second inverter performs a second synchronization process; The first synchronization process and the second synchronization process are used to synchronize the first inverter with the at least one second inverter.

9. An inverter, characterized in that, It includes a memory and a processor, wherein the memory stores a processing program, and when the processing program is executed by the processor, it implements the steps of the inverter synchronization method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the steps of the inverter synchronization method as described in any one of claims 1 to 7.

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