Driving circuit and method applied to flyback self-power supply

Abstract

The invention discloses a driving circuit and method applied to flyback self-power supply. The drive circuit comprises a power switch tube Q1, the drain electrode of which is connected with the source electrode of a primary side high-voltage tube GaN, and the source electrode of which is grounded; the input end of the power supply generation module is connected with the source electrode of the primary side high-voltage tube GaN, and the output end of the power supply generation module outputs an internal power supply VCC; the control module is used for outputting a control signal SW; the delay module is used for generating a first delay signal SW1 and a second delay signal SW2 according to the control signal SW; the first driving module is used for being switched on when receiving a first delay signal SW1, so that the source electrode of the primary side high-voltage tube GaN provides charging current for the grid electrode of the power switch tube Q1; the input end of the second driving module is connected with the power supply generation module, the output end of the second driving module is connected with the grid electrode of the power switch tube Q1, and the second driving module is used for being switched on when receiving the second delay signal SW2, so that the internal power supply VCC provides charging current for the grid electrode of the power switch tube Q1.

Description

Technical Field

[0001] This invention relates to the field of power supply drive technology, and more specifically to a drive circuit and method for flyback self-powered circuits. Background Technology

[0002] Flyback switching power supplies typically employ self-powered technology to provide operating power to the control chip, enabling system startup and stable operation. Existing self-powered solutions often draw power from the source node of the primary-side high-voltage transistor, harvesting energy through voltage changes at this node. However, during the conduction of the primary-side power switch, the potential of this node is pulled down to a low level, unable to continuously power the control chip. Therefore, such self-powered solutions are usually designed as switching structures, drawing power only during specific phases of the switching cycle and relying on energy storage capacitors to maintain normal power supply to the control chip. Although this type of self-powered circuit can achieve a certain voltage regulation effect by adjusting the capacitance of the energy storage capacitor, its load-carrying capacity is limited, and its adaptability to dynamic loads is poor. Especially when there is a large transient current demand within the control chip, i.e., at the instant the switch is turned on, the self-powered power supply voltage fluctuates significantly, affecting the system's operational stability.

[0003] Furthermore, during the driving process of the power transistor in a flyback circuit, the gate drive current of the power switch is large and varies periodically at the moment of conduction. If this current is directly provided by the self-powered circuit, it will further aggravate the losses of the self-powered power supply and reduce its voltage stability. Therefore, it is evident that the stability of the self-powered circuit in dealing with load current jumps is difficult to guarantee, and it cannot continuously meet the power supply requirements of the control chip. Thus, how to balance the driving performance of the power switch and the stability of the self-powered power supply in a flyback self-powered drive system is a key technical problem that needs to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a drive circuit and method for flyback self-powered circuits, so as to reasonably allocate the drive current source during the turn-on process of the power switch, thereby reducing the load pressure of the self-powered power supply, improving the stability of the internal power supply voltage, and thus improving the overall reliability of the drive system.

[0005] To achieve the above objectives, the present invention discloses the following technical solution: A first aspect of the present invention provides a drive circuit for a flyback self-powered circuit, comprising: The drain of the power switch Q1 is connected to the source of the GaN high-voltage transistor on the primary side of the transformer, and the source of the power switch Q1 is grounded. The power generation module has its input terminal connected to the source of the primary high-voltage transistor GaN, and its output terminal outputs the internal power supply VCC. The control module is used to output control signals SW; A delay module, connected to the control module, is used to generate a first delay signal SW1 and a second delay signal SW2 based on the control signal SW; The first driving module has its input terminal connected to the source of the primary-side high-voltage transistor GaN and its output terminal connected to the gate of the power switch Q1. It is used to turn on when the first delay signal SW1 is received, so that the source of the primary-side high-voltage transistor GaN provides charging current to the power switch Q1. The second driving module has its input terminal connected to the power generation module and its output terminal connected to the gate of the power switch Q1. It is used to turn on when the second delay signal SW2 is received, so that the internal power supply VCC provides charging current to the power switch Q1.

[0006] Optionally, when the control signal SW rises, the first delay signal SW1 rises synchronously with the control signal SW, and after a preset time Tdly, the first delay signal SW1 falls. When the first delay signal SW1 decreases, the second delay signal SW2 increases, and when the control signal SW decreases, the second delay signal SW2 decreases synchronously.

[0007] Optionally, the first driving module includes a first switch K1 and a first diode D1; The first terminal of the first switch K1 is connected to the cathode of the first diode D1, the second terminal of the first switch K1 is connected to the gate of the power switch Q1, and the control terminal of the first switch K1 is connected to the delay module for receiving the first delay signal SW1. The anode of the first diode D1 is connected to the source of the primary high-voltage transistor GaN.

[0008] Optionally, the first driving module further includes: The clamping diode Dz has its cathode connected to the second terminal of the first switch K1, and its anode grounded.

[0009] Optionally, the second drive module includes: The second switch K2 has its first end connected to the power generation module and its second end connected to the gate of the power switch Q1. The control terminal of the second switch K2 is connected to the delay module to receive the second delay signal SW2.

[0010] Optionally, the driving circuit further includes: The first resistor R1 has its first end connected to the source of the power switch Q1, and its second end grounded.

[0011] Optionally, the delay module includes a first inverter INV1, a second inverter INV2, a reference current source Iref, a first switch M1, a second switch M2, a delay capacitor Cdly, a Schmitt trigger smt, and a first AND gate A1; The input terminal of the first inverter INV1 is connected to the control signal SW, and the output terminal is connected to the gates of both the first switch M1 and the second switch M2. One end of the reference current source Iref is connected to the internal power supply VCC, and the other end is grounded through the first switch M1 and the second switch M2 in sequence. The first terminal of the delay capacitor Cdly is connected between the first switch M1 and the second switch M2, and the second terminal of the delay capacitor Cdly is grounded. The input terminal of the Schmitt trigger smt is connected to the first terminal of the delay capacitor Cdly, and the output terminal of the Schmitt trigger smt is connected to the first input terminal of the first AND gate A1; The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, the output terminal of the second inverter INV2 is connected to the second input terminal of the first AND gate A1, and the output terminal of the first AND gate A1 outputs the first delay signal SW1.

[0012] Optionally, the delay module further includes a third inverter INV3 and a second AND gate A2; The input terminal of the third inverter INV3 is connected to the output terminal of the first AND gate A1, and the output terminal of the third inverter INV3 is connected to the first input terminal of the second AND gate A2; The second input terminal of the second AND gate A2 is connected to the output terminal of the second inverter INV2, and the output terminal of the second AND gate A2 outputs the second delay signal SW2.

[0013] Optionally, the formula for the preset time Tdly is: ; Among them, V th_smt The toggling threshold of the Schmitt trigger (SMT) is given.

[0014] Secondly, the present invention provides a driving method for flyback self-powered circuits, comprising the following steps: Acquire control signal SW, and generate first delay signal SW1 and second delay signal SW2 based on control signal SW; When the control signal rises, the first delay signal SW1 rises synchronously with the control signal SW, so that the source of the primary high voltage tube GaN provides charging current to the power switch Q1. After a preset time Tdly, the first delay signal SW1 decreases and the second delay signal SW2 increases, causing the source of the primary high-voltage transistor GaN to stop providing charging current to the power switch Q1, and causing the internal power supply VCC to provide charging current to the power switch Q1.

[0015] The effects described in the invention are merely those of the embodiments, and not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects: The drive circuit for flyback self-powered systems provided in this application divides the power switch's turn-on process into two stages by setting up a power generation module, a delay module, and separately controlled first and second drive modules. In the initial turn-on stage, the source of the GaN high-voltage transistor on the primary side of the transformer provides the charging current. After a preset delay time, the internal power supply voltage output by the power generation module continues to charge the gate of the power switch. This segmented drive method effectively disperses the sources of drive current, reduces the transient load pressure on the internal power supply, significantly improves the stability of the self-powered power supply voltage, and thus improves the operational reliability of the flyback self-powered system during dynamic drive processes.

[0016] Furthermore, by setting a clamping diode Dz in the first driving module, the rise of the gate voltage of the power switch Q1 can be limited, preventing overvoltage from damaging the power switch Q1 and improving circuit stability.

[0017] Furthermore, the timing control of the two-stage drive phase is achieved through two delay signals generated by the delay module, enabling the first and second drive modules to conduct sequentially at different stages, thus achieving smooth current switching and avoiding jumps and oscillations in the gate voltage of the power switch. Specifically, the delay module, through the cooperation of an inverter, AND gate, Schmitt trigger, and delay capacitor, achieves controllable and precise delay adjustment. Its delay time is determined by the capacitor, current source, and Schmitt trigger threshold, facilitating design and debugging. This structure ensures the timing stability and consistency of the delay signal, enabling the drive circuit to maintain a reliable turn-on timing under different operating conditions. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the principles of this application.

[0019] Figure 1 A circuit topology diagram of a flyback self-powered drive circuit according to an embodiment of the present invention is shown; Figure 2 An embodiment of the present invention is shown. Figure 1 The waveforms of each signal in the driving circuit shown are shown. Figure 3 A circuit topology diagram of a delay module according to an embodiment of the present invention is shown; Figure 4 The diagram shows the waveforms of the control signal SW, the delay capacitor voltage Vdly, the first delay signal SW1, and the second delay signal SW2 according to an embodiment of the present invention. Figure 5 A schematic flowchart of a drive method for a flyback self-powered system according to an embodiment of the present invention is shown. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics; however, not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0022] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0023] Figure 1 A circuit topology diagram of a flyback self-powered drive circuit 100 according to an embodiment of the present invention is shown. Figure 1As shown, the drive circuit 100 applied to a flyback self-powered circuit includes a power switch Q1, a power generation module 110, a control module 120, a delay module 130, a first drive module 140, and a second drive module 150. The drain of the power switch Q1 is connected to the source of the primary high-voltage transistor GaN in the transformer 200, and the source of the power switch Q1 is grounded. The input terminal of the power generation module 110 is connected to the source of the primary high-voltage transistor GaN, and the output terminal outputs the internal power supply VCC. The control module 120 is used to output a control signal SW. The delay module 130 is connected to the control module 120 and is used to generate a first delay signal SW1 and a second delay signal SW2 according to the control signal SW, which are respectively connected to the first drive module 140 and the second drive module 150. The input terminal of the first driving module 140 is connected to the source of the primary-side high-voltage transistor GaN, and the output terminal is connected to the gate of the power switch Q1. It is turned on when the first delay signal SW1 is valid, allowing the source of the primary-side high-voltage transistor GaN to provide charging current to the gate of the power switch Q1. The input terminal of the second driving module 150 is connected to the power generation module 110, and the output terminal is connected to the gate of the power switch Q1. It is turned on when the second delay signal SW2 is valid, allowing the internal power supply VCC to provide charging current to the gate of the power switch Q1.

[0024] The power generation module 110 is a self-powered circuit. During the off period of the switching transistor Q1, it obtains and stores the voltage from the source of the primary high voltage transistor GAN to provide the voltage required for the normal operation of other modules. Figure 2 An embodiment of the present invention is shown. Figure 1 The waveforms of each signal in the driving circuit shown are illustrated. Figure 2 As shown, when the control signal SW rises, the first delayed signal SW1 rises synchronously with the control signal SW, and after a preset time Tdly, the first delayed signal SW1 falls. When the first delayed signal SW1 falls, the second delayed signal SW2 rises, and when the control signal SW falls, the second delayed signal SW2 falls synchronously.

[0025] This embodiment is illustrated by... Figure 2 The waveform shown further illustrates the dynamic change of the drive voltage at key nodes in the drive circuit. Here, VG is the gate voltage of power switch Q1, and VS is the source voltage of the primary-side high-voltage transistor GaN. Figure 2As can be seen, when the control signal SW rises, the first delay signal SW1 rises synchronously to a valid high level, driving the first switch K1 to conduct. This allows the source of the primary high-voltage transistor GaN to provide charging current to the gate of the power switch Q1 through the first diode D1. VG gradually rises to the threshold voltage of the power switch Q1, and the power switch Q1 begins to conduct and generates drain-source current. Subsequently, VG enters the Miller plateau stage, where the charging current mainly flows to the gate-drain parasitic capacitance Cgd of the power switch Q1, keeping VG at the plateau voltage for a period of time. At the same time, VS decreases in stages due to the extraction of source current. After the preset time Tdly is reached, the first delay signal SW1 drops to a low level, the second delay signal SW2 rises to a valid high level, the first switch K1 turns off, and the second switch K2 turns on. VG is further pulled high by the internal power supply VCC to a stable level, the power switch Q1 turns on, and thus the VS voltage is pulled low. This phased driving method utilizes the primary high-voltage GaN source to provide driving current in the initial stage to reduce the internal power supply load. The Miller plateau stage ensures the smooth conduction of the power switch Q1. Finally, the internal power supply VCC supplies power to stabilize VG to a high level, thereby ensuring the reliable conduction of the power switch Q1 and maintaining the stability of the system's self-powered operation.

[0026] According to the above embodiments, the present invention divides the turn-on process of the power switch into two stages by setting a power generation module 110, a delay module 130, and a first drive module 140 and a second drive module 150, which are respectively controlled. In the initial turn-on stage, the source of the GaN high-voltage transistor on the primary side of the transformer 200 provides the charging current. After a preset delay time, the internal power supply voltage VCC output by the power generation module 110 continues to charge the gate of the power switch. This segmented driving method effectively disperses the sources of drive current, reduces the transient load pressure on the internal power supply, and significantly improves the stability of the self-powered power supply voltage, thereby improving the operational reliability of the flyback self-powered system during dynamic driving.

[0027] In one embodiment, reference Figure 1 The first driving module 140 includes a first switch K1 and a first diode D1. The first terminal of the first switch K1 is connected to the cathode of the first diode D1, the second terminal of the first switch K1 is connected to the gate of the power switch Q1, and the control terminal of the first switch K1 is connected to the delay module 130 to receive a first delay signal SW1. The anode of the first diode D1 is connected to the source of the primary high-voltage transistor GaN.

[0028] In this embodiment, by setting a current path composed of a first switch K1 and a first diode D1 in the first driving path, the source of the primary-side high-voltage transistor GaN can provide charging current to the gate of the power switch Q1 at a specific timing, thereby achieving initial gate charging of the power switch Q1. The first delay signal SW1 output by the delay module 130 is used to control the conduction time of the first switch K1, so that the driving current is only turned on in a preset stage, ensuring the controllability of the charging process. This structure can fully utilize the electrical energy on the source side of the primary-side high-voltage transistor GaN to achieve stable driving under self-powered conditions, while avoiding transient load on the internal power supply, thus improving the overall stability of the system.

[0029] In one embodiment, reference Figure 1 The first drive module 140 also includes a clamping diode Dz. The cathode of the clamping diode Dz is connected to the second terminal of the first switch K1, and the anode is grounded.

[0030] In this embodiment, a clamping diode Dz is introduced into the first driving module 140 to clamp the gate voltage of the power switch Q1 during its conduction process, preventing damage. This structure can effectively suppress transient high voltage or current at the gate, avoiding device breakdown or reliability degradation due to overvoltage, thereby further improving the safety and stability of the driving circuit.

[0031] In one embodiment, reference Figure 1 The second drive module 150 includes a second switch K2. The first end of the second switch K2 is connected to the power generation module 110, the second end is connected to the gate of the power switch Q1, and the control end of the second switch K2 is connected to the delay module 130 to receive the second delay signal SW2.

[0032] In this embodiment, by setting a second driving module 150, the second switch K2 is turned on when the second delay signal SW2 is valid, and provides charging current to the gate of the power switch Q1. During the operation of the first driving module 140, the source voltage of the primary high-voltage transistor GaN gradually decreases. After a preset delay time Tdly, the first driving module 140 is turned off, and the second driving module 150 can immediately take over to provide a stable driving current to the gate of Q1, avoiding gate voltage fluctuations caused by power switching. By having different power paths undertake the driving power supply in different time periods, this embodiment can effectively share the load pressure of the self-powered power supply, ensuring continuous conduction behavior and stable driving characteristics of the power switch Q1, thereby improving the overall response speed and operational reliability of the driving circuit in self-powered mode.

[0033] In practical applications, the first switch K1 and the second switch K2 can be implemented using different types of devices, such as PMOS, NMOS or other devices with equivalent switching characteristics, according to the specific design requirements of the circuit, in order to adapt to different driving voltage polarities and conduction conditions, thereby optimizing driving performance and power consumption while ensuring the consistency of circuit functions.

[0034] In one embodiment, reference Figure 1 The driving circuit also includes a first resistor R1. The first end of the first resistor R1 is connected to the source of the power switch Q1, and the second end is grounded. In this embodiment, by placing the first resistor R1 between the source of the power switch Q1 and ground, the drain-source current of Q1 can be detected or current-limiting assisted. During the driving process, the first resistor R1 can provide a feedback signal so that the control circuit can monitor the operating state of the power switch Q1. Simultaneously, it attenuates the source current to a certain extent when the transient current is large, thereby helping to protect the device, improve switching stability, and enhance the overall safety and reliability of the driving circuit.

[0035] It should be noted that in actual design, it is necessary to ensure that when the preset delay time Tdly ends, although the source voltage VS of the primary high-voltage transistor GaN decreases, it can still provide charging current to the gate of the power switch Q1. That is, VS should remain greater than the sum of the Miller plateau voltage and the forward conduction voltage of the first diode D1, thereby ensuring that VG can rise smoothly to the Miller plateau stage. At the same time, since VS is usually higher than the internal power supply VCC before the power switch Q1 is turned on, for example, it may reach about 15V, the withstand voltage capability of the first switch K1 needs to be considered to accommodate the higher VS voltage. The withstand voltage of the second switch K2 can be selected according to the VCC level. For example, if VCC is 5V, the second switch K2 can be a 5V withstand voltage device, while the withstand voltage of the first switch K1 should be at least 15V.

[0036] According to the above embodiment, by dividing the turn-on process of the power switch Q1 into two stages, in the initial turn-on stage, the source of the charging current to the gate of the power switch Q1 is the source voltage VS of the primary high-voltage transistor GaN. Since the power switch Q1 is relatively large, the charging current in this stage is typically a fast and high-amplitude pulse current. By directly providing the drive current through VS, the internal power supply VCC can be spared from bearing this transient current, thereby significantly reducing the internal power supply losses and improving its voltage stability.

[0037] Figure 3 A circuit topology diagram of a delay module 130 according to an embodiment of the present invention is shown. Figure 3As shown, the delay module 130 includes a first inverter INV1, a second inverter INV2, a reference current source Iref, a first switch M1, a second switch M2, a delay capacitor Cdly, a Schmitt trigger smt, and a first AND gate A1. The input of the first inverter INV1 is connected to the control signal SW, and its output is connected to the gates of both the first and second switches M1 and M2. One end of the reference current source Iref is connected to the internal power supply VCC, and the other end is grounded through the first and second switches M1 and M2 respectively. The first end of the delay capacitor Cdly is connected between the first and second switches M1 and M2, and the second end of Cdly is grounded. The input of the Schmitt trigger smt is connected to the first end of the delay capacitor Cdly, and the output of the Schmitt trigger smt is connected to the first input of the first AND gate A1. The input of the second inverter INV2 is connected to the output of the first inverter INV1, the output of the second inverter INV2 is connected to the second input of the first AND gate A1, and the output of the first AND gate A1 outputs the first delayed signal SW1.

[0038] In one embodiment, reference Figure 3 The delay module 130 also includes a third inverter INV3 and a second AND gate A2. The input of the third inverter INV3 is connected to the output of the first AND gate A1, and the output of the third inverter INV3 is connected to the first input of the second AND gate A2. The second input of the second AND gate A2 is connected to the output of the second inverter INV2, and the output of the second AND gate A2 outputs the second delay signal SW2.

[0039] The first switch M1 can be a PMOS transistor, and the second switch M2 can be an NMOS transistor.

[0040] In the above embodiment, the delay module 130 is used to generate a first delay signal SW1 and a second delay signal SW2 according to the control signal SW, thereby realizing phased control of the driving process of the power switch Q1. When the control signal SW is at a low level, the delay module 130 keeps both the first delay signal SW1 and the second delay signal SW2 at a low level. When the control signal SW jumps from a low level to a high level, the delay capacitor Cdly inside the delay module 130 starts charging from its initial low value, and its voltage gradually increases. Before the voltage Vdly of the delay capacitor reaches the Schmitt trigger's toggling threshold Vth_smt, the Schmitt trigger output remains at a high level, causing the first delay signal SW1 to output a high level and the second delay signal SW2 to remain at a low level. When Vdly rises to Vth_smt, the Schmitt trigger flips to a low level, the first delay signal SW1 drops to a low level, and the second delay signal SW2 rises to a high level. This design allows the driving process to be precisely divided into two stages. The first stage is controlled by the first delay signal SW1 to initially turn on the power switch Q1. The second stage is controlled by the second delay signal SW2 to smoothly pull up the gate voltage of the power switch Q1 to the internal power supply VCC level, thereby ensuring smooth switching of the driving voltage and reliable operation of the system's self-powered system. The specific design of the preset delay time Tdly can be determined based on the charging characteristics of the delay capacitor Cdly and the switching threshold of the Schmitt trigger, thus achieving precise delay control.

[0041] In one embodiment, the formula for the preset time Tdly is: ; Among them, V th_smt The toggling threshold of the Schmitt trigger (SMT).

[0042] Figure 4 The diagram shows waveforms of the control signal SW, the delay capacitor voltage Vdly, the first delay signal SW1, and the second delay signal SW2 according to an embodiment of the present invention. Figure 4 As shown, when SW rises to a high level, Vdly gradually increases, reaching the Schmitt trigger threshold V. th_smt The first delayed signal SW1 is high, and the second delayed signal SW2 is low. When Vdly reaches the threshold V... th_smt Then, SW1 switches to low and SW2 switches to high, thereby achieving delayed switching control.

[0043] Figure 5 A schematic flowchart of a drive method for a flyback self-powered system according to an embodiment of the present invention is shown. Figure 5 As shown, the method includes the following steps: Step S100: Obtain the control signal SW, and generate the first delay signal SW1 and the second delay signal SW2 based on the control signal SW.

[0044] In step S200, when the control signal rises, the first delay signal SW1 rises synchronously with the control signal SW, so that the source of the primary high voltage transistor GaN provides charging current to the gate of the power switch transistor Q1.

[0045] In step S300, after a preset time Tdly, the first delay signal SW1 decreases and the second delay signal SW2 increases, causing the source of the primary high-voltage transistor GaN to stop providing charging current to the power switch Q1, and causing the internal power supply VCC to provide charging current to the gate of the power switch Q1.

[0046] The specific implementation methods of each step in the above-described drive method for flyback self-powered circuits refer to the relevant content of the embodiment in the above-described drive circuit 100 for flyback self-powered circuits, and will not be repeated here.

[0047] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0048] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A driving circuit applied to a flyback self-powered, characterized in that, The drive circuit comprises: a power switch tube Q1, a drain of which is connected with a source of a primary high-voltage tube GaN, and a source of the power switch tube Q1 is grounded; a power supply generation module, an input end of which is connected with the source of the primary high-voltage tube GaN, and an output end of which outputs an internal power supply VCC; a control module, used for outputting a control signal SW; a delay module, connected with the control module, used for generating a first delay signal SW1 and a second delay signal SW2 according to the control signal SW; a first drive module, an input end of which is connected with the source of the primary high-voltage tube GaN, and an output end of which is connected with a gate of the power switch tube Q1, used for turning on when the first delay signal SW1 is received, so that the source of the primary high-voltage tube GaN provides a charging current to the gate of the power switch tube Q1; a second drive module, an input end of which is connected with the power supply generation module, and an output end of which is connected with the gate of the power switch tube Q1, used for turning on when the second delay signal SW2 is received, so that the internal power supply VCC provides a charging current to the gate of the power switch tube Q1.

2. The drive circuit according to claim 1, characterized in that, When the control signal SW rises, the first delay signal SW1 rises synchronously with the control signal SW, and the first delay signal SW1 falls after a preset time Tdly; When the first delay signal SW1 falls, the second delay signal SW2 rises synchronously with the control signal SW falling.

3. The drive circuit according to claim 2, characterized in that, The first drive module comprises a first switch K1 and a first diode D1. A first end of the first switch K1 is connected to a cathode of the first diode D1, a second end of the first switch K1 is connected to the gate of the power switch tube Q1, and a control end of the first switch K1 is connected to the delay module, used for receiving the first delay signal SW1. An anode of the first diode D1 is connected to the source of the primary high-voltage tube GaN.

4. The drive circuit according to claim 3, characterized in that, The first drive module further comprises: a clamping diode Dz, a cathode of which is connected to the second end of the first switch K1, and an anode of which is grounded.

5. The drive circuit according to claim 2, characterized by The second drive module comprises: a second switch K2, a first end of which is connected to the power supply generation module, and a second end of which is connected to the gate of the power switch tube Q1, and a control end of the second switch K2 is connected to the delay module, used for receiving the second delay signal SW2.

6. The drive circuit according to claim 2, characterized by The drive circuit further comprises: a first resistor R1, a first end of which is connected to a source of the power switch tube Q1, and a second end of which is grounded.

7. The drive circuit according to any one of claims 2 to 6, characterized in that, The delay module comprises a first inverter INV1, a second inverter INV2, a reference current source Iref, a first switch tube M1, a second switch tube M2, a delay capacitor Cdly, a Schmitt trigger smt and a first AND gate A1. An input end of the first inverter INV1 is connected to the control signal SW, and an output end of the first inverter INV1 is connected with gates of the first switch tube M1 and the second switch tube M2. One end of the reference current source Iref is connected to the internal power supply VCC, and the other end of the reference current source Iref is grounded through the first switch tube M1 and the second switch tube M2 in sequence. A first end of the delay capacitor Cdly is connected between the first switch tube M1 and the second switch tube M2, and a second end of the delay capacitor Cdly is grounded. An input end of the Schmitt trigger smt is connected to the first end of the delay capacitor Cdly, and an output end of the Schmitt trigger smt is connected to a first input end of the first AND gate A1. An input end of the second inverter INV2 is connected to an output end of the first inverter INV1, an output end of the second inverter INV2 is connected to a second input end of the first AND gate A1, and an output end of the first AND gate A1 outputs the first delay signal SW1.

8. The drive circuit according to claim 7, characterized in that, The delay module further comprises a third inverter INV3 and a second AND gate A2. An input end of the third inverter INV3 is connected to an output end of the first AND gate A1, and an output end of the third inverter INV3 is connected to a first input end of the second AND gate A2. A second input end of the second AND gate A2 is connected to an output end of the second inverter INV2, and an output end of the second AND gate A2 outputs the second delay signal SW2.

9. The drive circuit according to claim 8, characterized in that, The formula of the preset time Tdly is: ； wherein V th_smt is the flip threshold of the Schmitt trigger smt.

10. A driving method applied to a flyback self-powered, characterized in that, The method comprises the following steps: obtaining a control signal SW, and generating a first delay signal SW1 and a second delay signal SW2 according to the control signal SW; when the control signal rises, the first delay signal SW1 rises synchronously with the control signal SW, so that the source of the primary high-voltage tube GaN provides charging current to the gate of the power switch tube Q1; after a preset time Tdly, the first delay signal SW1 falls, and the second delay signal SW2 rises, so that the source of the primary high-voltage tube GaN stops providing charging current to the gate of the power switch tube Q1, and the internal power supply VCC provides charging current to the gate of the power switch tube Q1.

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