FPGA-based serial port baud rate adaptive detection method
By sampling the serial port signal at the rising edge of the system clock using an FPGA, calculating the autocorrelation function and differential sequence, adaptive detection of the serial port baud rate is achieved. This solves the problems of low accuracy and high resource consumption in traditional methods, and improves the accuracy and adaptability of the detection.
Patent Information
- Application Number
- CN202511710151.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-02-27
AI Technical Summary
Existing serial communication receivers cannot accurately parse data when the baud rate is unknown. Furthermore, traditional adaptive detection methods are susceptible to noise interference, consume a lot of resources, and have a single data format, resulting in poor adaptability.
By sampling the serial port signal at the rising edge of the system clock using the FPGA, calculating the autocorrelation function and second-order difference sequence of the binary sequence, searching for the inflection point position, calculating the baud rate and matching it with the standard baud rate, the baud rate adaptive switching is achieved.
It achieves accurate detection of serial port baud rate under unknown baud rate, reduces FPGA resource consumption, adapts to different data structures, and improves detection accuracy and speed.
Smart Images
Figure CN121585584A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of serial communication technology, and more specifically to an FPGA-based adaptive serial port baud rate detection method. Background Technology
[0002] Currently, FPGAs are a common tool for implementing serial communication. However, serial communication requires both the sender and receiver to communicate at a fixed baud rate. If the sender changes the baud rate, the receiver will be unable to correctly parse the data. Existing serial communication receiver baud rate adaptive detection methods, such as start bit level detection, parity bit detection, and fixed data format analysis, have significant limitations in practical applications: firstly, they are susceptible to noise interference, resulting in low detection accuracy; secondly, they consume a lot of resources and have slow response speeds; and thirdly, they rely on a single data format, and changes in the data format can easily cause the detection scheme to fail. Summary of the Invention
[0003] The technical problem this invention aims to solve is: how to automatically detect the serial port baud rate when the current communication baud rate is unknown, thus overcoming the problems of low accuracy, high resource consumption, and limited data format in traditional adaptive methods. The specific implementation steps are as follows:
[0004] (1) The FPGA operating system clock frequency is The FPGA samples the serial port RX receive signal line on each rising edge of the system clock; the FPGA uses the current baud rate. Analyze the data, current bit period If the sampled value transitions from high to low, it is identified as the start of a new data transmission start bit. The transition time is used as a reference point, and after... The sampling points after the time are recorded as ;if Then thereafter For the sampling frequency, obtain the total Binary sampling sequence of points Otherwise, wait for the sampled value to transition from high to low again, where It equals 0 or 1. Binary sequence index, , It is a positive even number;
[0005] (2) For binary sequences Calculate different time-domain delays The autocorrelation function sequence below ,in This represents the XOR operation. For autocorrelation function sequence index, ;
[0006] (3) calculate second-order difference sequence of , wherein second-order difference sequence of index, ; sequentially search from the first index position satisfying recorded as the inflection point position ;
[0007] (4) according to the inflection point position and the sampling frequency , calculate , wherein the calculated baud rate; the FPGA matches the calculated baud rate with the standard baud rate, and selects the standard baud rate closest to as the final identified baud rate ;
[0008] (5) if , the FPGA switches to use the baud rate to analyze data, otherwise still uses the baud rate to analyze data.
[0009] The beneficial effects of the present application are that the serial port rate estimation is accurate, the FPGA resource occupation is small, only simple XOR gate, counter and comparator are needed to realize, and it is effective for any data structure, without fixed transmission data format, and has strong adaptability. BRIEF DESCRIPTION OF DRAWINGS
[0010] Figure 1 is a serial port baud rate self-adaptive detection flowchart based on FPGA. DETAILED DESCRIPTION
[0011] The FPGA samples the serial port RX receiving signal line at each rising edge of the system clock, first detects the start bit and obtains the binary sampling sequence, then calculates the autocorrelation function sequence of the binary sequence under different delays and the second-order difference sequence of the autocorrelation function sequence, searches for the first inflection point position, calculates the baud rate and matches it with the standard baud rate, and finally compares the result with the current baud rate to determine whether to switch. The overall steps are shown in Figure 1 , and the specific implementation steps are as follows:
[0012] (1) the working system clock frequency of the FPGA is , and the FPGA samples the serial port RX receiving signal line at each rising edge of the system clock; the FPGA uses the current baud rate to analyze data, and the current bit period ; if the sampling value jumps from high level to low level, it is identified as the start bit of new data transmission, taking the jumping time as the reference point, and the sampling point after time is recorded as ; if , then the sampling frequency is , and a binary sampling sequence of total points is obtained , otherwise, the FPGA re-waits for the sampling value to jump from high level to low level, wherein is equal to 0 or 1, is the index of the binary sequence , , is a positive even number.
[0013] (2) for the binary sequence , the autocorrelation function sequence under different time domain delays is calculated, wherein represents the exclusive or operation, is the index of the autocorrelation function sequence .
[0014] (3) the second-order difference sequence of is calculated, wherein is the index of the second-order difference sequence ; starting from , the FPGA sequentially searches to find the first index position satisfying , which is recorded as the inflection point position .
[0015] (4) according to the inflection point position and the sampling frequency , the baud rate is calculated, wherein is the calculated baud rate; the FPGA matches the calculated baud rate with the standard baud rate, and selects the standard baud rate closest to as the final identified baud rate .
[0016] (5) if , the FPGA switches to use the baud rate to analyze data, otherwise, the FPGA still uses the baud rate to analyze data.
Claims
1. An FPGA-based serial port baud rate adaptive detection method, the implementation steps of which are: (1) The FPGA operating system clock frequency is The FPGA samples the serial port RX receive signal line on each rising edge of the system clock; the FPGA uses the current baud rate. Analyze the data, current bit period If the sampled value transitions from high to low, it is identified as the start of a new data transmission start bit. The transition time is used as a reference point, and after... The sampling points after the time are recorded as ;if Then thereafter For the sampling frequency, obtain the total Binary sampling sequence of points Otherwise, wait for the sampled value to transition from high to low again, where It equals 0 or 1. Binary sequence index, , It is a positive even number; (2) For binary sequences Calculate different time-domain delays The autocorrelation function sequence below ,in This represents the XOR operation. For autocorrelation function sequence index, ; (3) Calculation Second-order difference sequence ,in Second-order difference sequence index, ;from Begin sequential search, find the first one that satisfies... index position Record as the inflection point position ; (4) Based on the location of the inflection point and sampling frequency calculate ,in The calculated baud rate; the FPGA will use the calculated baud rate Match to the standard baud rate and select the closest one. The standard baud rate is used as the final baud rate for identification. ; (5) If Then the FPGA switches to using the baud rate. Parse the data; otherwise, use the baud rate. Analyze the data.