Electronic device

Abstract

The invention discloses an electronic device which comprises a chip and a mainboard, the chip is electrically connected with the mainboard, the mainboard comprises a plurality of insulating layers and a plurality of conductor layers, the conductor layers and the insulating layers are sequentially and alternately stacked, the number of the conductor layers is one more than that of the insulating layers, and the number of the conductor layers is one more than that of the conductor layers. A through hole penetrating through the insulating layer is formed in the insulating layer between two outermost conductor layers in the multiple conductor layers, the through hole is formed in the direction of a vertical connecting line between the two outermost conductor layers, a first heat conduction piece is arranged in the through hole, and the two outermost conductor layers in the multiple conductor layers are connected through the first heat conduction piece arranged in each through hole. And the conductor layer located between the two outermost conductor layers is in heat conduction connection with the conductor layer located between the two outermost conductor layers. Thus, heat generated on the chip can be transmitted through the two outermost conductor layers, the first heat conduction piece arranged in each through hole and the conductor layer located between the two outermost conductor layers, and therefore the heat dissipation effect of the chip can be enhanced.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to an electronic device. Background Technology

[0002] With the continuous development of electronic technology, electronic devices are playing an increasingly important role in people's lives. To improve the computing power of electronic devices, chips and motherboards are usually installed. However, the side of the chip closest to the motherboard has poor heat dissipation due to the multiple insulating layers on the motherboard, which have poor heat dissipation performance. Summary of the Invention

[0003] This application aims to provide an electronic device that can solve the problem of poor heat dissipation of chips.

[0004] To solve the above-mentioned technical problems, this application is implemented as follows:

[0005] This application provides an electronic device, including a chip and a motherboard. The chip is electrically connected to the motherboard, and the motherboard includes multiple insulating layers and multiple conductive layers. The conductive layers and the insulating layers are stacked alternately in sequence. The number of conductive layers is one more than the number of insulating layers. An insulating layer between the two outermost conductive layers in the multi-layer conductive layers has a through-hole penetrating the insulating layer. The through-hole is arranged along the direction of the vertical line connecting the two outermost conductive layers. A first heat-conducting element is provided in the through-hole. The two outermost conductive layers in the multi-layer conductive layers are thermally connected through the first heat-conducting element provided in each through-hole and the conductive layer located between the two outermost conductive layers.

[0006] In the embodiments of this application, the chip is electrically connected to the motherboard, and the motherboard includes multiple insulating layers and multiple conductive layers. The conductive layers and insulating layers are stacked alternately in sequence. The two outermost conductive layers in the multiple conductive layers are thermally connected through a first heat-conducting element provided in each through hole and a conductive layer located between the two outermost conductive layers. In this way, the heat generated on the chip can be transferred through the two outermost conductive layers, the first heat-conducting element provided in each through hole, and the conductive layer located between the two outermost conductive layers, thereby enhancing the heat dissipation effect of the chip.

[0007] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0008] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0009] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0010] Figure 2 This is a schematic diagram of the structure of the first insulating layer group included in the electronic device provided in the embodiments of this application;

[0011] Figure 3 This is a schematic diagram of the structure of the second insulating layer group included in the electronic device provided in the embodiments of this application;

[0012] Figure 4 This is a schematic diagram of the structure of the motherboard included in the electronic device provided in the embodiments of this application;

[0013] Figure 5 This is a schematic diagram of the structure of the second heat-conducting component included in the electronic device provided in the embodiments of this application. Detailed Implementation

[0014] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0015] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0016] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0017] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0018] See Figure 1 , Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 1 As shown, the electronic device includes a chip 10 and a motherboard 20. The chip 10 is electrically connected to the motherboard 20, and the motherboard 20 includes multiple insulating layers 21 and multiple conductor layers 22. The conductor layers 22 and the insulating layers 21 are stacked alternately in sequence. The number of conductor layers 22 is one more than the number of insulating layers 21. The insulating layer 21 between the two outermost conductor layers 22 has a through hole penetrating the insulating layer 21. The through hole is arranged along the direction of the vertical line connecting the two outermost conductor layers 22. A first heat-conducting element 30 is provided in the through hole. The two outermost conductor layers 22 are thermally connected through the first heat-conducting element 30 provided in each through hole and the conductor layer 22 located between the two outermost conductor layers 22.

[0019] The specific type of chip 10 is not limited here. Optionally, chip 10 may include a system-on-chip (SoC) for electronic devices, a chip for short-range wireless connection, or a radio frequency chip, etc. The aforementioned SoC can be understood as a system-on-chip that integrates functional modules such as baseband, modem, and application processor.

[0020] Among them, the motherboard 20 can be referred to as a printed circuit board (PCB).

[0021] Among them, the two outermost conductor layers 22 can be referred to as the first conductor layer and the second conductor layer, respectively. The first conductor layer can be understood as the conductor layer 22 that is closest to the chip 10 in the multilayer conductor layers 22, while the second conductor layer can be understood as the conductor layer 22 that is farthest from the chip 10 in the multilayer conductor layers 22. That is, along the direction from the first conductor layer to the second conductor layer, the distance between the conductor layer 22 and the chip 10 gradually increases.

[0022] It should be noted that each insulating layer 21 located between the two outermost conductor layers 22 (i.e., the first conductor layer and the second conductor layer) is provided with a through hole penetrating the insulating layer 21, and a first heat-conducting element 30 is provided in the through hole. In this way, heat can be transferred between the first conductor layer and the second conductor layer through the first heat-conducting element 30 provided in the through hole of each insulating layer 21 and the conductor layer located between the first conductor layer and the second conductor layer. That is, the heat generated on the chip 10 can be discharged from the chip 10 through the first conductor layer, the second conductor layer, the first heat-conducting element 30 provided in the through hole of each insulating layer 21, and the conductor layer located between the first conductor layer and the second conductor layer, thereby enhancing the heat transfer effect. The first heat-conducting element 30 and the corresponding insulating layer 21 are both located between the first conductor layer and the second conductor layer.

[0023] For example: see Figure 1 Along the direction from near to far from chip 10, the conductor layers 22 included in the multilayer conductor layer 22 can be named sequentially as: outer conductor layer 201, second outer conductor layer 202, third outer conductor layer 203, intermediate conductor layer 204, third outer conductor layer 203, second outer conductor layer 202, and outer conductor layer 201. That is, the first conductor layer can be understood as the outer conductor layer 201 near chip 10, and the second conductor layer can be understood as the outer conductor layer 201 far from chip 10. In other words, the two outermost conductor layers 22 are the outer conductor layer 201 near chip 10 and the outer conductor layer 201 far from chip 10, respectively.

[0024] It should be noted that, optionally, the aforementioned multilayer conductor layers 22 can also be connected by signal connection conductors 205. In this way, the signal connection conductors 205 can play the role of signal connection between the aforementioned multilayer conductor layers 22, thereby enhancing the signal transmission effect between the aforementioned multilayer conductor layers 22.

[0025] In this embodiment, the chip 10 is electrically connected to the motherboard 20, and the motherboard 20 includes multiple insulating layers 21 and multiple conductor layers 22. The conductor layers 22 and the insulating layers 21 are stacked alternately in sequence. The two outermost conductor layers 22 in the multiple conductor layers 22 are thermally connected through the first heat-conducting element 30 provided in each through hole and the conductor layer 22 located between the two outermost conductor layers 22. In this way, the heat generated on the chip 10 can be transferred through the two outermost conductor layers 22 (i.e., the first conductor layer and the second conductor layer), the first heat-conducting element 30 provided in each through hole, and the conductor layer 22 located between the two outermost conductor layers 22, thereby enhancing the heat dissipation effect of the chip 10.

[0026] It should be noted that the specific method by which the heat generated on the chip 10 is transferred through the two outermost conductor layers 22, the first heat-conducting element 30 disposed in each through hole, and the conductor layer 22 located between the two outermost conductor layers 22 is not limited here. Optionally, a separate conductor heat-conducting element may be disposed on the conductor layer 22 between the two outermost conductor layers 22 (i.e., the first conductor layer and the second conductor layer), and the first heat-conducting element 30 located between the two outermost conductor layers 22 may be connected to the conductor heat-conducting element. In this way, the heat transfer between the two outermost conductor layers 22 can be completed through the first heat-conducting element 30 located between the two outermost conductor layers 22 and the conductor heat-conducting element.

[0027] As another optional implementation, any one of the first heat-conducting elements 30 is thermally connected to each of the two adjacent conductor layers 22. Since the conductor layer 22 is typically a metal layer, its thermal conductivity is generally good. By thermally connecting any one of the first heat-conducting elements 30 to each of the two adjacent conductor layers 22, there is no need to additionally install conductor heat-conducting elements on the conductor layer 22. This allows the conductor layer 22 to be reused for heat conduction, thereby reducing the number of components in the electronic device, lowering usage and manufacturing costs, and reducing the overall size of the electronic device.

[0028] Alternatively, see Figure 1 The electronic device may also include a flash memory chip 70, a fifth heat-conducting element 71, a sixth heat-conducting element 72, and a shielding cover 73. The sixth heat-conducting element 72, the fifth heat-conducting element 71, and the flash memory chip 70 can be stacked sequentially, and the flash memory chip 70 can abut against the chip 10. In this way, the heat generated on the chip 10 can be dissipated by passing through the flash memory chip 70, the fifth heat-conducting element 71, and the sixth heat-conducting element 72 in sequence. That is, the heat generated on the chip can be dissipated by passing through the two outermost conductor layers 22, the first heat-conducting element 30 in each through hole, and the conductor layer 22 located between the two outermost conductor layers 22 in sequence, as well as by passing through the flash memory chip 70, the fifth heat-conducting element 71, and the sixth heat-conducting element 72 in sequence, thereby further enhancing the heat dissipation effect of the chip 10.

[0029] It should be noted that the two outermost conductor layers 22, the first heat-conducting element 30 disposed in each through hole, and the conductor layer 22 located between the two outermost conductor layers 22 can be located on the first side of the chip 10, while the flash memory chip 70, the fifth heat-conducting element 71, and the sixth heat-conducting element 72 can be located on the second side of the chip 10. In this way, heat can be dissipated from both sides of the chip 10 at the same time, which further enhances the heat dissipation effect of the chip 10. The first side and the second side can be opposite sides.

[0030] It should be noted that the shielding cover 73 may have a receiving cavity, and the chip 10, motherboard 20, first heat-conducting component 30, flash memory chip 70, fifth heat-conducting component 71, second heat-conducting component 40, third heat-conducting component 50 and fourth heat-conducting component 60 (described later) may all be disposed in the receiving cavity. In this way, the shielding cover 73 can protect the above components and shield them from interference.

[0031] Optionally, the fifth thermal conductive component 71 may include a thermal conductive gel or a thermal conductive grease, etc. Optionally, the sixth thermal conductive component 72 may include a heat sink or a heat dissipation film, etc. For example, the sixth thermal conductive component 72 may include a vacuum chamber (VC) or a pyrolytic graphite sheet (PGS).

[0032] It should be noted that, due to the characteristics of electronic devices, such as mixed-signal and high component density, the motherboard 20 of the electronic device usually needs to be a high-order board. However, when high-order boards are processed to obtain mechanical through-holes, the mechanical through-holes are large in size and occupy a lot of space, resulting in a large overall size of the electronic device. At the same time, it is also easy to damage some circuits in the motherboard 20. In order to solve the above technical problems, the following implementation method is proposed:

[0033] As an optional implementation, see [link to implementation details]. Figure 1 The motherboard 20 includes a first insulating layer group 23 and a second insulating layer group 24, see [link / reference]. Figure 1 and Figure 2 The first insulating layer group 23 includes at least two insulating layers 21 of the multilayer insulating layers 21, and the through holes formed on each insulating layer 21 in the first insulating layer group 23 are obtained by laser drilling process, see [link to documentation]. Figure 1 and Figure 3 The second insulating layer group 24 includes at least one insulating layer 21 of the multilayer insulating layers 21, and the through holes opened on each insulating layer 21 in the second insulating layer group 24 are obtained by machining process.

[0034] In this embodiment, the through holes processed by laser drilling are smaller in size, thus reducing the space occupied by the through holes and consequently reducing the overall size of the electronic device. This also reduces the likelihood of damage to some circuits in the motherboard 20. Furthermore, because laser drilling is costly, in this embodiment, only the through holes on each insulating layer 21 of the first insulating layer group 23 are processed by laser drilling, while the through holes on each insulating layer 21 of the second insulating layer group 24 are processed by machining, thereby reducing processing costs.

[0035] It should be noted that the positions of the first insulating layer group 23 and the second insulating layer group 24 are not limited here. Optionally, the first insulating layer group 23 is set close to the chip 10, and the second insulating layer group 24 is set away from the chip 10.

[0036] As an optional implementation, see [link to implementation details]. Figure 1 and Figure 4 There are two first insulating layer groups 23, and the second insulating layer group 24 is located between the two first insulating layer groups 23. One of the two first insulating layer groups 23 is adjacent to one of the two outermost conductor layers 22, and the other of the two first insulating layer groups 23 is adjacent to the other of the two outermost conductor layers 22.

[0037] It should be noted that the number of insulating layers 21 included in the first insulating layer group 23 and the number of insulating layers 21 included in the second insulating layer group 24 are not limited here. Optionally, the number of insulating layers 21 included in the first insulating layer group 23 may be greater than the number of insulating layers 21 included in the second insulating layer group 24.

[0038] In this embodiment, since the second insulating layer group 24 is located between the two first insulating layer groups 23, and the through holes opened on each insulating layer 21 in the first insulating layer group 23 are obtained by laser drilling, while the through holes opened on each insulating layer 21 in the second insulating layer group 24 are obtained by mechanical processing, that is, the through holes opened on each insulating layer 21 in the first insulating layer group 23 are located on the outside, while the through holes opened on each insulating layer 21 in the second insulating layer group 24 are located in the middle. The size of the through holes opened on each insulating layer 21 in the first insulating layer group 23 is usually small, thereby enhancing the waterproof and dustproof effect.

[0039] As an optional implementation, see [link to implementation details]. Figures 1 to 4 The first heat-conducting element 30 is provided in the through holes of each insulating layer 21 included in the first insulating layer group 23 and the second insulating layer group 24, and the first heat-conducting element 30 is processed by electroplating.

[0040] In the first insulating layer group 23, each insulating layer 21 may have multiple through holes, and the multiple through holes may be combined to form a first through hole with a larger size. In the second insulating layer group 24, each insulating layer 21 may have multiple second through holes with a larger individual size, and the multiple second through holes may be spaced apart. Along the horizontal direction of the plane where each insulating layer 21 is located, the size of the first through hole may be greater than the sum of the sizes of the multiple second through holes.

[0041] It should be noted that, due to limitations in electroplating technology, if multiple second through holes are connected together to form a larger through hole, electroplating cannot be performed inside that through hole. However, electroplating can be performed inside a first through hole formed by connecting multiple through holes processed by laser engraving. Thus, since the size of the first through hole can be larger than the sum of the sizes of the multiple second through holes along the horizontal direction of the plane where each insulating layer 21 is located, the size of the first heat-conducting element 30 processed by electroplating inside the first through hole is also larger than the sum of the sizes of the first heat-conducting elements 30 inside the multiple second through holes along the horizontal direction of the plane where each insulating layer 21 is located. This increases the size of the first heat-conducting element 30 in the first insulating layer group 23, thereby further enhancing the heat dissipation effect on the chip 10.

[0042] It should be noted that, see Figure 1 The horizontal direction along the plane where each insulating layer 21 is located can be understood as the X direction, while the direction of the line connecting the first conductor layer to the second conductor layer can be understood as the Z direction. The Z direction can also be referred to as the thickness direction of the motherboard 20.

[0043] In addition, in this embodiment, each insulating layer 21 of the first insulating layer group 23 and the second insulating layer group 24 is provided with a first heat-conducting element 30 in its through hole, and the first heat-conducting element 30 has good thermal conductivity, thereby reducing the proportion of insulating material in each insulating layer 21 of the first insulating layer group 23 and the second insulating layer group 24, and improving the thermal conductivity and thermal conductivity coefficient of each insulating layer 21 of the first insulating layer group 23 and the second insulating layer group 24.

[0044] As an optional implementation, see [link to implementation details]. Figure 1 and Figure 5 The electronic device further includes a second heat-conducting component 40. The motherboard 20 is disposed between the chip 10 and the second heat-conducting component 40, and the second heat-conducting component 40 is connected to a target conductor layer. The target conductor layer is the conductor layer 22 that is closest to the second heat-conducting component 40 among the two outermost conductor layers 22.

[0045] The connection method between the second heat-conducting element 40 and the target conductor layer is not limited here. Optionally, the connection method between the second heat-conducting element 40 and the target conductor layer may include patch or adhesive. For example: see Figure 1 The second heat-conducting element 40 and the target conductor layer can be bonded together by an adhesive layer 41. The orthographic projection of the adhesive layer 41 on the plane containing the upper surface of the second heat-conducting element 40 can be greater than or equal to the area of ​​the upper surface of the second heat-conducting element 40. This makes the connection between the second heat-conducting element 40 and the target conductor layer more stable. The upper surface of the second heat-conducting element 40 can refer to the surface of the second heat-conducting element 40 facing the adhesive layer 41.

[0046] For example: See also Figure 5 The second heat-conducting element 40 can also be connected to the target conductor layer through a patch 42. The number of patches 42 is not limited here. Optionally, there can be two patches 42, and the two patches 42 can be arranged opposite each other, and there can also be a gap between the two patches 42.

[0047] It should be noted that the shape of the patch 42 is not limited here. Optionally, the patch 42 can be a rectangular patch, or alternatively, the patch 42 can be a trapezoidal patch. The lateral dimension of the surface of the trapezoidal patch facing the target conductor layer can be greater than the lateral dimension of the surface of the trapezoidal patch facing the second heat conductor 40. In this way, the bonding area between the trapezoidal patch and the target conductor layer can be larger, thereby further enhancing the heat conduction effect.

[0048] In this embodiment of the application, since the electronic device also includes a second heat-conducting element 40, the motherboard 20 is disposed between the chip 10 and the second heat-conducting element 40, and the second heat-conducting element 40 is connected to the target conductor layer, the heat generated on the chip 10 can be transferred to the target conductor layer and then dissipated through the second heat-conducting element 40, thereby further enhancing the heat dissipation performance of the chip 10.

[0049] It should be noted that the specific structure of the second heat-conducting element 40 is not limited here.

[0050] As an optional implementation, the second heat-conducting element 40 includes a heat-conducting block or a heat-conducting sheet.

[0051] In this embodiment, the second heat-conducting element 40 includes a heat-conducting block or a heat-conducting sheet, which increases the diversity and flexibility of the second heat-conducting element 40.

[0052] For example, the second heat-conducting element 40 can be made of metal, such as a copper block or copper sheet.

[0053] As an optional implementation, see [link to implementation details]. Figure 1 The electronic device further includes a third heat-conducting element 50, and the second heat-conducting element 40 is disposed inside the third heat-conducting element 50.

[0054] Optionally, the second conductor layer on the electronic device (i.e., the conductor layer 22 that is farther away from the chip 10 among the two outermost conductor layers 22) may also be provided with a back-mounted capacitor 51. The back-mounted capacitor 51 can be used to filter the power supply of the chip 10. The third heat-conducting component 50 can wrap around the back-mounted capacitor 51, thereby enhancing the protection performance of the back-mounted capacitor 51 and also enhancing the heat dissipation performance of the back-mounted capacitor 51.

[0055] In this embodiment of the application, since the electronic device also includes a third heat-conducting element 50, and the second heat-conducting element 40 is disposed inside the third heat-conducting element 50, that is, the third heat-conducting element 50 wraps the second heat-conducting element 40, the heat generated on the chip 10 can be transferred to the second heat-conducting element 40 and then dissipated through the third heat-conducting element 50, thereby further enhancing the heat dissipation performance of the chip 10.

[0056] In addition, since the third heat-conducting component 50 wraps around the second heat-conducting component 40, that is, the third heat-conducting component 50 can come into contact with the motherboard 20, the heat generated by the chip 10 can be directly transferred from the motherboard 20 to the third heat-conducting component 50, thereby further enhancing the heat dissipation effect of the chip 10.

[0057] It should be noted that the specific structure of the third heat-conducting component 50 is not limited here.

[0058] As an optional implementation, the third thermal conductive element 50 may include a thermally conductive gel or a thermally conductive silicone grease.

[0059] In this embodiment, the third heat-conducting component 50 includes a thermally conductive gel component or a thermally conductive silicone grease component. The thermally conductive gel component or the thermally conductive silicone grease component has a high thermal conductivity and strong heat dissipation capacity, thereby enhancing the heat dissipation capacity of the third heat-conducting component 50.

[0060] As an optional implementation, see [link to implementation details]. Figure 1 The electronic device further includes a fourth heat-conducting component 60, which is located on the side of the third heat-conducting component 50 away from the motherboard 20, and is connected to the third heat-conducting component 50.

[0061] In this embodiment of the application, since the electronic device also includes a fourth heat-conducting element 60, which is located on the side of the third heat-conducting element 50 away from the motherboard 20 and is connected to the third heat-conducting element 50, the heat generated on the chip 10 can be transferred to the third heat-conducting element 50 and then dissipated through the fourth heat-conducting element 60, thereby further enhancing the heat dissipation performance of the chip 10.

[0062] It should be noted that the specific structure of the fourth heat-conducting component 60 is not limited here.

[0063] As an optional implementation, the fourth heat-conducting element 60 includes a heat sink or a heat dissipation film.

[0064] In this embodiment of the application, the fourth heat-conducting element 60 includes a heat sink or a heat dissipation film, which can increase the heat transfer effect of the fourth heat-conducting element 60. That is, the heat generated on the chip 10 can be transferred to the low-temperature area through the fourth heat-conducting element 60 to achieve cooling and heat dissipation of the chip 10.

[0065] Alternatively, the fourth heat-conducting element 60 may also include a vacuum chamber (VC).

[0066] It should be noted that the first heat-conducting component 30, the second heat-conducting component 40, the third heat-conducting component 50, and the fourth heat-conducting component 60 mentioned above can be used in combination or individually, and no specific limitation is made here.

[0067] As an optional implementation, the orthographic projection of the target area of ​​the chip 10 on the motherboard 20 at least partially coincides with the first heat-conducting component 30, and the target area is the area on the chip 10 where the heat generation exceeds a preset value.

[0068] Optionally, the target area may include the large core area of ​​the chip 10, or the target area may include the graphics processing unit (GPU) area.

[0069] In this embodiment, the target area is the region on the chip 10 where the heat generation exceeds a preset value. That is, the target area can be understood as the region on the chip 10 where the heat generation is more severe. Therefore, the orthogonal projection of the target area of ​​the chip 10 on the motherboard 20 can at least partially coincide with the first heat-conducting component 30, thereby shortening the distance between the first heat-conducting component 30 and the target area, and further enhancing the heat dissipation effect on the target area of ​​the chip 10.

[0070] It should be noted that the specific values ​​of the above preset values ​​are not limited here.

[0071] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0072] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. An electronic device, characterized in that, include: The chip and the motherboard are electrically connected. The motherboard includes multiple insulating layers and multiple conductive layers, which are stacked alternately. The number of conductive layers is one more than the number of insulating layers. An insulating layer between the two outermost conductive layers has a through-hole that penetrates the insulating layer. The through-hole is located along the direction of the vertical line connecting the two outermost conductive layers. A first heat-conducting element is provided in the through-hole. The two outermost conductive layers are thermally connected through the first heat-conducting element in each through-hole and the conductive layer between the two outermost conductive layers.

2. The electronic device according to claim 1, characterized in that, Each of the first heat-conducting elements is thermally connected to two adjacent conductor layers.

3. The electronic device according to claim 1, characterized in that, The motherboard includes a first insulating layer group and a second insulating layer group. The first insulating layer group includes at least two insulating layers from the multilayer insulating layers, and the through holes in each insulating layer of the first insulating layer group are obtained by laser drilling. The second insulating layer group includes at least one insulating layer from the multilayer insulating layers, and the through holes in each insulating layer of the second insulating layer group are obtained by machining.

4. The electronic device according to claim 3, characterized in that, There are two first insulating layer groups, and the second insulating layer group is located between the two first insulating layer groups. One of the two first insulating layer groups is adjacent to one of the two outermost conductor layers, and the other of the two first insulating layer groups is adjacent to the other of the two outermost conductor layers.

5. The electronic device according to claim 3, characterized in that, The first heat-conducting element is provided in the through holes of each insulating layer in the first insulating layer group and the second insulating layer group, and the first heat-conducting element is processed by electroplating.

6. The electronic device according to any one of claims 1 to 5, characterized in that, The electronic device further includes a second heat-conducting component. The motherboard is disposed between the chip and the second heat-conducting component, and the second heat-conducting component is connected to a target conductor layer, which is the conductor layer closest to the second heat-conducting component among the two outermost conductor layers.

7. The electronic device according to claim 6, characterized in that, The electronic device further includes a third heat-conducting component, and the second heat-conducting component is disposed inside the third heat-conducting component.

8. The electronic device according to claim 7, characterized in that, The third thermal conductive component includes a thermally conductive gel component or a thermally conductive silicone grease component.

9. The electronic device according to claim 7, characterized in that, The electronic device further includes a fourth heat-conducting component, which is located on the side of the third heat-conducting component away from the motherboard, and is connected to the third heat-conducting component.

10. The electronic device according to claim 1, characterized in that, The target area of ​​the chip, when projected onto the motherboard, at least partially overlaps with the first heat-conducting component. The target area is the region on the chip where the heat generation exceeds a preset value.

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